drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 /* Really want an OS-independent resettable timer.  Would like to have
  35  * this loop run for (eg) 3 sec, but have the timer reset every time
  36  * the head pointer changes, so that EBUSY only happens if the ring
  37  * actually stalls for (eg) 3 seconds.
  38  */
  39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  40 {
  41         drm_i915_private_t *dev_priv = dev->dev_private;
  42         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  43         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
  44         u32 last_acthd = I915_READ(acthd_reg);
  45         u32 acthd;
  46         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  47         int i;
  48
  49         for (i = 0; i < 100000; i++) {
  50                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  51                 acthd = I915_READ(acthd_reg);
  52                 ring->space = ring->head - (ring->tail + 8);
  53                 if (ring->space < 0)
  54                         ring->space += ring->Size;
  55                 if (ring->space >= n)
  56                         return 0;
  57
  58                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  59
  60                 if (ring->head != last_head)
  61                         i = 0;
  62                 if (acthd != last_acthd)
  63                         i = 0;
  64
  65                 last_head = ring->head;
  66                 last_acthd = acthd;
  67                 msleep_interruptible(10);
  68
  69         }
  70
  71         return -EBUSY;
  72 }
  73
  74 /**
  75  * Sets up the hardware status page for devices that need a physical address
  76  * in the register.
  77  */
  78 int i915_init_phys_hws(struct drm_device *dev)
  79 {
  80         drm_i915_private_t *dev_priv = dev->dev_private;
  81         /* Program Hardware Status Page */
  82         dev_priv->status_page_dmah =
  83                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  84
  85         if (!dev_priv->status_page_dmah) {
  86                 DRM_ERROR("Can not allocate hardware status page\n");
  87                 return -ENOMEM;
  88         }
  89         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
  90         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  91
  92         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  93
  94         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  95         DRM_DEBUG("Enabled hardware status page\n");
  96         return 0;
  97 }
  98
  99 /**
 100  * Frees the hardware status page, whether it's a physical address or a virtual
 101  * address set up by the X Server.
 102  */
 103 void i915_free_hws(struct drm_device *dev)
 104 {
 105         drm_i915_private_t *dev_priv = dev->dev_private;
 106         if (dev_priv->status_page_dmah) {
 107                 drm_pci_free(dev, dev_priv->status_page_dmah);
 108                 dev_priv->status_page_dmah = NULL;
 109         }
 110
 111         if (dev_priv->status_gfx_addr) {
 112                 dev_priv->status_gfx_addr = 0;
 113                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 114         }
 115
 116         /* Need to rewrite hardware status page */
 117         I915_WRITE(HWS_PGA, 0x1ffff000);
 118 }
 119
 120 void i915_kernel_lost_context(struct drm_device * dev)
 121 {
 122         drm_i915_private_t *dev_priv = dev->dev_private;
 123         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
 124
 125         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 126         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 127         ring->space = ring->head - (ring->tail + 8);
 128         if (ring->space < 0)
 129                 ring->space += ring->Size;
 130
 131         if (ring->head == ring->tail)
 132                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 133 }
 134
 135 static int i915_dma_cleanup(struct drm_device * dev)
 136 {
 137         drm_i915_private_t *dev_priv = dev->dev_private;
 138         /* Make sure interrupts are disabled here because the uninstall ioctl
 139          * may not have been called from userspace and after dev_private
 140          * is freed, it's too late.
 141          */
 142         if (dev->irq_enabled)
 143                 drm_irq_uninstall(dev);
 144
 145         if (dev_priv->ring.virtual_start) {
 146                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 147                 dev_priv->ring.virtual_start = 0;
 148                 dev_priv->ring.map.handle = 0;
 149                 dev_priv->ring.map.size = 0;
 150         }
 151
 152         /* Clear the HWS virtual address at teardown */
 153         if (I915_NEED_GFX_HWS(dev))
 154                 i915_free_hws(dev);
 155
 156         return 0;
 157 }
 158
 159 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 160 {
 161         drm_i915_private_t *dev_priv = dev->dev_private;
 162
 163         dev_priv->sarea = drm_getsarea(dev);
 164         if (!dev_priv->sarea) {
 165                 DRM_ERROR("can not find sarea!\n");
 166                 i915_dma_cleanup(dev);
 167                 return -EINVAL;
 168         }
 169
 170         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 171             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 172
 173         dev_priv->ring.Start = init->ring_start;
 174         dev_priv->ring.End = init->ring_end;
 175         dev_priv->ring.Size = init->ring_size;
 176         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 177
 178         dev_priv->ring.map.offset = init->ring_start;
 179         dev_priv->ring.map.size = init->ring_size;
 180         dev_priv->ring.map.type = 0;
 181         dev_priv->ring.map.flags = 0;
 182         dev_priv->ring.map.mtrr = 0;
 183
 184         drm_core_ioremap(&dev_priv->ring.map, dev);
 185
 186         if (dev_priv->ring.map.handle == NULL) {
 187                 i915_dma_cleanup(dev);
 188                 DRM_ERROR("can not ioremap virtual address for"
 189                           " ring buffer\n");
 190                 return -ENOMEM;
 191         }
 192
 193         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 194
 195         dev_priv->cpp = init->cpp;
 196         dev_priv->back_offset = init->back_offset;
 197         dev_priv->front_offset = init->front_offset;
 198         dev_priv->current_page = 0;
 199         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 200
 201         /* Allow hardware batchbuffers unless told otherwise.
 202          */
 203         dev_priv->allow_batchbuffer = 1;
 204
 205         return 0;
 206 }
 207
 208 static int i915_dma_resume(struct drm_device * dev)
 209 {
 210         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 211
 212         DRM_DEBUG("%s\n", __func__);
 213
 214         if (!dev_priv->sarea) {
 215                 DRM_ERROR("can not find sarea!\n");
 216                 return -EINVAL;
 217         }
 218
 219         if (dev_priv->ring.map.handle == NULL) {
 220                 DRM_ERROR("can not ioremap virtual address for"
 221                           " ring buffer\n");
 222                 return -ENOMEM;
 223         }
 224
 225         /* Program Hardware Status Page */
 226         if (!dev_priv->hw_status_page) {
 227                 DRM_ERROR("Can not find hardware status page\n");
 228                 return -EINVAL;
 229         }
 230         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 231
 232         if (dev_priv->status_gfx_addr != 0)
 233                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 234         else
 235                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 236         DRM_DEBUG("Enabled hardware status page\n");
 237
 238         return 0;
 239 }
 240
 241 static int i915_dma_init(struct drm_device *dev, void *data,
 242                          struct drm_file *file_priv)
 243 {
 244         drm_i915_init_t *init = data;
 245         int retcode = 0;
 246
 247         switch (init->func) {
 248         case I915_INIT_DMA:
 249                 retcode = i915_initialize(dev, init);
 250                 break;
 251         case I915_CLEANUP_DMA:
 252                 retcode = i915_dma_cleanup(dev);
 253                 break;
 254         case I915_RESUME_DMA:
 255                 retcode = i915_dma_resume(dev);
 256                 break;
 257         default:
 258                 retcode = -EINVAL;
 259                 break;
 260         }
 261
 262         return retcode;
 263 }
 264
 265 /* Implement basically the same security restrictions as hardware does
 266  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 267  *
 268  * Most of the calculations below involve calculating the size of a
 269  * particular instruction.  It's important to get the size right as
 270  * that tells us where the next instruction to check is.  Any illegal
 271  * instruction detected will be given a size of zero, which is a
 272  * signal to abort the rest of the buffer.
 273  */
 274 static int do_validate_cmd(int cmd)
 275 {
 276         switch (((cmd >> 29) & 0x7)) {
 277         case 0x0:
 278                 switch ((cmd >> 23) & 0x3f) {
 279                 case 0x0:
 280                         return 1;       /* MI_NOOP */
 281                 case 0x4:
 282                         return 1;       /* MI_FLUSH */
 283                 default:
 284                         return 0;       /* disallow everything else */
 285                 }
 286                 break;
 287         case 0x1:
 288                 return 0;       /* reserved */
 289         case 0x2:
 290                 return (cmd & 0xff) + 2;        /* 2d commands */
 291         case 0x3:
 292                 if (((cmd >> 24) & 0x1f) <= 0x18)
 293                         return 1;
 294
 295                 switch ((cmd >> 24) & 0x1f) {
 296                 case 0x1c:
 297                         return 1;
 298                 case 0x1d:
 299                         switch ((cmd >> 16) & 0xff) {
 300                         case 0x3:
 301                                 return (cmd & 0x1f) + 2;
 302                         case 0x4:
 303                                 return (cmd & 0xf) + 2;
 304                         default:
 305                                 return (cmd & 0xffff) + 2;
 306                         }
 307                 case 0x1e:
 308                         if (cmd & (1 << 23))
 309                                 return (cmd & 0xffff) + 1;
 310                         else
 311                                 return 1;
 312                 case 0x1f:
 313                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 314                                 return (cmd & 0x1ffff) + 2;
 315                         else if (cmd & (1 << 17))       /* indirect random */
 316                                 if ((cmd & 0xffff) == 0)
 317                                         return 0;       /* unknown length, too hard */
 318                                 else
 319                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 320                         else
 321                                 return 2;       /* indirect sequential */
 322                 default:
 323                         return 0;
 324                 }
 325         default:
 326                 return 0;
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int validate_cmd(int cmd)
 333 {
 334         int ret = do_validate_cmd(cmd);
 335
 336 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 337
 338         return ret;
 339 }
 340
 341 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords)
 342 {
 343         drm_i915_private_t *dev_priv = dev->dev_private;
 344         int i;
 345         RING_LOCALS;
 346
 347         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 348                 return -EINVAL;
 349
 350         BEGIN_LP_RING((dwords+1)&~1);
 351
 352         for (i = 0; i < dwords;) {
 353                 int cmd, sz;
 354
 355                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 356                         return -EINVAL;
 357
 358                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 359                         return -EINVAL;
 360
 361                 OUT_RING(cmd);
 362
 363                 while (++i, --sz) {
 364                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 365                                                          sizeof(cmd))) {
 366                                 return -EINVAL;
 367                         }
 368                         OUT_RING(cmd);
 369                 }
 370         }
 371
 372         if (dwords & 1)
 373                 OUT_RING(0);
 374
 375         ADVANCE_LP_RING();
 376
 377         return 0;
 378 }
 379
 380 static int i915_emit_box(struct drm_device * dev,
 381                          struct drm_clip_rect __user * boxes,
 382                          int i, int DR1, int DR4)
 383 {
 384         drm_i915_private_t *dev_priv = dev->dev_private;
 385         struct drm_clip_rect box;
 386         RING_LOCALS;
 387
 388         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 389                 return -EFAULT;
 390         }
 391
 392         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 393                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 394                           box.x1, box.y1, box.x2, box.y2);
 395                 return -EINVAL;
 396         }
 397
 398         if (IS_I965G(dev)) {
 399                 BEGIN_LP_RING(4);
 400                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 401                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 402                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 403                 OUT_RING(DR4);
 404                 ADVANCE_LP_RING();
 405         } else {
 406                 BEGIN_LP_RING(6);
 407                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 408                 OUT_RING(DR1);
 409                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 410                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 411                 OUT_RING(DR4);
 412                 OUT_RING(0);
 413                 ADVANCE_LP_RING();
 414         }
 415
 416         return 0;
 417 }
 418
 419 /* XXX: Emitting the counter should really be moved to part of the IRQ
 420  * emit. For now, do it in both places:
 421  */
 422
 423 static void i915_emit_breadcrumb(struct drm_device *dev)
 424 {
 425         drm_i915_private_t *dev_priv = dev->dev_private;
 426         RING_LOCALS;
 427
 428         dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
 429
 430         if (dev_priv->counter > 0x7FFFFFFFUL)
 431                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
 432
 433         BEGIN_LP_RING(4);
 434         OUT_RING(MI_STORE_DWORD_INDEX);
 435         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 436         OUT_RING(dev_priv->counter);
 437         OUT_RING(0);
 438         ADVANCE_LP_RING();
 439 }
 440
 441 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 442                                    drm_i915_cmdbuffer_t * cmd)
 443 {
 444         int nbox = cmd->num_cliprects;
 445         int i = 0, count, ret;
 446
 447         if (cmd->sz & 0x3) {
 448                 DRM_ERROR("alignment");
 449                 return -EINVAL;
 450         }
 451
 452         i915_kernel_lost_context(dev);
 453
 454         count = nbox ? nbox : 1;
 455
 456         for (i = 0; i < count; i++) {
 457                 if (i < nbox) {
 458                         ret = i915_emit_box(dev, cmd->cliprects, i,
 459                                             cmd->DR1, cmd->DR4);
 460                         if (ret)
 461                                 return ret;
 462                 }
 463
 464                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 465                 if (ret)
 466                         return ret;
 467         }
 468
 469         i915_emit_breadcrumb(dev);
 470         return 0;
 471 }
 472
 473 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 474                                      drm_i915_batchbuffer_t * batch)
 475 {
 476         drm_i915_private_t *dev_priv = dev->dev_private;
 477         struct drm_clip_rect __user *boxes = batch->cliprects;
 478         int nbox = batch->num_cliprects;
 479         int i = 0, count;
 480         RING_LOCALS;
 481
 482         if ((batch->start | batch->used) & 0x7) {
 483                 DRM_ERROR("alignment");
 484                 return -EINVAL;
 485         }
 486
 487         i915_kernel_lost_context(dev);
 488
 489         count = nbox ? nbox : 1;
 490
 491         for (i = 0; i < count; i++) {
 492                 if (i < nbox) {
 493                         int ret = i915_emit_box(dev, boxes, i,
 494                                                 batch->DR1, batch->DR4);
 495                         if (ret)
 496                                 return ret;
 497                 }
 498
 499                 if (!IS_I830(dev) && !IS_845G(dev)) {
 500                         BEGIN_LP_RING(2);
 501                         if (IS_I965G(dev)) {
 502                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 503                                 OUT_RING(batch->start);
 504                         } else {
 505                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 506                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 507                         }
 508                         ADVANCE_LP_RING();
 509                 } else {
 510                         BEGIN_LP_RING(4);
 511                         OUT_RING(MI_BATCH_BUFFER);
 512                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 513                         OUT_RING(batch->start + batch->used - 4);
 514                         OUT_RING(0);
 515                         ADVANCE_LP_RING();
 516                 }
 517         }
 518
 519         i915_emit_breadcrumb(dev);
 520
 521         return 0;
 522 }
 523
 524 static int i915_dispatch_flip(struct drm_device * dev)
 525 {
 526         drm_i915_private_t *dev_priv = dev->dev_private;
 527         RING_LOCALS;
 528
 529         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 530                   __func__,
 531                   dev_priv->current_page,
 532                   dev_priv->sarea_priv->pf_current_page);
 533
 534         i915_kernel_lost_context(dev);
 535
 536         BEGIN_LP_RING(2);
 537         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 538         OUT_RING(0);
 539         ADVANCE_LP_RING();
 540
 541         BEGIN_LP_RING(6);
 542         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 543         OUT_RING(0);
 544         if (dev_priv->current_page == 0) {
 545                 OUT_RING(dev_priv->back_offset);
 546                 dev_priv->current_page = 1;
 547         } else {
 548                 OUT_RING(dev_priv->front_offset);
 549                 dev_priv->current_page = 0;
 550         }
 551         OUT_RING(0);
 552         ADVANCE_LP_RING();
 553
 554         BEGIN_LP_RING(2);
 555         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 556         OUT_RING(0);
 557         ADVANCE_LP_RING();
 558
 559         dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 560
 561         BEGIN_LP_RING(4);
 562         OUT_RING(MI_STORE_DWORD_INDEX);
 563         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 564         OUT_RING(dev_priv->counter);
 565         OUT_RING(0);
 566         ADVANCE_LP_RING();
 567
 568         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 569         return 0;
 570 }
 571
 572 static int i915_quiescent(struct drm_device * dev)
 573 {
 574         drm_i915_private_t *dev_priv = dev->dev_private;
 575
 576         i915_kernel_lost_context(dev);
 577         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
 578 }
 579
 580 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 581                             struct drm_file *file_priv)
 582 {
 583         LOCK_TEST_WITH_RETURN(dev, file_priv);
 584
 585         return i915_quiescent(dev);
 586 }
 587
 588 static int i915_batchbuffer(struct drm_device *dev, void *data,
 589                             struct drm_file *file_priv)
 590 {
 591         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 592         u32 *hw_status = dev_priv->hw_status_page;
 593         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 594             dev_priv->sarea_priv;
 595         drm_i915_batchbuffer_t *batch = data;
 596         int ret;
 597
 598         if (!dev_priv->allow_batchbuffer) {
 599                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 600                 return -EINVAL;
 601         }
 602
 603         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 604                   batch->start, batch->used, batch->num_cliprects);
 605
 606         LOCK_TEST_WITH_RETURN(dev, file_priv);
 607
 608         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 609                                                        batch->num_cliprects *
 610                                                        sizeof(struct drm_clip_rect)))
 611                 return -EFAULT;
 612
 613         ret = i915_dispatch_batchbuffer(dev, batch);
 614
 615         sarea_priv->last_dispatch = (int)hw_status[5];
 616         return ret;
 617 }
 618
 619 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 620                           struct drm_file *file_priv)
 621 {
 622         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 623         u32 *hw_status = dev_priv->hw_status_page;
 624         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 625             dev_priv->sarea_priv;
 626         drm_i915_cmdbuffer_t *cmdbuf = data;
 627         int ret;
 628
 629         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 630                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 631
 632         LOCK_TEST_WITH_RETURN(dev, file_priv);
 633
 634         if (cmdbuf->num_cliprects &&
 635             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 636                                 cmdbuf->num_cliprects *
 637                                 sizeof(struct drm_clip_rect))) {
 638                 DRM_ERROR("Fault accessing cliprects\n");
 639                 return -EFAULT;
 640         }
 641
 642         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 643         if (ret) {
 644                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 645                 return ret;
 646         }
 647
 648         sarea_priv->last_dispatch = (int)hw_status[5];
 649         return 0;
 650 }
 651
 652 static int i915_flip_bufs(struct drm_device *dev, void *data,
 653                           struct drm_file *file_priv)
 654 {
 655         DRM_DEBUG("%s\n", __func__);
 656
 657         LOCK_TEST_WITH_RETURN(dev, file_priv);
 658
 659         return i915_dispatch_flip(dev);
 660 }
 661
 662 static int i915_getparam(struct drm_device *dev, void *data,
 663                          struct drm_file *file_priv)
 664 {
 665         drm_i915_private_t *dev_priv = dev->dev_private;
 666         drm_i915_getparam_t *param = data;
 667         int value;
 668
 669         if (!dev_priv) {
 670                 DRM_ERROR("called with no initialization\n");
 671                 return -EINVAL;
 672         }
 673
 674         switch (param->param) {
 675         case I915_PARAM_IRQ_ACTIVE:
 676                 value = dev->irq_enabled;
 677                 break;
 678         case I915_PARAM_ALLOW_BATCHBUFFER:
 679                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 680                 break;
 681         case I915_PARAM_LAST_DISPATCH:
 682                 value = READ_BREADCRUMB(dev_priv);
 683                 break;
 684         default:
 685                 DRM_ERROR("Unknown parameter %d\n", param->param);
 686                 return -EINVAL;
 687         }
 688
 689         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 690                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 691                 return -EFAULT;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int i915_setparam(struct drm_device *dev, void *data,
 698                          struct drm_file *file_priv)
 699 {
 700         drm_i915_private_t *dev_priv = dev->dev_private;
 701         drm_i915_setparam_t *param = data;
 702
 703         if (!dev_priv) {
 704                 DRM_ERROR("called with no initialization\n");
 705                 return -EINVAL;
 706         }
 707
 708         switch (param->param) {
 709         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 710                 break;
 711         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 712                 dev_priv->tex_lru_log_granularity = param->value;
 713                 break;
 714         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 715                 dev_priv->allow_batchbuffer = param->value;
 716                 break;
 717         default:
 718                 DRM_ERROR("unknown parameter %d\n", param->param);
 719                 return -EINVAL;
 720         }
 721
 722         return 0;
 723 }
 724
 725 static int i915_set_status_page(struct drm_device *dev, void *data,
 726                                 struct drm_file *file_priv)
 727 {
 728         drm_i915_private_t *dev_priv = dev->dev_private;
 729         drm_i915_hws_addr_t *hws = data;
 730
 731         if (!I915_NEED_GFX_HWS(dev))
 732                 return -EINVAL;
 733
 734         if (!dev_priv) {
 735                 DRM_ERROR("called with no initialization\n");
 736                 return -EINVAL;
 737         }
 738
 739         printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
 740
 741         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 742
 743         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 744         dev_priv->hws_map.size = 4*1024;
 745         dev_priv->hws_map.type = 0;
 746         dev_priv->hws_map.flags = 0;
 747         dev_priv->hws_map.mtrr = 0;
 748
 749         drm_core_ioremap(&dev_priv->hws_map, dev);
 750         if (dev_priv->hws_map.handle == NULL) {
 751                 i915_dma_cleanup(dev);
 752                 dev_priv->status_gfx_addr = 0;
 753                 DRM_ERROR("can not ioremap virtual address for"
 754                                 " G33 hw status page\n");
 755                 return -ENOMEM;
 756         }
 757         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 758
 759         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 760         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 761         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
 762                         dev_priv->status_gfx_addr);
 763         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 764         return 0;
 765 }
 766
 767 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 768 {
 769         struct drm_i915_private *dev_priv = dev->dev_private;
 770         unsigned long base, size;
 771         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
 772
 773         /* i915 has 4 more counters */
 774         dev->counters += 4;
 775         dev->types[6] = _DRM_STAT_IRQ;
 776         dev->types[7] = _DRM_STAT_PRIMARY;
 777         dev->types[8] = _DRM_STAT_SECONDARY;
 778         dev->types[9] = _DRM_STAT_DMA;
 779
 780         dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
 781         if (dev_priv == NULL)
 782                 return -ENOMEM;
 783
 784         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 785
 786         dev->dev_private = (void *)dev_priv;
 787
 788         /* Add register map (needed for suspend/resume) */
 789         base = drm_get_resource_start(dev, mmio_bar);
 790         size = drm_get_resource_len(dev, mmio_bar);
 791
 792         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
 793                          _DRM_KERNEL | _DRM_DRIVER,
 794                          &dev_priv->mmio_map);
 795
 796         /* Init HWS */
 797         if (!I915_NEED_GFX_HWS(dev)) {
 798                 ret = i915_init_phys_hws(dev);
 799                 if (ret != 0)
 800                         return ret;
 801         }
 802
 803         /* On the 945G/GM, the chipset reports the MSI capability on the
 804          * integrated graphics even though the support isn't actually there
 805          * according to the published specs.  It doesn't appear to function
 806          * correctly in testing on 945G.
 807          * This may be a side effect of MSI having been made available for PEG
 808          * and the registers being closely associated.
 809          */
 810         if (!IS_I945G(dev) && !IS_I945GM(dev))
 811                 pci_enable_msi(dev->pdev);
 812
 813         intel_opregion_init(dev);
 814
 815         spin_lock_init(&dev_priv->user_irq_lock);
 816
 817         return ret;
 818 }
 819
 820 int i915_driver_unload(struct drm_device *dev)
 821 {
 822         struct drm_i915_private *dev_priv = dev->dev_private;
 823
 824         if (dev->pdev->msi_enabled)
 825                 pci_disable_msi(dev->pdev);
 826
 827         i915_free_hws(dev);
 828
 829         if (dev_priv->mmio_map)
 830                 drm_rmmap(dev, dev_priv->mmio_map);
 831
 832         intel_opregion_free(dev);
 833
 834         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 835                  DRM_MEM_DRIVER);
 836
 837         return 0;
 838 }
 839
 840 void i915_driver_lastclose(struct drm_device * dev)
 841 {
 842         drm_i915_private_t *dev_priv = dev->dev_private;
 843
 844         if (!dev_priv)
 845                 return;
 846
 847         if (dev_priv->agp_heap)
 848                 i915_mem_takedown(&(dev_priv->agp_heap));
 849
 850         i915_dma_cleanup(dev);
 851 }
 852
 853 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
 854 {
 855         drm_i915_private_t *dev_priv = dev->dev_private;
 856         i915_mem_release(dev, file_priv, dev_priv->agp_heap);
 857 }
 858
 859 struct drm_ioctl_desc i915_ioctls[] = {
 860         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 861         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
 862         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
 863         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
 864         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
 865         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
 866         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
 867         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 868         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
 869         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
 870         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 871         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
 872         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 873         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 874         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
 875         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
 876         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
 877 };
 878
 879 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 880
 881 /**
 882  * Determine if the device really is AGP or not.
 883  *
 884  * All Intel graphics chipsets are treated as AGP, even if they are really
 885  * PCI-e.
 886  *
 887  * \param dev   The device to be tested.
 888  *
 889  * \returns
 890  * A value of 1 is always retured to indictate every i9x5 is AGP.
 891  */
 892 int i915_driver_device_is_agp(struct drm_device * dev)
 893 {
 894         return 1;
 895 }