drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 /* Really want an OS-independent resettable timer.  Would like to have
  35  * this loop run for (eg) 3 sec, but have the timer reset every time
  36  * the head pointer changes, so that EBUSY only happens if the ring
  37  * actually stalls for (eg) 3 seconds.
  38  */
  39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  40 {
  41         drm_i915_private_t *dev_priv = dev->dev_private;
  42         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  43         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  44         int i;
  45
  46         for (i = 0; i < 10000; i++) {
  47                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  48                 ring->space = ring->head - (ring->tail + 8);
  49                 if (ring->space < 0)
  50                         ring->space += ring->Size;
  51                 if (ring->space >= n)
  52                         return 0;
  53
  54                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  55
  56                 if (ring->head != last_head)
  57                         i = 0;
  58
  59                 last_head = ring->head;
  60         }
  61
  62         return -EBUSY;
  63 }
  64
  65 void i915_kernel_lost_context(struct drm_device * dev)
  66 {
  67         drm_i915_private_t *dev_priv = dev->dev_private;
  68         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  69
  70         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  71         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  72         ring->space = ring->head - (ring->tail + 8);
  73         if (ring->space < 0)
  74                 ring->space += ring->Size;
  75
  76         if (ring->head == ring->tail)
  77                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  78 }
  79
  80 static int i915_dma_cleanup(struct drm_device * dev)
  81 {
  82         drm_i915_private_t *dev_priv = dev->dev_private;
  83         /* Make sure interrupts are disabled here because the uninstall ioctl
  84          * may not have been called from userspace and after dev_private
  85          * is freed, it's too late.
  86          */
  87         if (dev->irq)
  88                 drm_irq_uninstall(dev);
  89
  90         if (dev_priv->ring.virtual_start) {
  91                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
  92                 dev_priv->ring.virtual_start = 0;
  93                 dev_priv->ring.map.handle = 0;
  94                 dev_priv->ring.map.size = 0;
  95         }
  96
  97         if (dev_priv->status_page_dmah) {
  98                 drm_pci_free(dev, dev_priv->status_page_dmah);
  99                 dev_priv->status_page_dmah = NULL;
 100                 /* Need to rewrite hardware status page */
 101                 I915_WRITE(0x02080, 0x1ffff000);
 102         }
 103
 104         if (dev_priv->status_gfx_addr) {
 105                 dev_priv->status_gfx_addr = 0;
 106                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 107                 I915_WRITE(0x2080, 0x1ffff000);
 108         }
 109
 110         return 0;
 111 }
 112
 113 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 114 {
 115         drm_i915_private_t *dev_priv = dev->dev_private;
 116
 117         dev_priv->sarea = drm_getsarea(dev);
 118         if (!dev_priv->sarea) {
 119                 DRM_ERROR("can not find sarea!\n");
 120                 i915_dma_cleanup(dev);
 121                 return -EINVAL;
 122         }
 123
 124         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 125         if (!dev_priv->mmio_map) {
 126                 i915_dma_cleanup(dev);
 127                 DRM_ERROR("can not find mmio map!\n");
 128                 return -EINVAL;
 129         }
 130
 131         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 132             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 133
 134         dev_priv->ring.Start = init->ring_start;
 135         dev_priv->ring.End = init->ring_end;
 136         dev_priv->ring.Size = init->ring_size;
 137         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 138
 139         dev_priv->ring.map.offset = init->ring_start;
 140         dev_priv->ring.map.size = init->ring_size;
 141         dev_priv->ring.map.type = 0;
 142         dev_priv->ring.map.flags = 0;
 143         dev_priv->ring.map.mtrr = 0;
 144
 145         drm_core_ioremap(&dev_priv->ring.map, dev);
 146
 147         if (dev_priv->ring.map.handle == NULL) {
 148                 i915_dma_cleanup(dev);
 149                 DRM_ERROR("can not ioremap virtual address for"
 150                           " ring buffer\n");
 151                 return -ENOMEM;
 152         }
 153
 154         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 155
 156         dev_priv->cpp = init->cpp;
 157         dev_priv->back_offset = init->back_offset;
 158         dev_priv->front_offset = init->front_offset;
 159         dev_priv->current_page = 0;
 160         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 161
 162         /* Allow hardware batchbuffers unless told otherwise.
 163          */
 164         dev_priv->allow_batchbuffer = 1;
 165
 166         /* Program Hardware Status Page */
 167         if (!I915_NEED_GFX_HWS(dev)) {
 168                 dev_priv->status_page_dmah =
 169                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 170
 171                 if (!dev_priv->status_page_dmah) {
 172                         i915_dma_cleanup(dev);
 173                         DRM_ERROR("Can not allocate hardware status page\n");
 174                         return -ENOMEM;
 175                 }
 176                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 177                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 178
 179                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 180                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 181         }
 182         DRM_DEBUG("Enabled hardware status page\n");
 183         return 0;
 184 }
 185
 186 static int i915_dma_resume(struct drm_device * dev)
 187 {
 188         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 189
 190         DRM_DEBUG("%s\n", __func__);
 191
 192         if (!dev_priv->sarea) {
 193                 DRM_ERROR("can not find sarea!\n");
 194                 return -EINVAL;
 195         }
 196
 197         if (!dev_priv->mmio_map) {
 198                 DRM_ERROR("can not find mmio map!\n");
 199                 return -EINVAL;
 200         }
 201
 202         if (dev_priv->ring.map.handle == NULL) {
 203                 DRM_ERROR("can not ioremap virtual address for"
 204                           " ring buffer\n");
 205                 return -ENOMEM;
 206         }
 207
 208         /* Program Hardware Status Page */
 209         if (!dev_priv->hw_status_page) {
 210                 DRM_ERROR("Can not find hardware status page\n");
 211                 return -EINVAL;
 212         }
 213         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 214
 215         if (dev_priv->status_gfx_addr != 0)
 216                 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 217         else
 218                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 219         DRM_DEBUG("Enabled hardware status page\n");
 220
 221         return 0;
 222 }
 223
 224 static int i915_dma_init(struct drm_device *dev, void *data,
 225                          struct drm_file *file_priv)
 226 {
 227         drm_i915_init_t *init = data;
 228         int retcode = 0;
 229
 230         switch (init->func) {
 231         case I915_INIT_DMA:
 232                 retcode = i915_initialize(dev, init);
 233                 break;
 234         case I915_CLEANUP_DMA:
 235                 retcode = i915_dma_cleanup(dev);
 236                 break;
 237         case I915_RESUME_DMA:
 238                 retcode = i915_dma_resume(dev);
 239                 break;
 240         default:
 241                 retcode = -EINVAL;
 242                 break;
 243         }
 244
 245         return retcode;
 246 }
 247
 248 /* Implement basically the same security restrictions as hardware does
 249  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 250  *
 251  * Most of the calculations below involve calculating the size of a
 252  * particular instruction.  It's important to get the size right as
 253  * that tells us where the next instruction to check is.  Any illegal
 254  * instruction detected will be given a size of zero, which is a
 255  * signal to abort the rest of the buffer.
 256  */
 257 static int do_validate_cmd(int cmd)
 258 {
 259         switch (((cmd >> 29) & 0x7)) {
 260         case 0x0:
 261                 switch ((cmd >> 23) & 0x3f) {
 262                 case 0x0:
 263                         return 1;       /* MI_NOOP */
 264                 case 0x4:
 265                         return 1;       /* MI_FLUSH */
 266                 default:
 267                         return 0;       /* disallow everything else */
 268                 }
 269                 break;
 270         case 0x1:
 271                 return 0;       /* reserved */
 272         case 0x2:
 273                 return (cmd & 0xff) + 2;        /* 2d commands */
 274         case 0x3:
 275                 if (((cmd >> 24) & 0x1f) <= 0x18)
 276                         return 1;
 277
 278                 switch ((cmd >> 24) & 0x1f) {
 279                 case 0x1c:
 280                         return 1;
 281                 case 0x1d:
 282                         switch ((cmd >> 16) & 0xff) {
 283                         case 0x3:
 284                                 return (cmd & 0x1f) + 2;
 285                         case 0x4:
 286                                 return (cmd & 0xf) + 2;
 287                         default:
 288                                 return (cmd & 0xffff) + 2;
 289                         }
 290                 case 0x1e:
 291                         if (cmd & (1 << 23))
 292                                 return (cmd & 0xffff) + 1;
 293                         else
 294                                 return 1;
 295                 case 0x1f:
 296                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 297                                 return (cmd & 0x1ffff) + 2;
 298                         else if (cmd & (1 << 17))       /* indirect random */
 299                                 if ((cmd & 0xffff) == 0)
 300                                         return 0;       /* unknown length, too hard */
 301                                 else
 302                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 303                         else
 304                                 return 2;       /* indirect sequential */
 305                 default:
 306                         return 0;
 307                 }
 308         default:
 309                 return 0;
 310         }
 311
 312         return 0;
 313 }
 314
 315 static int validate_cmd(int cmd)
 316 {
 317         int ret = do_validate_cmd(cmd);
 318
 319 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 320
 321         return ret;
 322 }
 323
 324 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords)
 325 {
 326         drm_i915_private_t *dev_priv = dev->dev_private;
 327         int i;
 328         RING_LOCALS;
 329
 330         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 331                 return -EINVAL;
 332
 333         BEGIN_LP_RING((dwords+1)&~1);
 334
 335         for (i = 0; i < dwords;) {
 336                 int cmd, sz;
 337
 338                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 339                         return -EINVAL;
 340
 341                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 342                         return -EINVAL;
 343
 344                 OUT_RING(cmd);
 345
 346                 while (++i, --sz) {
 347                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 348                                                          sizeof(cmd))) {
 349                                 return -EINVAL;
 350                         }
 351                         OUT_RING(cmd);
 352                 }
 353         }
 354
 355         if (dwords & 1)
 356                 OUT_RING(0);
 357
 358         ADVANCE_LP_RING();
 359
 360         return 0;
 361 }
 362
 363 static int i915_emit_box(struct drm_device * dev,
 364                          struct drm_clip_rect __user * boxes,
 365                          int i, int DR1, int DR4)
 366 {
 367         drm_i915_private_t *dev_priv = dev->dev_private;
 368         struct drm_clip_rect box;
 369         RING_LOCALS;
 370
 371         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 372                 return -EFAULT;
 373         }
 374
 375         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 376                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 377                           box.x1, box.y1, box.x2, box.y2);
 378                 return -EINVAL;
 379         }
 380
 381         if (IS_I965G(dev)) {
 382                 BEGIN_LP_RING(4);
 383                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 384                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 385                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 386                 OUT_RING(DR4);
 387                 ADVANCE_LP_RING();
 388         } else {
 389                 BEGIN_LP_RING(6);
 390                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 391                 OUT_RING(DR1);
 392                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 393                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 394                 OUT_RING(DR4);
 395                 OUT_RING(0);
 396                 ADVANCE_LP_RING();
 397         }
 398
 399         return 0;
 400 }
 401
 402 /* XXX: Emitting the counter should really be moved to part of the IRQ
 403  * emit. For now, do it in both places:
 404  */
 405
 406 static void i915_emit_breadcrumb(struct drm_device *dev)
 407 {
 408         drm_i915_private_t *dev_priv = dev->dev_private;
 409         RING_LOCALS;
 410
 411         dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
 412
 413         if (dev_priv->counter > 0x7FFFFFFFUL)
 414                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
 415
 416         BEGIN_LP_RING(4);
 417         OUT_RING(CMD_STORE_DWORD_IDX);
 418         OUT_RING(20);
 419         OUT_RING(dev_priv->counter);
 420         OUT_RING(0);
 421         ADVANCE_LP_RING();
 422 }
 423
 424 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 425                                    drm_i915_cmdbuffer_t * cmd)
 426 {
 427         int nbox = cmd->num_cliprects;
 428         int i = 0, count, ret;
 429
 430         if (cmd->sz & 0x3) {
 431                 DRM_ERROR("alignment");
 432                 return -EINVAL;
 433         }
 434
 435         i915_kernel_lost_context(dev);
 436
 437         count = nbox ? nbox : 1;
 438
 439         for (i = 0; i < count; i++) {
 440                 if (i < nbox) {
 441                         ret = i915_emit_box(dev, cmd->cliprects, i,
 442                                             cmd->DR1, cmd->DR4);
 443                         if (ret)
 444                                 return ret;
 445                 }
 446
 447                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 448                 if (ret)
 449                         return ret;
 450         }
 451
 452         i915_emit_breadcrumb(dev);
 453         return 0;
 454 }
 455
 456 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 457                                      drm_i915_batchbuffer_t * batch)
 458 {
 459         drm_i915_private_t *dev_priv = dev->dev_private;
 460         struct drm_clip_rect __user *boxes = batch->cliprects;
 461         int nbox = batch->num_cliprects;
 462         int i = 0, count;
 463         RING_LOCALS;
 464
 465         if ((batch->start | batch->used) & 0x7) {
 466                 DRM_ERROR("alignment");
 467                 return -EINVAL;
 468         }
 469
 470         i915_kernel_lost_context(dev);
 471
 472         count = nbox ? nbox : 1;
 473
 474         for (i = 0; i < count; i++) {
 475                 if (i < nbox) {
 476                         int ret = i915_emit_box(dev, boxes, i,
 477                                                 batch->DR1, batch->DR4);
 478                         if (ret)
 479                                 return ret;
 480                 }
 481
 482                 if (!IS_I830(dev) && !IS_845G(dev)) {
 483                         BEGIN_LP_RING(2);
 484                         if (IS_I965G(dev)) {
 485                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 486                                 OUT_RING(batch->start);
 487                         } else {
 488                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 489                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 490                         }
 491                         ADVANCE_LP_RING();
 492                 } else {
 493                         BEGIN_LP_RING(4);
 494                         OUT_RING(MI_BATCH_BUFFER);
 495                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 496                         OUT_RING(batch->start + batch->used - 4);
 497                         OUT_RING(0);
 498                         ADVANCE_LP_RING();
 499                 }
 500         }
 501
 502         i915_emit_breadcrumb(dev);
 503
 504         return 0;
 505 }
 506
 507 static int i915_dispatch_flip(struct drm_device * dev)
 508 {
 509         drm_i915_private_t *dev_priv = dev->dev_private;
 510         RING_LOCALS;
 511
 512         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 513                   __func__,
 514                   dev_priv->current_page,
 515                   dev_priv->sarea_priv->pf_current_page);
 516
 517         i915_kernel_lost_context(dev);
 518
 519         BEGIN_LP_RING(2);
 520         OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
 521         OUT_RING(0);
 522         ADVANCE_LP_RING();
 523
 524         BEGIN_LP_RING(6);
 525         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 526         OUT_RING(0);
 527         if (dev_priv->current_page == 0) {
 528                 OUT_RING(dev_priv->back_offset);
 529                 dev_priv->current_page = 1;
 530         } else {
 531                 OUT_RING(dev_priv->front_offset);
 532                 dev_priv->current_page = 0;
 533         }
 534         OUT_RING(0);
 535         ADVANCE_LP_RING();
 536
 537         BEGIN_LP_RING(2);
 538         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 539         OUT_RING(0);
 540         ADVANCE_LP_RING();
 541
 542         dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 543
 544         BEGIN_LP_RING(4);
 545         OUT_RING(CMD_STORE_DWORD_IDX);
 546         OUT_RING(20);
 547         OUT_RING(dev_priv->counter);
 548         OUT_RING(0);
 549         ADVANCE_LP_RING();
 550
 551         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 552         return 0;
 553 }
 554
 555 static int i915_quiescent(struct drm_device * dev)
 556 {
 557         drm_i915_private_t *dev_priv = dev->dev_private;
 558
 559         i915_kernel_lost_context(dev);
 560         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
 561 }
 562
 563 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 564                             struct drm_file *file_priv)
 565 {
 566         LOCK_TEST_WITH_RETURN(dev, file_priv);
 567
 568         return i915_quiescent(dev);
 569 }
 570
 571 static int i915_batchbuffer(struct drm_device *dev, void *data,
 572                             struct drm_file *file_priv)
 573 {
 574         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 575         u32 *hw_status = dev_priv->hw_status_page;
 576         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 577             dev_priv->sarea_priv;
 578         drm_i915_batchbuffer_t *batch = data;
 579         int ret;
 580
 581         if (!dev_priv->allow_batchbuffer) {
 582                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 583                 return -EINVAL;
 584         }
 585
 586         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 587                   batch->start, batch->used, batch->num_cliprects);
 588
 589         LOCK_TEST_WITH_RETURN(dev, file_priv);
 590
 591         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 592                                                        batch->num_cliprects *
 593                                                        sizeof(struct drm_clip_rect)))
 594                 return -EFAULT;
 595
 596         ret = i915_dispatch_batchbuffer(dev, batch);
 597
 598         sarea_priv->last_dispatch = (int)hw_status[5];
 599         return ret;
 600 }
 601
 602 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 603                           struct drm_file *file_priv)
 604 {
 605         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 606         u32 *hw_status = dev_priv->hw_status_page;
 607         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 608             dev_priv->sarea_priv;
 609         drm_i915_cmdbuffer_t *cmdbuf = data;
 610         int ret;
 611
 612         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 613                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 614
 615         LOCK_TEST_WITH_RETURN(dev, file_priv);
 616
 617         if (cmdbuf->num_cliprects &&
 618             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 619                                 cmdbuf->num_cliprects *
 620                                 sizeof(struct drm_clip_rect))) {
 621                 DRM_ERROR("Fault accessing cliprects\n");
 622                 return -EFAULT;
 623         }
 624
 625         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 626         if (ret) {
 627                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 628                 return ret;
 629         }
 630
 631         sarea_priv->last_dispatch = (int)hw_status[5];
 632         return 0;
 633 }
 634
 635 static int i915_flip_bufs(struct drm_device *dev, void *data,
 636                           struct drm_file *file_priv)
 637 {
 638         DRM_DEBUG("%s\n", __func__);
 639
 640         LOCK_TEST_WITH_RETURN(dev, file_priv);
 641
 642         return i915_dispatch_flip(dev);
 643 }
 644
 645 static int i915_getparam(struct drm_device *dev, void *data,
 646                          struct drm_file *file_priv)
 647 {
 648         drm_i915_private_t *dev_priv = dev->dev_private;
 649         drm_i915_getparam_t *param = data;
 650         int value;
 651
 652         if (!dev_priv) {
 653                 DRM_ERROR("called with no initialization\n");
 654                 return -EINVAL;
 655         }
 656
 657         switch (param->param) {
 658         case I915_PARAM_IRQ_ACTIVE:
 659                 value = dev->irq ? 1 : 0;
 660                 break;
 661         case I915_PARAM_ALLOW_BATCHBUFFER:
 662                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 663                 break;
 664         case I915_PARAM_LAST_DISPATCH:
 665                 value = READ_BREADCRUMB(dev_priv);
 666                 break;
 667         default:
 668                 DRM_ERROR("Unknown parameter %d\n", param->param);
 669                 return -EINVAL;
 670         }
 671
 672         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 673                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 674                 return -EFAULT;
 675         }
 676
 677         return 0;
 678 }
 679
 680 static int i915_setparam(struct drm_device *dev, void *data,
 681                          struct drm_file *file_priv)
 682 {
 683         drm_i915_private_t *dev_priv = dev->dev_private;
 684         drm_i915_setparam_t *param = data;
 685
 686         if (!dev_priv) {
 687                 DRM_ERROR("called with no initialization\n");
 688                 return -EINVAL;
 689         }
 690
 691         switch (param->param) {
 692         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 693                 break;
 694         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 695                 dev_priv->tex_lru_log_granularity = param->value;
 696                 break;
 697         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 698                 dev_priv->allow_batchbuffer = param->value;
 699                 break;
 700         default:
 701                 DRM_ERROR("unknown parameter %d\n", param->param);
 702                 return -EINVAL;
 703         }
 704
 705         return 0;
 706 }
 707
 708 static int i915_set_status_page(struct drm_device *dev, void *data,
 709                                 struct drm_file *file_priv)
 710 {
 711         drm_i915_private_t *dev_priv = dev->dev_private;
 712         drm_i915_hws_addr_t *hws = data;
 713
 714         if (!I915_NEED_GFX_HWS(dev))
 715                 return -EINVAL;
 716
 717         if (!dev_priv) {
 718                 DRM_ERROR("called with no initialization\n");
 719                 return -EINVAL;
 720         }
 721
 722         printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
 723
 724         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 725
 726         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 727         dev_priv->hws_map.size = 4*1024;
 728         dev_priv->hws_map.type = 0;
 729         dev_priv->hws_map.flags = 0;
 730         dev_priv->hws_map.mtrr = 0;
 731
 732         drm_core_ioremap(&dev_priv->hws_map, dev);
 733         if (dev_priv->hws_map.handle == NULL) {
 734                 i915_dma_cleanup(dev);
 735                 dev_priv->status_gfx_addr = 0;
 736                 DRM_ERROR("can not ioremap virtual address for"
 737                                 " G33 hw status page\n");
 738                 return -ENOMEM;
 739         }
 740         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 741
 742         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 743         I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 744         DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
 745                         dev_priv->status_gfx_addr);
 746         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 747         return 0;
 748 }
 749
 750 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 751 {
 752         struct drm_i915_private *dev_priv = dev->dev_private;
 753         unsigned long base, size;
 754         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
 755
 756         /* i915 has 4 more counters */
 757         dev->counters += 4;
 758         dev->types[6] = _DRM_STAT_IRQ;
 759         dev->types[7] = _DRM_STAT_PRIMARY;
 760         dev->types[8] = _DRM_STAT_SECONDARY;
 761         dev->types[9] = _DRM_STAT_DMA;
 762
 763         dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
 764         if (dev_priv == NULL)
 765                 return -ENOMEM;
 766
 767         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 768
 769         dev->dev_private = (void *)dev_priv;
 770
 771         /* Add register map (needed for suspend/resume) */
 772         base = drm_get_resource_start(dev, mmio_bar);
 773         size = drm_get_resource_len(dev, mmio_bar);
 774
 775         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
 776                          _DRM_KERNEL | _DRM_DRIVER,
 777                          &dev_priv->mmio_map);
 778         return ret;
 779 }
 780
 781 int i915_driver_unload(struct drm_device *dev)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784
 785         if (dev_priv->mmio_map)
 786                 drm_rmmap(dev, dev_priv->mmio_map);
 787
 788         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 789                  DRM_MEM_DRIVER);
 790
 791         return 0;
 792 }
 793
 794 void i915_driver_lastclose(struct drm_device * dev)
 795 {
 796         drm_i915_private_t *dev_priv = dev->dev_private;
 797
 798         if (!dev_priv)
 799                 return;
 800
 801         if (dev_priv->agp_heap)
 802                 i915_mem_takedown(&(dev_priv->agp_heap));
 803
 804         i915_dma_cleanup(dev);
 805 }
 806
 807 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
 808 {
 809         drm_i915_private_t *dev_priv = dev->dev_private;
 810         i915_mem_release(dev, file_priv, dev_priv->agp_heap);
 811 }
 812
 813 struct drm_ioctl_desc i915_ioctls[] = {
 814         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 815         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
 816         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
 817         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
 818         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
 819         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
 820         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
 821         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 822         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
 823         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
 824         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 825         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
 826         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 827         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 828         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
 829         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
 830         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
 831 };
 832
 833 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 834
 835 /**
 836  * Determine if the device really is AGP or not.
 837  *
 838  * All Intel graphics chipsets are treated as AGP, even if they are really
 839  * PCI-e.
 840  *
 841  * \param dev   The device to be tested.
 842  *
 843  * \returns
 844  * A value of 1 is always retured to indictate every i9x5 is AGP.
 845  */
 846 int i915_driver_device_is_agp(struct drm_device * dev)
 847 {
 848         return 1;
 849 }