drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 /* Really want an OS-independent resettable timer.  Would like to have
  35  * this loop run for (eg) 3 sec, but have the timer reset every time
  36  * the head pointer changes, so that EBUSY only happens if the ring
  37  * actually stalls for (eg) 3 seconds.
  38  */
  39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  40 {
  41         drm_i915_private_t *dev_priv = dev->dev_private;
  42         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  43         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
  44         u32 last_acthd = I915_READ(acthd_reg);
  45         u32 acthd;
  46         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  47         int i;
  48
  49         for (i = 0; i < 100000; i++) {
  50                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  51                 acthd = I915_READ(acthd_reg);
  52                 ring->space = ring->head - (ring->tail + 8);
  53                 if (ring->space < 0)
  54                         ring->space += ring->Size;
  55                 if (ring->space >= n)
  56                         return 0;
  57
  58                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  59
  60                 if (ring->head != last_head)
  61                         i = 0;
  62                 if (acthd != last_acthd)
  63                         i = 0;
  64
  65                 last_head = ring->head;
  66                 last_acthd = acthd;
  67                 msleep_interruptible(10);
  68
  69         }
  70
  71         return -EBUSY;
  72 }
  73
  74 void i915_kernel_lost_context(struct drm_device * dev)
  75 {
  76         drm_i915_private_t *dev_priv = dev->dev_private;
  77         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  78
  79         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  80         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  81         ring->space = ring->head - (ring->tail + 8);
  82         if (ring->space < 0)
  83                 ring->space += ring->Size;
  84
  85         if (ring->head == ring->tail)
  86                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  87 }
  88
  89 static int i915_dma_cleanup(struct drm_device * dev)
  90 {
  91         drm_i915_private_t *dev_priv = dev->dev_private;
  92         /* Make sure interrupts are disabled here because the uninstall ioctl
  93          * may not have been called from userspace and after dev_private
  94          * is freed, it's too late.
  95          */
  96         if (dev->irq_enabled)
  97                 drm_irq_uninstall(dev);
  98
  99         if (dev_priv->ring.virtual_start) {
 100                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 101                 dev_priv->ring.virtual_start = 0;
 102                 dev_priv->ring.map.handle = 0;
 103                 dev_priv->ring.map.size = 0;
 104         }
 105
 106         if (dev_priv->status_page_dmah) {
 107                 drm_pci_free(dev, dev_priv->status_page_dmah);
 108                 dev_priv->status_page_dmah = NULL;
 109                 /* Need to rewrite hardware status page */
 110                 I915_WRITE(HWS_PGA, 0x1ffff000);
 111         }
 112
 113         if (dev_priv->status_gfx_addr) {
 114                 dev_priv->status_gfx_addr = 0;
 115                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 116                 I915_WRITE(HWS_PGA, 0x1ffff000);
 117         }
 118
 119         return 0;
 120 }
 121
 122 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 123 {
 124         drm_i915_private_t *dev_priv = dev->dev_private;
 125
 126         dev_priv->sarea = drm_getsarea(dev);
 127         if (!dev_priv->sarea) {
 128                 DRM_ERROR("can not find sarea!\n");
 129                 i915_dma_cleanup(dev);
 130                 return -EINVAL;
 131         }
 132
 133         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 134             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 135
 136         dev_priv->ring.Start = init->ring_start;
 137         dev_priv->ring.End = init->ring_end;
 138         dev_priv->ring.Size = init->ring_size;
 139         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 140
 141         dev_priv->ring.map.offset = init->ring_start;
 142         dev_priv->ring.map.size = init->ring_size;
 143         dev_priv->ring.map.type = 0;
 144         dev_priv->ring.map.flags = 0;
 145         dev_priv->ring.map.mtrr = 0;
 146
 147         drm_core_ioremap(&dev_priv->ring.map, dev);
 148
 149         if (dev_priv->ring.map.handle == NULL) {
 150                 i915_dma_cleanup(dev);
 151                 DRM_ERROR("can not ioremap virtual address for"
 152                           " ring buffer\n");
 153                 return -ENOMEM;
 154         }
 155
 156         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 157
 158         dev_priv->cpp = init->cpp;
 159         dev_priv->back_offset = init->back_offset;
 160         dev_priv->front_offset = init->front_offset;
 161         dev_priv->current_page = 0;
 162         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 163
 164         /* Allow hardware batchbuffers unless told otherwise.
 165          */
 166         dev_priv->allow_batchbuffer = 1;
 167
 168         /* Program Hardware Status Page */
 169         if (!I915_NEED_GFX_HWS(dev)) {
 170                 dev_priv->status_page_dmah =
 171                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 172
 173                 if (!dev_priv->status_page_dmah) {
 174                         i915_dma_cleanup(dev);
 175                         DRM_ERROR("Can not allocate hardware status page\n");
 176                         return -ENOMEM;
 177                 }
 178                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 179                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 180
 181                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 182                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 183         }
 184         DRM_DEBUG("Enabled hardware status page\n");
 185         return 0;
 186 }
 187
 188 static int i915_dma_resume(struct drm_device * dev)
 189 {
 190         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 191
 192         DRM_DEBUG("%s\n", __func__);
 193
 194         if (!dev_priv->sarea) {
 195                 DRM_ERROR("can not find sarea!\n");
 196                 return -EINVAL;
 197         }
 198
 199         if (dev_priv->ring.map.handle == NULL) {
 200                 DRM_ERROR("can not ioremap virtual address for"
 201                           " ring buffer\n");
 202                 return -ENOMEM;
 203         }
 204
 205         /* Program Hardware Status Page */
 206         if (!dev_priv->hw_status_page) {
 207                 DRM_ERROR("Can not find hardware status page\n");
 208                 return -EINVAL;
 209         }
 210         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 211
 212         if (dev_priv->status_gfx_addr != 0)
 213                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 214         else
 215                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 216         DRM_DEBUG("Enabled hardware status page\n");
 217
 218         return 0;
 219 }
 220
 221 static int i915_dma_init(struct drm_device *dev, void *data,
 222                          struct drm_file *file_priv)
 223 {
 224         drm_i915_init_t *init = data;
 225         int retcode = 0;
 226
 227         switch (init->func) {
 228         case I915_INIT_DMA:
 229                 retcode = i915_initialize(dev, init);
 230                 break;
 231         case I915_CLEANUP_DMA:
 232                 retcode = i915_dma_cleanup(dev);
 233                 break;
 234         case I915_RESUME_DMA:
 235                 retcode = i915_dma_resume(dev);
 236                 break;
 237         default:
 238                 retcode = -EINVAL;
 239                 break;
 240         }
 241
 242         return retcode;
 243 }
 244
 245 /* Implement basically the same security restrictions as hardware does
 246  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 247  *
 248  * Most of the calculations below involve calculating the size of a
 249  * particular instruction.  It's important to get the size right as
 250  * that tells us where the next instruction to check is.  Any illegal
 251  * instruction detected will be given a size of zero, which is a
 252  * signal to abort the rest of the buffer.
 253  */
 254 static int do_validate_cmd(int cmd)
 255 {
 256         switch (((cmd >> 29) & 0x7)) {
 257         case 0x0:
 258                 switch ((cmd >> 23) & 0x3f) {
 259                 case 0x0:
 260                         return 1;       /* MI_NOOP */
 261                 case 0x4:
 262                         return 1;       /* MI_FLUSH */
 263                 default:
 264                         return 0;       /* disallow everything else */
 265                 }
 266                 break;
 267         case 0x1:
 268                 return 0;       /* reserved */
 269         case 0x2:
 270                 return (cmd & 0xff) + 2;        /* 2d commands */
 271         case 0x3:
 272                 if (((cmd >> 24) & 0x1f) <= 0x18)
 273                         return 1;
 274
 275                 switch ((cmd >> 24) & 0x1f) {
 276                 case 0x1c:
 277                         return 1;
 278                 case 0x1d:
 279                         switch ((cmd >> 16) & 0xff) {
 280                         case 0x3:
 281                                 return (cmd & 0x1f) + 2;
 282                         case 0x4:
 283                                 return (cmd & 0xf) + 2;
 284                         default:
 285                                 return (cmd & 0xffff) + 2;
 286                         }
 287                 case 0x1e:
 288                         if (cmd & (1 << 23))
 289                                 return (cmd & 0xffff) + 1;
 290                         else
 291                                 return 1;
 292                 case 0x1f:
 293                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 294                                 return (cmd & 0x1ffff) + 2;
 295                         else if (cmd & (1 << 17))       /* indirect random */
 296                                 if ((cmd & 0xffff) == 0)
 297                                         return 0;       /* unknown length, too hard */
 298                                 else
 299                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 300                         else
 301                                 return 2;       /* indirect sequential */
 302                 default:
 303                         return 0;
 304                 }
 305         default:
 306                 return 0;
 307         }
 308
 309         return 0;
 310 }
 311
 312 static int validate_cmd(int cmd)
 313 {
 314         int ret = do_validate_cmd(cmd);
 315
 316 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 317
 318         return ret;
 319 }
 320
 321 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords)
 322 {
 323         drm_i915_private_t *dev_priv = dev->dev_private;
 324         int i;
 325         RING_LOCALS;
 326
 327         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 328                 return -EINVAL;
 329
 330         BEGIN_LP_RING((dwords+1)&~1);
 331
 332         for (i = 0; i < dwords;) {
 333                 int cmd, sz;
 334
 335                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 336                         return -EINVAL;
 337
 338                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 339                         return -EINVAL;
 340
 341                 OUT_RING(cmd);
 342
 343                 while (++i, --sz) {
 344                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 345                                                          sizeof(cmd))) {
 346                                 return -EINVAL;
 347                         }
 348                         OUT_RING(cmd);
 349                 }
 350         }
 351
 352         if (dwords & 1)
 353                 OUT_RING(0);
 354
 355         ADVANCE_LP_RING();
 356
 357         return 0;
 358 }
 359
 360 static int i915_emit_box(struct drm_device * dev,
 361                          struct drm_clip_rect __user * boxes,
 362                          int i, int DR1, int DR4)
 363 {
 364         drm_i915_private_t *dev_priv = dev->dev_private;
 365         struct drm_clip_rect box;
 366         RING_LOCALS;
 367
 368         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 369                 return -EFAULT;
 370         }
 371
 372         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 373                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 374                           box.x1, box.y1, box.x2, box.y2);
 375                 return -EINVAL;
 376         }
 377
 378         if (IS_I965G(dev)) {
 379                 BEGIN_LP_RING(4);
 380                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 381                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 382                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 383                 OUT_RING(DR4);
 384                 ADVANCE_LP_RING();
 385         } else {
 386                 BEGIN_LP_RING(6);
 387                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 388                 OUT_RING(DR1);
 389                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 390                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 391                 OUT_RING(DR4);
 392                 OUT_RING(0);
 393                 ADVANCE_LP_RING();
 394         }
 395
 396         return 0;
 397 }
 398
 399 /* XXX: Emitting the counter should really be moved to part of the IRQ
 400  * emit. For now, do it in both places:
 401  */
 402
 403 static void i915_emit_breadcrumb(struct drm_device *dev)
 404 {
 405         drm_i915_private_t *dev_priv = dev->dev_private;
 406         RING_LOCALS;
 407
 408         dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
 409
 410         if (dev_priv->counter > 0x7FFFFFFFUL)
 411                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
 412
 413         BEGIN_LP_RING(4);
 414         OUT_RING(MI_STORE_DWORD_INDEX);
 415         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 416         OUT_RING(dev_priv->counter);
 417         OUT_RING(0);
 418         ADVANCE_LP_RING();
 419 }
 420
 421 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 422                                    drm_i915_cmdbuffer_t * cmd)
 423 {
 424         int nbox = cmd->num_cliprects;
 425         int i = 0, count, ret;
 426
 427         if (cmd->sz & 0x3) {
 428                 DRM_ERROR("alignment");
 429                 return -EINVAL;
 430         }
 431
 432         i915_kernel_lost_context(dev);
 433
 434         count = nbox ? nbox : 1;
 435
 436         for (i = 0; i < count; i++) {
 437                 if (i < nbox) {
 438                         ret = i915_emit_box(dev, cmd->cliprects, i,
 439                                             cmd->DR1, cmd->DR4);
 440                         if (ret)
 441                                 return ret;
 442                 }
 443
 444                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 445                 if (ret)
 446                         return ret;
 447         }
 448
 449         i915_emit_breadcrumb(dev);
 450         return 0;
 451 }
 452
 453 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 454                                      drm_i915_batchbuffer_t * batch)
 455 {
 456         drm_i915_private_t *dev_priv = dev->dev_private;
 457         struct drm_clip_rect __user *boxes = batch->cliprects;
 458         int nbox = batch->num_cliprects;
 459         int i = 0, count;
 460         RING_LOCALS;
 461
 462         if ((batch->start | batch->used) & 0x7) {
 463                 DRM_ERROR("alignment");
 464                 return -EINVAL;
 465         }
 466
 467         i915_kernel_lost_context(dev);
 468
 469         count = nbox ? nbox : 1;
 470
 471         for (i = 0; i < count; i++) {
 472                 if (i < nbox) {
 473                         int ret = i915_emit_box(dev, boxes, i,
 474                                                 batch->DR1, batch->DR4);
 475                         if (ret)
 476                                 return ret;
 477                 }
 478
 479                 if (!IS_I830(dev) && !IS_845G(dev)) {
 480                         BEGIN_LP_RING(2);
 481                         if (IS_I965G(dev)) {
 482                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 483                                 OUT_RING(batch->start);
 484                         } else {
 485                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 486                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 487                         }
 488                         ADVANCE_LP_RING();
 489                 } else {
 490                         BEGIN_LP_RING(4);
 491                         OUT_RING(MI_BATCH_BUFFER);
 492                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 493                         OUT_RING(batch->start + batch->used - 4);
 494                         OUT_RING(0);
 495                         ADVANCE_LP_RING();
 496                 }
 497         }
 498
 499         i915_emit_breadcrumb(dev);
 500
 501         return 0;
 502 }
 503
 504 static int i915_dispatch_flip(struct drm_device * dev)
 505 {
 506         drm_i915_private_t *dev_priv = dev->dev_private;
 507         RING_LOCALS;
 508
 509         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 510                   __func__,
 511                   dev_priv->current_page,
 512                   dev_priv->sarea_priv->pf_current_page);
 513
 514         i915_kernel_lost_context(dev);
 515
 516         BEGIN_LP_RING(2);
 517         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 518         OUT_RING(0);
 519         ADVANCE_LP_RING();
 520
 521         BEGIN_LP_RING(6);
 522         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 523         OUT_RING(0);
 524         if (dev_priv->current_page == 0) {
 525                 OUT_RING(dev_priv->back_offset);
 526                 dev_priv->current_page = 1;
 527         } else {
 528                 OUT_RING(dev_priv->front_offset);
 529                 dev_priv->current_page = 0;
 530         }
 531         OUT_RING(0);
 532         ADVANCE_LP_RING();
 533
 534         BEGIN_LP_RING(2);
 535         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 536         OUT_RING(0);
 537         ADVANCE_LP_RING();
 538
 539         dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 540
 541         BEGIN_LP_RING(4);
 542         OUT_RING(MI_STORE_DWORD_INDEX);
 543         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 544         OUT_RING(dev_priv->counter);
 545         OUT_RING(0);
 546         ADVANCE_LP_RING();
 547
 548         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 549         return 0;
 550 }
 551
 552 static int i915_quiescent(struct drm_device * dev)
 553 {
 554         drm_i915_private_t *dev_priv = dev->dev_private;
 555
 556         i915_kernel_lost_context(dev);
 557         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
 558 }
 559
 560 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 561                             struct drm_file *file_priv)
 562 {
 563         LOCK_TEST_WITH_RETURN(dev, file_priv);
 564
 565         return i915_quiescent(dev);
 566 }
 567
 568 static int i915_batchbuffer(struct drm_device *dev, void *data,
 569                             struct drm_file *file_priv)
 570 {
 571         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 572         u32 *hw_status = dev_priv->hw_status_page;
 573         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 574             dev_priv->sarea_priv;
 575         drm_i915_batchbuffer_t *batch = data;
 576         int ret;
 577
 578         if (!dev_priv->allow_batchbuffer) {
 579                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 580                 return -EINVAL;
 581         }
 582
 583         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 584                   batch->start, batch->used, batch->num_cliprects);
 585
 586         LOCK_TEST_WITH_RETURN(dev, file_priv);
 587
 588         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 589                                                        batch->num_cliprects *
 590                                                        sizeof(struct drm_clip_rect)))
 591                 return -EFAULT;
 592
 593         ret = i915_dispatch_batchbuffer(dev, batch);
 594
 595         sarea_priv->last_dispatch = (int)hw_status[5];
 596         return ret;
 597 }
 598
 599 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 600                           struct drm_file *file_priv)
 601 {
 602         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 603         u32 *hw_status = dev_priv->hw_status_page;
 604         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 605             dev_priv->sarea_priv;
 606         drm_i915_cmdbuffer_t *cmdbuf = data;
 607         int ret;
 608
 609         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 610                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 611
 612         LOCK_TEST_WITH_RETURN(dev, file_priv);
 613
 614         if (cmdbuf->num_cliprects &&
 615             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 616                                 cmdbuf->num_cliprects *
 617                                 sizeof(struct drm_clip_rect))) {
 618                 DRM_ERROR("Fault accessing cliprects\n");
 619                 return -EFAULT;
 620         }
 621
 622         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 623         if (ret) {
 624                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 625                 return ret;
 626         }
 627
 628         sarea_priv->last_dispatch = (int)hw_status[5];
 629         return 0;
 630 }
 631
 632 static int i915_flip_bufs(struct drm_device *dev, void *data,
 633                           struct drm_file *file_priv)
 634 {
 635         DRM_DEBUG("%s\n", __func__);
 636
 637         LOCK_TEST_WITH_RETURN(dev, file_priv);
 638
 639         return i915_dispatch_flip(dev);
 640 }
 641
 642 static int i915_getparam(struct drm_device *dev, void *data,
 643                          struct drm_file *file_priv)
 644 {
 645         drm_i915_private_t *dev_priv = dev->dev_private;
 646         drm_i915_getparam_t *param = data;
 647         int value;
 648
 649         if (!dev_priv) {
 650                 DRM_ERROR("called with no initialization\n");
 651                 return -EINVAL;
 652         }
 653
 654         switch (param->param) {
 655         case I915_PARAM_IRQ_ACTIVE:
 656                 value = dev->irq_enabled;
 657                 break;
 658         case I915_PARAM_ALLOW_BATCHBUFFER:
 659                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 660                 break;
 661         case I915_PARAM_LAST_DISPATCH:
 662                 value = READ_BREADCRUMB(dev_priv);
 663                 break;
 664         default:
 665                 DRM_ERROR("Unknown parameter %d\n", param->param);
 666                 return -EINVAL;
 667         }
 668
 669         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 670                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 671                 return -EFAULT;
 672         }
 673
 674         return 0;
 675 }
 676
 677 static int i915_setparam(struct drm_device *dev, void *data,
 678                          struct drm_file *file_priv)
 679 {
 680         drm_i915_private_t *dev_priv = dev->dev_private;
 681         drm_i915_setparam_t *param = data;
 682
 683         if (!dev_priv) {
 684                 DRM_ERROR("called with no initialization\n");
 685                 return -EINVAL;
 686         }
 687
 688         switch (param->param) {
 689         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 690                 break;
 691         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 692                 dev_priv->tex_lru_log_granularity = param->value;
 693                 break;
 694         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 695                 dev_priv->allow_batchbuffer = param->value;
 696                 break;
 697         default:
 698                 DRM_ERROR("unknown parameter %d\n", param->param);
 699                 return -EINVAL;
 700         }
 701
 702         return 0;
 703 }
 704
 705 static int i915_set_status_page(struct drm_device *dev, void *data,
 706                                 struct drm_file *file_priv)
 707 {
 708         drm_i915_private_t *dev_priv = dev->dev_private;
 709         drm_i915_hws_addr_t *hws = data;
 710
 711         if (!I915_NEED_GFX_HWS(dev))
 712                 return -EINVAL;
 713
 714         if (!dev_priv) {
 715                 DRM_ERROR("called with no initialization\n");
 716                 return -EINVAL;
 717         }
 718
 719         printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
 720
 721         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 722
 723         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 724         dev_priv->hws_map.size = 4*1024;
 725         dev_priv->hws_map.type = 0;
 726         dev_priv->hws_map.flags = 0;
 727         dev_priv->hws_map.mtrr = 0;
 728
 729         drm_core_ioremap(&dev_priv->hws_map, dev);
 730         if (dev_priv->hws_map.handle == NULL) {
 731                 i915_dma_cleanup(dev);
 732                 dev_priv->status_gfx_addr = 0;
 733                 DRM_ERROR("can not ioremap virtual address for"
 734                                 " G33 hw status page\n");
 735                 return -ENOMEM;
 736         }
 737         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 738
 739         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 740         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 741         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
 742                         dev_priv->status_gfx_addr);
 743         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 744         return 0;
 745 }
 746
 747 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750         unsigned long base, size;
 751         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
 752
 753         /* i915 has 4 more counters */
 754         dev->counters += 4;
 755         dev->types[6] = _DRM_STAT_IRQ;
 756         dev->types[7] = _DRM_STAT_PRIMARY;
 757         dev->types[8] = _DRM_STAT_SECONDARY;
 758         dev->types[9] = _DRM_STAT_DMA;
 759
 760         dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
 761         if (dev_priv == NULL)
 762                 return -ENOMEM;
 763
 764         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 765
 766         dev->dev_private = (void *)dev_priv;
 767
 768         /* Add register map (needed for suspend/resume) */
 769         base = drm_get_resource_start(dev, mmio_bar);
 770         size = drm_get_resource_len(dev, mmio_bar);
 771
 772         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
 773                          _DRM_KERNEL | _DRM_DRIVER,
 774                          &dev_priv->mmio_map);
 775
 776
 777         /* On the 945G/GM, the chipset reports the MSI capability on the
 778          * integrated graphics even though the support isn't actually there
 779          * according to the published specs.  It doesn't appear to function
 780          * correctly in testing on 945G.
 781          * This may be a side effect of MSI having been made available for PEG
 782          * and the registers being closely associated.
 783          */
 784         if (!IS_I945G(dev) && !IS_I945GM(dev))
 785                 pci_enable_msi(dev->pdev);
 786
 787         spin_lock_init(&dev_priv->user_irq_lock);
 788
 789         return ret;
 790 }
 791
 792 int i915_driver_unload(struct drm_device *dev)
 793 {
 794         struct drm_i915_private *dev_priv = dev->dev_private;
 795
 796         if (dev->pdev->msi_enabled)
 797                 pci_disable_msi(dev->pdev);
 798
 799         if (dev_priv->mmio_map)
 800                 drm_rmmap(dev, dev_priv->mmio_map);
 801
 802         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 803                  DRM_MEM_DRIVER);
 804
 805         return 0;
 806 }
 807
 808 void i915_driver_lastclose(struct drm_device * dev)
 809 {
 810         drm_i915_private_t *dev_priv = dev->dev_private;
 811
 812         if (!dev_priv)
 813                 return;
 814
 815         if (dev_priv->agp_heap)
 816                 i915_mem_takedown(&(dev_priv->agp_heap));
 817
 818         i915_dma_cleanup(dev);
 819 }
 820
 821 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
 822 {
 823         drm_i915_private_t *dev_priv = dev->dev_private;
 824         i915_mem_release(dev, file_priv, dev_priv->agp_heap);
 825 }
 826
 827 struct drm_ioctl_desc i915_ioctls[] = {
 828         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 829         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
 830         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
 831         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
 832         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
 833         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
 834         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
 835         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 836         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
 837         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
 838         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 839         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
 840         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 841         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 842         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
 843         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
 844         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
 845 };
 846
 847 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 848
 849 /**
 850  * Determine if the device really is AGP or not.
 851  *
 852  * All Intel graphics chipsets are treated as AGP, even if they are really
 853  * PCI-e.
 854  *
 855  * \param dev   The device to be tested.
 856  *
 857  * \returns
 858  * A value of 1 is always retured to indictate every i9x5 is AGP.
 859  */
 860 int i915_driver_device_is_agp(struct drm_device * dev)
 861 {
 862         return 1;
 863 }