2 * twl4030_gpio.c -- access to GPIOs on TWL4030/TPS659x0 chips
4 * Copyright (C) 2006-2007 Texas Instruments, Inc.
5 * Copyright (C) 2006 MontaVista Software, Inc.
7 * Code re-arranged and cleaned up by:
8 * Syed Mohammed Khasim <x0khasim@ti.com>
11 * Andy Lowe / Nishanth Menon
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/module.h>
29 #include <linux/kernel_stat.h>
30 #include <linux/init.h>
31 #include <linux/time.h>
32 #include <linux/interrupt.h>
33 #include <linux/device.h>
34 #include <linux/kthread.h>
35 #include <linux/irq.h>
36 #include <linux/gpio.h>
37 #include <linux/platform_device.h>
38 #include <linux/slab.h>
40 #include <linux/i2c/twl4030.h>
41 #include <linux/i2c/twl4030-gpio.h>
43 #include <mach/irqs.h>
44 #include <asm/mach/irq.h>
45 #include <mach/gpio.h>
49 /* REVISIT when these symbols vanish elsewhere, remove them here too */
50 /* #undef TWL4030_GPIO_IRQ_BASE */
51 /* #undef TWL4030_GPIO_IRQ_END */
53 static struct gpio_chip twl_gpiochip;
54 static int twl4030_gpio_irq_base;
55 static int twl4030_gpio_irq_end;
58 #define is_module() true
60 #define is_module() false
63 /* BitField Definitions */
65 /* Data banks : 3 banks for 8 gpios each */
66 #define DATA_BANK_MAX 8
67 #define GET_GPIO_DATA_BANK(x) ((x)/DATA_BANK_MAX)
68 #define GET_GPIO_DATA_OFF(x) ((x)%DATA_BANK_MAX)
70 /* GPIODATADIR Fields each block 0-7 */
71 #define BIT_GPIODATADIR_GPIOxDIR(x) (x)
72 #define MASK_GPIODATADIR_GPIOxDIR(x) (0x01 << (x))
74 /* GPIODATAIN Fields each block 0-7 */
75 #define BIT_GPIODATAIN_GPIOxIN(x) (x)
76 #define MASK_GPIODATAIN_GPIOxIN(x) (0x01 << (x))
78 /* GPIODATAOUT Fields each block 0-7 */
79 #define BIT_GPIODATAOUT_GPIOxOUT(x) (x)
80 #define MASK_GPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
82 /* CLEARGPIODATAOUT Fields */
83 #define BIT_CLEARGPIODATAOUT_GPIOxOUT(x) (x)
84 #define MASK_CLEARGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
86 /* SETGPIODATAOUT Fields */
87 #define BIT_SETGPIODATAOUT_GPIOxOUT(x) (x)
88 #define MASK_SETGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
90 /* GPIO_DEBEN Fields */
91 #define BIT_GPIO_DEBEN_GPIOxDEB(x) (x)
92 #define MASK_GPIO_DEBEN_GPIOxDEB(x) (0x01 << (x))
94 /* GPIO_ISR1A Fields */
95 #define BIT_GPIO_ISR_GPIOxISR(x) (x)
96 #define MASK_GPIO_ISR_GPIOxISR(x) (0x01 << (x))
98 /* GPIO_IMR1A Fields */
99 #define BIT_GPIO_IMR1A_GPIOxIMR(x) (x)
100 #define MASK_GPIO_IMR1A_GPIOxIMR(x) (0x01 << (x))
102 /* GPIO_SIR1 Fields */
103 #define BIT_GPIO_SIR1_GPIOxSIR(x) (x)
104 #define MASK_GPIO_SIR1_GPIO0SIR (0x01 << (x))
107 /* Control banks : 5 banks for 4 gpios each */
108 #define DATA_CTL_MAX 4
109 #define GET_GPIO_CTL_BANK(x) ((x)/DATA_CTL_MAX)
110 #define GET_GPIO_CTL_OFF(x) ((x)%DATA_CTL_MAX)
111 #define GPIO_BANK_MAX GET_GPIO_CTL_BANK(TWL4030_GPIO_MAX)
113 /* GPIOPUPDCTRx Fields 5 banks of 4 gpios each */
114 #define BIT_GPIOPUPDCTR1_GPIOxPD(x) (2 * (x))
115 #define MASK_GPIOPUPDCTR1_GPIOxPD(x) (0x01 << (2 * (x)))
116 #define BIT_GPIOPUPDCTR1_GPIOxPU(x) ((x) + 1)
117 #define MASK_GPIOPUPDCTR1_GPIOxPU(x) (0x01 << (((2 * (x)) + 1)))
119 /* GPIO_EDR1 Fields */
120 #define BIT_GPIO_EDR1_GPIOxFALLING(x) (2 * (x))
121 #define MASK_GPIO_EDR1_GPIOxFALLING(x) (0x01 << (2 * (x)))
122 #define BIT_GPIO_EDR1_GPIOxRISING(x) ((x) + 1)
123 #define MASK_GPIO_EDR1_GPIOxRISING(x) (0x01 << (((2 * (x)) + 1)))
125 /* GPIO_SIH_CTRL Fields */
126 #define BIT_GPIO_SIH_CTRL_EXCLEN (0x000)
127 #define MASK_GPIO_SIH_CTRL_EXCLEN (0x00000001)
128 #define BIT_GPIO_SIH_CTRL_PENDDIS (0x001)
129 #define MASK_GPIO_SIH_CTRL_PENDDIS (0x00000002)
130 #define BIT_GPIO_SIH_CTRL_COR (0x002)
131 #define MASK_GPIO_SIH_CTRL_COR (0x00000004)
133 /* GPIO_CTRL Fields */
134 #define BIT_GPIO_CTRL_GPIO0CD1 (0x000)
135 #define MASK_GPIO_CTRL_GPIO0CD1 (0x00000001)
136 #define BIT_GPIO_CTRL_GPIO1CD2 (0x001)
137 #define MASK_GPIO_CTRL_GPIO1CD2 (0x00000002)
138 #define BIT_GPIO_CTRL_GPIO_ON (0x002)
139 #define MASK_GPIO_CTRL_GPIO_ON (0x00000004)
141 /* Mask for GPIO registers when aggregated into a 32-bit integer */
142 #define GPIO_32_MASK 0x0003ffff
144 /* Data structures */
145 static DEFINE_MUTEX(gpio_lock);
147 /* store usage of each GPIO. - each bit represents one GPIO */
148 static unsigned int gpio_usage_count;
150 /* shadow the imr register */
151 static unsigned int gpio_imr_shadow;
153 /* bitmask of pending requests to unmask gpio interrupts */
154 static unsigned int gpio_pending_unmask;
156 /* bitmask of requests to set gpio irq trigger type */
157 static unsigned int gpio_pending_trigger;
159 /* pointer to gpio unmask thread struct */
160 static struct task_struct *gpio_unmask_thread;
163 * Helper functions to read and write the GPIO ISR and IMR registers as
164 * 32-bit integers. Functions return 0 on success, non-zero otherwise.
165 * The caller must hold gpio_lock.
168 static int gpio_read_isr(unsigned int *isr)
173 ret = twl4030_i2c_read(TWL4030_MODULE_GPIO, (u8 *) isr,
176 *isr &= GPIO_32_MASK;
181 static int gpio_write_isr(unsigned int isr)
185 * The buffer passed to the twl4030_i2c_write() routine must have an
186 * extra byte at the beginning reserved for its internal use.
189 isr = cpu_to_le32(isr);
190 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &isr,
194 static int gpio_write_imr(unsigned int imr)
198 * The buffer passed to the twl4030_i2c_write() routine must have an
199 * extra byte at the beginning reserved for its internal use.
202 imr = cpu_to_le32(imr);
203 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &imr,
208 * These routines are analagous to the irqchip methods, but they are designed
209 * to be called from thread context with cpu interrupts enabled and with no
210 * locked spinlocks. We call these routines from our custom IRQ handler
211 * instead of the usual irqchip methods.
213 static void twl4030_gpio_mask_and_ack(unsigned int irq)
215 int gpio = irq - twl4030_gpio_irq_base;
217 mutex_lock(&gpio_lock);
219 gpio_imr_shadow |= (1 << gpio);
220 gpio_write_imr(gpio_imr_shadow);
222 gpio_write_isr(1 << gpio);
223 mutex_unlock(&gpio_lock);
226 static void twl4030_gpio_unmask(unsigned int irq)
228 int gpio = irq - twl4030_gpio_irq_base;
230 mutex_lock(&gpio_lock);
231 gpio_imr_shadow &= ~(1 << gpio);
232 gpio_write_imr(gpio_imr_shadow);
233 mutex_unlock(&gpio_lock);
237 * These are the irqchip methods for the TWL4030 GPIO interrupts.
238 * Our IRQ handle method doesn't call these, but they will be called by
239 * other routines such as setup_irq() and enable_irq(). They are called
240 * with cpu interrupts disabled and with a lock on the irq_controller_lock
241 * spinlock. This complicates matters, because accessing the TWL4030 GPIO
242 * interrupt controller requires I2C bus transactions that can't be initiated
243 * in this context. Our solution is to defer accessing the interrupt
244 * controller to a kernel thread. We only need to support the unmask method.
247 static void twl4030_gpio_irq_mask_and_ack(unsigned int irq)
251 static void twl4030_gpio_irq_mask(unsigned int irq)
255 static void twl4030_gpio_irq_unmask(unsigned int irq)
257 int gpio = irq - twl4030_gpio_irq_base;
259 gpio_pending_unmask |= (1 << gpio);
260 if (gpio_unmask_thread && gpio_unmask_thread->state != TASK_RUNNING)
261 wake_up_process(gpio_unmask_thread);
264 static int twl4030_gpio_irq_set_type(unsigned int irq, unsigned trigger)
266 struct irq_desc *desc = irq_desc + irq;
267 int gpio = irq - twl4030_gpio_irq_base;
269 trigger &= IRQ_TYPE_SENSE_MASK;
270 if (trigger & ~IRQ_TYPE_EDGE_BOTH)
272 if ((desc->status & IRQ_TYPE_SENSE_MASK) == trigger)
275 desc->status &= ~IRQ_TYPE_SENSE_MASK;
276 desc->status |= trigger;
278 /* REVISIT This makes the "unmask" thread do double duty,
279 * updating IRQ trigger modes too. Rename appropriately...
281 gpio_pending_trigger |= (1 << gpio);
282 if (gpio_unmask_thread && gpio_unmask_thread->state != TASK_RUNNING)
283 wake_up_process(gpio_unmask_thread);
288 static struct irq_chip twl4030_gpio_irq_chip = {
290 .ack = twl4030_gpio_irq_mask_and_ack,
291 .mask = twl4030_gpio_irq_mask,
292 .unmask = twl4030_gpio_irq_unmask,
293 .set_type = twl4030_gpio_irq_set_type,
297 * These are the irqchip methods for the TWL4030 PIH GPIO module interrupt.
298 * The PIH module doesn't have interrupt masking capability, so these
301 static void twl4030_gpio_module_ack(unsigned int irq) {}
302 static void twl4030_gpio_module_mask(unsigned int irq) {}
303 static void twl4030_gpio_module_unmask(unsigned int irq) {}
304 static struct irq_chip twl4030_gpio_module_irq_chip = {
305 .ack = twl4030_gpio_module_ack,
306 .mask = twl4030_gpio_module_mask,
307 .unmask = twl4030_gpio_module_unmask,
311 * To configure TWL4030 GPIO module registers
313 static inline int gpio_twl4030_write(u8 address, u8 data)
317 ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, data, address);
322 * To read a TWL4030 GPIO module register
324 static inline int gpio_twl4030_read(u8 address)
329 ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &data, address);
336 * twl4030 GPIO request function
338 int twl4030_request_gpio(int gpio)
342 if (unlikely(gpio >= TWL4030_GPIO_MAX))
345 ret = gpio_request(twl_gpiochip.base + gpio, NULL);
349 mutex_lock(&gpio_lock);
350 if (gpio_usage_count & (0x1 << gpio)) {
353 /* First time usage? - switch on GPIO module */
354 if (!gpio_usage_count) {
355 ret = gpio_twl4030_write(REG_GPIO_CTRL,
356 MASK_GPIO_CTRL_GPIO_ON);
357 ret = gpio_twl4030_write(REG_GPIO_SIH_CTRL, 0x00);
360 gpio_usage_count |= (0x1 << gpio);
362 gpio_free(twl_gpiochip.base + gpio);
364 mutex_unlock(&gpio_lock);
367 EXPORT_SYMBOL(twl4030_request_gpio);
370 * TWL4030 GPIO free module
372 int twl4030_free_gpio(int gpio)
376 if (unlikely(gpio >= TWL4030_GPIO_MAX))
379 mutex_lock(&gpio_lock);
381 if ((gpio_usage_count & (0x1 << gpio)) == 0) {
384 gpio_usage_count &= ~(0x1 << gpio);
385 gpio_free(twl_gpiochip.base + gpio);
388 /* Last time usage? - switch off GPIO module */
389 if (ret == 0 && !gpio_usage_count)
390 ret = gpio_twl4030_write(REG_GPIO_CTRL, 0x0);
392 mutex_unlock(&gpio_lock);
395 EXPORT_SYMBOL(twl4030_free_gpio);
398 * Set direction for TWL4030 GPIO
400 static int twl4030_set_gpio_direction(int gpio, int is_input)
402 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
403 u8 d_msk = MASK_GPIODATADIR_GPIOxDIR(GET_GPIO_DATA_OFF(gpio));
405 u8 base = REG_GPIODATADIR1 + d_bnk;
408 if (unlikely(!(gpio_usage_count & (0x1 << gpio))))
411 mutex_lock(&gpio_lock);
412 ret = gpio_twl4030_read(base);
415 reg = (u8) ((ret) & ~(d_msk));
417 reg = (u8) ((ret) | (d_msk));
419 ret = gpio_twl4030_write(base, reg);
421 mutex_unlock(&gpio_lock);
426 * To enable/disable GPIO pin on TWL4030
428 static int twl4030_set_gpio_dataout(int gpio, int enable)
430 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
431 u8 d_msk = MASK_GPIODATAOUT_GPIOxOUT(GET_GPIO_DATA_OFF(gpio));
435 if (unlikely(!(gpio_usage_count & (0x1 << gpio))))
439 base = REG_SETGPIODATAOUT1 + d_bnk;
441 base = REG_CLEARGPIODATAOUT1 + d_bnk;
443 mutex_lock(&gpio_lock);
444 ret = gpio_twl4030_write(base, d_msk);
445 mutex_unlock(&gpio_lock);
450 * To get the status of a GPIO pin on TWL4030
452 int twl4030_get_gpio_datain(int gpio)
454 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
455 u8 d_off = BIT_GPIODATAIN_GPIOxIN(GET_GPIO_DATA_OFF(gpio));
459 if (unlikely((gpio >= TWL4030_GPIO_MAX)
460 || !(gpio_usage_count & (0x1 << gpio))))
463 base = REG_GPIODATAIN1 + d_bnk;
464 mutex_lock(&gpio_lock);
465 ret = gpio_twl4030_read(base);
466 mutex_unlock(&gpio_lock);
468 ret = (ret >> d_off) & 0x1;
472 EXPORT_SYMBOL(twl4030_get_gpio_datain);
476 * Configure PULL type for a GPIO pin on TWL4030
478 int twl4030_set_gpio_pull(int gpio, int pull_dircn)
480 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
481 u8 c_off = GET_GPIO_CTL_OFF(gpio);
487 if (unlikely((gpio >= TWL4030_GPIO_MAX) ||
488 !(gpio_usage_count & (0x1 << gpio))))
491 base = REG_GPIOPUPDCTR1 + c_bnk;
492 if (pull_dircn == TWL4030_GPIO_PULL_DOWN)
493 c_msk = MASK_GPIOPUPDCTR1_GPIOxPD(c_off);
494 else if (pull_dircn == TWL4030_GPIO_PULL_UP)
495 c_msk = MASK_GPIOPUPDCTR1_GPIOxPU(c_off);
497 mutex_lock(&gpio_lock);
498 ret = gpio_twl4030_read(base);
500 /* clear the previous up/down values */
502 reg &= ~(MASK_GPIOPUPDCTR1_GPIOxPU(c_off) |
503 MASK_GPIOPUPDCTR1_GPIOxPD(c_off));
505 ret = gpio_twl4030_write(base, reg);
507 mutex_unlock(&gpio_lock);
513 * Configure Edge control for a GPIO pin on TWL4030
515 int twl4030_set_gpio_edge_ctrl(int gpio, int edge)
517 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
518 u8 c_off = GET_GPIO_CTL_OFF(gpio);
524 if (unlikely((gpio >= TWL4030_GPIO_MAX)
525 || !(gpio_usage_count & (0x1 << gpio))))
528 base = REG_GPIO_EDR1 + c_bnk;
530 if (edge & TWL4030_GPIO_EDGE_RISING)
531 c_msk |= MASK_GPIO_EDR1_GPIOxRISING(c_off);
533 if (edge & TWL4030_GPIO_EDGE_FALLING)
534 c_msk |= MASK_GPIO_EDR1_GPIOxFALLING(c_off);
536 mutex_lock(&gpio_lock);
537 ret = gpio_twl4030_read(base);
539 /* clear the previous rising/falling values */
542 ~(MASK_GPIO_EDR1_GPIOxFALLING(c_off) |
543 MASK_GPIO_EDR1_GPIOxRISING(c_off)));
545 ret = gpio_twl4030_write(base, reg);
547 mutex_unlock(&gpio_lock);
550 EXPORT_SYMBOL(twl4030_set_gpio_edge_ctrl);
553 * Configure debounce timing value for a GPIO pin on TWL4030
555 int twl4030_set_gpio_debounce(int gpio, int enable)
557 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
558 u8 d_msk = MASK_GPIO_DEBEN_GPIOxDEB(GET_GPIO_DATA_OFF(gpio));
563 if (unlikely((gpio >= TWL4030_GPIO_MAX)
564 || !(gpio_usage_count & (0x1 << gpio))))
567 base = REG_GPIO_DEBEN1 + d_bnk;
568 mutex_lock(&gpio_lock);
569 ret = gpio_twl4030_read(base);
572 reg = (u8) ((ret) | (d_msk));
574 reg = (u8) ((ret) & ~(d_msk));
576 ret = gpio_twl4030_write(base, reg);
578 mutex_unlock(&gpio_lock);
581 EXPORT_SYMBOL(twl4030_set_gpio_debounce);
585 * Configure Card detect for GPIO pin on TWL4030
587 int twl4030_set_gpio_card_detect(int gpio, int enable)
590 u8 msk = (1 << gpio);
593 /* Only GPIO 0 or 1 can be used for CD feature.. */
594 if (unlikely((gpio >= TWL4030_GPIO_MAX)
595 || !(gpio_usage_count & (0x1 << gpio))
596 || (gpio >= TWL4030_GPIO_MAX_CD))) {
600 mutex_lock(&gpio_lock);
601 ret = gpio_twl4030_read(REG_GPIO_CTRL);
604 reg = (u8) (ret | msk);
606 reg = (u8) (ret & ~msk);
608 ret = gpio_twl4030_write(REG_GPIO_CTRL, reg);
610 mutex_unlock(&gpio_lock);
615 /* MODULE FUNCTIONS */
618 * gpio_unmask_thread() runs as a kernel thread. It is awakened by the unmask
619 * method for the GPIO interrupts. It unmasks all of the GPIO interrupts
620 * specified in the gpio_pending_unmask bitmask. We have to do the unmasking
621 * in a kernel thread rather than directly in the unmask method because of the
622 * need to access the TWL4030 via the I2C bus. Note that we don't need to be
623 * concerned about race conditions where the request to unmask a GPIO interrupt
624 * has already been cancelled before this thread does the unmasking. If a GPIO
625 * interrupt is improperly unmasked, then the IRQ handler for it will mask it
626 * when an interrupt occurs.
628 static int twl4030_gpio_unmask_thread(void *data)
630 current->flags |= PF_NOFREEZE;
632 while (!kthread_should_stop()) {
634 unsigned int gpio_unmask;
635 unsigned int gpio_trigger;
638 gpio_unmask = gpio_pending_unmask;
639 gpio_pending_unmask = 0;
641 gpio_trigger = gpio_pending_trigger;
642 gpio_pending_trigger = 0;
645 for (irq = twl4030_gpio_irq_base; 0 != gpio_unmask;
646 gpio_unmask >>= 1, irq++) {
647 if (gpio_unmask & 0x1)
648 twl4030_gpio_unmask(irq);
651 for (irq = twl4030_gpio_irq_base;
653 gpio_trigger >>= 1, irq++) {
654 struct irq_desc *desc;
657 if (!(gpio_trigger & 0x1))
660 desc = irq_desc + irq;
661 spin_lock_irq(&desc->lock);
662 type = desc->status & IRQ_TYPE_SENSE_MASK;
663 spin_unlock_irq(&desc->lock);
666 case IRQ_TYPE_EDGE_RISING:
667 edge = TWL4030_GPIO_EDGE_RISING;
669 case IRQ_TYPE_EDGE_FALLING:
670 edge = TWL4030_GPIO_EDGE_FALLING;
673 edge = TWL4030_GPIO_EDGE_RISING
674 | TWL4030_GPIO_EDGE_FALLING;
677 twl4030_set_gpio_edge_ctrl(irq, edge);
681 if (!gpio_pending_unmask && !gpio_pending_trigger)
682 set_current_state(TASK_INTERRUPTIBLE);
687 set_current_state(TASK_RUNNING);
692 * do_twl4030_gpio_irq() is the desc->handle method for each of the twl4030
693 * gpio interrupts. It executes in kernel thread context.
694 * On entry, cpu interrupts are enabled.
696 static void do_twl4030_gpio_irq(unsigned int irq, irq_desc_t *desc)
698 struct irqaction *action;
699 const unsigned int cpu = smp_processor_id();
701 desc->status |= IRQ_LEVEL;
704 * Acknowledge, clear _AND_ disable the interrupt.
706 twl4030_gpio_mask_and_ack(irq);
709 kstat_cpu(cpu).irqs[irq]++;
711 action = desc->action;
717 /* Call the ISR with cpu interrupts enabled. */
718 ret = action->handler(irq, action->dev_id);
719 if (ret == IRQ_HANDLED)
720 status |= action->flags;
722 action = action->next;
725 if (retval != IRQ_HANDLED)
726 printk(KERN_ERR "ISR for TWL4030 GPIO"
727 " irq %d can't handle interrupt\n",
731 twl4030_gpio_unmask(irq);
737 * do_twl4030_gpio_module_irq() is the desc->handle method for the twl4030 gpio
738 * module interrupt. It executes in kernel thread context.
739 * This is a chained interrupt, so there is no desc->action method for it.
740 * We query the gpio module interrupt controller in the twl4030 to determine
741 * which gpio lines are generating interrupt requests, and then call the
742 * desc->handle method for each gpio that needs service.
743 * On entry, cpu interrupts are disabled.
745 static void do_twl4030_gpio_module_irq(unsigned int irq, irq_desc_t *desc)
747 const unsigned int cpu = smp_processor_id();
749 desc->status |= IRQ_LEVEL;
751 * The desc->handle method would normally call the desc->chip->ack
752 * method here, but we won't bother since our ack method is NULL.
756 unsigned int gpio_isr;
758 kstat_cpu(cpu).irqs[irq]++;
761 mutex_lock(&gpio_lock);
762 if (gpio_read_isr(&gpio_isr))
764 mutex_unlock(&gpio_lock);
766 for (gpio_irq = twl4030_gpio_irq_base; 0 != gpio_isr;
767 gpio_isr >>= 1, gpio_irq++) {
768 if (gpio_isr & 0x1) {
769 irq_desc_t *d = irq_desc + gpio_irq;
770 d->handle_irq(gpio_irq, d);
776 * Here is where we should call the unmask method, but again we
777 * won't bother since it is NULL.
782 /*----------------------------------------------------------------------*/
784 static int twl_direction_in(struct gpio_chip *chip, unsigned offset)
786 return twl4030_set_gpio_direction(offset, 1);
789 static int twl_get(struct gpio_chip *chip, unsigned offset)
791 int status = twl4030_get_gpio_datain(offset);
793 return (status < 0) ? 0 : status;
796 static int twl_direction_out(struct gpio_chip *chip, unsigned offset, int value)
798 twl4030_set_gpio_dataout(offset, value);
799 return twl4030_set_gpio_direction(offset, 0);
802 static void twl_set(struct gpio_chip *chip, unsigned offset, int value)
804 twl4030_set_gpio_dataout(offset, value);
807 static struct gpio_chip twl_gpiochip = {
809 .owner = THIS_MODULE,
810 .direction_input = twl_direction_in,
812 .direction_output = twl_direction_out,
817 /*----------------------------------------------------------------------*/
819 static int gpio_twl4030_remove(struct platform_device *pdev);
821 static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
823 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
827 /* All GPIO interrupts are initially masked */
828 gpio_pending_unmask = 0;
829 gpio_imr_shadow = GPIO_32_MASK;
830 ret = gpio_write_imr(gpio_imr_shadow);
832 twl4030_gpio_irq_base = pdata->irq_base;
833 twl4030_gpio_irq_end = pdata->irq_end;
835 if ((twl4030_gpio_irq_end - twl4030_gpio_irq_base) > 0) {
838 "can't dispatch IRQs from modules\n");
841 if (twl4030_gpio_irq_end > NR_IRQS) {
843 "last IRQ is too large: %d\n",
844 twl4030_gpio_irq_end);
848 dev_notice(&pdev->dev,
849 "no IRQs being dispatched\n");
855 * Create a kernel thread to handle deferred unmasking of gpio
858 gpio_unmask_thread = kthread_create(twl4030_gpio_unmask_thread,
859 NULL, "twl4030 gpio");
860 if (!gpio_unmask_thread) {
862 "could not create twl4030 gpio unmask"
869 /* install an irq handler for each of the gpio interrupts */
870 for (irq = twl4030_gpio_irq_base; irq < twl4030_gpio_irq_end;
872 set_irq_chip(irq, &twl4030_gpio_irq_chip);
873 set_irq_handler(irq, do_twl4030_gpio_irq);
874 set_irq_flags(irq, IRQF_VALID);
877 /* gpio module IRQ */
878 irq = platform_get_irq(pdev, 0);
881 * Install an irq handler to demultiplex the gpio module
884 set_irq_chip(irq, &twl4030_gpio_module_irq_chip);
885 set_irq_chained_handler(irq, do_twl4030_gpio_module_irq);
886 wake_up_process(gpio_unmask_thread);
888 dev_info(&pdev->dev, "IRQ %d chains IRQs %d..%d\n", irq,
889 twl4030_gpio_irq_base, twl4030_gpio_irq_end - 1);
894 twl_gpiochip.base = pdata->gpio_base;
895 twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
896 twl_gpiochip.dev = &pdev->dev;
898 ret = gpiochip_add(&twl_gpiochip);
901 "could not register gpiochip, %d\n",
903 twl_gpiochip.ngpio = 0;
904 gpio_twl4030_remove(pdev);
905 } else if (pdata->setup) {
908 status = pdata->setup(&pdev->dev,
909 pdata->gpio_base, TWL4030_GPIO_MAX);
911 dev_dbg(&pdev->dev, "setup --> %d\n", status);
918 static int __devexit gpio_twl4030_remove(struct platform_device *pdev)
920 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
924 if (pdata->teardown) {
925 status = pdata->teardown(&pdev->dev,
926 pdata->gpio_base, TWL4030_GPIO_MAX);
928 dev_dbg(&pdev->dev, "teardown --> %d\n", status);
933 status = gpiochip_remove(&twl_gpiochip);
937 if (is_module() || (twl4030_gpio_irq_end - twl4030_gpio_irq_base) <= 0)
940 /* uninstall the gpio demultiplexing interrupt handler */
941 irq = platform_get_irq(pdev, 0);
942 set_irq_handler(irq, NULL);
943 set_irq_flags(irq, 0);
945 /* uninstall the irq handler for each of the gpio interrupts */
946 for (irq = twl4030_gpio_irq_base; irq < twl4030_gpio_irq_end; irq++) {
947 set_irq_handler(irq, NULL);
948 set_irq_flags(irq, 0);
951 /* stop the gpio unmask kernel thread */
952 if (gpio_unmask_thread) {
953 kthread_stop(gpio_unmask_thread);
954 gpio_unmask_thread = NULL;
960 /* Note: this hardware lives inside an I2C-based multi-function device. */
961 MODULE_ALIAS("platform:twl4030_gpio");
963 static struct platform_driver gpio_twl4030_driver = {
964 .driver.name = "twl4030_gpio",
965 .driver.owner = THIS_MODULE,
966 .probe = gpio_twl4030_probe,
967 .remove = __devexit_p(gpio_twl4030_remove),
970 static int __init gpio_twl4030_init(void)
972 return platform_driver_register(&gpio_twl4030_driver);
974 subsys_initcall(gpio_twl4030_init);
976 static void __exit gpio_twl4030_exit(void)
978 platform_driver_unregister(&gpio_twl4030_driver);
980 module_exit(gpio_twl4030_exit);
982 MODULE_AUTHOR("Texas Instruments, Inc.");
983 MODULE_DESCRIPTION("GPIO interface for TWL4030");
984 MODULE_LICENSE("GPL");