2 * twl4030_gpio.c -- access to GPIOs on TWL4030/TPS659x0 chips
4 * Copyright (C) 2006-2007 Texas Instruments, Inc.
5 * Copyright (C) 2006 MontaVista Software, Inc.
7 * Code re-arranged and cleaned up by:
8 * Syed Mohammed Khasim <x0khasim@ti.com>
11 * Andy Lowe / Nishanth Menon
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/module.h>
29 #include <linux/kernel_stat.h>
30 #include <linux/init.h>
31 #include <linux/time.h>
32 #include <linux/interrupt.h>
33 #include <linux/device.h>
34 #include <linux/kthread.h>
35 #include <linux/irq.h>
36 #include <linux/gpio.h>
37 #include <linux/platform_device.h>
38 #include <linux/slab.h>
40 #include <linux/i2c/twl4030.h>
41 #include <linux/i2c/twl4030-gpio.h>
43 #include <mach/irqs.h>
44 #include <asm/mach/irq.h>
45 #include <mach/gpio.h>
49 /* REVISIT when these symbols vanish elsewhere, remove them here too */
50 /* #undef TWL4030_GPIO_IRQ_BASE */
51 /* #undef TWL4030_GPIO_IRQ_END */
53 static struct gpio_chip twl_gpiochip;
54 static int twl4030_gpio_irq_base;
55 static int twl4030_gpio_irq_end;
58 #define is_module() true
60 #define is_module() false
63 /* BitField Definitions */
65 /* Data banks : 3 banks for 8 gpios each */
66 #define DATA_BANK_MAX 8
67 #define GET_GPIO_DATA_BANK(x) ((x)/DATA_BANK_MAX)
68 #define GET_GPIO_DATA_OFF(x) ((x)%DATA_BANK_MAX)
70 /* GPIODATADIR Fields each block 0-7 */
71 #define BIT_GPIODATADIR_GPIOxDIR(x) (x)
72 #define MASK_GPIODATADIR_GPIOxDIR(x) (0x01 << (x))
74 /* GPIODATAIN Fields each block 0-7 */
75 #define BIT_GPIODATAIN_GPIOxIN(x) (x)
76 #define MASK_GPIODATAIN_GPIOxIN(x) (0x01 << (x))
78 /* GPIODATAOUT Fields each block 0-7 */
79 #define BIT_GPIODATAOUT_GPIOxOUT(x) (x)
80 #define MASK_GPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
82 /* CLEARGPIODATAOUT Fields */
83 #define BIT_CLEARGPIODATAOUT_GPIOxOUT(x) (x)
84 #define MASK_CLEARGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
86 /* SETGPIODATAOUT Fields */
87 #define BIT_SETGPIODATAOUT_GPIOxOUT(x) (x)
88 #define MASK_SETGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
90 /* GPIO_DEBEN Fields */
91 #define BIT_GPIO_DEBEN_GPIOxDEB(x) (x)
92 #define MASK_GPIO_DEBEN_GPIOxDEB(x) (0x01 << (x))
94 /* GPIO_ISR1A Fields */
95 #define BIT_GPIO_ISR_GPIOxISR(x) (x)
96 #define MASK_GPIO_ISR_GPIOxISR(x) (0x01 << (x))
98 /* GPIO_IMR1A Fields */
99 #define BIT_GPIO_IMR1A_GPIOxIMR(x) (x)
100 #define MASK_GPIO_IMR1A_GPIOxIMR(x) (0x01 << (x))
102 /* GPIO_SIR1 Fields */
103 #define BIT_GPIO_SIR1_GPIOxSIR(x) (x)
104 #define MASK_GPIO_SIR1_GPIO0SIR (0x01 << (x))
107 /* Control banks : 5 banks for 4 gpios each */
108 #define DATA_CTL_MAX 4
109 #define GET_GPIO_CTL_BANK(x) ((x)/DATA_CTL_MAX)
110 #define GET_GPIO_CTL_OFF(x) ((x)%DATA_CTL_MAX)
111 #define GPIO_BANK_MAX GET_GPIO_CTL_BANK(TWL4030_GPIO_MAX)
113 /* GPIOPUPDCTRx Fields 5 banks of 4 gpios each */
114 #define BIT_GPIOPUPDCTR1_GPIOxPD(x) (2 * (x))
115 #define MASK_GPIOPUPDCTR1_GPIOxPD(x) (0x01 << (2 * (x)))
116 #define BIT_GPIOPUPDCTR1_GPIOxPU(x) ((x) + 1)
117 #define MASK_GPIOPUPDCTR1_GPIOxPU(x) (0x01 << (((2 * (x)) + 1)))
119 /* GPIO_EDR1 Fields */
120 #define BIT_GPIO_EDR1_GPIOxFALLING(x) (2 * (x))
121 #define MASK_GPIO_EDR1_GPIOxFALLING(x) (0x01 << (2 * (x)))
122 #define BIT_GPIO_EDR1_GPIOxRISING(x) ((x) + 1)
123 #define MASK_GPIO_EDR1_GPIOxRISING(x) (0x01 << (((2 * (x)) + 1)))
125 /* GPIO_SIH_CTRL Fields */
126 #define BIT_GPIO_SIH_CTRL_EXCLEN (0x000)
127 #define MASK_GPIO_SIH_CTRL_EXCLEN (0x00000001)
128 #define BIT_GPIO_SIH_CTRL_PENDDIS (0x001)
129 #define MASK_GPIO_SIH_CTRL_PENDDIS (0x00000002)
130 #define BIT_GPIO_SIH_CTRL_COR (0x002)
131 #define MASK_GPIO_SIH_CTRL_COR (0x00000004)
133 /* GPIO_CTRL Fields */
134 #define BIT_GPIO_CTRL_GPIO0CD1 (0x000)
135 #define MASK_GPIO_CTRL_GPIO0CD1 (0x00000001)
136 #define BIT_GPIO_CTRL_GPIO1CD2 (0x001)
137 #define MASK_GPIO_CTRL_GPIO1CD2 (0x00000002)
138 #define BIT_GPIO_CTRL_GPIO_ON (0x002)
139 #define MASK_GPIO_CTRL_GPIO_ON (0x00000004)
141 /* Mask for GPIO registers when aggregated into a 32-bit integer */
142 #define GPIO_32_MASK 0x0003ffff
144 /* Data structures */
145 static DEFINE_MUTEX(gpio_lock);
147 /* store usage of each GPIO. - each bit represents one GPIO */
148 static unsigned int gpio_usage_count;
150 /* shadow the imr register */
151 static unsigned int gpio_imr_shadow;
153 /* bitmask of pending requests to unmask gpio interrupts */
154 static unsigned int gpio_pending_unmask;
156 /* pointer to gpio unmask thread struct */
157 static struct task_struct *gpio_unmask_thread;
160 * Helper functions to read and write the GPIO ISR and IMR registers as
161 * 32-bit integers. Functions return 0 on success, non-zero otherwise.
162 * The caller must hold gpio_lock.
165 static int gpio_read_isr(unsigned int *isr)
170 ret = twl4030_i2c_read(TWL4030_MODULE_GPIO, (u8 *) isr,
173 *isr &= GPIO_32_MASK;
178 static int gpio_write_isr(unsigned int isr)
182 * The buffer passed to the twl4030_i2c_write() routine must have an
183 * extra byte at the beginning reserved for its internal use.
186 isr = cpu_to_le32(isr);
187 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &isr,
191 static int gpio_write_imr(unsigned int imr)
195 * The buffer passed to the twl4030_i2c_write() routine must have an
196 * extra byte at the beginning reserved for its internal use.
199 imr = cpu_to_le32(imr);
200 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &imr,
205 * These routines are analagous to the irqchip methods, but they are designed
206 * to be called from thread context with cpu interrupts enabled and with no
207 * locked spinlocks. We call these routines from our custom IRQ handler
208 * instead of the usual irqchip methods.
210 static void twl4030_gpio_mask_and_ack(unsigned int irq)
212 int gpio = irq - twl4030_gpio_irq_base;
214 mutex_lock(&gpio_lock);
216 gpio_imr_shadow |= (1 << gpio);
217 gpio_write_imr(gpio_imr_shadow);
219 gpio_write_isr(1 << gpio);
220 mutex_unlock(&gpio_lock);
223 static void twl4030_gpio_unmask(unsigned int irq)
225 int gpio = irq - twl4030_gpio_irq_base;
227 mutex_lock(&gpio_lock);
228 gpio_imr_shadow &= ~(1 << gpio);
229 gpio_write_imr(gpio_imr_shadow);
230 mutex_unlock(&gpio_lock);
234 * These are the irqchip methods for the TWL4030 GPIO interrupts.
235 * Our IRQ handle method doesn't call these, but they will be called by
236 * other routines such as setup_irq() and enable_irq(). They are called
237 * with cpu interrupts disabled and with a lock on the irq_controller_lock
238 * spinlock. This complicates matters, because accessing the TWL4030 GPIO
239 * interrupt controller requires I2C bus transactions that can't be initiated
240 * in this context. Our solution is to defer accessing the interrupt
241 * controller to a kernel thread. We only need to support the unmask method.
244 static void twl4030_gpio_mask_and_ack_irqchip(unsigned int irq) {}
245 static void twl4030_gpio_mask_irqchip(unsigned int irq) {}
247 static void twl4030_gpio_unmask_irqchip(unsigned int irq)
249 int gpio = irq - twl4030_gpio_irq_base;
251 gpio_pending_unmask |= (1 << gpio);
252 if (gpio_unmask_thread && gpio_unmask_thread->state != TASK_RUNNING)
253 wake_up_process(gpio_unmask_thread);
256 static struct irq_chip twl4030_gpio_irq_chip = {
258 .ack = twl4030_gpio_mask_and_ack_irqchip,
259 .mask = twl4030_gpio_mask_irqchip,
260 .unmask = twl4030_gpio_unmask_irqchip,
264 * These are the irqchip methods for the TWL4030 PIH GPIO module interrupt.
265 * The PIH module doesn't have interrupt masking capability, so these
268 static void twl4030_gpio_module_ack(unsigned int irq) {}
269 static void twl4030_gpio_module_mask(unsigned int irq) {}
270 static void twl4030_gpio_module_unmask(unsigned int irq) {}
271 static struct irq_chip twl4030_gpio_module_irq_chip = {
272 .ack = twl4030_gpio_module_ack,
273 .mask = twl4030_gpio_module_mask,
274 .unmask = twl4030_gpio_module_unmask,
278 * To configure TWL4030 GPIO module registers
280 static inline int gpio_twl4030_write(u8 address, u8 data)
284 ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, data, address);
289 * To read a TWL4030 GPIO module register
291 static inline int gpio_twl4030_read(u8 address)
296 ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &data, address);
303 * twl4030 GPIO request function
305 int twl4030_request_gpio(int gpio)
309 if (unlikely(gpio >= TWL4030_GPIO_MAX))
312 ret = gpio_request(twl_gpiochip.base + gpio, NULL);
316 mutex_lock(&gpio_lock);
317 if (gpio_usage_count & (0x1 << gpio)) {
320 /* First time usage? - switch on GPIO module */
321 if (!gpio_usage_count) {
322 ret = gpio_twl4030_write(REG_GPIO_CTRL,
323 MASK_GPIO_CTRL_GPIO_ON);
324 ret = gpio_twl4030_write(REG_GPIO_SIH_CTRL, 0x00);
327 gpio_usage_count |= (0x1 << gpio);
329 gpio_free(twl_gpiochip.base + gpio);
331 mutex_unlock(&gpio_lock);
334 EXPORT_SYMBOL(twl4030_request_gpio);
337 * TWL4030 GPIO free module
339 int twl4030_free_gpio(int gpio)
343 if (unlikely(gpio >= TWL4030_GPIO_MAX))
346 mutex_lock(&gpio_lock);
348 if ((gpio_usage_count & (0x1 << gpio)) == 0) {
351 gpio_usage_count &= ~(0x1 << gpio);
352 gpio_free(twl_gpiochip.base + gpio);
355 /* Last time usage? - switch off GPIO module */
356 if (ret == 0 && !gpio_usage_count)
357 ret = gpio_twl4030_write(REG_GPIO_CTRL, 0x0);
359 mutex_unlock(&gpio_lock);
362 EXPORT_SYMBOL(twl4030_free_gpio);
365 * Set direction for TWL4030 GPIO
367 static int twl4030_set_gpio_direction(int gpio, int is_input)
369 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
370 u8 d_msk = MASK_GPIODATADIR_GPIOxDIR(GET_GPIO_DATA_OFF(gpio));
372 u8 base = REG_GPIODATADIR1 + d_bnk;
375 if (unlikely(!(gpio_usage_count & (0x1 << gpio))))
378 mutex_lock(&gpio_lock);
379 ret = gpio_twl4030_read(base);
382 reg = (u8) ((ret) & ~(d_msk));
384 reg = (u8) ((ret) | (d_msk));
386 ret = gpio_twl4030_write(base, reg);
388 mutex_unlock(&gpio_lock);
393 * To enable/disable GPIO pin on TWL4030
395 static int twl4030_set_gpio_dataout(int gpio, int enable)
397 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
398 u8 d_msk = MASK_GPIODATAOUT_GPIOxOUT(GET_GPIO_DATA_OFF(gpio));
402 if (unlikely(!(gpio_usage_count & (0x1 << gpio))))
406 base = REG_SETGPIODATAOUT1 + d_bnk;
408 base = REG_CLEARGPIODATAOUT1 + d_bnk;
410 mutex_lock(&gpio_lock);
411 ret = gpio_twl4030_write(base, d_msk);
412 mutex_unlock(&gpio_lock);
417 * To get the status of a GPIO pin on TWL4030
419 int twl4030_get_gpio_datain(int gpio)
421 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
422 u8 d_off = BIT_GPIODATAIN_GPIOxIN(GET_GPIO_DATA_OFF(gpio));
426 if (unlikely((gpio >= TWL4030_GPIO_MAX)
427 || !(gpio_usage_count & (0x1 << gpio))))
430 base = REG_GPIODATAIN1 + d_bnk;
431 mutex_lock(&gpio_lock);
432 ret = gpio_twl4030_read(base);
433 mutex_unlock(&gpio_lock);
435 ret = (ret >> d_off) & 0x1;
439 EXPORT_SYMBOL(twl4030_get_gpio_datain);
443 * Configure PULL type for a GPIO pin on TWL4030
445 int twl4030_set_gpio_pull(int gpio, int pull_dircn)
447 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
448 u8 c_off = GET_GPIO_CTL_OFF(gpio);
454 if (unlikely((gpio >= TWL4030_GPIO_MAX) ||
455 !(gpio_usage_count & (0x1 << gpio))))
458 base = REG_GPIOPUPDCTR1 + c_bnk;
459 if (pull_dircn == TWL4030_GPIO_PULL_DOWN)
460 c_msk = MASK_GPIOPUPDCTR1_GPIOxPD(c_off);
461 else if (pull_dircn == TWL4030_GPIO_PULL_UP)
462 c_msk = MASK_GPIOPUPDCTR1_GPIOxPU(c_off);
464 mutex_lock(&gpio_lock);
465 ret = gpio_twl4030_read(base);
467 /* clear the previous up/down values */
469 reg &= ~(MASK_GPIOPUPDCTR1_GPIOxPU(c_off) |
470 MASK_GPIOPUPDCTR1_GPIOxPD(c_off));
472 ret = gpio_twl4030_write(base, reg);
474 mutex_unlock(&gpio_lock);
480 * Configure Edge control for a GPIO pin on TWL4030
482 * FIXME this should just be the irq_chip.set_type() method
484 int twl4030_set_gpio_edge_ctrl(int gpio, int edge)
486 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
487 u8 c_off = GET_GPIO_CTL_OFF(gpio);
493 if (unlikely((gpio >= TWL4030_GPIO_MAX)
494 || !(gpio_usage_count & (0x1 << gpio))))
497 base = REG_GPIO_EDR1 + c_bnk;
499 if (edge & TWL4030_GPIO_EDGE_RISING)
500 c_msk |= MASK_GPIO_EDR1_GPIOxRISING(c_off);
502 if (edge & TWL4030_GPIO_EDGE_FALLING)
503 c_msk |= MASK_GPIO_EDR1_GPIOxFALLING(c_off);
505 mutex_lock(&gpio_lock);
506 ret = gpio_twl4030_read(base);
508 /* clear the previous rising/falling values */
511 ~(MASK_GPIO_EDR1_GPIOxFALLING(c_off) |
512 MASK_GPIO_EDR1_GPIOxRISING(c_off)));
514 ret = gpio_twl4030_write(base, reg);
516 mutex_unlock(&gpio_lock);
519 EXPORT_SYMBOL(twl4030_set_gpio_edge_ctrl);
522 * Configure debounce timing value for a GPIO pin on TWL4030
524 int twl4030_set_gpio_debounce(int gpio, int enable)
526 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
527 u8 d_msk = MASK_GPIO_DEBEN_GPIOxDEB(GET_GPIO_DATA_OFF(gpio));
532 if (unlikely((gpio >= TWL4030_GPIO_MAX)
533 || !(gpio_usage_count & (0x1 << gpio))))
536 base = REG_GPIO_DEBEN1 + d_bnk;
537 mutex_lock(&gpio_lock);
538 ret = gpio_twl4030_read(base);
541 reg = (u8) ((ret) | (d_msk));
543 reg = (u8) ((ret) & ~(d_msk));
545 ret = gpio_twl4030_write(base, reg);
547 mutex_unlock(&gpio_lock);
550 EXPORT_SYMBOL(twl4030_set_gpio_debounce);
554 * Configure Card detect for GPIO pin on TWL4030
556 int twl4030_set_gpio_card_detect(int gpio, int enable)
559 u8 msk = (1 << gpio);
562 /* Only GPIO 0 or 1 can be used for CD feature.. */
563 if (unlikely((gpio >= TWL4030_GPIO_MAX)
564 || !(gpio_usage_count & (0x1 << gpio))
565 || (gpio >= TWL4030_GPIO_MAX_CD))) {
569 mutex_lock(&gpio_lock);
570 ret = gpio_twl4030_read(REG_GPIO_CTRL);
573 reg = (u8) (ret | msk);
575 reg = (u8) (ret & ~msk);
577 ret = gpio_twl4030_write(REG_GPIO_CTRL, reg);
579 mutex_unlock(&gpio_lock);
584 /* MODULE FUNCTIONS */
587 * gpio_unmask_thread() runs as a kernel thread. It is awakened by the unmask
588 * method for the GPIO interrupts. It unmasks all of the GPIO interrupts
589 * specified in the gpio_pending_unmask bitmask. We have to do the unmasking
590 * in a kernel thread rather than directly in the unmask method because of the
591 * need to access the TWL4030 via the I2C bus. Note that we don't need to be
592 * concerned about race conditions where the request to unmask a GPIO interrupt
593 * has already been cancelled before this thread does the unmasking. If a GPIO
594 * interrupt is improperly unmasked, then the IRQ handler for it will mask it
595 * when an interrupt occurs.
597 static int twl4030_gpio_unmask_thread(void *data)
599 current->flags |= PF_NOFREEZE;
601 while (!kthread_should_stop()) {
603 unsigned int gpio_unmask;
606 gpio_unmask = gpio_pending_unmask;
607 gpio_pending_unmask = 0;
610 for (irq = twl4030_gpio_irq_base; 0 != gpio_unmask;
611 gpio_unmask >>= 1, irq++) {
612 if (gpio_unmask & 0x1)
613 twl4030_gpio_unmask(irq);
617 if (!gpio_pending_unmask)
618 set_current_state(TASK_INTERRUPTIBLE);
623 set_current_state(TASK_RUNNING);
628 * do_twl4030_gpio_irq() is the desc->handle method for each of the twl4030
629 * gpio interrupts. It executes in kernel thread context.
630 * On entry, cpu interrupts are enabled.
632 static void do_twl4030_gpio_irq(unsigned int irq, irq_desc_t *desc)
634 struct irqaction *action;
635 const unsigned int cpu = smp_processor_id();
637 desc->status |= IRQ_LEVEL;
640 * Acknowledge, clear _AND_ disable the interrupt.
642 twl4030_gpio_mask_and_ack(irq);
645 kstat_cpu(cpu).irqs[irq]++;
647 action = desc->action;
653 /* Call the ISR with cpu interrupts enabled. */
654 ret = action->handler(irq, action->dev_id);
655 if (ret == IRQ_HANDLED)
656 status |= action->flags;
658 action = action->next;
661 if (retval != IRQ_HANDLED)
662 printk(KERN_ERR "ISR for TWL4030 GPIO"
663 " irq %d can't handle interrupt\n",
667 twl4030_gpio_unmask(irq);
673 * do_twl4030_gpio_module_irq() is the desc->handle method for the twl4030 gpio
674 * module interrupt. It executes in kernel thread context.
675 * This is a chained interrupt, so there is no desc->action method for it.
676 * We query the gpio module interrupt controller in the twl4030 to determine
677 * which gpio lines are generating interrupt requests, and then call the
678 * desc->handle method for each gpio that needs service.
679 * On entry, cpu interrupts are disabled.
681 static void do_twl4030_gpio_module_irq(unsigned int irq, irq_desc_t *desc)
683 const unsigned int cpu = smp_processor_id();
685 desc->status |= IRQ_LEVEL;
687 * The desc->handle method would normally call the desc->chip->ack
688 * method here, but we won't bother since our ack method is NULL.
692 unsigned int gpio_isr;
694 kstat_cpu(cpu).irqs[irq]++;
697 mutex_lock(&gpio_lock);
698 if (gpio_read_isr(&gpio_isr))
700 mutex_unlock(&gpio_lock);
702 for (gpio_irq = twl4030_gpio_irq_base; 0 != gpio_isr;
703 gpio_isr >>= 1, gpio_irq++) {
704 if (gpio_isr & 0x1) {
705 irq_desc_t *d = irq_desc + gpio_irq;
706 d->handle_irq(gpio_irq, d);
712 * Here is where we should call the unmask method, but again we
713 * won't bother since it is NULL.
718 /*----------------------------------------------------------------------*/
720 static int twl_direction_in(struct gpio_chip *chip, unsigned offset)
722 return twl4030_set_gpio_direction(offset, 1);
725 static int twl_get(struct gpio_chip *chip, unsigned offset)
727 int status = twl4030_get_gpio_datain(offset);
729 return (status < 0) ? 0 : status;
732 static int twl_direction_out(struct gpio_chip *chip, unsigned offset, int value)
734 twl4030_set_gpio_dataout(offset, value);
735 return twl4030_set_gpio_direction(offset, 0);
738 static void twl_set(struct gpio_chip *chip, unsigned offset, int value)
740 twl4030_set_gpio_dataout(offset, value);
743 static struct gpio_chip twl_gpiochip = {
745 .owner = THIS_MODULE,
746 .direction_input = twl_direction_in,
748 .direction_output = twl_direction_out,
753 /*----------------------------------------------------------------------*/
755 static int gpio_twl4030_remove(struct platform_device *pdev);
757 static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
759 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
763 /* All GPIO interrupts are initially masked */
764 gpio_pending_unmask = 0;
765 gpio_imr_shadow = GPIO_32_MASK;
766 ret = gpio_write_imr(gpio_imr_shadow);
768 twl4030_gpio_irq_base = pdata->irq_base;
769 twl4030_gpio_irq_end = pdata->irq_end;
771 if ((twl4030_gpio_irq_end - twl4030_gpio_irq_base) > 0) {
774 "can't dispatch IRQs from modules\n");
777 if (twl4030_gpio_irq_end > NR_IRQS) {
779 "last IRQ is too large: %d\n",
780 twl4030_gpio_irq_end);
784 dev_notice(&pdev->dev,
785 "no IRQs being dispatched\n");
791 * Create a kernel thread to handle deferred unmasking of gpio
794 gpio_unmask_thread = kthread_create(twl4030_gpio_unmask_thread,
795 NULL, "twl4030 gpio");
796 if (!gpio_unmask_thread) {
798 "could not create twl4030 gpio unmask"
805 /* install an irq handler for each of the gpio interrupts */
806 for (irq = twl4030_gpio_irq_base; irq < twl4030_gpio_irq_end;
808 set_irq_chip(irq, &twl4030_gpio_irq_chip);
809 set_irq_handler(irq, do_twl4030_gpio_irq);
810 set_irq_flags(irq, IRQF_VALID);
813 /* gpio module IRQ */
814 irq = platform_get_irq(pdev, 0);
817 * Install an irq handler to demultiplex the gpio module
820 set_irq_chip(irq, &twl4030_gpio_module_irq_chip);
821 set_irq_chained_handler(irq, do_twl4030_gpio_module_irq);
822 wake_up_process(gpio_unmask_thread);
824 dev_info(&pdev->dev, "IRQ %d chains IRQs %d..%d\n", irq,
825 twl4030_gpio_irq_base, twl4030_gpio_irq_end - 1);
830 twl_gpiochip.base = pdata->gpio_base;
831 twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
832 twl_gpiochip.dev = &pdev->dev;
834 ret = gpiochip_add(&twl_gpiochip);
837 "could not register gpiochip, %d\n",
839 twl_gpiochip.ngpio = 0;
840 gpio_twl4030_remove(pdev);
841 } else if (pdata->setup) {
844 status = pdata->setup(&pdev->dev,
845 pdata->gpio_base, TWL4030_GPIO_MAX);
847 dev_dbg(&pdev->dev, "setup --> %d\n", status);
854 static int __devexit gpio_twl4030_remove(struct platform_device *pdev)
856 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
860 if (pdata->teardown) {
861 status = pdata->teardown(&pdev->dev,
862 pdata->gpio_base, TWL4030_GPIO_MAX);
864 dev_dbg(&pdev->dev, "teardown --> %d\n", status);
869 status = gpiochip_remove(&twl_gpiochip);
873 if (is_module() || (twl4030_gpio_irq_end - twl4030_gpio_irq_base) <= 0)
876 /* uninstall the gpio demultiplexing interrupt handler */
877 irq = platform_get_irq(pdev, 0);
878 set_irq_handler(irq, NULL);
879 set_irq_flags(irq, 0);
881 /* uninstall the irq handler for each of the gpio interrupts */
882 for (irq = twl4030_gpio_irq_base; irq < twl4030_gpio_irq_end; irq++) {
883 set_irq_handler(irq, NULL);
884 set_irq_flags(irq, 0);
887 /* stop the gpio unmask kernel thread */
888 if (gpio_unmask_thread) {
889 kthread_stop(gpio_unmask_thread);
890 gpio_unmask_thread = NULL;
896 /* Note: this hardware lives inside an I2C-based multi-function device. */
897 MODULE_ALIAS("platform:twl4030_gpio");
899 static struct platform_driver gpio_twl4030_driver = {
900 .driver.name = "twl4030_gpio",
901 .driver.owner = THIS_MODULE,
902 .probe = gpio_twl4030_probe,
903 .remove = __devexit_p(gpio_twl4030_remove),
906 static int __init gpio_twl4030_init(void)
908 return platform_driver_register(&gpio_twl4030_driver);
910 subsys_initcall(gpio_twl4030_init);
912 static void __exit gpio_twl4030_exit(void)
914 platform_driver_unregister(&gpio_twl4030_driver);
916 module_exit(gpio_twl4030_exit);
918 MODULE_AUTHOR("Texas Instruments, Inc.");
919 MODULE_DESCRIPTION("GPIO interface for TWL4030");
920 MODULE_LICENSE("GPL");