2 * twl4030_gpio.c -- access to GPIOs on TWL4030/TPS659x0 chips
4 * Copyright (C) 2006-2007 Texas Instruments, Inc.
5 * Copyright (C) 2006 MontaVista Software, Inc.
7 * Code re-arranged and cleaned up by:
8 * Syed Mohammed Khasim <x0khasim@ti.com>
11 * Andy Lowe / Nishanth Menon
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/module.h>
29 #include <linux/kernel_stat.h>
30 #include <linux/init.h>
31 #include <linux/time.h>
32 #include <linux/interrupt.h>
33 #include <linux/device.h>
34 #include <linux/kthread.h>
35 #include <linux/irq.h>
36 #include <linux/gpio.h>
37 #include <linux/platform_device.h>
38 #include <linux/slab.h>
40 #include <linux/i2c/twl4030.h>
41 #include <linux/i2c/twl4030-gpio.h>
43 #include <mach/irqs.h>
44 #include <asm/mach/irq.h>
45 #include <mach/gpio.h>
49 /* REVISIT when these symbols vanish elsewhere, remove them here too */
50 /* #undef TWL4030_GPIO_IRQ_BASE */
51 /* #undef TWL4030_GPIO_IRQ_END */
52 #undef TWL4030_MODIRQ_GPIO
54 static struct gpio_chip twl_gpiochip;
55 static int twl4030_gpio_irq_base;
56 static int twl4030_gpio_irq_end;
59 #define is_module() true
61 #define is_module() false
64 /* BitField Definitions */
66 /* Data banks : 3 banks for 8 gpios each */
67 #define DATA_BANK_MAX 8
68 #define GET_GPIO_DATA_BANK(x) ((x)/DATA_BANK_MAX)
69 #define GET_GPIO_DATA_OFF(x) ((x)%DATA_BANK_MAX)
71 /* GPIODATADIR Fields each block 0-7 */
72 #define BIT_GPIODATADIR_GPIOxDIR(x) (x)
73 #define MASK_GPIODATADIR_GPIOxDIR(x) (0x01 << (x))
75 /* GPIODATAIN Fields each block 0-7 */
76 #define BIT_GPIODATAIN_GPIOxIN(x) (x)
77 #define MASK_GPIODATAIN_GPIOxIN(x) (0x01 << (x))
79 /* GPIODATAOUT Fields each block 0-7 */
80 #define BIT_GPIODATAOUT_GPIOxOUT(x) (x)
81 #define MASK_GPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
83 /* CLEARGPIODATAOUT Fields */
84 #define BIT_CLEARGPIODATAOUT_GPIOxOUT(x) (x)
85 #define MASK_CLEARGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
87 /* SETGPIODATAOUT Fields */
88 #define BIT_SETGPIODATAOUT_GPIOxOUT(x) (x)
89 #define MASK_SETGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
91 /* GPIO_DEBEN Fields */
92 #define BIT_GPIO_DEBEN_GPIOxDEB(x) (x)
93 #define MASK_GPIO_DEBEN_GPIOxDEB(x) (0x01 << (x))
95 /* GPIO_ISR1A Fields */
96 #define BIT_GPIO_ISR_GPIOxISR(x) (x)
97 #define MASK_GPIO_ISR_GPIOxISR(x) (0x01 << (x))
99 /* GPIO_IMR1A Fields */
100 #define BIT_GPIO_IMR1A_GPIOxIMR(x) (x)
101 #define MASK_GPIO_IMR1A_GPIOxIMR(x) (0x01 << (x))
103 /* GPIO_SIR1 Fields */
104 #define BIT_GPIO_SIR1_GPIOxSIR(x) (x)
105 #define MASK_GPIO_SIR1_GPIO0SIR (0x01 << (x))
108 /* Control banks : 5 banks for 4 gpios each */
109 #define DATA_CTL_MAX 4
110 #define GET_GPIO_CTL_BANK(x) ((x)/DATA_CTL_MAX)
111 #define GET_GPIO_CTL_OFF(x) ((x)%DATA_CTL_MAX)
112 #define GPIO_BANK_MAX GET_GPIO_CTL_BANK(TWL4030_GPIO_MAX)
114 /* GPIOPUPDCTRx Fields 5 banks of 4 gpios each */
115 #define BIT_GPIOPUPDCTR1_GPIOxPD(x) (2 * (x))
116 #define MASK_GPIOPUPDCTR1_GPIOxPD(x) (0x01 << (2 * (x)))
117 #define BIT_GPIOPUPDCTR1_GPIOxPU(x) ((x) + 1)
118 #define MASK_GPIOPUPDCTR1_GPIOxPU(x) (0x01 << (((2 * (x)) + 1)))
120 /* GPIO_EDR1 Fields */
121 #define BIT_GPIO_EDR1_GPIOxFALLING(x) (2 * (x))
122 #define MASK_GPIO_EDR1_GPIOxFALLING(x) (0x01 << (2 * (x)))
123 #define BIT_GPIO_EDR1_GPIOxRISING(x) ((x) + 1)
124 #define MASK_GPIO_EDR1_GPIOxRISING(x) (0x01 << (((2 * (x)) + 1)))
126 /* GPIO_SIH_CTRL Fields */
127 #define BIT_GPIO_SIH_CTRL_EXCLEN (0x000)
128 #define MASK_GPIO_SIH_CTRL_EXCLEN (0x00000001)
129 #define BIT_GPIO_SIH_CTRL_PENDDIS (0x001)
130 #define MASK_GPIO_SIH_CTRL_PENDDIS (0x00000002)
131 #define BIT_GPIO_SIH_CTRL_COR (0x002)
132 #define MASK_GPIO_SIH_CTRL_COR (0x00000004)
134 /* GPIO_CTRL Fields */
135 #define BIT_GPIO_CTRL_GPIO0CD1 (0x000)
136 #define MASK_GPIO_CTRL_GPIO0CD1 (0x00000001)
137 #define BIT_GPIO_CTRL_GPIO1CD2 (0x001)
138 #define MASK_GPIO_CTRL_GPIO1CD2 (0x00000002)
139 #define BIT_GPIO_CTRL_GPIO_ON (0x002)
140 #define MASK_GPIO_CTRL_GPIO_ON (0x00000004)
142 /* Mask for GPIO registers when aggregated into a 32-bit integer */
143 #define GPIO_32_MASK 0x0003ffff
145 /* Data structures */
146 static DEFINE_MUTEX(gpio_lock);
148 /* store usage of each GPIO. - each bit represents one GPIO */
149 static unsigned int gpio_usage_count;
151 /* shadow the imr register */
152 static unsigned int gpio_imr_shadow;
154 /* bitmask of pending requests to unmask gpio interrupts */
155 static unsigned int gpio_pending_unmask;
157 /* pointer to gpio unmask thread struct */
158 static struct task_struct *gpio_unmask_thread;
161 * Helper functions to read and write the GPIO ISR and IMR registers as
162 * 32-bit integers. Functions return 0 on success, non-zero otherwise.
163 * The caller must hold gpio_lock.
166 static int gpio_read_isr(unsigned int *isr)
171 ret = twl4030_i2c_read(TWL4030_MODULE_GPIO, (u8 *) isr,
174 *isr &= GPIO_32_MASK;
179 static int gpio_write_isr(unsigned int isr)
183 * The buffer passed to the twl4030_i2c_write() routine must have an
184 * extra byte at the beginning reserved for its internal use.
187 isr = cpu_to_le32(isr);
188 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &isr,
192 static int gpio_write_imr(unsigned int imr)
196 * The buffer passed to the twl4030_i2c_write() routine must have an
197 * extra byte at the beginning reserved for its internal use.
200 imr = cpu_to_le32(imr);
201 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &imr,
206 * These routines are analagous to the irqchip methods, but they are designed
207 * to be called from thread context with cpu interrupts enabled and with no
208 * locked spinlocks. We call these routines from our custom IRQ handler
209 * instead of the usual irqchip methods.
211 static void twl4030_gpio_mask_and_ack(unsigned int irq)
213 int gpio = irq - twl4030_gpio_irq_base;
215 mutex_lock(&gpio_lock);
217 gpio_imr_shadow |= (1 << gpio);
218 gpio_write_imr(gpio_imr_shadow);
220 gpio_write_isr(1 << gpio);
221 mutex_unlock(&gpio_lock);
224 static void twl4030_gpio_unmask(unsigned int irq)
226 int gpio = irq - twl4030_gpio_irq_base;
228 mutex_lock(&gpio_lock);
229 gpio_imr_shadow &= ~(1 << gpio);
230 gpio_write_imr(gpio_imr_shadow);
231 mutex_unlock(&gpio_lock);
235 * These are the irqchip methods for the TWL4030 GPIO interrupts.
236 * Our IRQ handle method doesn't call these, but they will be called by
237 * other routines such as setup_irq() and enable_irq(). They are called
238 * with cpu interrupts disabled and with a lock on the irq_controller_lock
239 * spinlock. This complicates matters, because accessing the TWL4030 GPIO
240 * interrupt controller requires I2C bus transactions that can't be initiated
241 * in this context. Our solution is to defer accessing the interrupt
242 * controller to a kernel thread. We only need to support the unmask method.
245 static void twl4030_gpio_mask_and_ack_irqchip(unsigned int irq) {}
246 static void twl4030_gpio_mask_irqchip(unsigned int irq) {}
248 static void twl4030_gpio_unmask_irqchip(unsigned int irq)
250 int gpio = irq - twl4030_gpio_irq_base;
252 gpio_pending_unmask |= (1 << gpio);
253 if (gpio_unmask_thread && gpio_unmask_thread->state != TASK_RUNNING)
254 wake_up_process(gpio_unmask_thread);
257 static struct irq_chip twl4030_gpio_irq_chip = {
259 .ack = twl4030_gpio_mask_and_ack_irqchip,
260 .mask = twl4030_gpio_mask_irqchip,
261 .unmask = twl4030_gpio_unmask_irqchip,
265 * These are the irqchip methods for the TWL4030 PIH GPIO module interrupt.
266 * The PIH module doesn't have interrupt masking capability, so these
269 static void twl4030_gpio_module_ack(unsigned int irq) {}
270 static void twl4030_gpio_module_mask(unsigned int irq) {}
271 static void twl4030_gpio_module_unmask(unsigned int irq) {}
272 static struct irq_chip twl4030_gpio_module_irq_chip = {
273 .ack = twl4030_gpio_module_ack,
274 .mask = twl4030_gpio_module_mask,
275 .unmask = twl4030_gpio_module_unmask,
279 * To configure TWL4030 GPIO module registers
281 static inline int gpio_twl4030_write(u8 address, u8 data)
285 ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, data, address);
290 * To read a TWL4030 GPIO module register
292 static inline int gpio_twl4030_read(u8 address)
297 ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &data, address);
304 * twl4030 GPIO request function
306 int twl4030_request_gpio(int gpio)
310 if (unlikely(gpio >= TWL4030_GPIO_MAX))
313 ret = gpio_request(twl_gpiochip.base + gpio, NULL);
317 mutex_lock(&gpio_lock);
318 if (gpio_usage_count & (0x1 << gpio)) {
321 /* First time usage? - switch on GPIO module */
322 if (!gpio_usage_count) {
323 ret = gpio_twl4030_write(REG_GPIO_CTRL,
324 MASK_GPIO_CTRL_GPIO_ON);
325 ret = gpio_twl4030_write(REG_GPIO_SIH_CTRL, 0x00);
328 gpio_usage_count |= (0x1 << gpio);
330 gpio_free(twl_gpiochip.base + gpio);
332 mutex_unlock(&gpio_lock);
335 EXPORT_SYMBOL(twl4030_request_gpio);
338 * TWL4030 GPIO free module
340 int twl4030_free_gpio(int gpio)
344 if (unlikely(gpio >= TWL4030_GPIO_MAX))
347 mutex_lock(&gpio_lock);
349 if ((gpio_usage_count & (0x1 << gpio)) == 0) {
352 gpio_usage_count &= ~(0x1 << gpio);
353 gpio_free(twl_gpiochip.base + gpio);
356 /* Last time usage? - switch off GPIO module */
357 if (ret == 0 && !gpio_usage_count)
358 ret = gpio_twl4030_write(REG_GPIO_CTRL, 0x0);
360 mutex_unlock(&gpio_lock);
363 EXPORT_SYMBOL(twl4030_free_gpio);
366 * Set direction for TWL4030 GPIO
368 static int twl4030_set_gpio_direction(int gpio, int is_input)
370 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
371 u8 d_msk = MASK_GPIODATADIR_GPIOxDIR(GET_GPIO_DATA_OFF(gpio));
373 u8 base = REG_GPIODATADIR1 + d_bnk;
376 if (unlikely(!(gpio_usage_count & (0x1 << gpio))))
379 mutex_lock(&gpio_lock);
380 ret = gpio_twl4030_read(base);
383 reg = (u8) ((ret) & ~(d_msk));
385 reg = (u8) ((ret) | (d_msk));
387 ret = gpio_twl4030_write(base, reg);
389 mutex_unlock(&gpio_lock);
394 * To enable/disable GPIO pin on TWL4030
396 static int twl4030_set_gpio_dataout(int gpio, int enable)
398 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
399 u8 d_msk = MASK_GPIODATAOUT_GPIOxOUT(GET_GPIO_DATA_OFF(gpio));
403 if (unlikely(!(gpio_usage_count & (0x1 << gpio))))
407 base = REG_SETGPIODATAOUT1 + d_bnk;
409 base = REG_CLEARGPIODATAOUT1 + d_bnk;
411 mutex_lock(&gpio_lock);
412 ret = gpio_twl4030_write(base, d_msk);
413 mutex_unlock(&gpio_lock);
418 * To get the status of a GPIO pin on TWL4030
420 int twl4030_get_gpio_datain(int gpio)
422 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
423 u8 d_off = BIT_GPIODATAIN_GPIOxIN(GET_GPIO_DATA_OFF(gpio));
427 if (unlikely((gpio >= TWL4030_GPIO_MAX)
428 || !(gpio_usage_count & (0x1 << gpio))))
431 base = REG_GPIODATAIN1 + d_bnk;
432 mutex_lock(&gpio_lock);
433 ret = gpio_twl4030_read(base);
434 mutex_unlock(&gpio_lock);
436 ret = (ret >> d_off) & 0x1;
440 EXPORT_SYMBOL(twl4030_get_gpio_datain);
444 * Configure PULL type for a GPIO pin on TWL4030
446 int twl4030_set_gpio_pull(int gpio, int pull_dircn)
448 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
449 u8 c_off = GET_GPIO_CTL_OFF(gpio);
455 if (unlikely((gpio >= TWL4030_GPIO_MAX) ||
456 !(gpio_usage_count & (0x1 << gpio))))
459 base = REG_GPIOPUPDCTR1 + c_bnk;
460 if (pull_dircn == TWL4030_GPIO_PULL_DOWN)
461 c_msk = MASK_GPIOPUPDCTR1_GPIOxPD(c_off);
462 else if (pull_dircn == TWL4030_GPIO_PULL_UP)
463 c_msk = MASK_GPIOPUPDCTR1_GPIOxPU(c_off);
465 mutex_lock(&gpio_lock);
466 ret = gpio_twl4030_read(base);
468 /* clear the previous up/down values */
470 reg &= ~(MASK_GPIOPUPDCTR1_GPIOxPU(c_off) |
471 MASK_GPIOPUPDCTR1_GPIOxPD(c_off));
473 ret = gpio_twl4030_write(base, reg);
475 mutex_unlock(&gpio_lock);
481 * Configure Edge control for a GPIO pin on TWL4030
483 * FIXME this should just be the irq_chip.set_type() method
485 int twl4030_set_gpio_edge_ctrl(int gpio, int edge)
487 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
488 u8 c_off = GET_GPIO_CTL_OFF(gpio);
494 if (unlikely((gpio >= TWL4030_GPIO_MAX)
495 || !(gpio_usage_count & (0x1 << gpio))))
498 base = REG_GPIO_EDR1 + c_bnk;
500 if (edge & TWL4030_GPIO_EDGE_RISING)
501 c_msk |= MASK_GPIO_EDR1_GPIOxRISING(c_off);
503 if (edge & TWL4030_GPIO_EDGE_FALLING)
504 c_msk |= MASK_GPIO_EDR1_GPIOxFALLING(c_off);
506 mutex_lock(&gpio_lock);
507 ret = gpio_twl4030_read(base);
509 /* clear the previous rising/falling values */
512 ~(MASK_GPIO_EDR1_GPIOxFALLING(c_off) |
513 MASK_GPIO_EDR1_GPIOxRISING(c_off)));
515 ret = gpio_twl4030_write(base, reg);
517 mutex_unlock(&gpio_lock);
520 EXPORT_SYMBOL(twl4030_set_gpio_edge_ctrl);
523 * Configure debounce timing value for a GPIO pin on TWL4030
525 int twl4030_set_gpio_debounce(int gpio, int enable)
527 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
528 u8 d_msk = MASK_GPIO_DEBEN_GPIOxDEB(GET_GPIO_DATA_OFF(gpio));
533 if (unlikely((gpio >= TWL4030_GPIO_MAX)
534 || !(gpio_usage_count & (0x1 << gpio))))
537 base = REG_GPIO_DEBEN1 + d_bnk;
538 mutex_lock(&gpio_lock);
539 ret = gpio_twl4030_read(base);
542 reg = (u8) ((ret) | (d_msk));
544 reg = (u8) ((ret) & ~(d_msk));
546 ret = gpio_twl4030_write(base, reg);
548 mutex_unlock(&gpio_lock);
551 EXPORT_SYMBOL(twl4030_set_gpio_debounce);
555 * Configure Card detect for GPIO pin on TWL4030
557 int twl4030_set_gpio_card_detect(int gpio, int enable)
560 u8 msk = (1 << gpio);
563 /* Only GPIO 0 or 1 can be used for CD feature.. */
564 if (unlikely((gpio >= TWL4030_GPIO_MAX)
565 || !(gpio_usage_count & (0x1 << gpio))
566 || (gpio >= TWL4030_GPIO_MAX_CD))) {
570 mutex_lock(&gpio_lock);
571 ret = gpio_twl4030_read(REG_GPIO_CTRL);
574 reg = (u8) (ret | msk);
576 reg = (u8) (ret & ~msk);
578 ret = gpio_twl4030_write(REG_GPIO_CTRL, reg);
580 mutex_unlock(&gpio_lock);
585 /* MODULE FUNCTIONS */
588 * gpio_unmask_thread() runs as a kernel thread. It is awakened by the unmask
589 * method for the GPIO interrupts. It unmasks all of the GPIO interrupts
590 * specified in the gpio_pending_unmask bitmask. We have to do the unmasking
591 * in a kernel thread rather than directly in the unmask method because of the
592 * need to access the TWL4030 via the I2C bus. Note that we don't need to be
593 * concerned about race conditions where the request to unmask a GPIO interrupt
594 * has already been cancelled before this thread does the unmasking. If a GPIO
595 * interrupt is improperly unmasked, then the IRQ handler for it will mask it
596 * when an interrupt occurs.
598 static int twl4030_gpio_unmask_thread(void *data)
600 current->flags |= PF_NOFREEZE;
602 while (!kthread_should_stop()) {
604 unsigned int gpio_unmask;
607 gpio_unmask = gpio_pending_unmask;
608 gpio_pending_unmask = 0;
611 for (irq = twl4030_gpio_irq_base; 0 != gpio_unmask;
612 gpio_unmask >>= 1, irq++) {
613 if (gpio_unmask & 0x1)
614 twl4030_gpio_unmask(irq);
618 if (!gpio_pending_unmask)
619 set_current_state(TASK_INTERRUPTIBLE);
624 set_current_state(TASK_RUNNING);
629 * do_twl4030_gpio_irq() is the desc->handle method for each of the twl4030
630 * gpio interrupts. It executes in kernel thread context.
631 * On entry, cpu interrupts are enabled.
633 static void do_twl4030_gpio_irq(unsigned int irq, irq_desc_t *desc)
635 struct irqaction *action;
636 const unsigned int cpu = smp_processor_id();
638 desc->status |= IRQ_LEVEL;
641 * Acknowledge, clear _AND_ disable the interrupt.
643 twl4030_gpio_mask_and_ack(irq);
646 kstat_cpu(cpu).irqs[irq]++;
648 action = desc->action;
654 /* Call the ISR with cpu interrupts enabled. */
655 ret = action->handler(irq, action->dev_id);
656 if (ret == IRQ_HANDLED)
657 status |= action->flags;
659 action = action->next;
662 if (retval != IRQ_HANDLED)
663 printk(KERN_ERR "ISR for TWL4030 GPIO"
664 " irq %d can't handle interrupt\n",
668 twl4030_gpio_unmask(irq);
674 * do_twl4030_gpio_module_irq() is the desc->handle method for the twl4030 gpio
675 * module interrupt. It executes in kernel thread context.
676 * This is a chained interrupt, so there is no desc->action method for it.
677 * We query the gpio module interrupt controller in the twl4030 to determine
678 * which gpio lines are generating interrupt requests, and then call the
679 * desc->handle method for each gpio that needs service.
680 * On entry, cpu interrupts are disabled.
682 static void do_twl4030_gpio_module_irq(unsigned int irq, irq_desc_t *desc)
684 const unsigned int cpu = smp_processor_id();
686 desc->status |= IRQ_LEVEL;
688 * The desc->handle method would normally call the desc->chip->ack
689 * method here, but we won't bother since our ack method is NULL.
693 unsigned int gpio_isr;
695 kstat_cpu(cpu).irqs[irq]++;
698 mutex_lock(&gpio_lock);
699 if (gpio_read_isr(&gpio_isr))
701 mutex_unlock(&gpio_lock);
703 for (gpio_irq = twl4030_gpio_irq_base; 0 != gpio_isr;
704 gpio_isr >>= 1, gpio_irq++) {
705 if (gpio_isr & 0x1) {
706 irq_desc_t *d = irq_desc + gpio_irq;
707 d->handle_irq(gpio_irq, d);
713 * Here is where we should call the unmask method, but again we
714 * won't bother since it is NULL.
719 /*----------------------------------------------------------------------*/
721 static int twl_direction_in(struct gpio_chip *chip, unsigned offset)
723 return twl4030_set_gpio_direction(offset, 1);
726 static int twl_get(struct gpio_chip *chip, unsigned offset)
728 int status = twl4030_get_gpio_datain(offset);
730 return (status < 0) ? 0 : status;
733 static int twl_direction_out(struct gpio_chip *chip, unsigned offset, int value)
735 twl4030_set_gpio_dataout(offset, value);
736 return twl4030_set_gpio_direction(offset, 0);
739 static void twl_set(struct gpio_chip *chip, unsigned offset, int value)
741 twl4030_set_gpio_dataout(offset, value);
744 static struct gpio_chip twl_gpiochip = {
746 .owner = THIS_MODULE,
747 .direction_input = twl_direction_in,
749 .direction_output = twl_direction_out,
754 /*----------------------------------------------------------------------*/
756 static int gpio_twl4030_remove(struct platform_device *pdev);
758 static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
760 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
764 /* All GPIO interrupts are initially masked */
765 gpio_pending_unmask = 0;
766 gpio_imr_shadow = GPIO_32_MASK;
767 ret = gpio_write_imr(gpio_imr_shadow);
769 twl4030_gpio_irq_base = pdata->irq_base;
770 twl4030_gpio_irq_end = pdata->irq_end;
772 if ((twl4030_gpio_irq_end - twl4030_gpio_irq_base) > 0) {
775 "can't dispatch IRQs from modules\n");
778 if (twl4030_gpio_irq_end > NR_IRQS) {
780 "last IRQ is too large: %d\n",
781 twl4030_gpio_irq_end);
785 dev_notice(&pdev->dev,
786 "no IRQs being dispatched\n");
792 * Create a kernel thread to handle deferred unmasking of gpio
795 gpio_unmask_thread = kthread_create(twl4030_gpio_unmask_thread,
796 NULL, "twl4030 gpio");
797 if (!gpio_unmask_thread) {
799 "could not create twl4030 gpio unmask"
806 /* install an irq handler for each of the gpio interrupts */
807 for (irq = twl4030_gpio_irq_base; irq < twl4030_gpio_irq_end;
809 set_irq_chip(irq, &twl4030_gpio_irq_chip);
810 set_irq_handler(irq, do_twl4030_gpio_irq);
811 set_irq_flags(irq, IRQF_VALID);
814 /* gpio module IRQ */
815 irq = platform_get_irq(pdev, 0);
818 * Install an irq handler to demultiplex the gpio module
821 set_irq_chip(irq, &twl4030_gpio_module_irq_chip);
822 set_irq_chained_handler(irq, do_twl4030_gpio_module_irq);
823 wake_up_process(gpio_unmask_thread);
825 dev_info(&pdev->dev, "IRQ %d chains IRQs %d..%d\n", irq,
826 twl4030_gpio_irq_base, twl4030_gpio_irq_end - 1);
831 twl_gpiochip.base = pdata->gpio_base;
832 twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
833 twl_gpiochip.dev = &pdev->dev;
835 ret = gpiochip_add(&twl_gpiochip);
838 "could not register gpiochip, %d\n",
840 twl_gpiochip.ngpio = 0;
841 gpio_twl4030_remove(pdev);
842 } else if (pdata->setup) {
845 status = pdata->setup(&pdev->dev,
846 pdata->gpio_base, TWL4030_GPIO_MAX);
848 dev_dbg(&pdev->dev, "setup --> %d\n", status);
855 static int __devexit gpio_twl4030_remove(struct platform_device *pdev)
857 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
861 if (pdata->teardown) {
862 status = pdata->teardown(&pdev->dev,
863 pdata->gpio_base, TWL4030_GPIO_MAX);
865 dev_dbg(&pdev->dev, "teardown --> %d\n", status);
870 status = gpiochip_remove(&twl_gpiochip);
874 if (is_module() || (twl4030_gpio_irq_end - twl4030_gpio_irq_base) <= 0)
877 /* uninstall the gpio demultiplexing interrupt handler */
878 irq = platform_get_irq(pdev, 0);
879 set_irq_handler(irq, NULL);
880 set_irq_flags(irq, 0);
882 /* uninstall the irq handler for each of the gpio interrupts */
883 for (irq = twl4030_gpio_irq_base; irq < twl4030_gpio_irq_end; irq++) {
884 set_irq_handler(irq, NULL);
885 set_irq_flags(irq, 0);
888 /* stop the gpio unmask kernel thread */
889 if (gpio_unmask_thread) {
890 kthread_stop(gpio_unmask_thread);
891 gpio_unmask_thread = NULL;
897 /* Note: this hardware lives inside an I2C-based multi-function device. */
898 MODULE_ALIAS("platform:twl4030_gpio");
900 static struct platform_driver gpio_twl4030_driver = {
901 .driver.name = "twl4030_gpio",
902 .driver.owner = THIS_MODULE,
903 .probe = gpio_twl4030_probe,
904 .remove = __devexit_p(gpio_twl4030_remove),
907 static int __init gpio_twl4030_init(void)
909 return platform_driver_register(&gpio_twl4030_driver);
911 subsys_initcall(gpio_twl4030_init);
913 static void __exit gpio_twl4030_exit(void)
915 platform_driver_unregister(&gpio_twl4030_driver);
917 module_exit(gpio_twl4030_exit);
919 MODULE_AUTHOR("Texas Instruments, Inc.");
920 MODULE_DESCRIPTION("GPIO interface for TWL4030");
921 MODULE_LICENSE("GPL");