drivers/firewire/fw-ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/compiler.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/gfp.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/kernel.h>
  28 #include <linux/mm.h>
  29 #include <linux/module.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/pci.h>
  32 #include <linux/spinlock.h>
  33
  34 #include <asm/page.h>
  35 #include <asm/system.h>
  36
  37 #ifdef CONFIG_PPC_PMAC
  38 #include <asm/pmac_feature.h>
  39 #endif
  40
  41 #include "fw-ohci.h"
  42 #include "fw-transaction.h"
  43
  44 #define DESCRIPTOR_OUTPUT_MORE          0
  45 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  46 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  47 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  48 #define DESCRIPTOR_STATUS               (1 << 11)
  49 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  50 #define DESCRIPTOR_PING                 (1 << 7)
  51 #define DESCRIPTOR_YY                   (1 << 6)
  52 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  53 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  54 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  55 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  56 #define DESCRIPTOR_WAIT                 (3 << 0)
  57
  58 struct descriptor {
  59         __le16 req_count;
  60         __le16 control;
  61         __le32 data_address;
  62         __le32 branch_address;
  63         __le16 res_count;
  64         __le16 transfer_status;
  65 } __attribute__((aligned(16)));
  66
  67 struct db_descriptor {
  68         __le16 first_size;
  69         __le16 control;
  70         __le16 second_req_count;
  71         __le16 first_req_count;
  72         __le32 branch_address;
  73         __le16 second_res_count;
  74         __le16 first_res_count;
  75         __le32 reserved0;
  76         __le32 first_buffer;
  77         __le32 second_buffer;
  78         __le32 reserved1;
  79 } __attribute__((aligned(16)));
  80
  81 #define CONTROL_SET(regs)       (regs)
  82 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  83 #define COMMAND_PTR(regs)       ((regs) + 12)
  84 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  85
  86 struct ar_buffer {
  87         struct descriptor descriptor;
  88         struct ar_buffer *next;
  89         __le32 data[0];
  90 };
  91
  92 struct ar_context {
  93         struct fw_ohci *ohci;
  94         struct ar_buffer *current_buffer;
  95         struct ar_buffer *last_buffer;
  96         void *pointer;
  97         u32 regs;
  98         struct tasklet_struct tasklet;
  99 };
 100
 101 struct context;
 102
 103 typedef int (*descriptor_callback_t)(struct context *ctx,
 104                                      struct descriptor *d,
 105                                      struct descriptor *last);
 106
 107 /*
 108  * A buffer that contains a block of DMA-able coherent memory used for
 109  * storing a portion of a DMA descriptor program.
 110  */
 111 struct descriptor_buffer {
 112         struct list_head list;
 113         dma_addr_t buffer_bus;
 114         size_t buffer_size;
 115         size_t used;
 116         struct descriptor buffer[0];
 117 };
 118
 119 struct context {
 120         struct fw_ohci *ohci;
 121         u32 regs;
 122         int total_allocation;
 123
 124         /*
 125          * List of page-sized buffers for storing DMA descriptors.
 126          * Head of list contains buffers in use and tail of list contains
 127          * free buffers.
 128          */
 129         struct list_head buffer_list;
 130
 131         /*
 132          * Pointer to a buffer inside buffer_list that contains the tail
 133          * end of the current DMA program.
 134          */
 135         struct descriptor_buffer *buffer_tail;
 136
 137         /*
 138          * The descriptor containing the branch address of the first
 139          * descriptor that has not yet been filled by the device.
 140          */
 141         struct descriptor *last;
 142
 143         /*
 144          * The last descriptor in the DMA program.  It contains the branch
 145          * address that must be updated upon appending a new descriptor.
 146          */
 147         struct descriptor *prev;
 148
 149         descriptor_callback_t callback;
 150
 151         struct tasklet_struct tasklet;
 152 };
 153
 154 #define IT_HEADER_SY(v)          ((v) <<  0)
 155 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 156 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 157 #define IT_HEADER_TAG(v)         ((v) << 14)
 158 #define IT_HEADER_SPEED(v)       ((v) << 16)
 159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 160
 161 struct iso_context {
 162         struct fw_iso_context base;
 163         struct context context;
 164         int excess_bytes;
 165         void *header;
 166         size_t header_length;
 167 };
 168
 169 #define CONFIG_ROM_SIZE 1024
 170
 171 struct fw_ohci {
 172         struct fw_card card;
 173
 174         u32 version;
 175         __iomem char *registers;
 176         dma_addr_t self_id_bus;
 177         __le32 *self_id_cpu;
 178         struct tasklet_struct bus_reset_tasklet;
 179         int node_id;
 180         int generation;
 181         int request_generation;
 182         u32 bus_seconds;
 183         bool old_uninorth;
 184
 185         /*
 186          * Spinlock for accessing fw_ohci data.  Never call out of
 187          * this driver with this lock held.
 188          */
 189         spinlock_t lock;
 190         u32 self_id_buffer[512];
 191
 192         /* Config rom buffers */
 193         __be32 *config_rom;
 194         dma_addr_t config_rom_bus;
 195         __be32 *next_config_rom;
 196         dma_addr_t next_config_rom_bus;
 197         u32 next_header;
 198
 199         struct ar_context ar_request_ctx;
 200         struct ar_context ar_response_ctx;
 201         struct context at_request_ctx;
 202         struct context at_response_ctx;
 203
 204         u32 it_context_mask;
 205         struct iso_context *it_context_list;
 206         u32 ir_context_mask;
 207         struct iso_context *ir_context_list;
 208 };
 209
 210 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 211 {
 212         return container_of(card, struct fw_ohci, card);
 213 }
 214
 215 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 216 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 217 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 218 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 219 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 220 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 221
 222 #define CONTEXT_RUN     0x8000
 223 #define CONTEXT_WAKE    0x1000
 224 #define CONTEXT_DEAD    0x0800
 225 #define CONTEXT_ACTIVE  0x0400
 226
 227 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
 228 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 229 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 230
 231 #define FW_OHCI_MAJOR                   240
 232 #define OHCI1394_REGISTER_SIZE          0x800
 233 #define OHCI_LOOP_COUNT                 500
 234 #define OHCI1394_PCI_HCI_Control        0x40
 235 #define SELF_ID_BUF_SIZE                0x800
 236 #define OHCI_TCODE_PHY_PACKET           0x0e
 237 #define OHCI_VERSION_1_1                0x010010
 238
 239 static char ohci_driver_name[] = KBUILD_MODNAME;
 240
 241 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 242
 243 #define OHCI_PARAM_DEBUG_IRQS           1
 244 #define OHCI_PARAM_DEBUG_SELFIDS        2
 245 #define OHCI_PARAM_DEBUG_AT_AR          4
 246
 247 static int param_debug;
 248 module_param_named(debug, param_debug, int, 0644);
 249 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 250         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 251         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 252         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 253         ", or a combination, or all = -1)");
 254
 255 static void log_irqs(u32 evt)
 256 {
 257         if (likely(!(param_debug & OHCI_PARAM_DEBUG_IRQS)))
 258                 return;
 259
 260         printk(KERN_DEBUG KBUILD_MODNAME ": IRQ %08x%s%s%s%s%s%s%s%s%s%s%s\n",
 261                evt,
 262                evt & OHCI1394_selfIDComplete    ? " selfID"             : "",
 263                evt & OHCI1394_RQPkt             ? " AR_req"             : "",
 264                evt & OHCI1394_RSPkt             ? " AR_resp"            : "",
 265                evt & OHCI1394_reqTxComplete     ? " AT_req"             : "",
 266                evt & OHCI1394_respTxComplete    ? " AT_resp"            : "",
 267                evt & OHCI1394_isochRx           ? " IR"                 : "",
 268                evt & OHCI1394_isochTx           ? " IT"                 : "",
 269                evt & OHCI1394_postedWriteErr    ? " postedWriteErr"     : "",
 270                evt & OHCI1394_cycleTooLong      ? " cycleTooLong"       : "",
 271                evt & OHCI1394_cycle64Seconds    ? " cycle64Seconds"     : "",
 272                evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 273                        OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 274                        OHCI1394_respTxComplete | OHCI1394_isochRx |
 275                        OHCI1394_isochTx | OHCI1394_postedWriteErr |
 276                        OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds)
 277                                                 ? " ?"                  : "");
 278 }
 279
 280 static const char *speed[] = {
 281         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 282 };
 283 static const char *power[] = {
 284         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 285         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 286 };
 287 static const char port[] = { '.', '-', 'p', 'c', };
 288
 289 static char _p(u32 *s, int shift)
 290 {
 291         return port[*s >> shift & 3];
 292 }
 293
 294 static void log_selfids(int generation, int self_id_count, u32 *s)
 295 {
 296         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 297                 return;
 298
 299         printk(KERN_DEBUG KBUILD_MODNAME ": %d selfIDs, generation %d\n",
 300                self_id_count, generation);
 301
 302         for (; self_id_count--; ++s)
 303                 if ((*s & 1 << 23) == 0)
 304                         printk(KERN_DEBUG "selfID 0: %08x, phy %d [%c%c%c] "
 305                                "%s gc=%d %s %s%s%s\n",
 306                                *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 307                                speed[*s >> 14 & 3], *s >> 16 & 63,
 308                                power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 309                                *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 310                 else
 311                         printk(KERN_DEBUG "selfID n: %08x, phy %d "
 312                                "[%c%c%c%c%c%c%c%c]\n",
 313                                *s, *s >> 24 & 63,
 314                                _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 315                                _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 316 }
 317
 318 static const char *evts[] = {
 319         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 320         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 321         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 322         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 323         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 324         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 325         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 326         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 327         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 328         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 329         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 330         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 331         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 332         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 333         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 334         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 335         [0x20] = "pending/cancelled",
 336 };
 337 static const char *tcodes[] = {
 338         [0x0] = "QW req",               [0x1] = "BW req",
 339         [0x2] = "W resp",               [0x3] = "-reserved-",
 340         [0x4] = "QR req",               [0x5] = "BR req",
 341         [0x6] = "QR resp",              [0x7] = "BR resp",
 342         [0x8] = "cycle start",          [0x9] = "Lk req",
 343         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 344         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 345         [0xe] = "link internal",        [0xf] = "-reserved-",
 346 };
 347 static const char *phys[] = {
 348         [0x0] = "phy config packet",    [0x1] = "link-on packet",
 349         [0x2] = "self-id packet",       [0x3] = "-reserved-",
 350 };
 351
 352 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 353 {
 354         int tcode = header[0] >> 4 & 0xf;
 355         char specific[12];
 356
 357         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 358                 return;
 359
 360         if (unlikely(evt >= ARRAY_SIZE(evts)))
 361                         evt = 0x1f;
 362
 363         if (header[0] == ~header[1]) {
 364                 printk(KERN_DEBUG "A%c %s, %s, %08x\n",
 365                        dir, evts[evt], phys[header[0] >> 30 & 0x3],
 366                        header[0]);
 367                 return;
 368         }
 369
 370         switch (tcode) {
 371         case 0x0: case 0x6: case 0x8:
 372                 snprintf(specific, sizeof(specific), " = %08x",
 373                          be32_to_cpu((__force __be32)header[3]));
 374                 break;
 375         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 376                 snprintf(specific, sizeof(specific), " %x,%x",
 377                          header[3] >> 16, header[3] & 0xffff);
 378                 break;
 379         default:
 380                 specific[0] = '\0';
 381         }
 382
 383         switch (tcode) {
 384         case 0xe: case 0xa:
 385                 printk(KERN_DEBUG "A%c %s, %s\n",
 386                        dir, evts[evt], tcodes[tcode]);
 387                 break;
 388         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 389                 printk(KERN_DEBUG "A%c spd %x tl %02x, "
 390                        "%04x -> %04x, %s, "
 391                        "%s, %04x%08x%s\n",
 392                        dir, speed, header[0] >> 10 & 0x3f,
 393                        header[1] >> 16, header[0] >> 16, evts[evt],
 394                        tcodes[tcode], header[1] & 0xffff, header[2], specific);
 395                 break;
 396         default:
 397                 printk(KERN_DEBUG "A%c spd %x tl %02x, "
 398                        "%04x -> %04x, %s, "
 399                        "%s%s\n",
 400                        dir, speed, header[0] >> 10 & 0x3f,
 401                        header[1] >> 16, header[0] >> 16, evts[evt],
 402                        tcodes[tcode], specific);
 403         }
 404 }
 405
 406 #else
 407
 408 #define log_irqs(evt)
 409 #define log_selfids(generation, self_id_count, sid)
 410 #define log_ar_at_event(dir, speed, header, evt)
 411
 412 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 413
 414 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 415 {
 416         writel(data, ohci->registers + offset);
 417 }
 418
 419 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 420 {
 421         return readl(ohci->registers + offset);
 422 }
 423
 424 static inline void flush_writes(const struct fw_ohci *ohci)
 425 {
 426         /* Do a dummy read to flush writes. */
 427         reg_read(ohci, OHCI1394_Version);
 428 }
 429
 430 static int
 431 ohci_update_phy_reg(struct fw_card *card, int addr,
 432                     int clear_bits, int set_bits)
 433 {
 434         struct fw_ohci *ohci = fw_ohci(card);
 435         u32 val, old;
 436
 437         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 438         flush_writes(ohci);
 439         msleep(2);
 440         val = reg_read(ohci, OHCI1394_PhyControl);
 441         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
 442                 fw_error("failed to set phy reg bits.\n");
 443                 return -EBUSY;
 444         }
 445
 446         old = OHCI1394_PhyControl_ReadData(val);
 447         old = (old & ~clear_bits) | set_bits;
 448         reg_write(ohci, OHCI1394_PhyControl,
 449                   OHCI1394_PhyControl_Write(addr, old));
 450
 451         return 0;
 452 }
 453
 454 static int ar_context_add_page(struct ar_context *ctx)
 455 {
 456         struct device *dev = ctx->ohci->card.device;
 457         struct ar_buffer *ab;
 458         dma_addr_t uninitialized_var(ab_bus);
 459         size_t offset;
 460
 461         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
 462         if (ab == NULL)
 463                 return -ENOMEM;
 464
 465         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 466         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 467                                                     DESCRIPTOR_STATUS |
 468                                                     DESCRIPTOR_BRANCH_ALWAYS);
 469         offset = offsetof(struct ar_buffer, data);
 470         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 471         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 472         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 473         ab->descriptor.branch_address = 0;
 474
 475         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 476         ctx->last_buffer->next = ab;
 477         ctx->last_buffer = ab;
 478
 479         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 480         flush_writes(ctx->ohci);
 481
 482         return 0;
 483 }
 484
 485 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 486 #define cond_le32_to_cpu(v) \
 487         (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
 488 #else
 489 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 490 #endif
 491
 492 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 493 {
 494         struct fw_ohci *ohci = ctx->ohci;
 495         struct fw_packet p;
 496         u32 status, length, tcode;
 497         int evt;
 498
 499         p.header[0] = cond_le32_to_cpu(buffer[0]);
 500         p.header[1] = cond_le32_to_cpu(buffer[1]);
 501         p.header[2] = cond_le32_to_cpu(buffer[2]);
 502
 503         tcode = (p.header[0] >> 4) & 0x0f;
 504         switch (tcode) {
 505         case TCODE_WRITE_QUADLET_REQUEST:
 506         case TCODE_READ_QUADLET_RESPONSE:
 507                 p.header[3] = (__force __u32) buffer[3];
 508                 p.header_length = 16;
 509                 p.payload_length = 0;
 510                 break;
 511
 512         case TCODE_READ_BLOCK_REQUEST :
 513                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 514                 p.header_length = 16;
 515                 p.payload_length = 0;
 516                 break;
 517
 518         case TCODE_WRITE_BLOCK_REQUEST:
 519         case TCODE_READ_BLOCK_RESPONSE:
 520         case TCODE_LOCK_REQUEST:
 521         case TCODE_LOCK_RESPONSE:
 522                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 523                 p.header_length = 16;
 524                 p.payload_length = p.header[3] >> 16;
 525                 break;
 526
 527         case TCODE_WRITE_RESPONSE:
 528         case TCODE_READ_QUADLET_REQUEST:
 529         case OHCI_TCODE_PHY_PACKET:
 530                 p.header_length = 12;
 531                 p.payload_length = 0;
 532                 break;
 533         }
 534
 535         p.payload = (void *) buffer + p.header_length;
 536
 537         /* FIXME: What to do about evt_* errors? */
 538         length = (p.header_length + p.payload_length + 3) / 4;
 539         status = cond_le32_to_cpu(buffer[length]);
 540         evt    = (status >> 16) & 0x1f;
 541
 542         p.ack        = evt - 16;
 543         p.speed      = (status >> 21) & 0x7;
 544         p.timestamp  = status & 0xffff;
 545         p.generation = ohci->request_generation;
 546
 547         log_ar_at_event('R', p.speed, p.header, evt);
 548
 549         /*
 550          * The OHCI bus reset handler synthesizes a phy packet with
 551          * the new generation number when a bus reset happens (see
 552          * section 8.4.2.3).  This helps us determine when a request
 553          * was received and make sure we send the response in the same
 554          * generation.  We only need this for requests; for responses
 555          * we use the unique tlabel for finding the matching
 556          * request.
 557          */
 558
 559         if (evt == OHCI1394_evt_bus_reset)
 560                 ohci->request_generation = (p.header[2] >> 16) & 0xff;
 561         else if (ctx == &ohci->ar_request_ctx)
 562                 fw_core_handle_request(&ohci->card, &p);
 563         else
 564                 fw_core_handle_response(&ohci->card, &p);
 565
 566         return buffer + length + 1;
 567 }
 568
 569 static void ar_context_tasklet(unsigned long data)
 570 {
 571         struct ar_context *ctx = (struct ar_context *)data;
 572         struct fw_ohci *ohci = ctx->ohci;
 573         struct ar_buffer *ab;
 574         struct descriptor *d;
 575         void *buffer, *end;
 576
 577         ab = ctx->current_buffer;
 578         d = &ab->descriptor;
 579
 580         if (d->res_count == 0) {
 581                 size_t size, rest, offset;
 582                 dma_addr_t start_bus;
 583                 void *start;
 584
 585                 /*
 586                  * This descriptor is finished and we may have a
 587                  * packet split across this and the next buffer. We
 588                  * reuse the page for reassembling the split packet.
 589                  */
 590
 591                 offset = offsetof(struct ar_buffer, data);
 592                 start = buffer = ab;
 593                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 594
 595                 ab = ab->next;
 596                 d = &ab->descriptor;
 597                 size = buffer + PAGE_SIZE - ctx->pointer;
 598                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 599                 memmove(buffer, ctx->pointer, size);
 600                 memcpy(buffer + size, ab->data, rest);
 601                 ctx->current_buffer = ab;
 602                 ctx->pointer = (void *) ab->data + rest;
 603                 end = buffer + size + rest;
 604
 605                 while (buffer < end)
 606                         buffer = handle_ar_packet(ctx, buffer);
 607
 608                 dma_free_coherent(ohci->card.device, PAGE_SIZE,
 609                                   start, start_bus);
 610                 ar_context_add_page(ctx);
 611         } else {
 612                 buffer = ctx->pointer;
 613                 ctx->pointer = end =
 614                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 615
 616                 while (buffer < end)
 617                         buffer = handle_ar_packet(ctx, buffer);
 618         }
 619 }
 620
 621 static int
 622 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
 623 {
 624         struct ar_buffer ab;
 625
 626         ctx->regs        = regs;
 627         ctx->ohci        = ohci;
 628         ctx->last_buffer = &ab;
 629         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 630
 631         ar_context_add_page(ctx);
 632         ar_context_add_page(ctx);
 633         ctx->current_buffer = ab.next;
 634         ctx->pointer = ctx->current_buffer->data;
 635
 636         return 0;
 637 }
 638
 639 static void ar_context_run(struct ar_context *ctx)
 640 {
 641         struct ar_buffer *ab = ctx->current_buffer;
 642         dma_addr_t ab_bus;
 643         size_t offset;
 644
 645         offset = offsetof(struct ar_buffer, data);
 646         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 647
 648         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 649         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 650         flush_writes(ctx->ohci);
 651 }
 652
 653 static struct descriptor *
 654 find_branch_descriptor(struct descriptor *d, int z)
 655 {
 656         int b, key;
 657
 658         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
 659         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
 660
 661         /* figure out which descriptor the branch address goes in */
 662         if (z == 2 && (b == 3 || key == 2))
 663                 return d;
 664         else
 665                 return d + z - 1;
 666 }
 667
 668 static void context_tasklet(unsigned long data)
 669 {
 670         struct context *ctx = (struct context *) data;
 671         struct descriptor *d, *last;
 672         u32 address;
 673         int z;
 674         struct descriptor_buffer *desc;
 675
 676         desc = list_entry(ctx->buffer_list.next,
 677                         struct descriptor_buffer, list);
 678         last = ctx->last;
 679         while (last->branch_address != 0) {
 680                 struct descriptor_buffer *old_desc = desc;
 681                 address = le32_to_cpu(last->branch_address);
 682                 z = address & 0xf;
 683                 address &= ~0xf;
 684
 685                 /* If the branch address points to a buffer outside of the
 686                  * current buffer, advance to the next buffer. */
 687                 if (address < desc->buffer_bus ||
 688                                 address >= desc->buffer_bus + desc->used)
 689                         desc = list_entry(desc->list.next,
 690                                         struct descriptor_buffer, list);
 691                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
 692                 last = find_branch_descriptor(d, z);
 693
 694                 if (!ctx->callback(ctx, d, last))
 695                         break;
 696
 697                 if (old_desc != desc) {
 698                         /* If we've advanced to the next buffer, move the
 699                          * previous buffer to the free list. */
 700                         unsigned long flags;
 701                         old_desc->used = 0;
 702                         spin_lock_irqsave(&ctx->ohci->lock, flags);
 703                         list_move_tail(&old_desc->list, &ctx->buffer_list);
 704                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 705                 }
 706                 ctx->last = last;
 707         }
 708 }
 709
 710 /*
 711  * Allocate a new buffer and add it to the list of free buffers for this
 712  * context.  Must be called with ohci->lock held.
 713  */
 714 static int
 715 context_add_buffer(struct context *ctx)
 716 {
 717         struct descriptor_buffer *desc;
 718         dma_addr_t uninitialized_var(bus_addr);
 719         int offset;
 720
 721         /*
 722          * 16MB of descriptors should be far more than enough for any DMA
 723          * program.  This will catch run-away userspace or DoS attacks.
 724          */
 725         if (ctx->total_allocation >= 16*1024*1024)
 726                 return -ENOMEM;
 727
 728         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
 729                         &bus_addr, GFP_ATOMIC);
 730         if (!desc)
 731                 return -ENOMEM;
 732
 733         offset = (void *)&desc->buffer - (void *)desc;
 734         desc->buffer_size = PAGE_SIZE - offset;
 735         desc->buffer_bus = bus_addr + offset;
 736         desc->used = 0;
 737
 738         list_add_tail(&desc->list, &ctx->buffer_list);
 739         ctx->total_allocation += PAGE_SIZE;
 740
 741         return 0;
 742 }
 743
 744 static int
 745 context_init(struct context *ctx, struct fw_ohci *ohci,
 746              u32 regs, descriptor_callback_t callback)
 747 {
 748         ctx->ohci = ohci;
 749         ctx->regs = regs;
 750         ctx->total_allocation = 0;
 751
 752         INIT_LIST_HEAD(&ctx->buffer_list);
 753         if (context_add_buffer(ctx) < 0)
 754                 return -ENOMEM;
 755
 756         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
 757                         struct descriptor_buffer, list);
 758
 759         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 760         ctx->callback = callback;
 761
 762         /*
 763          * We put a dummy descriptor in the buffer that has a NULL
 764          * branch address and looks like it's been sent.  That way we
 765          * have a descriptor to append DMA programs to.
 766          */
 767         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
 768         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 769         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
 770         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
 771         ctx->last = ctx->buffer_tail->buffer;
 772         ctx->prev = ctx->buffer_tail->buffer;
 773
 774         return 0;
 775 }
 776
 777 static void
 778 context_release(struct context *ctx)
 779 {
 780         struct fw_card *card = &ctx->ohci->card;
 781         struct descriptor_buffer *desc, *tmp;
 782
 783         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
 784                 dma_free_coherent(card->device, PAGE_SIZE, desc,
 785                         desc->buffer_bus -
 786                         ((void *)&desc->buffer - (void *)desc));
 787 }
 788
 789 /* Must be called with ohci->lock held */
 790 static struct descriptor *
 791 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
 792 {
 793         struct descriptor *d = NULL;
 794         struct descriptor_buffer *desc = ctx->buffer_tail;
 795
 796         if (z * sizeof(*d) > desc->buffer_size)
 797                 return NULL;
 798
 799         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
 800                 /* No room for the descriptor in this buffer, so advance to the
 801                  * next one. */
 802
 803                 if (desc->list.next == &ctx->buffer_list) {
 804                         /* If there is no free buffer next in the list,
 805                          * allocate one. */
 806                         if (context_add_buffer(ctx) < 0)
 807                                 return NULL;
 808                 }
 809                 desc = list_entry(desc->list.next,
 810                                 struct descriptor_buffer, list);
 811                 ctx->buffer_tail = desc;
 812         }
 813
 814         d = desc->buffer + desc->used / sizeof(*d);
 815         memset(d, 0, z * sizeof(*d));
 816         *d_bus = desc->buffer_bus + desc->used;
 817
 818         return d;
 819 }
 820
 821 static void context_run(struct context *ctx, u32 extra)
 822 {
 823         struct fw_ohci *ohci = ctx->ohci;
 824
 825         reg_write(ohci, COMMAND_PTR(ctx->regs),
 826                   le32_to_cpu(ctx->last->branch_address));
 827         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
 828         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
 829         flush_writes(ohci);
 830 }
 831
 832 static void context_append(struct context *ctx,
 833                            struct descriptor *d, int z, int extra)
 834 {
 835         dma_addr_t d_bus;
 836         struct descriptor_buffer *desc = ctx->buffer_tail;
 837
 838         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
 839
 840         desc->used += (z + extra) * sizeof(*d);
 841         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
 842         ctx->prev = find_branch_descriptor(d, z);
 843
 844         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 845         flush_writes(ctx->ohci);
 846 }
 847
 848 static void context_stop(struct context *ctx)
 849 {
 850         u32 reg;
 851         int i;
 852
 853         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 854         flush_writes(ctx->ohci);
 855
 856         for (i = 0; i < 10; i++) {
 857                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 858                 if ((reg & CONTEXT_ACTIVE) == 0)
 859                         break;
 860
 861                 fw_notify("context_stop: still active (0x%08x)\n", reg);
 862                 mdelay(1);
 863         }
 864 }
 865
 866 struct driver_data {
 867         struct fw_packet *packet;
 868 };
 869
 870 /*
 871  * This function apppends a packet to the DMA queue for transmission.
 872  * Must always be called with the ochi->lock held to ensure proper
 873  * generation handling and locking around packet queue manipulation.
 874  */
 875 static int
 876 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
 877 {
 878         struct fw_ohci *ohci = ctx->ohci;
 879         dma_addr_t d_bus, uninitialized_var(payload_bus);
 880         struct driver_data *driver_data;
 881         struct descriptor *d, *last;
 882         __le32 *header;
 883         int z, tcode;
 884         u32 reg;
 885
 886         d = context_get_descriptors(ctx, 4, &d_bus);
 887         if (d == NULL) {
 888                 packet->ack = RCODE_SEND_ERROR;
 889                 return -1;
 890         }
 891
 892         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
 893         d[0].res_count = cpu_to_le16(packet->timestamp);
 894
 895         /*
 896          * The DMA format for asyncronous link packets is different
 897          * from the IEEE1394 layout, so shift the fields around
 898          * accordingly.  If header_length is 8, it's a PHY packet, to
 899          * which we need to prepend an extra quadlet.
 900          */
 901
 902         header = (__le32 *) &d[1];
 903         if (packet->header_length > 8) {
 904                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 905                                         (packet->speed << 16));
 906                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 907                                         (packet->header[0] & 0xffff0000));
 908                 header[2] = cpu_to_le32(packet->header[2]);
 909
 910                 tcode = (packet->header[0] >> 4) & 0x0f;
 911                 if (TCODE_IS_BLOCK_PACKET(tcode))
 912                         header[3] = cpu_to_le32(packet->header[3]);
 913                 else
 914                         header[3] = (__force __le32) packet->header[3];
 915
 916                 d[0].req_count = cpu_to_le16(packet->header_length);
 917         } else {
 918                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
 919                                         (packet->speed << 16));
 920                 header[1] = cpu_to_le32(packet->header[0]);
 921                 header[2] = cpu_to_le32(packet->header[1]);
 922                 d[0].req_count = cpu_to_le16(12);
 923         }
 924
 925         driver_data = (struct driver_data *) &d[3];
 926         driver_data->packet = packet;
 927         packet->driver_data = driver_data;
 928
 929         if (packet->payload_length > 0) {
 930                 payload_bus =
 931                         dma_map_single(ohci->card.device, packet->payload,
 932                                        packet->payload_length, DMA_TO_DEVICE);
 933                 if (dma_mapping_error(payload_bus)) {
 934                         packet->ack = RCODE_SEND_ERROR;
 935                         return -1;
 936                 }
 937
 938                 d[2].req_count    = cpu_to_le16(packet->payload_length);
 939                 d[2].data_address = cpu_to_le32(payload_bus);
 940                 last = &d[2];
 941                 z = 3;
 942         } else {
 943                 last = &d[0];
 944                 z = 2;
 945         }
 946
 947         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
 948                                      DESCRIPTOR_IRQ_ALWAYS |
 949                                      DESCRIPTOR_BRANCH_ALWAYS);
 950
 951         /* FIXME: Document how the locking works. */
 952         if (ohci->generation != packet->generation) {
 953                 if (packet->payload_length > 0)
 954                         dma_unmap_single(ohci->card.device, payload_bus,
 955                                          packet->payload_length, DMA_TO_DEVICE);
 956                 packet->ack = RCODE_GENERATION;
 957                 return -1;
 958         }
 959
 960         context_append(ctx, d, z, 4 - z);
 961
 962         /* If the context isn't already running, start it up. */
 963         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 964         if ((reg & CONTEXT_RUN) == 0)
 965                 context_run(ctx, 0);
 966
 967         return 0;
 968 }
 969
 970 static int handle_at_packet(struct context *context,
 971                             struct descriptor *d,
 972                             struct descriptor *last)
 973 {
 974         struct driver_data *driver_data;
 975         struct fw_packet *packet;
 976         struct fw_ohci *ohci = context->ohci;
 977         dma_addr_t payload_bus;
 978         int evt;
 979
 980         if (last->transfer_status == 0)
 981                 /* This descriptor isn't done yet, stop iteration. */
 982                 return 0;
 983
 984         driver_data = (struct driver_data *) &d[3];
 985         packet = driver_data->packet;
 986         if (packet == NULL)
 987                 /* This packet was cancelled, just continue. */
 988                 return 1;
 989
 990         payload_bus = le32_to_cpu(last->data_address);
 991         if (payload_bus != 0)
 992                 dma_unmap_single(ohci->card.device, payload_bus,
 993                                  packet->payload_length, DMA_TO_DEVICE);
 994
 995         evt = le16_to_cpu(last->transfer_status) & 0x1f;
 996         packet->timestamp = le16_to_cpu(last->res_count);
 997
 998         log_ar_at_event('T', packet->speed, packet->header, evt);
 999
1000         switch (evt) {
1001         case OHCI1394_evt_timeout:
1002                 /* Async response transmit timed out. */
1003                 packet->ack = RCODE_CANCELLED;
1004                 break;
1005
1006         case OHCI1394_evt_flushed:
1007                 /*
1008                  * The packet was flushed should give same error as
1009                  * when we try to use a stale generation count.
1010                  */
1011                 packet->ack = RCODE_GENERATION;
1012                 break;
1013
1014         case OHCI1394_evt_missing_ack:
1015                 /*
1016                  * Using a valid (current) generation count, but the
1017                  * node is not on the bus or not sending acks.
1018                  */
1019                 packet->ack = RCODE_NO_ACK;
1020                 break;
1021
1022         case ACK_COMPLETE + 0x10:
1023         case ACK_PENDING + 0x10:
1024         case ACK_BUSY_X + 0x10:
1025         case ACK_BUSY_A + 0x10:
1026         case ACK_BUSY_B + 0x10:
1027         case ACK_DATA_ERROR + 0x10:
1028         case ACK_TYPE_ERROR + 0x10:
1029                 packet->ack = evt - 0x10;
1030                 break;
1031
1032         default:
1033                 packet->ack = RCODE_SEND_ERROR;
1034                 break;
1035         }
1036
1037         packet->callback(packet, &ohci->card, packet->ack);
1038
1039         return 1;
1040 }
1041
1042 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1043 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1044 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1045 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1046 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1047
1048 static void
1049 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1050 {
1051         struct fw_packet response;
1052         int tcode, length, i;
1053
1054         tcode = HEADER_GET_TCODE(packet->header[0]);
1055         if (TCODE_IS_BLOCK_PACKET(tcode))
1056                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1057         else
1058                 length = 4;
1059
1060         i = csr - CSR_CONFIG_ROM;
1061         if (i + length > CONFIG_ROM_SIZE) {
1062                 fw_fill_response(&response, packet->header,
1063                                  RCODE_ADDRESS_ERROR, NULL, 0);
1064         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1065                 fw_fill_response(&response, packet->header,
1066                                  RCODE_TYPE_ERROR, NULL, 0);
1067         } else {
1068                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1069                                  (void *) ohci->config_rom + i, length);
1070         }
1071
1072         fw_core_handle_response(&ohci->card, &response);
1073 }
1074
1075 static void
1076 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1077 {
1078         struct fw_packet response;
1079         int tcode, length, ext_tcode, sel;
1080         __be32 *payload, lock_old;
1081         u32 lock_arg, lock_data;
1082
1083         tcode = HEADER_GET_TCODE(packet->header[0]);
1084         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1085         payload = packet->payload;
1086         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1087
1088         if (tcode == TCODE_LOCK_REQUEST &&
1089             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1090                 lock_arg = be32_to_cpu(payload[0]);
1091                 lock_data = be32_to_cpu(payload[1]);
1092         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1093                 lock_arg = 0;
1094                 lock_data = 0;
1095         } else {
1096                 fw_fill_response(&response, packet->header,
1097                                  RCODE_TYPE_ERROR, NULL, 0);
1098                 goto out;
1099         }
1100
1101         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1102         reg_write(ohci, OHCI1394_CSRData, lock_data);
1103         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1104         reg_write(ohci, OHCI1394_CSRControl, sel);
1105
1106         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1107                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1108         else
1109                 fw_notify("swap not done yet\n");
1110
1111         fw_fill_response(&response, packet->header,
1112                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1113  out:
1114         fw_core_handle_response(&ohci->card, &response);
1115 }
1116
1117 static void
1118 handle_local_request(struct context *ctx, struct fw_packet *packet)
1119 {
1120         u64 offset;
1121         u32 csr;
1122
1123         if (ctx == &ctx->ohci->at_request_ctx) {
1124                 packet->ack = ACK_PENDING;
1125                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1126         }
1127
1128         offset =
1129                 ((unsigned long long)
1130                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1131                 packet->header[2];
1132         csr = offset - CSR_REGISTER_BASE;
1133
1134         /* Handle config rom reads. */
1135         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1136                 handle_local_rom(ctx->ohci, packet, csr);
1137         else switch (csr) {
1138         case CSR_BUS_MANAGER_ID:
1139         case CSR_BANDWIDTH_AVAILABLE:
1140         case CSR_CHANNELS_AVAILABLE_HI:
1141         case CSR_CHANNELS_AVAILABLE_LO:
1142                 handle_local_lock(ctx->ohci, packet, csr);
1143                 break;
1144         default:
1145                 if (ctx == &ctx->ohci->at_request_ctx)
1146                         fw_core_handle_request(&ctx->ohci->card, packet);
1147                 else
1148                         fw_core_handle_response(&ctx->ohci->card, packet);
1149                 break;
1150         }
1151
1152         if (ctx == &ctx->ohci->at_response_ctx) {
1153                 packet->ack = ACK_COMPLETE;
1154                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1155         }
1156 }
1157
1158 static void
1159 at_context_transmit(struct context *ctx, struct fw_packet *packet)
1160 {
1161         unsigned long flags;
1162         int retval;
1163
1164         spin_lock_irqsave(&ctx->ohci->lock, flags);
1165
1166         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1167             ctx->ohci->generation == packet->generation) {
1168                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1169                 handle_local_request(ctx, packet);
1170                 return;
1171         }
1172
1173         retval = at_context_queue_packet(ctx, packet);
1174         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1175
1176         if (retval < 0)
1177                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1178
1179 }
1180
1181 static void bus_reset_tasklet(unsigned long data)
1182 {
1183         struct fw_ohci *ohci = (struct fw_ohci *)data;
1184         int self_id_count, i, j, reg;
1185         int generation, new_generation;
1186         unsigned long flags;
1187         void *free_rom = NULL;
1188         dma_addr_t free_rom_bus = 0;
1189
1190         reg = reg_read(ohci, OHCI1394_NodeID);
1191         if (!(reg & OHCI1394_NodeID_idValid)) {
1192                 fw_notify("node ID not valid, new bus reset in progress\n");
1193                 return;
1194         }
1195         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1196                 fw_notify("malconfigured bus\n");
1197                 return;
1198         }
1199         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1200                                OHCI1394_NodeID_nodeNumber);
1201
1202         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1203         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1204                 fw_notify("inconsistent self IDs\n");
1205                 return;
1206         }
1207         /*
1208          * The count in the SelfIDCount register is the number of
1209          * bytes in the self ID receive buffer.  Since we also receive
1210          * the inverted quadlets and a header quadlet, we shift one
1211          * bit extra to get the actual number of self IDs.
1212          */
1213         self_id_count = (reg >> 3) & 0x3ff;
1214         if (self_id_count == 0) {
1215                 fw_notify("inconsistent self IDs\n");
1216                 return;
1217         }
1218         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1219         rmb();
1220
1221         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1222                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1223                         fw_notify("inconsistent self IDs\n");
1224                         return;
1225                 }
1226                 ohci->self_id_buffer[j] =
1227                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1228         }
1229         rmb();
1230
1231         /*
1232          * Check the consistency of the self IDs we just read.  The
1233          * problem we face is that a new bus reset can start while we
1234          * read out the self IDs from the DMA buffer. If this happens,
1235          * the DMA buffer will be overwritten with new self IDs and we
1236          * will read out inconsistent data.  The OHCI specification
1237          * (section 11.2) recommends a technique similar to
1238          * linux/seqlock.h, where we remember the generation of the
1239          * self IDs in the buffer before reading them out and compare
1240          * it to the current generation after reading them out.  If
1241          * the two generations match we know we have a consistent set
1242          * of self IDs.
1243          */
1244
1245         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1246         if (new_generation != generation) {
1247                 fw_notify("recursive bus reset detected, "
1248                           "discarding self ids\n");
1249                 return;
1250         }
1251
1252         /* FIXME: Document how the locking works. */
1253         spin_lock_irqsave(&ohci->lock, flags);
1254
1255         ohci->generation = generation;
1256         context_stop(&ohci->at_request_ctx);
1257         context_stop(&ohci->at_response_ctx);
1258         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1259
1260         /*
1261          * This next bit is unrelated to the AT context stuff but we
1262          * have to do it under the spinlock also.  If a new config rom
1263          * was set up before this reset, the old one is now no longer
1264          * in use and we can free it. Update the config rom pointers
1265          * to point to the current config rom and clear the
1266          * next_config_rom pointer so a new udpate can take place.
1267          */
1268
1269         if (ohci->next_config_rom != NULL) {
1270                 if (ohci->next_config_rom != ohci->config_rom) {
1271                         free_rom      = ohci->config_rom;
1272                         free_rom_bus  = ohci->config_rom_bus;
1273                 }
1274                 ohci->config_rom      = ohci->next_config_rom;
1275                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1276                 ohci->next_config_rom = NULL;
1277
1278                 /*
1279                  * Restore config_rom image and manually update
1280                  * config_rom registers.  Writing the header quadlet
1281                  * will indicate that the config rom is ready, so we
1282                  * do that last.
1283                  */
1284                 reg_write(ohci, OHCI1394_BusOptions,
1285                           be32_to_cpu(ohci->config_rom[2]));
1286                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1287                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1288         }
1289
1290 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1291         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1292         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1293 #endif
1294
1295         spin_unlock_irqrestore(&ohci->lock, flags);
1296
1297         if (free_rom)
1298                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1299                                   free_rom, free_rom_bus);
1300
1301         log_selfids(generation, self_id_count, ohci->self_id_buffer);
1302
1303         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1304                                  self_id_count, ohci->self_id_buffer);
1305 }
1306
1307 static irqreturn_t irq_handler(int irq, void *data)
1308 {
1309         struct fw_ohci *ohci = data;
1310         u32 event, iso_event, cycle_time;
1311         int i;
1312
1313         event = reg_read(ohci, OHCI1394_IntEventClear);
1314
1315         if (!event || !~event)
1316                 return IRQ_NONE;
1317
1318         reg_write(ohci, OHCI1394_IntEventClear, event);
1319         log_irqs(event);
1320
1321         if (event & OHCI1394_selfIDComplete)
1322                 tasklet_schedule(&ohci->bus_reset_tasklet);
1323
1324         if (event & OHCI1394_RQPkt)
1325                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1326
1327         if (event & OHCI1394_RSPkt)
1328                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1329
1330         if (event & OHCI1394_reqTxComplete)
1331                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1332
1333         if (event & OHCI1394_respTxComplete)
1334                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1335
1336         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1337         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1338
1339         while (iso_event) {
1340                 i = ffs(iso_event) - 1;
1341                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1342                 iso_event &= ~(1 << i);
1343         }
1344
1345         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1346         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1347
1348         while (iso_event) {
1349                 i = ffs(iso_event) - 1;
1350                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1351                 iso_event &= ~(1 << i);
1352         }
1353
1354         if (unlikely(event & OHCI1394_postedWriteErr))
1355                 fw_error("PCI posted write error\n");
1356
1357         if (unlikely(event & OHCI1394_cycleTooLong)) {
1358                 if (printk_ratelimit())
1359                         fw_notify("isochronous cycle too long\n");
1360                 reg_write(ohci, OHCI1394_LinkControlSet,
1361                           OHCI1394_LinkControl_cycleMaster);
1362         }
1363
1364         if (event & OHCI1394_cycle64Seconds) {
1365                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1366                 if ((cycle_time & 0x80000000) == 0)
1367                         ohci->bus_seconds++;
1368         }
1369
1370         return IRQ_HANDLED;
1371 }
1372
1373 static int software_reset(struct fw_ohci *ohci)
1374 {
1375         int i;
1376
1377         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1378
1379         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1380                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1381                      OHCI1394_HCControl_softReset) == 0)
1382                         return 0;
1383                 msleep(1);
1384         }
1385
1386         return -EBUSY;
1387 }
1388
1389 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1390 {
1391         struct fw_ohci *ohci = fw_ohci(card);
1392         struct pci_dev *dev = to_pci_dev(card->device);
1393
1394         if (software_reset(ohci)) {
1395                 fw_error("Failed to reset ohci card.\n");
1396                 return -EBUSY;
1397         }
1398
1399         /*
1400          * Now enable LPS, which we need in order to start accessing
1401          * most of the registers.  In fact, on some cards (ALI M5251),
1402          * accessing registers in the SClk domain without LPS enabled
1403          * will lock up the machine.  Wait 50msec to make sure we have
1404          * full link enabled.
1405          */
1406         reg_write(ohci, OHCI1394_HCControlSet,
1407                   OHCI1394_HCControl_LPS |
1408                   OHCI1394_HCControl_postedWriteEnable);
1409         flush_writes(ohci);
1410         msleep(50);
1411
1412         reg_write(ohci, OHCI1394_HCControlClear,
1413                   OHCI1394_HCControl_noByteSwapData);
1414
1415         reg_write(ohci, OHCI1394_LinkControlSet,
1416                   OHCI1394_LinkControl_rcvSelfID |
1417                   OHCI1394_LinkControl_cycleTimerEnable |
1418                   OHCI1394_LinkControl_cycleMaster);
1419
1420         reg_write(ohci, OHCI1394_ATRetries,
1421                   OHCI1394_MAX_AT_REQ_RETRIES |
1422                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1423                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1424
1425         ar_context_run(&ohci->ar_request_ctx);
1426         ar_context_run(&ohci->ar_response_ctx);
1427
1428         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1429         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1430         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1431         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1432         reg_write(ohci, OHCI1394_IntMaskSet,
1433                   OHCI1394_selfIDComplete |
1434                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1435                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1436                   OHCI1394_isochRx | OHCI1394_isochTx |
1437                   OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1438                   OHCI1394_cycle64Seconds | OHCI1394_masterIntEnable);
1439
1440         /* Activate link_on bit and contender bit in our self ID packets.*/
1441         if (ohci_update_phy_reg(card, 4, 0,
1442                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1443                 return -EIO;
1444
1445         /*
1446          * When the link is not yet enabled, the atomic config rom
1447          * update mechanism described below in ohci_set_config_rom()
1448          * is not active.  We have to update ConfigRomHeader and
1449          * BusOptions manually, and the write to ConfigROMmap takes
1450          * effect immediately.  We tie this to the enabling of the
1451          * link, so we have a valid config rom before enabling - the
1452          * OHCI requires that ConfigROMhdr and BusOptions have valid
1453          * values before enabling.
1454          *
1455          * However, when the ConfigROMmap is written, some controllers
1456          * always read back quadlets 0 and 2 from the config rom to
1457          * the ConfigRomHeader and BusOptions registers on bus reset.
1458          * They shouldn't do that in this initial case where the link
1459          * isn't enabled.  This means we have to use the same
1460          * workaround here, setting the bus header to 0 and then write
1461          * the right values in the bus reset tasklet.
1462          */
1463
1464         if (config_rom) {
1465                 ohci->next_config_rom =
1466                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1467                                            &ohci->next_config_rom_bus,
1468                                            GFP_KERNEL);
1469                 if (ohci->next_config_rom == NULL)
1470                         return -ENOMEM;
1471
1472                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1473                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1474         } else {
1475                 /*
1476                  * In the suspend case, config_rom is NULL, which
1477                  * means that we just reuse the old config rom.
1478                  */
1479                 ohci->next_config_rom = ohci->config_rom;
1480                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1481         }
1482
1483         ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1484         ohci->next_config_rom[0] = 0;
1485         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1486         reg_write(ohci, OHCI1394_BusOptions,
1487                   be32_to_cpu(ohci->next_config_rom[2]));
1488         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1489
1490         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1491
1492         if (request_irq(dev->irq, irq_handler,
1493                         IRQF_SHARED, ohci_driver_name, ohci)) {
1494                 fw_error("Failed to allocate shared interrupt %d.\n",
1495                          dev->irq);
1496                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1497                                   ohci->config_rom, ohci->config_rom_bus);
1498                 return -EIO;
1499         }
1500
1501         reg_write(ohci, OHCI1394_HCControlSet,
1502                   OHCI1394_HCControl_linkEnable |
1503                   OHCI1394_HCControl_BIBimageValid);
1504         flush_writes(ohci);
1505
1506         /*
1507          * We are ready to go, initiate bus reset to finish the
1508          * initialization.
1509          */
1510
1511         fw_core_initiate_bus_reset(&ohci->card, 1);
1512
1513         return 0;
1514 }
1515
1516 static int
1517 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1518 {
1519         struct fw_ohci *ohci;
1520         unsigned long flags;
1521         int retval = -EBUSY;
1522         __be32 *next_config_rom;
1523         dma_addr_t uninitialized_var(next_config_rom_bus);
1524
1525         ohci = fw_ohci(card);
1526
1527         /*
1528          * When the OHCI controller is enabled, the config rom update
1529          * mechanism is a bit tricky, but easy enough to use.  See
1530          * section 5.5.6 in the OHCI specification.
1531          *
1532          * The OHCI controller caches the new config rom address in a
1533          * shadow register (ConfigROMmapNext) and needs a bus reset
1534          * for the changes to take place.  When the bus reset is
1535          * detected, the controller loads the new values for the
1536          * ConfigRomHeader and BusOptions registers from the specified
1537          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1538          * shadow register. All automatically and atomically.
1539          *
1540          * Now, there's a twist to this story.  The automatic load of
1541          * ConfigRomHeader and BusOptions doesn't honor the
1542          * noByteSwapData bit, so with a be32 config rom, the
1543          * controller will load be32 values in to these registers
1544          * during the atomic update, even on litte endian
1545          * architectures.  The workaround we use is to put a 0 in the
1546          * header quadlet; 0 is endian agnostic and means that the
1547          * config rom isn't ready yet.  In the bus reset tasklet we
1548          * then set up the real values for the two registers.
1549          *
1550          * We use ohci->lock to avoid racing with the code that sets
1551          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1552          */
1553
1554         next_config_rom =
1555                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1556                                    &next_config_rom_bus, GFP_KERNEL);
1557         if (next_config_rom == NULL)
1558                 return -ENOMEM;
1559
1560         spin_lock_irqsave(&ohci->lock, flags);
1561
1562         if (ohci->next_config_rom == NULL) {
1563                 ohci->next_config_rom = next_config_rom;
1564                 ohci->next_config_rom_bus = next_config_rom_bus;
1565
1566                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1567                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1568                                   length * 4);
1569
1570                 ohci->next_header = config_rom[0];
1571                 ohci->next_config_rom[0] = 0;
1572
1573                 reg_write(ohci, OHCI1394_ConfigROMmap,
1574                           ohci->next_config_rom_bus);
1575                 retval = 0;
1576         }
1577
1578         spin_unlock_irqrestore(&ohci->lock, flags);
1579
1580         /*
1581          * Now initiate a bus reset to have the changes take
1582          * effect. We clean up the old config rom memory and DMA
1583          * mappings in the bus reset tasklet, since the OHCI
1584          * controller could need to access it before the bus reset
1585          * takes effect.
1586          */
1587         if (retval == 0)
1588                 fw_core_initiate_bus_reset(&ohci->card, 1);
1589         else
1590                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1591                                   next_config_rom, next_config_rom_bus);
1592
1593         return retval;
1594 }
1595
1596 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1597 {
1598         struct fw_ohci *ohci = fw_ohci(card);
1599
1600         at_context_transmit(&ohci->at_request_ctx, packet);
1601 }
1602
1603 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1604 {
1605         struct fw_ohci *ohci = fw_ohci(card);
1606
1607         at_context_transmit(&ohci->at_response_ctx, packet);
1608 }
1609
1610 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1611 {
1612         struct fw_ohci *ohci = fw_ohci(card);
1613         struct context *ctx = &ohci->at_request_ctx;
1614         struct driver_data *driver_data = packet->driver_data;
1615         int retval = -ENOENT;
1616
1617         tasklet_disable(&ctx->tasklet);
1618
1619         if (packet->ack != 0)
1620                 goto out;
1621
1622         log_ar_at_event('T', packet->speed, packet->header, 0x20);
1623         driver_data->packet = NULL;
1624         packet->ack = RCODE_CANCELLED;
1625         packet->callback(packet, &ohci->card, packet->ack);
1626         retval = 0;
1627
1628  out:
1629         tasklet_enable(&ctx->tasklet);
1630
1631         return retval;
1632 }
1633
1634 static int
1635 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1636 {
1637 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1638         return 0;
1639 #else
1640         struct fw_ohci *ohci = fw_ohci(card);
1641         unsigned long flags;
1642         int n, retval = 0;
1643
1644         /*
1645          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1646          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1647          */
1648
1649         spin_lock_irqsave(&ohci->lock, flags);
1650
1651         if (ohci->generation != generation) {
1652                 retval = -ESTALE;
1653                 goto out;
1654         }
1655
1656         /*
1657          * Note, if the node ID contains a non-local bus ID, physical DMA is
1658          * enabled for _all_ nodes on remote buses.
1659          */
1660
1661         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1662         if (n < 32)
1663                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1664         else
1665                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1666
1667         flush_writes(ohci);
1668  out:
1669         spin_unlock_irqrestore(&ohci->lock, flags);
1670         return retval;
1671 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1672 }
1673
1674 static u64
1675 ohci_get_bus_time(struct fw_card *card)
1676 {
1677         struct fw_ohci *ohci = fw_ohci(card);
1678         u32 cycle_time;
1679         u64 bus_time;
1680
1681         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1682         bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1683
1684         return bus_time;
1685 }
1686
1687 static int handle_ir_dualbuffer_packet(struct context *context,
1688                                        struct descriptor *d,
1689                                        struct descriptor *last)
1690 {
1691         struct iso_context *ctx =
1692                 container_of(context, struct iso_context, context);
1693         struct db_descriptor *db = (struct db_descriptor *) d;
1694         __le32 *ir_header;
1695         size_t header_length;
1696         void *p, *end;
1697         int i;
1698
1699         if (db->first_res_count != 0 && db->second_res_count != 0) {
1700                 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1701                         /* This descriptor isn't done yet, stop iteration. */
1702                         return 0;
1703                 }
1704                 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1705         }
1706
1707         header_length = le16_to_cpu(db->first_req_count) -
1708                 le16_to_cpu(db->first_res_count);
1709
1710         i = ctx->header_length;
1711         p = db + 1;
1712         end = p + header_length;
1713         while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1714                 /*
1715                  * The iso header is byteswapped to little endian by
1716                  * the controller, but the remaining header quadlets
1717                  * are big endian.  We want to present all the headers
1718                  * as big endian, so we have to swap the first
1719                  * quadlet.
1720                  */
1721                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1722                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1723                 i += ctx->base.header_size;
1724                 ctx->excess_bytes +=
1725                         (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1726                 p += ctx->base.header_size + 4;
1727         }
1728         ctx->header_length = i;
1729
1730         ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1731                 le16_to_cpu(db->second_res_count);
1732
1733         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1734                 ir_header = (__le32 *) (db + 1);
1735                 ctx->base.callback(&ctx->base,
1736                                    le32_to_cpu(ir_header[0]) & 0xffff,
1737                                    ctx->header_length, ctx->header,
1738                                    ctx->base.callback_data);
1739                 ctx->header_length = 0;
1740         }
1741
1742         return 1;
1743 }
1744
1745 static int handle_ir_packet_per_buffer(struct context *context,
1746                                        struct descriptor *d,
1747                                        struct descriptor *last)
1748 {
1749         struct iso_context *ctx =
1750                 container_of(context, struct iso_context, context);
1751         struct descriptor *pd;
1752         __le32 *ir_header;
1753         void *p;
1754         int i;
1755
1756         for (pd = d; pd <= last; pd++) {
1757                 if (pd->transfer_status)
1758                         break;
1759         }
1760         if (pd > last)
1761                 /* Descriptor(s) not done yet, stop iteration */
1762                 return 0;
1763
1764         i   = ctx->header_length;
1765         p   = last + 1;
1766
1767         if (ctx->base.header_size > 0 &&
1768                         i + ctx->base.header_size <= PAGE_SIZE) {
1769                 /*
1770                  * The iso header is byteswapped to little endian by
1771                  * the controller, but the remaining header quadlets
1772                  * are big endian.  We want to present all the headers
1773                  * as big endian, so we have to swap the first quadlet.
1774                  */
1775                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1776                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1777                 ctx->header_length += ctx->base.header_size;
1778         }
1779
1780         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1781                 ir_header = (__le32 *) p;
1782                 ctx->base.callback(&ctx->base,
1783                                    le32_to_cpu(ir_header[0]) & 0xffff,
1784                                    ctx->header_length, ctx->header,
1785                                    ctx->base.callback_data);
1786                 ctx->header_length = 0;
1787         }
1788
1789         return 1;
1790 }
1791
1792 static int handle_it_packet(struct context *context,
1793                             struct descriptor *d,
1794                             struct descriptor *last)
1795 {
1796         struct iso_context *ctx =
1797                 container_of(context, struct iso_context, context);
1798
1799         if (last->transfer_status == 0)
1800                 /* This descriptor isn't done yet, stop iteration. */
1801                 return 0;
1802
1803         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1804                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1805                                    0, NULL, ctx->base.callback_data);
1806
1807         return 1;
1808 }
1809
1810 static struct fw_iso_context *
1811 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1812 {
1813         struct fw_ohci *ohci = fw_ohci(card);
1814         struct iso_context *ctx, *list;
1815         descriptor_callback_t callback;
1816         u32 *mask, regs;
1817         unsigned long flags;
1818         int index, retval = -ENOMEM;
1819
1820         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1821                 mask = &ohci->it_context_mask;
1822                 list = ohci->it_context_list;
1823                 callback = handle_it_packet;
1824         } else {
1825                 mask = &ohci->ir_context_mask;
1826                 list = ohci->ir_context_list;
1827                 if (ohci->version >= OHCI_VERSION_1_1)
1828                         callback = handle_ir_dualbuffer_packet;
1829                 else
1830                         callback = handle_ir_packet_per_buffer;
1831         }
1832
1833         spin_lock_irqsave(&ohci->lock, flags);
1834         index = ffs(*mask) - 1;
1835         if (index >= 0)
1836                 *mask &= ~(1 << index);
1837         spin_unlock_irqrestore(&ohci->lock, flags);
1838
1839         if (index < 0)
1840                 return ERR_PTR(-EBUSY);
1841
1842         if (type == FW_ISO_CONTEXT_TRANSMIT)
1843                 regs = OHCI1394_IsoXmitContextBase(index);
1844         else
1845                 regs = OHCI1394_IsoRcvContextBase(index);
1846
1847         ctx = &list[index];
1848         memset(ctx, 0, sizeof(*ctx));
1849         ctx->header_length = 0;
1850         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1851         if (ctx->header == NULL)
1852                 goto out;
1853
1854         retval = context_init(&ctx->context, ohci, regs, callback);
1855         if (retval < 0)
1856                 goto out_with_header;
1857
1858         return &ctx->base;
1859
1860  out_with_header:
1861         free_page((unsigned long)ctx->header);
1862  out:
1863         spin_lock_irqsave(&ohci->lock, flags);
1864         *mask |= 1 << index;
1865         spin_unlock_irqrestore(&ohci->lock, flags);
1866
1867         return ERR_PTR(retval);
1868 }
1869
1870 static int ohci_start_iso(struct fw_iso_context *base,
1871                           s32 cycle, u32 sync, u32 tags)
1872 {
1873         struct iso_context *ctx = container_of(base, struct iso_context, base);
1874         struct fw_ohci *ohci = ctx->context.ohci;
1875         u32 control, match;
1876         int index;
1877
1878         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1879                 index = ctx - ohci->it_context_list;
1880                 match = 0;
1881                 if (cycle >= 0)
1882                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1883                                 (cycle & 0x7fff) << 16;
1884
1885                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1886                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1887                 context_run(&ctx->context, match);
1888         } else {
1889                 index = ctx - ohci->ir_context_list;
1890                 control = IR_CONTEXT_ISOCH_HEADER;
1891                 if (ohci->version >= OHCI_VERSION_1_1)
1892                         control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1893                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1894                 if (cycle >= 0) {
1895                         match |= (cycle & 0x07fff) << 12;
1896                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1897                 }
1898
1899                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1900                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1901                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1902                 context_run(&ctx->context, control);
1903         }
1904
1905         return 0;
1906 }
1907
1908 static int ohci_stop_iso(struct fw_iso_context *base)
1909 {
1910         struct fw_ohci *ohci = fw_ohci(base->card);
1911         struct iso_context *ctx = container_of(base, struct iso_context, base);
1912         int index;
1913
1914         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1915                 index = ctx - ohci->it_context_list;
1916                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1917         } else {
1918                 index = ctx - ohci->ir_context_list;
1919                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1920         }
1921         flush_writes(ohci);
1922         context_stop(&ctx->context);
1923
1924         return 0;
1925 }
1926
1927 static void ohci_free_iso_context(struct fw_iso_context *base)
1928 {
1929         struct fw_ohci *ohci = fw_ohci(base->card);
1930         struct iso_context *ctx = container_of(base, struct iso_context, base);
1931         unsigned long flags;
1932         int index;
1933
1934         ohci_stop_iso(base);
1935         context_release(&ctx->context);
1936         free_page((unsigned long)ctx->header);
1937
1938         spin_lock_irqsave(&ohci->lock, flags);
1939
1940         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1941                 index = ctx - ohci->it_context_list;
1942                 ohci->it_context_mask |= 1 << index;
1943         } else {
1944                 index = ctx - ohci->ir_context_list;
1945                 ohci->ir_context_mask |= 1 << index;
1946         }
1947
1948         spin_unlock_irqrestore(&ohci->lock, flags);
1949 }
1950
1951 static int
1952 ohci_queue_iso_transmit(struct fw_iso_context *base,
1953                         struct fw_iso_packet *packet,
1954                         struct fw_iso_buffer *buffer,
1955                         unsigned long payload)
1956 {
1957         struct iso_context *ctx = container_of(base, struct iso_context, base);
1958         struct descriptor *d, *last, *pd;
1959         struct fw_iso_packet *p;
1960         __le32 *header;
1961         dma_addr_t d_bus, page_bus;
1962         u32 z, header_z, payload_z, irq;
1963         u32 payload_index, payload_end_index, next_page_index;
1964         int page, end_page, i, length, offset;
1965
1966         /*
1967          * FIXME: Cycle lost behavior should be configurable: lose
1968          * packet, retransmit or terminate..
1969          */
1970
1971         p = packet;
1972         payload_index = payload;
1973
1974         if (p->skip)
1975                 z = 1;
1976         else
1977                 z = 2;
1978         if (p->header_length > 0)
1979                 z++;
1980
1981         /* Determine the first page the payload isn't contained in. */
1982         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1983         if (p->payload_length > 0)
1984                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1985         else
1986                 payload_z = 0;
1987
1988         z += payload_z;
1989
1990         /* Get header size in number of descriptors. */
1991         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
1992
1993         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1994         if (d == NULL)
1995                 return -ENOMEM;
1996
1997         if (!p->skip) {
1998                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1999                 d[0].req_count = cpu_to_le16(8);
2000
2001                 header = (__le32 *) &d[1];
2002                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2003                                         IT_HEADER_TAG(p->tag) |
2004                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2005                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2006                                         IT_HEADER_SPEED(ctx->base.speed));
2007                 header[1] =
2008                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2009                                                           p->payload_length));
2010         }
2011
2012         if (p->header_length > 0) {
2013                 d[2].req_count    = cpu_to_le16(p->header_length);
2014                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2015                 memcpy(&d[z], p->header, p->header_length);
2016         }
2017
2018         pd = d + z - payload_z;
2019         payload_end_index = payload_index + p->payload_length;
2020         for (i = 0; i < payload_z; i++) {
2021                 page               = payload_index >> PAGE_SHIFT;
2022                 offset             = payload_index & ~PAGE_MASK;
2023                 next_page_index    = (page + 1) << PAGE_SHIFT;
2024                 length             =
2025                         min(next_page_index, payload_end_index) - payload_index;
2026                 pd[i].req_count    = cpu_to_le16(length);
2027
2028                 page_bus = page_private(buffer->pages[page]);
2029                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2030
2031                 payload_index += length;
2032         }
2033
2034         if (p->interrupt)
2035                 irq = DESCRIPTOR_IRQ_ALWAYS;
2036         else
2037                 irq = DESCRIPTOR_NO_IRQ;
2038
2039         last = z == 2 ? d : d + z - 1;
2040         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2041                                      DESCRIPTOR_STATUS |
2042                                      DESCRIPTOR_BRANCH_ALWAYS |
2043                                      irq);
2044
2045         context_append(&ctx->context, d, z, header_z);
2046
2047         return 0;
2048 }
2049
2050 static int
2051 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2052                                   struct fw_iso_packet *packet,
2053                                   struct fw_iso_buffer *buffer,
2054                                   unsigned long payload)
2055 {
2056         struct iso_context *ctx = container_of(base, struct iso_context, base);
2057         struct db_descriptor *db = NULL;
2058         struct descriptor *d;
2059         struct fw_iso_packet *p;
2060         dma_addr_t d_bus, page_bus;
2061         u32 z, header_z, length, rest;
2062         int page, offset, packet_count, header_size;
2063
2064         /*
2065          * FIXME: Cycle lost behavior should be configurable: lose
2066          * packet, retransmit or terminate..
2067          */
2068
2069         p = packet;
2070         z = 2;
2071
2072         /*
2073          * The OHCI controller puts the status word in the header
2074          * buffer too, so we need 4 extra bytes per packet.
2075          */
2076         packet_count = p->header_length / ctx->base.header_size;
2077         header_size = packet_count * (ctx->base.header_size + 4);
2078
2079         /* Get header size in number of descriptors. */
2080         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2081         page     = payload >> PAGE_SHIFT;
2082         offset   = payload & ~PAGE_MASK;
2083         rest     = p->payload_length;
2084
2085         /* FIXME: make packet-per-buffer/dual-buffer a context option */
2086         while (rest > 0) {
2087                 d = context_get_descriptors(&ctx->context,
2088                                             z + header_z, &d_bus);
2089                 if (d == NULL)
2090                         return -ENOMEM;
2091
2092                 db = (struct db_descriptor *) d;
2093                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2094                                           DESCRIPTOR_BRANCH_ALWAYS);
2095                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
2096                 if (p->skip && rest == p->payload_length) {
2097                         db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2098                         db->first_req_count = db->first_size;
2099                 } else {
2100                         db->first_req_count = cpu_to_le16(header_size);
2101                 }
2102                 db->first_res_count = db->first_req_count;
2103                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2104
2105                 if (p->skip && rest == p->payload_length)
2106                         length = 4;
2107                 else if (offset + rest < PAGE_SIZE)
2108                         length = rest;
2109                 else
2110                         length = PAGE_SIZE - offset;
2111
2112                 db->second_req_count = cpu_to_le16(length);
2113                 db->second_res_count = db->second_req_count;
2114                 page_bus = page_private(buffer->pages[page]);
2115                 db->second_buffer = cpu_to_le32(page_bus + offset);
2116
2117                 if (p->interrupt && length == rest)
2118                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2119
2120                 context_append(&ctx->context, d, z, header_z);
2121                 offset = (offset + length) & ~PAGE_MASK;
2122                 rest -= length;
2123                 if (offset == 0)
2124                         page++;
2125         }
2126
2127         return 0;
2128 }
2129
2130 static int
2131 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2132                                          struct fw_iso_packet *packet,
2133                                          struct fw_iso_buffer *buffer,
2134                                          unsigned long payload)
2135 {
2136         struct iso_context *ctx = container_of(base, struct iso_context, base);
2137         struct descriptor *d = NULL, *pd = NULL;
2138         struct fw_iso_packet *p = packet;
2139         dma_addr_t d_bus, page_bus;
2140         u32 z, header_z, rest;
2141         int i, j, length;
2142         int page, offset, packet_count, header_size, payload_per_buffer;
2143
2144         /*
2145          * The OHCI controller puts the status word in the
2146          * buffer too, so we need 4 extra bytes per packet.
2147          */
2148         packet_count = p->header_length / ctx->base.header_size;
2149         header_size  = ctx->base.header_size + 4;
2150
2151         /* Get header size in number of descriptors. */
2152         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2153         page     = payload >> PAGE_SHIFT;
2154         offset   = payload & ~PAGE_MASK;
2155         payload_per_buffer = p->payload_length / packet_count;
2156
2157         for (i = 0; i < packet_count; i++) {
2158                 /* d points to the header descriptor */
2159                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2160                 d = context_get_descriptors(&ctx->context,
2161                                 z + header_z, &d_bus);
2162                 if (d == NULL)
2163                         return -ENOMEM;
2164
2165                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2166                                               DESCRIPTOR_INPUT_MORE);
2167                 if (p->skip && i == 0)
2168                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2169                 d->req_count    = cpu_to_le16(header_size);
2170                 d->res_count    = d->req_count;
2171                 d->transfer_status = 0;
2172                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2173
2174                 rest = payload_per_buffer;
2175                 for (j = 1; j < z; j++) {
2176                         pd = d + j;
2177                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2178                                                   DESCRIPTOR_INPUT_MORE);
2179
2180                         if (offset + rest < PAGE_SIZE)
2181                                 length = rest;
2182                         else
2183                                 length = PAGE_SIZE - offset;
2184                         pd->req_count = cpu_to_le16(length);
2185                         pd->res_count = pd->req_count;
2186                         pd->transfer_status = 0;
2187
2188                         page_bus = page_private(buffer->pages[page]);
2189                         pd->data_address = cpu_to_le32(page_bus + offset);
2190
2191                         offset = (offset + length) & ~PAGE_MASK;
2192                         rest -= length;
2193                         if (offset == 0)
2194                                 page++;
2195                 }
2196                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2197                                           DESCRIPTOR_INPUT_LAST |
2198                                           DESCRIPTOR_BRANCH_ALWAYS);
2199                 if (p->interrupt && i == packet_count - 1)
2200                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2201
2202                 context_append(&ctx->context, d, z, header_z);
2203         }
2204
2205         return 0;
2206 }
2207
2208 static int
2209 ohci_queue_iso(struct fw_iso_context *base,
2210                struct fw_iso_packet *packet,
2211                struct fw_iso_buffer *buffer,
2212                unsigned long payload)
2213 {
2214         struct iso_context *ctx = container_of(base, struct iso_context, base);
2215         unsigned long flags;
2216         int retval;
2217
2218         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2219         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2220                 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
2221         else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
2222                 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
2223                                                          buffer, payload);
2224         else
2225                 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2226                                                                 buffer,
2227                                                                 payload);
2228         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2229
2230         return retval;
2231 }
2232
2233 static const struct fw_card_driver ohci_driver = {
2234         .name                   = ohci_driver_name,
2235         .enable                 = ohci_enable,
2236         .update_phy_reg         = ohci_update_phy_reg,
2237         .set_config_rom         = ohci_set_config_rom,
2238         .send_request           = ohci_send_request,
2239         .send_response          = ohci_send_response,
2240         .cancel_packet          = ohci_cancel_packet,
2241         .enable_phys_dma        = ohci_enable_phys_dma,
2242         .get_bus_time           = ohci_get_bus_time,
2243
2244         .allocate_iso_context   = ohci_allocate_iso_context,
2245         .free_iso_context       = ohci_free_iso_context,
2246         .queue_iso              = ohci_queue_iso,
2247         .start_iso              = ohci_start_iso,
2248         .stop_iso               = ohci_stop_iso,
2249 };
2250
2251 #ifdef CONFIG_PPC_PMAC
2252 static void ohci_pmac_on(struct pci_dev *dev)
2253 {
2254         if (machine_is(powermac)) {
2255                 struct device_node *ofn = pci_device_to_OF_node(dev);
2256
2257                 if (ofn) {
2258                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2259                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2260                 }
2261         }
2262 }
2263
2264 static void ohci_pmac_off(struct pci_dev *dev)
2265 {
2266         if (machine_is(powermac)) {
2267                 struct device_node *ofn = pci_device_to_OF_node(dev);
2268
2269                 if (ofn) {
2270                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2271                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2272                 }
2273         }
2274 }
2275 #else
2276 #define ohci_pmac_on(dev)
2277 #define ohci_pmac_off(dev)
2278 #endif /* CONFIG_PPC_PMAC */
2279
2280 static int __devinit
2281 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2282 {
2283         struct fw_ohci *ohci;
2284         u32 bus_options, max_receive, link_speed;
2285         u64 guid;
2286         int err;
2287         size_t size;
2288
2289         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2290         if (ohci == NULL) {
2291                 fw_error("Could not malloc fw_ohci data.\n");
2292                 return -ENOMEM;
2293         }
2294
2295         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2296
2297         ohci_pmac_on(dev);
2298
2299         err = pci_enable_device(dev);
2300         if (err) {
2301                 fw_error("Failed to enable OHCI hardware.\n");
2302                 goto fail_free;
2303         }
2304
2305         pci_set_master(dev);
2306         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2307         pci_set_drvdata(dev, ohci);
2308
2309 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2310         ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2311                              dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2312 #endif
2313         spin_lock_init(&ohci->lock);
2314
2315         tasklet_init(&ohci->bus_reset_tasklet,
2316                      bus_reset_tasklet, (unsigned long)ohci);
2317
2318         err = pci_request_region(dev, 0, ohci_driver_name);
2319         if (err) {
2320                 fw_error("MMIO resource unavailable\n");
2321                 goto fail_disable;
2322         }
2323
2324         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2325         if (ohci->registers == NULL) {
2326                 fw_error("Failed to remap registers\n");
2327                 err = -ENXIO;
2328                 goto fail_iomem;
2329         }
2330
2331         ar_context_init(&ohci->ar_request_ctx, ohci,
2332                         OHCI1394_AsReqRcvContextControlSet);
2333
2334         ar_context_init(&ohci->ar_response_ctx, ohci,
2335                         OHCI1394_AsRspRcvContextControlSet);
2336
2337         context_init(&ohci->at_request_ctx, ohci,
2338                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2339
2340         context_init(&ohci->at_response_ctx, ohci,
2341                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2342
2343         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2344         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2345         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2346         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2347         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2348
2349         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2350         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2351         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2352         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2353         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2354
2355         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2356                 fw_error("Out of memory for it/ir contexts.\n");
2357                 err = -ENOMEM;
2358                 goto fail_registers;
2359         }
2360
2361         /* self-id dma buffer allocation */
2362         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2363                                                SELF_ID_BUF_SIZE,
2364                                                &ohci->self_id_bus,
2365                                                GFP_KERNEL);
2366         if (ohci->self_id_cpu == NULL) {
2367                 fw_error("Out of memory for self ID buffer.\n");
2368                 err = -ENOMEM;
2369                 goto fail_registers;
2370         }
2371
2372         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2373         max_receive = (bus_options >> 12) & 0xf;
2374         link_speed = bus_options & 0x7;
2375         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2376                 reg_read(ohci, OHCI1394_GUIDLo);
2377
2378         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2379         if (err < 0)
2380                 goto fail_self_id;
2381
2382         ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2383         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2384                   dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
2385         return 0;
2386
2387  fail_self_id:
2388         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2389                           ohci->self_id_cpu, ohci->self_id_bus);
2390  fail_registers:
2391         kfree(ohci->it_context_list);
2392         kfree(ohci->ir_context_list);
2393         pci_iounmap(dev, ohci->registers);
2394  fail_iomem:
2395         pci_release_region(dev, 0);
2396  fail_disable:
2397         pci_disable_device(dev);
2398  fail_free:
2399         kfree(&ohci->card);
2400         ohci_pmac_off(dev);
2401
2402         return err;
2403 }
2404
2405 static void pci_remove(struct pci_dev *dev)
2406 {
2407         struct fw_ohci *ohci;
2408
2409         ohci = pci_get_drvdata(dev);
2410         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2411         flush_writes(ohci);
2412         fw_core_remove_card(&ohci->card);
2413
2414         /*
2415          * FIXME: Fail all pending packets here, now that the upper
2416          * layers can't queue any more.
2417          */
2418
2419         software_reset(ohci);
2420         free_irq(dev->irq, ohci);
2421         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2422                           ohci->self_id_cpu, ohci->self_id_bus);
2423         kfree(ohci->it_context_list);
2424         kfree(ohci->ir_context_list);
2425         pci_iounmap(dev, ohci->registers);
2426         pci_release_region(dev, 0);
2427         pci_disable_device(dev);
2428         kfree(&ohci->card);
2429         ohci_pmac_off(dev);
2430
2431         fw_notify("Removed fw-ohci device.\n");
2432 }
2433
2434 #ifdef CONFIG_PM
2435 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2436 {
2437         struct fw_ohci *ohci = pci_get_drvdata(dev);
2438         int err;
2439
2440         software_reset(ohci);
2441         free_irq(dev->irq, ohci);
2442         err = pci_save_state(dev);
2443         if (err) {
2444                 fw_error("pci_save_state failed\n");
2445                 return err;
2446         }
2447         err = pci_set_power_state(dev, pci_choose_state(dev, state));
2448         if (err)
2449                 fw_error("pci_set_power_state failed with %d\n", err);
2450         ohci_pmac_off(dev);
2451
2452         return 0;
2453 }
2454
2455 static int pci_resume(struct pci_dev *dev)
2456 {
2457         struct fw_ohci *ohci = pci_get_drvdata(dev);
2458         int err;
2459
2460         ohci_pmac_on(dev);
2461         pci_set_power_state(dev, PCI_D0);
2462         pci_restore_state(dev);
2463         err = pci_enable_device(dev);
2464         if (err) {
2465                 fw_error("pci_enable_device failed\n");
2466                 return err;
2467         }
2468
2469         return ohci_enable(&ohci->card, NULL, 0);
2470 }
2471 #endif
2472
2473 static struct pci_device_id pci_table[] = {
2474         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2475         { }
2476 };
2477
2478 MODULE_DEVICE_TABLE(pci, pci_table);
2479
2480 static struct pci_driver fw_ohci_pci_driver = {
2481         .name           = ohci_driver_name,
2482         .id_table       = pci_table,
2483         .probe          = pci_probe,
2484         .remove         = pci_remove,
2485 #ifdef CONFIG_PM
2486         .resume         = pci_resume,
2487         .suspend        = pci_suspend,
2488 #endif
2489 };
2490
2491 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2492 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2493 MODULE_LICENSE("GPL");
2494
2495 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2496 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2497 MODULE_ALIAS("ohci1394");
2498 #endif
2499
2500 static int __init fw_ohci_init(void)
2501 {
2502         return pci_register_driver(&fw_ohci_pci_driver);
2503 }
2504
2505 static void __exit fw_ohci_cleanup(void)
2506 {
2507         pci_unregister_driver(&fw_ohci_pci_driver);
2508 }
2509
2510 module_init(fw_ohci_init);
2511 module_exit(fw_ohci_cleanup);