2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/pci.h>
32 #include <linux/spinlock.h>
35 #include <asm/system.h>
37 #ifdef CONFIG_PPC_PMAC
38 #include <asm/pmac_feature.h>
42 #include "fw-transaction.h"
44 #define DESCRIPTOR_OUTPUT_MORE 0
45 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
46 #define DESCRIPTOR_INPUT_MORE (2 << 12)
47 #define DESCRIPTOR_INPUT_LAST (3 << 12)
48 #define DESCRIPTOR_STATUS (1 << 11)
49 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
50 #define DESCRIPTOR_PING (1 << 7)
51 #define DESCRIPTOR_YY (1 << 6)
52 #define DESCRIPTOR_NO_IRQ (0 << 4)
53 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
54 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
55 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
56 #define DESCRIPTOR_WAIT (3 << 0)
62 __le32 branch_address;
64 __le16 transfer_status;
65 } __attribute__((aligned(16)));
67 struct db_descriptor {
70 __le16 second_req_count;
71 __le16 first_req_count;
72 __le32 branch_address;
73 __le16 second_res_count;
74 __le16 first_res_count;
79 } __attribute__((aligned(16)));
81 #define CONTROL_SET(regs) (regs)
82 #define CONTROL_CLEAR(regs) ((regs) + 4)
83 #define COMMAND_PTR(regs) ((regs) + 12)
84 #define CONTEXT_MATCH(regs) ((regs) + 16)
87 struct descriptor descriptor;
88 struct ar_buffer *next;
94 struct ar_buffer *current_buffer;
95 struct ar_buffer *last_buffer;
98 struct tasklet_struct tasklet;
103 typedef int (*descriptor_callback_t)(struct context *ctx,
104 struct descriptor *d,
105 struct descriptor *last);
108 * A buffer that contains a block of DMA-able coherent memory used for
109 * storing a portion of a DMA descriptor program.
111 struct descriptor_buffer {
112 struct list_head list;
113 dma_addr_t buffer_bus;
116 struct descriptor buffer[0];
120 struct fw_ohci *ohci;
122 int total_allocation;
125 * List of page-sized buffers for storing DMA descriptors.
126 * Head of list contains buffers in use and tail of list contains
129 struct list_head buffer_list;
132 * Pointer to a buffer inside buffer_list that contains the tail
133 * end of the current DMA program.
135 struct descriptor_buffer *buffer_tail;
138 * The descriptor containing the branch address of the first
139 * descriptor that has not yet been filled by the device.
141 struct descriptor *last;
144 * The last descriptor in the DMA program. It contains the branch
145 * address that must be updated upon appending a new descriptor.
147 struct descriptor *prev;
149 descriptor_callback_t callback;
151 struct tasklet_struct tasklet;
154 #define IT_HEADER_SY(v) ((v) << 0)
155 #define IT_HEADER_TCODE(v) ((v) << 4)
156 #define IT_HEADER_CHANNEL(v) ((v) << 8)
157 #define IT_HEADER_TAG(v) ((v) << 14)
158 #define IT_HEADER_SPEED(v) ((v) << 16)
159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
162 struct fw_iso_context base;
163 struct context context;
166 size_t header_length;
169 #define CONFIG_ROM_SIZE 1024
175 __iomem char *registers;
176 dma_addr_t self_id_bus;
178 struct tasklet_struct bus_reset_tasklet;
181 int request_generation;
186 * Spinlock for accessing fw_ohci data. Never call out of
187 * this driver with this lock held.
190 u32 self_id_buffer[512];
192 /* Config rom buffers */
194 dma_addr_t config_rom_bus;
195 __be32 *next_config_rom;
196 dma_addr_t next_config_rom_bus;
199 struct ar_context ar_request_ctx;
200 struct ar_context ar_response_ctx;
201 struct context at_request_ctx;
202 struct context at_response_ctx;
205 struct iso_context *it_context_list;
207 struct iso_context *ir_context_list;
210 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
212 return container_of(card, struct fw_ohci, card);
215 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
216 #define IR_CONTEXT_BUFFER_FILL 0x80000000
217 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
218 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
219 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
220 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
222 #define CONTEXT_RUN 0x8000
223 #define CONTEXT_WAKE 0x1000
224 #define CONTEXT_DEAD 0x0800
225 #define CONTEXT_ACTIVE 0x0400
227 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
228 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
229 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
231 #define FW_OHCI_MAJOR 240
232 #define OHCI1394_REGISTER_SIZE 0x800
233 #define OHCI_LOOP_COUNT 500
234 #define OHCI1394_PCI_HCI_Control 0x40
235 #define SELF_ID_BUF_SIZE 0x800
236 #define OHCI_TCODE_PHY_PACKET 0x0e
237 #define OHCI_VERSION_1_1 0x010010
239 static char ohci_driver_name[] = KBUILD_MODNAME;
241 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
243 #define OHCI_PARAM_DEBUG_AT_AR 1
244 #define OHCI_PARAM_DEBUG_SELFIDS 2
245 #define OHCI_PARAM_DEBUG_IRQS 4
246 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
248 static int param_debug;
249 module_param_named(debug, param_debug, int, 0644);
250 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
251 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
252 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
253 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
254 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
255 ", or a combination, or all = -1)");
257 static void log_irqs(u32 evt)
259 if (likely(!(param_debug &
260 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
263 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
264 !(evt & OHCI1394_busReset))
267 printk(KERN_DEBUG KBUILD_MODNAME ": IRQ "
268 "%08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
270 evt & OHCI1394_selfIDComplete ? " selfID" : "",
271 evt & OHCI1394_RQPkt ? " AR_req" : "",
272 evt & OHCI1394_RSPkt ? " AR_resp" : "",
273 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
274 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
275 evt & OHCI1394_isochRx ? " IR" : "",
276 evt & OHCI1394_isochTx ? " IT" : "",
277 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
278 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
279 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
280 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
281 evt & OHCI1394_busReset ? " busReset" : "",
282 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
283 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
284 OHCI1394_respTxComplete | OHCI1394_isochRx |
285 OHCI1394_isochTx | OHCI1394_postedWriteErr |
286 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
287 OHCI1394_regAccessFail | OHCI1394_busReset)
291 static const char *speed[] = {
292 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
294 static const char *power[] = {
295 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
296 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
298 static const char port[] = { '.', '-', 'p', 'c', };
300 static char _p(u32 *s, int shift)
302 return port[*s >> shift & 3];
305 static void log_selfids(int generation, int self_id_count, u32 *s)
307 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
310 printk(KERN_DEBUG KBUILD_MODNAME ": %d selfIDs, generation %d\n",
311 self_id_count, generation);
313 for (; self_id_count--; ++s)
314 if ((*s & 1 << 23) == 0)
315 printk(KERN_DEBUG "selfID 0: %08x, phy %d [%c%c%c] "
316 "%s gc=%d %s %s%s%s\n",
317 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
318 speed[*s >> 14 & 3], *s >> 16 & 63,
319 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
320 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
322 printk(KERN_DEBUG "selfID n: %08x, phy %d "
323 "[%c%c%c%c%c%c%c%c]\n",
325 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
326 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
329 static const char *evts[] = {
330 [0x00] = "evt_no_status", [0x01] = "-reserved-",
331 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
332 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
333 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
334 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
335 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
336 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
337 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
338 [0x10] = "-reserved-", [0x11] = "ack_complete",
339 [0x12] = "ack_pending ", [0x13] = "-reserved-",
340 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
341 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
342 [0x18] = "-reserved-", [0x19] = "-reserved-",
343 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
344 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
345 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
346 [0x20] = "pending/cancelled",
348 static const char *tcodes[] = {
349 [0x0] = "QW req", [0x1] = "BW req",
350 [0x2] = "W resp", [0x3] = "-reserved-",
351 [0x4] = "QR req", [0x5] = "BR req",
352 [0x6] = "QR resp", [0x7] = "BR resp",
353 [0x8] = "cycle start", [0x9] = "Lk req",
354 [0xa] = "async stream packet", [0xb] = "Lk resp",
355 [0xc] = "-reserved-", [0xd] = "-reserved-",
356 [0xe] = "link internal", [0xf] = "-reserved-",
358 static const char *phys[] = {
359 [0x0] = "phy config packet", [0x1] = "link-on packet",
360 [0x2] = "self-id packet", [0x3] = "-reserved-",
363 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
365 int tcode = header[0] >> 4 & 0xf;
368 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
371 if (unlikely(evt >= ARRAY_SIZE(evts)))
374 if (header[0] == ~header[1]) {
375 printk(KERN_DEBUG "A%c %s, %s, %08x\n",
376 dir, evts[evt], phys[header[0] >> 30 & 0x3],
382 case 0x0: case 0x6: case 0x8:
383 snprintf(specific, sizeof(specific), " = %08x",
384 be32_to_cpu((__force __be32)header[3]));
386 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
387 snprintf(specific, sizeof(specific), " %x,%x",
388 header[3] >> 16, header[3] & 0xffff);
396 printk(KERN_DEBUG "A%c %s, %s\n",
397 dir, evts[evt], tcodes[tcode]);
399 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
400 printk(KERN_DEBUG "A%c spd %x tl %02x, "
403 dir, speed, header[0] >> 10 & 0x3f,
404 header[1] >> 16, header[0] >> 16, evts[evt],
405 tcodes[tcode], header[1] & 0xffff, header[2], specific);
408 printk(KERN_DEBUG "A%c spd %x tl %02x, "
411 dir, speed, header[0] >> 10 & 0x3f,
412 header[1] >> 16, header[0] >> 16, evts[evt],
413 tcodes[tcode], specific);
419 #define log_irqs(evt)
420 #define log_selfids(generation, self_id_count, sid)
421 #define log_ar_at_event(dir, speed, header, evt)
423 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
425 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
427 writel(data, ohci->registers + offset);
430 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
432 return readl(ohci->registers + offset);
435 static inline void flush_writes(const struct fw_ohci *ohci)
437 /* Do a dummy read to flush writes. */
438 reg_read(ohci, OHCI1394_Version);
442 ohci_update_phy_reg(struct fw_card *card, int addr,
443 int clear_bits, int set_bits)
445 struct fw_ohci *ohci = fw_ohci(card);
448 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
451 val = reg_read(ohci, OHCI1394_PhyControl);
452 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
453 fw_error("failed to set phy reg bits.\n");
457 old = OHCI1394_PhyControl_ReadData(val);
458 old = (old & ~clear_bits) | set_bits;
459 reg_write(ohci, OHCI1394_PhyControl,
460 OHCI1394_PhyControl_Write(addr, old));
465 static int ar_context_add_page(struct ar_context *ctx)
467 struct device *dev = ctx->ohci->card.device;
468 struct ar_buffer *ab;
469 dma_addr_t uninitialized_var(ab_bus);
472 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
476 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
477 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
479 DESCRIPTOR_BRANCH_ALWAYS);
480 offset = offsetof(struct ar_buffer, data);
481 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
482 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
483 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
484 ab->descriptor.branch_address = 0;
486 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
487 ctx->last_buffer->next = ab;
488 ctx->last_buffer = ab;
490 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
491 flush_writes(ctx->ohci);
496 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
497 #define cond_le32_to_cpu(v) \
498 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
500 #define cond_le32_to_cpu(v) le32_to_cpu(v)
503 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
505 struct fw_ohci *ohci = ctx->ohci;
507 u32 status, length, tcode;
510 p.header[0] = cond_le32_to_cpu(buffer[0]);
511 p.header[1] = cond_le32_to_cpu(buffer[1]);
512 p.header[2] = cond_le32_to_cpu(buffer[2]);
514 tcode = (p.header[0] >> 4) & 0x0f;
516 case TCODE_WRITE_QUADLET_REQUEST:
517 case TCODE_READ_QUADLET_RESPONSE:
518 p.header[3] = (__force __u32) buffer[3];
519 p.header_length = 16;
520 p.payload_length = 0;
523 case TCODE_READ_BLOCK_REQUEST :
524 p.header[3] = cond_le32_to_cpu(buffer[3]);
525 p.header_length = 16;
526 p.payload_length = 0;
529 case TCODE_WRITE_BLOCK_REQUEST:
530 case TCODE_READ_BLOCK_RESPONSE:
531 case TCODE_LOCK_REQUEST:
532 case TCODE_LOCK_RESPONSE:
533 p.header[3] = cond_le32_to_cpu(buffer[3]);
534 p.header_length = 16;
535 p.payload_length = p.header[3] >> 16;
538 case TCODE_WRITE_RESPONSE:
539 case TCODE_READ_QUADLET_REQUEST:
540 case OHCI_TCODE_PHY_PACKET:
541 p.header_length = 12;
542 p.payload_length = 0;
546 p.payload = (void *) buffer + p.header_length;
548 /* FIXME: What to do about evt_* errors? */
549 length = (p.header_length + p.payload_length + 3) / 4;
550 status = cond_le32_to_cpu(buffer[length]);
551 evt = (status >> 16) & 0x1f;
554 p.speed = (status >> 21) & 0x7;
555 p.timestamp = status & 0xffff;
556 p.generation = ohci->request_generation;
558 log_ar_at_event('R', p.speed, p.header, evt);
561 * The OHCI bus reset handler synthesizes a phy packet with
562 * the new generation number when a bus reset happens (see
563 * section 8.4.2.3). This helps us determine when a request
564 * was received and make sure we send the response in the same
565 * generation. We only need this for requests; for responses
566 * we use the unique tlabel for finding the matching
570 if (evt == OHCI1394_evt_bus_reset)
571 ohci->request_generation = (p.header[2] >> 16) & 0xff;
572 else if (ctx == &ohci->ar_request_ctx)
573 fw_core_handle_request(&ohci->card, &p);
575 fw_core_handle_response(&ohci->card, &p);
577 return buffer + length + 1;
580 static void ar_context_tasklet(unsigned long data)
582 struct ar_context *ctx = (struct ar_context *)data;
583 struct fw_ohci *ohci = ctx->ohci;
584 struct ar_buffer *ab;
585 struct descriptor *d;
588 ab = ctx->current_buffer;
591 if (d->res_count == 0) {
592 size_t size, rest, offset;
593 dma_addr_t start_bus;
597 * This descriptor is finished and we may have a
598 * packet split across this and the next buffer. We
599 * reuse the page for reassembling the split packet.
602 offset = offsetof(struct ar_buffer, data);
604 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
608 size = buffer + PAGE_SIZE - ctx->pointer;
609 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
610 memmove(buffer, ctx->pointer, size);
611 memcpy(buffer + size, ab->data, rest);
612 ctx->current_buffer = ab;
613 ctx->pointer = (void *) ab->data + rest;
614 end = buffer + size + rest;
617 buffer = handle_ar_packet(ctx, buffer);
619 dma_free_coherent(ohci->card.device, PAGE_SIZE,
621 ar_context_add_page(ctx);
623 buffer = ctx->pointer;
625 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
628 buffer = handle_ar_packet(ctx, buffer);
633 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
639 ctx->last_buffer = &ab;
640 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
642 ar_context_add_page(ctx);
643 ar_context_add_page(ctx);
644 ctx->current_buffer = ab.next;
645 ctx->pointer = ctx->current_buffer->data;
650 static void ar_context_run(struct ar_context *ctx)
652 struct ar_buffer *ab = ctx->current_buffer;
656 offset = offsetof(struct ar_buffer, data);
657 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
659 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
660 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
661 flush_writes(ctx->ohci);
664 static struct descriptor *
665 find_branch_descriptor(struct descriptor *d, int z)
669 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
670 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
672 /* figure out which descriptor the branch address goes in */
673 if (z == 2 && (b == 3 || key == 2))
679 static void context_tasklet(unsigned long data)
681 struct context *ctx = (struct context *) data;
682 struct descriptor *d, *last;
685 struct descriptor_buffer *desc;
687 desc = list_entry(ctx->buffer_list.next,
688 struct descriptor_buffer, list);
690 while (last->branch_address != 0) {
691 struct descriptor_buffer *old_desc = desc;
692 address = le32_to_cpu(last->branch_address);
696 /* If the branch address points to a buffer outside of the
697 * current buffer, advance to the next buffer. */
698 if (address < desc->buffer_bus ||
699 address >= desc->buffer_bus + desc->used)
700 desc = list_entry(desc->list.next,
701 struct descriptor_buffer, list);
702 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
703 last = find_branch_descriptor(d, z);
705 if (!ctx->callback(ctx, d, last))
708 if (old_desc != desc) {
709 /* If we've advanced to the next buffer, move the
710 * previous buffer to the free list. */
713 spin_lock_irqsave(&ctx->ohci->lock, flags);
714 list_move_tail(&old_desc->list, &ctx->buffer_list);
715 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
722 * Allocate a new buffer and add it to the list of free buffers for this
723 * context. Must be called with ohci->lock held.
726 context_add_buffer(struct context *ctx)
728 struct descriptor_buffer *desc;
729 dma_addr_t uninitialized_var(bus_addr);
733 * 16MB of descriptors should be far more than enough for any DMA
734 * program. This will catch run-away userspace or DoS attacks.
736 if (ctx->total_allocation >= 16*1024*1024)
739 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
740 &bus_addr, GFP_ATOMIC);
744 offset = (void *)&desc->buffer - (void *)desc;
745 desc->buffer_size = PAGE_SIZE - offset;
746 desc->buffer_bus = bus_addr + offset;
749 list_add_tail(&desc->list, &ctx->buffer_list);
750 ctx->total_allocation += PAGE_SIZE;
756 context_init(struct context *ctx, struct fw_ohci *ohci,
757 u32 regs, descriptor_callback_t callback)
761 ctx->total_allocation = 0;
763 INIT_LIST_HEAD(&ctx->buffer_list);
764 if (context_add_buffer(ctx) < 0)
767 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
768 struct descriptor_buffer, list);
770 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
771 ctx->callback = callback;
774 * We put a dummy descriptor in the buffer that has a NULL
775 * branch address and looks like it's been sent. That way we
776 * have a descriptor to append DMA programs to.
778 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
779 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
780 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
781 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
782 ctx->last = ctx->buffer_tail->buffer;
783 ctx->prev = ctx->buffer_tail->buffer;
789 context_release(struct context *ctx)
791 struct fw_card *card = &ctx->ohci->card;
792 struct descriptor_buffer *desc, *tmp;
794 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
795 dma_free_coherent(card->device, PAGE_SIZE, desc,
797 ((void *)&desc->buffer - (void *)desc));
800 /* Must be called with ohci->lock held */
801 static struct descriptor *
802 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
804 struct descriptor *d = NULL;
805 struct descriptor_buffer *desc = ctx->buffer_tail;
807 if (z * sizeof(*d) > desc->buffer_size)
810 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
811 /* No room for the descriptor in this buffer, so advance to the
814 if (desc->list.next == &ctx->buffer_list) {
815 /* If there is no free buffer next in the list,
817 if (context_add_buffer(ctx) < 0)
820 desc = list_entry(desc->list.next,
821 struct descriptor_buffer, list);
822 ctx->buffer_tail = desc;
825 d = desc->buffer + desc->used / sizeof(*d);
826 memset(d, 0, z * sizeof(*d));
827 *d_bus = desc->buffer_bus + desc->used;
832 static void context_run(struct context *ctx, u32 extra)
834 struct fw_ohci *ohci = ctx->ohci;
836 reg_write(ohci, COMMAND_PTR(ctx->regs),
837 le32_to_cpu(ctx->last->branch_address));
838 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
839 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
843 static void context_append(struct context *ctx,
844 struct descriptor *d, int z, int extra)
847 struct descriptor_buffer *desc = ctx->buffer_tail;
849 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
851 desc->used += (z + extra) * sizeof(*d);
852 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
853 ctx->prev = find_branch_descriptor(d, z);
855 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
856 flush_writes(ctx->ohci);
859 static void context_stop(struct context *ctx)
864 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
865 flush_writes(ctx->ohci);
867 for (i = 0; i < 10; i++) {
868 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
869 if ((reg & CONTEXT_ACTIVE) == 0)
872 fw_notify("context_stop: still active (0x%08x)\n", reg);
878 struct fw_packet *packet;
882 * This function apppends a packet to the DMA queue for transmission.
883 * Must always be called with the ochi->lock held to ensure proper
884 * generation handling and locking around packet queue manipulation.
887 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
889 struct fw_ohci *ohci = ctx->ohci;
890 dma_addr_t d_bus, uninitialized_var(payload_bus);
891 struct driver_data *driver_data;
892 struct descriptor *d, *last;
897 d = context_get_descriptors(ctx, 4, &d_bus);
899 packet->ack = RCODE_SEND_ERROR;
903 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
904 d[0].res_count = cpu_to_le16(packet->timestamp);
907 * The DMA format for asyncronous link packets is different
908 * from the IEEE1394 layout, so shift the fields around
909 * accordingly. If header_length is 8, it's a PHY packet, to
910 * which we need to prepend an extra quadlet.
913 header = (__le32 *) &d[1];
914 if (packet->header_length > 8) {
915 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
916 (packet->speed << 16));
917 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
918 (packet->header[0] & 0xffff0000));
919 header[2] = cpu_to_le32(packet->header[2]);
921 tcode = (packet->header[0] >> 4) & 0x0f;
922 if (TCODE_IS_BLOCK_PACKET(tcode))
923 header[3] = cpu_to_le32(packet->header[3]);
925 header[3] = (__force __le32) packet->header[3];
927 d[0].req_count = cpu_to_le16(packet->header_length);
929 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
930 (packet->speed << 16));
931 header[1] = cpu_to_le32(packet->header[0]);
932 header[2] = cpu_to_le32(packet->header[1]);
933 d[0].req_count = cpu_to_le16(12);
936 driver_data = (struct driver_data *) &d[3];
937 driver_data->packet = packet;
938 packet->driver_data = driver_data;
940 if (packet->payload_length > 0) {
942 dma_map_single(ohci->card.device, packet->payload,
943 packet->payload_length, DMA_TO_DEVICE);
944 if (dma_mapping_error(payload_bus)) {
945 packet->ack = RCODE_SEND_ERROR;
949 d[2].req_count = cpu_to_le16(packet->payload_length);
950 d[2].data_address = cpu_to_le32(payload_bus);
958 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
959 DESCRIPTOR_IRQ_ALWAYS |
960 DESCRIPTOR_BRANCH_ALWAYS);
963 * If the controller and packet generations don't match, we need to
964 * bail out and try again. If IntEvent.busReset is set, the AT context
965 * is halted, so appending to the context and trying to run it is
966 * futile. Most controllers do the right thing and just flush the AT
967 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
968 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
969 * up stalling out. So we just bail out in software and try again
970 * later, and everyone is happy.
971 * FIXME: Document how the locking works.
973 if (ohci->generation != packet->generation ||
974 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
975 if (packet->payload_length > 0)
976 dma_unmap_single(ohci->card.device, payload_bus,
977 packet->payload_length, DMA_TO_DEVICE);
978 packet->ack = RCODE_GENERATION;
982 context_append(ctx, d, z, 4 - z);
984 /* If the context isn't already running, start it up. */
985 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
986 if ((reg & CONTEXT_RUN) == 0)
992 static int handle_at_packet(struct context *context,
993 struct descriptor *d,
994 struct descriptor *last)
996 struct driver_data *driver_data;
997 struct fw_packet *packet;
998 struct fw_ohci *ohci = context->ohci;
999 dma_addr_t payload_bus;
1002 if (last->transfer_status == 0)
1003 /* This descriptor isn't done yet, stop iteration. */
1006 driver_data = (struct driver_data *) &d[3];
1007 packet = driver_data->packet;
1009 /* This packet was cancelled, just continue. */
1012 payload_bus = le32_to_cpu(last->data_address);
1013 if (payload_bus != 0)
1014 dma_unmap_single(ohci->card.device, payload_bus,
1015 packet->payload_length, DMA_TO_DEVICE);
1017 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1018 packet->timestamp = le16_to_cpu(last->res_count);
1020 log_ar_at_event('T', packet->speed, packet->header, evt);
1023 case OHCI1394_evt_timeout:
1024 /* Async response transmit timed out. */
1025 packet->ack = RCODE_CANCELLED;
1028 case OHCI1394_evt_flushed:
1030 * The packet was flushed should give same error as
1031 * when we try to use a stale generation count.
1033 packet->ack = RCODE_GENERATION;
1036 case OHCI1394_evt_missing_ack:
1038 * Using a valid (current) generation count, but the
1039 * node is not on the bus or not sending acks.
1041 packet->ack = RCODE_NO_ACK;
1044 case ACK_COMPLETE + 0x10:
1045 case ACK_PENDING + 0x10:
1046 case ACK_BUSY_X + 0x10:
1047 case ACK_BUSY_A + 0x10:
1048 case ACK_BUSY_B + 0x10:
1049 case ACK_DATA_ERROR + 0x10:
1050 case ACK_TYPE_ERROR + 0x10:
1051 packet->ack = evt - 0x10;
1055 packet->ack = RCODE_SEND_ERROR;
1059 packet->callback(packet, &ohci->card, packet->ack);
1064 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1065 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1066 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1067 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1068 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1071 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1073 struct fw_packet response;
1074 int tcode, length, i;
1076 tcode = HEADER_GET_TCODE(packet->header[0]);
1077 if (TCODE_IS_BLOCK_PACKET(tcode))
1078 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1082 i = csr - CSR_CONFIG_ROM;
1083 if (i + length > CONFIG_ROM_SIZE) {
1084 fw_fill_response(&response, packet->header,
1085 RCODE_ADDRESS_ERROR, NULL, 0);
1086 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1087 fw_fill_response(&response, packet->header,
1088 RCODE_TYPE_ERROR, NULL, 0);
1090 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1091 (void *) ohci->config_rom + i, length);
1094 fw_core_handle_response(&ohci->card, &response);
1098 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1100 struct fw_packet response;
1101 int tcode, length, ext_tcode, sel;
1102 __be32 *payload, lock_old;
1103 u32 lock_arg, lock_data;
1105 tcode = HEADER_GET_TCODE(packet->header[0]);
1106 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1107 payload = packet->payload;
1108 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1110 if (tcode == TCODE_LOCK_REQUEST &&
1111 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1112 lock_arg = be32_to_cpu(payload[0]);
1113 lock_data = be32_to_cpu(payload[1]);
1114 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1118 fw_fill_response(&response, packet->header,
1119 RCODE_TYPE_ERROR, NULL, 0);
1123 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1124 reg_write(ohci, OHCI1394_CSRData, lock_data);
1125 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1126 reg_write(ohci, OHCI1394_CSRControl, sel);
1128 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1129 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1131 fw_notify("swap not done yet\n");
1133 fw_fill_response(&response, packet->header,
1134 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1136 fw_core_handle_response(&ohci->card, &response);
1140 handle_local_request(struct context *ctx, struct fw_packet *packet)
1145 if (ctx == &ctx->ohci->at_request_ctx) {
1146 packet->ack = ACK_PENDING;
1147 packet->callback(packet, &ctx->ohci->card, packet->ack);
1151 ((unsigned long long)
1152 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1154 csr = offset - CSR_REGISTER_BASE;
1156 /* Handle config rom reads. */
1157 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1158 handle_local_rom(ctx->ohci, packet, csr);
1160 case CSR_BUS_MANAGER_ID:
1161 case CSR_BANDWIDTH_AVAILABLE:
1162 case CSR_CHANNELS_AVAILABLE_HI:
1163 case CSR_CHANNELS_AVAILABLE_LO:
1164 handle_local_lock(ctx->ohci, packet, csr);
1167 if (ctx == &ctx->ohci->at_request_ctx)
1168 fw_core_handle_request(&ctx->ohci->card, packet);
1170 fw_core_handle_response(&ctx->ohci->card, packet);
1174 if (ctx == &ctx->ohci->at_response_ctx) {
1175 packet->ack = ACK_COMPLETE;
1176 packet->callback(packet, &ctx->ohci->card, packet->ack);
1181 at_context_transmit(struct context *ctx, struct fw_packet *packet)
1183 unsigned long flags;
1186 spin_lock_irqsave(&ctx->ohci->lock, flags);
1188 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1189 ctx->ohci->generation == packet->generation) {
1190 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1191 handle_local_request(ctx, packet);
1195 retval = at_context_queue_packet(ctx, packet);
1196 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1199 packet->callback(packet, &ctx->ohci->card, packet->ack);
1203 static void bus_reset_tasklet(unsigned long data)
1205 struct fw_ohci *ohci = (struct fw_ohci *)data;
1206 int self_id_count, i, j, reg;
1207 int generation, new_generation;
1208 unsigned long flags;
1209 void *free_rom = NULL;
1210 dma_addr_t free_rom_bus = 0;
1212 reg = reg_read(ohci, OHCI1394_NodeID);
1213 if (!(reg & OHCI1394_NodeID_idValid)) {
1214 fw_notify("node ID not valid, new bus reset in progress\n");
1217 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1218 fw_notify("malconfigured bus\n");
1221 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1222 OHCI1394_NodeID_nodeNumber);
1224 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1225 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1226 fw_notify("inconsistent self IDs\n");
1230 * The count in the SelfIDCount register is the number of
1231 * bytes in the self ID receive buffer. Since we also receive
1232 * the inverted quadlets and a header quadlet, we shift one
1233 * bit extra to get the actual number of self IDs.
1235 self_id_count = (reg >> 3) & 0x3ff;
1236 if (self_id_count == 0) {
1237 fw_notify("inconsistent self IDs\n");
1240 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1243 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1244 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1245 fw_notify("inconsistent self IDs\n");
1248 ohci->self_id_buffer[j] =
1249 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1254 * Check the consistency of the self IDs we just read. The
1255 * problem we face is that a new bus reset can start while we
1256 * read out the self IDs from the DMA buffer. If this happens,
1257 * the DMA buffer will be overwritten with new self IDs and we
1258 * will read out inconsistent data. The OHCI specification
1259 * (section 11.2) recommends a technique similar to
1260 * linux/seqlock.h, where we remember the generation of the
1261 * self IDs in the buffer before reading them out and compare
1262 * it to the current generation after reading them out. If
1263 * the two generations match we know we have a consistent set
1267 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1268 if (new_generation != generation) {
1269 fw_notify("recursive bus reset detected, "
1270 "discarding self ids\n");
1274 /* FIXME: Document how the locking works. */
1275 spin_lock_irqsave(&ohci->lock, flags);
1277 ohci->generation = generation;
1278 context_stop(&ohci->at_request_ctx);
1279 context_stop(&ohci->at_response_ctx);
1280 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1283 * This next bit is unrelated to the AT context stuff but we
1284 * have to do it under the spinlock also. If a new config rom
1285 * was set up before this reset, the old one is now no longer
1286 * in use and we can free it. Update the config rom pointers
1287 * to point to the current config rom and clear the
1288 * next_config_rom pointer so a new udpate can take place.
1291 if (ohci->next_config_rom != NULL) {
1292 if (ohci->next_config_rom != ohci->config_rom) {
1293 free_rom = ohci->config_rom;
1294 free_rom_bus = ohci->config_rom_bus;
1296 ohci->config_rom = ohci->next_config_rom;
1297 ohci->config_rom_bus = ohci->next_config_rom_bus;
1298 ohci->next_config_rom = NULL;
1301 * Restore config_rom image and manually update
1302 * config_rom registers. Writing the header quadlet
1303 * will indicate that the config rom is ready, so we
1306 reg_write(ohci, OHCI1394_BusOptions,
1307 be32_to_cpu(ohci->config_rom[2]));
1308 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1309 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1312 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1313 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1314 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1317 spin_unlock_irqrestore(&ohci->lock, flags);
1320 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1321 free_rom, free_rom_bus);
1323 log_selfids(generation, self_id_count, ohci->self_id_buffer);
1325 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1326 self_id_count, ohci->self_id_buffer);
1329 static irqreturn_t irq_handler(int irq, void *data)
1331 struct fw_ohci *ohci = data;
1332 u32 event, iso_event, cycle_time;
1335 event = reg_read(ohci, OHCI1394_IntEventClear);
1337 if (!event || !~event)
1340 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1341 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1344 if (event & OHCI1394_selfIDComplete)
1345 tasklet_schedule(&ohci->bus_reset_tasklet);
1347 if (event & OHCI1394_RQPkt)
1348 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1350 if (event & OHCI1394_RSPkt)
1351 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1353 if (event & OHCI1394_reqTxComplete)
1354 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1356 if (event & OHCI1394_respTxComplete)
1357 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1359 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1360 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1363 i = ffs(iso_event) - 1;
1364 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1365 iso_event &= ~(1 << i);
1368 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1369 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1372 i = ffs(iso_event) - 1;
1373 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1374 iso_event &= ~(1 << i);
1377 if (unlikely(event & OHCI1394_regAccessFail))
1378 fw_error("Register access failure - "
1379 "please notify linux1394-devel@lists.sf.net\n");
1381 if (unlikely(event & OHCI1394_postedWriteErr))
1382 fw_error("PCI posted write error\n");
1384 if (unlikely(event & OHCI1394_cycleTooLong)) {
1385 if (printk_ratelimit())
1386 fw_notify("isochronous cycle too long\n");
1387 reg_write(ohci, OHCI1394_LinkControlSet,
1388 OHCI1394_LinkControl_cycleMaster);
1391 if (event & OHCI1394_cycle64Seconds) {
1392 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1393 if ((cycle_time & 0x80000000) == 0)
1394 ohci->bus_seconds++;
1400 static int software_reset(struct fw_ohci *ohci)
1404 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1406 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1407 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1408 OHCI1394_HCControl_softReset) == 0)
1416 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1418 struct fw_ohci *ohci = fw_ohci(card);
1419 struct pci_dev *dev = to_pci_dev(card->device);
1423 if (software_reset(ohci)) {
1424 fw_error("Failed to reset ohci card.\n");
1429 * Now enable LPS, which we need in order to start accessing
1430 * most of the registers. In fact, on some cards (ALI M5251),
1431 * accessing registers in the SClk domain without LPS enabled
1432 * will lock up the machine. Wait 50msec to make sure we have
1433 * full link enabled. However, with some cards (well, at least
1434 * a JMicron PCIe card), we have to try again sometimes.
1436 reg_write(ohci, OHCI1394_HCControlSet,
1437 OHCI1394_HCControl_LPS |
1438 OHCI1394_HCControl_postedWriteEnable);
1441 for (lps = 0, i = 0; !lps && i < 3; i++) {
1443 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1444 OHCI1394_HCControl_LPS;
1448 fw_error("Failed to set Link Power Status\n");
1452 reg_write(ohci, OHCI1394_HCControlClear,
1453 OHCI1394_HCControl_noByteSwapData);
1455 reg_write(ohci, OHCI1394_LinkControlSet,
1456 OHCI1394_LinkControl_rcvSelfID |
1457 OHCI1394_LinkControl_cycleTimerEnable |
1458 OHCI1394_LinkControl_cycleMaster);
1460 reg_write(ohci, OHCI1394_ATRetries,
1461 OHCI1394_MAX_AT_REQ_RETRIES |
1462 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1463 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1465 ar_context_run(&ohci->ar_request_ctx);
1466 ar_context_run(&ohci->ar_response_ctx);
1468 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1469 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1470 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1471 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1472 reg_write(ohci, OHCI1394_IntMaskSet,
1473 OHCI1394_selfIDComplete |
1474 OHCI1394_RQPkt | OHCI1394_RSPkt |
1475 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1476 OHCI1394_isochRx | OHCI1394_isochTx |
1477 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1478 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1479 OHCI1394_masterIntEnable);
1480 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1481 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1483 /* Activate link_on bit and contender bit in our self ID packets.*/
1484 if (ohci_update_phy_reg(card, 4, 0,
1485 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1489 * When the link is not yet enabled, the atomic config rom
1490 * update mechanism described below in ohci_set_config_rom()
1491 * is not active. We have to update ConfigRomHeader and
1492 * BusOptions manually, and the write to ConfigROMmap takes
1493 * effect immediately. We tie this to the enabling of the
1494 * link, so we have a valid config rom before enabling - the
1495 * OHCI requires that ConfigROMhdr and BusOptions have valid
1496 * values before enabling.
1498 * However, when the ConfigROMmap is written, some controllers
1499 * always read back quadlets 0 and 2 from the config rom to
1500 * the ConfigRomHeader and BusOptions registers on bus reset.
1501 * They shouldn't do that in this initial case where the link
1502 * isn't enabled. This means we have to use the same
1503 * workaround here, setting the bus header to 0 and then write
1504 * the right values in the bus reset tasklet.
1508 ohci->next_config_rom =
1509 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1510 &ohci->next_config_rom_bus,
1512 if (ohci->next_config_rom == NULL)
1515 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1516 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1519 * In the suspend case, config_rom is NULL, which
1520 * means that we just reuse the old config rom.
1522 ohci->next_config_rom = ohci->config_rom;
1523 ohci->next_config_rom_bus = ohci->config_rom_bus;
1526 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1527 ohci->next_config_rom[0] = 0;
1528 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1529 reg_write(ohci, OHCI1394_BusOptions,
1530 be32_to_cpu(ohci->next_config_rom[2]));
1531 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1533 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1535 if (request_irq(dev->irq, irq_handler,
1536 IRQF_SHARED, ohci_driver_name, ohci)) {
1537 fw_error("Failed to allocate shared interrupt %d.\n",
1539 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1540 ohci->config_rom, ohci->config_rom_bus);
1544 reg_write(ohci, OHCI1394_HCControlSet,
1545 OHCI1394_HCControl_linkEnable |
1546 OHCI1394_HCControl_BIBimageValid);
1550 * We are ready to go, initiate bus reset to finish the
1554 fw_core_initiate_bus_reset(&ohci->card, 1);
1560 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1562 struct fw_ohci *ohci;
1563 unsigned long flags;
1564 int retval = -EBUSY;
1565 __be32 *next_config_rom;
1566 dma_addr_t uninitialized_var(next_config_rom_bus);
1568 ohci = fw_ohci(card);
1571 * When the OHCI controller is enabled, the config rom update
1572 * mechanism is a bit tricky, but easy enough to use. See
1573 * section 5.5.6 in the OHCI specification.
1575 * The OHCI controller caches the new config rom address in a
1576 * shadow register (ConfigROMmapNext) and needs a bus reset
1577 * for the changes to take place. When the bus reset is
1578 * detected, the controller loads the new values for the
1579 * ConfigRomHeader and BusOptions registers from the specified
1580 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1581 * shadow register. All automatically and atomically.
1583 * Now, there's a twist to this story. The automatic load of
1584 * ConfigRomHeader and BusOptions doesn't honor the
1585 * noByteSwapData bit, so with a be32 config rom, the
1586 * controller will load be32 values in to these registers
1587 * during the atomic update, even on litte endian
1588 * architectures. The workaround we use is to put a 0 in the
1589 * header quadlet; 0 is endian agnostic and means that the
1590 * config rom isn't ready yet. In the bus reset tasklet we
1591 * then set up the real values for the two registers.
1593 * We use ohci->lock to avoid racing with the code that sets
1594 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1598 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1599 &next_config_rom_bus, GFP_KERNEL);
1600 if (next_config_rom == NULL)
1603 spin_lock_irqsave(&ohci->lock, flags);
1605 if (ohci->next_config_rom == NULL) {
1606 ohci->next_config_rom = next_config_rom;
1607 ohci->next_config_rom_bus = next_config_rom_bus;
1609 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1610 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1613 ohci->next_header = config_rom[0];
1614 ohci->next_config_rom[0] = 0;
1616 reg_write(ohci, OHCI1394_ConfigROMmap,
1617 ohci->next_config_rom_bus);
1621 spin_unlock_irqrestore(&ohci->lock, flags);
1624 * Now initiate a bus reset to have the changes take
1625 * effect. We clean up the old config rom memory and DMA
1626 * mappings in the bus reset tasklet, since the OHCI
1627 * controller could need to access it before the bus reset
1631 fw_core_initiate_bus_reset(&ohci->card, 1);
1633 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1634 next_config_rom, next_config_rom_bus);
1639 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1641 struct fw_ohci *ohci = fw_ohci(card);
1643 at_context_transmit(&ohci->at_request_ctx, packet);
1646 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1648 struct fw_ohci *ohci = fw_ohci(card);
1650 at_context_transmit(&ohci->at_response_ctx, packet);
1653 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1655 struct fw_ohci *ohci = fw_ohci(card);
1656 struct context *ctx = &ohci->at_request_ctx;
1657 struct driver_data *driver_data = packet->driver_data;
1658 int retval = -ENOENT;
1660 tasklet_disable(&ctx->tasklet);
1662 if (packet->ack != 0)
1665 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1666 driver_data->packet = NULL;
1667 packet->ack = RCODE_CANCELLED;
1668 packet->callback(packet, &ohci->card, packet->ack);
1672 tasklet_enable(&ctx->tasklet);
1678 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1680 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1683 struct fw_ohci *ohci = fw_ohci(card);
1684 unsigned long flags;
1688 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1689 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1692 spin_lock_irqsave(&ohci->lock, flags);
1694 if (ohci->generation != generation) {
1700 * Note, if the node ID contains a non-local bus ID, physical DMA is
1701 * enabled for _all_ nodes on remote buses.
1704 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1706 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1708 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1712 spin_unlock_irqrestore(&ohci->lock, flags);
1714 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1718 ohci_get_bus_time(struct fw_card *card)
1720 struct fw_ohci *ohci = fw_ohci(card);
1724 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1725 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1730 static int handle_ir_dualbuffer_packet(struct context *context,
1731 struct descriptor *d,
1732 struct descriptor *last)
1734 struct iso_context *ctx =
1735 container_of(context, struct iso_context, context);
1736 struct db_descriptor *db = (struct db_descriptor *) d;
1738 size_t header_length;
1742 if (db->first_res_count != 0 && db->second_res_count != 0) {
1743 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1744 /* This descriptor isn't done yet, stop iteration. */
1747 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1750 header_length = le16_to_cpu(db->first_req_count) -
1751 le16_to_cpu(db->first_res_count);
1753 i = ctx->header_length;
1755 end = p + header_length;
1756 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1758 * The iso header is byteswapped to little endian by
1759 * the controller, but the remaining header quadlets
1760 * are big endian. We want to present all the headers
1761 * as big endian, so we have to swap the first
1764 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1765 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1766 i += ctx->base.header_size;
1767 ctx->excess_bytes +=
1768 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1769 p += ctx->base.header_size + 4;
1771 ctx->header_length = i;
1773 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1774 le16_to_cpu(db->second_res_count);
1776 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1777 ir_header = (__le32 *) (db + 1);
1778 ctx->base.callback(&ctx->base,
1779 le32_to_cpu(ir_header[0]) & 0xffff,
1780 ctx->header_length, ctx->header,
1781 ctx->base.callback_data);
1782 ctx->header_length = 0;
1788 static int handle_ir_packet_per_buffer(struct context *context,
1789 struct descriptor *d,
1790 struct descriptor *last)
1792 struct iso_context *ctx =
1793 container_of(context, struct iso_context, context);
1794 struct descriptor *pd;
1799 for (pd = d; pd <= last; pd++) {
1800 if (pd->transfer_status)
1804 /* Descriptor(s) not done yet, stop iteration */
1807 i = ctx->header_length;
1810 if (ctx->base.header_size > 0 &&
1811 i + ctx->base.header_size <= PAGE_SIZE) {
1813 * The iso header is byteswapped to little endian by
1814 * the controller, but the remaining header quadlets
1815 * are big endian. We want to present all the headers
1816 * as big endian, so we have to swap the first quadlet.
1818 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1819 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1820 ctx->header_length += ctx->base.header_size;
1823 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1824 ir_header = (__le32 *) p;
1825 ctx->base.callback(&ctx->base,
1826 le32_to_cpu(ir_header[0]) & 0xffff,
1827 ctx->header_length, ctx->header,
1828 ctx->base.callback_data);
1829 ctx->header_length = 0;
1835 static int handle_it_packet(struct context *context,
1836 struct descriptor *d,
1837 struct descriptor *last)
1839 struct iso_context *ctx =
1840 container_of(context, struct iso_context, context);
1842 if (last->transfer_status == 0)
1843 /* This descriptor isn't done yet, stop iteration. */
1846 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1847 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1848 0, NULL, ctx->base.callback_data);
1853 static struct fw_iso_context *
1854 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1856 struct fw_ohci *ohci = fw_ohci(card);
1857 struct iso_context *ctx, *list;
1858 descriptor_callback_t callback;
1860 unsigned long flags;
1861 int index, retval = -ENOMEM;
1863 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1864 mask = &ohci->it_context_mask;
1865 list = ohci->it_context_list;
1866 callback = handle_it_packet;
1868 mask = &ohci->ir_context_mask;
1869 list = ohci->ir_context_list;
1870 if (ohci->version >= OHCI_VERSION_1_1)
1871 callback = handle_ir_dualbuffer_packet;
1873 callback = handle_ir_packet_per_buffer;
1876 spin_lock_irqsave(&ohci->lock, flags);
1877 index = ffs(*mask) - 1;
1879 *mask &= ~(1 << index);
1880 spin_unlock_irqrestore(&ohci->lock, flags);
1883 return ERR_PTR(-EBUSY);
1885 if (type == FW_ISO_CONTEXT_TRANSMIT)
1886 regs = OHCI1394_IsoXmitContextBase(index);
1888 regs = OHCI1394_IsoRcvContextBase(index);
1891 memset(ctx, 0, sizeof(*ctx));
1892 ctx->header_length = 0;
1893 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1894 if (ctx->header == NULL)
1897 retval = context_init(&ctx->context, ohci, regs, callback);
1899 goto out_with_header;
1904 free_page((unsigned long)ctx->header);
1906 spin_lock_irqsave(&ohci->lock, flags);
1907 *mask |= 1 << index;
1908 spin_unlock_irqrestore(&ohci->lock, flags);
1910 return ERR_PTR(retval);
1913 static int ohci_start_iso(struct fw_iso_context *base,
1914 s32 cycle, u32 sync, u32 tags)
1916 struct iso_context *ctx = container_of(base, struct iso_context, base);
1917 struct fw_ohci *ohci = ctx->context.ohci;
1921 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1922 index = ctx - ohci->it_context_list;
1925 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1926 (cycle & 0x7fff) << 16;
1928 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1929 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1930 context_run(&ctx->context, match);
1932 index = ctx - ohci->ir_context_list;
1933 control = IR_CONTEXT_ISOCH_HEADER;
1934 if (ohci->version >= OHCI_VERSION_1_1)
1935 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1936 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1938 match |= (cycle & 0x07fff) << 12;
1939 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1942 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1943 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1944 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1945 context_run(&ctx->context, control);
1951 static int ohci_stop_iso(struct fw_iso_context *base)
1953 struct fw_ohci *ohci = fw_ohci(base->card);
1954 struct iso_context *ctx = container_of(base, struct iso_context, base);
1957 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1958 index = ctx - ohci->it_context_list;
1959 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1961 index = ctx - ohci->ir_context_list;
1962 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1965 context_stop(&ctx->context);
1970 static void ohci_free_iso_context(struct fw_iso_context *base)
1972 struct fw_ohci *ohci = fw_ohci(base->card);
1973 struct iso_context *ctx = container_of(base, struct iso_context, base);
1974 unsigned long flags;
1977 ohci_stop_iso(base);
1978 context_release(&ctx->context);
1979 free_page((unsigned long)ctx->header);
1981 spin_lock_irqsave(&ohci->lock, flags);
1983 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1984 index = ctx - ohci->it_context_list;
1985 ohci->it_context_mask |= 1 << index;
1987 index = ctx - ohci->ir_context_list;
1988 ohci->ir_context_mask |= 1 << index;
1991 spin_unlock_irqrestore(&ohci->lock, flags);
1995 ohci_queue_iso_transmit(struct fw_iso_context *base,
1996 struct fw_iso_packet *packet,
1997 struct fw_iso_buffer *buffer,
1998 unsigned long payload)
2000 struct iso_context *ctx = container_of(base, struct iso_context, base);
2001 struct descriptor *d, *last, *pd;
2002 struct fw_iso_packet *p;
2004 dma_addr_t d_bus, page_bus;
2005 u32 z, header_z, payload_z, irq;
2006 u32 payload_index, payload_end_index, next_page_index;
2007 int page, end_page, i, length, offset;
2010 * FIXME: Cycle lost behavior should be configurable: lose
2011 * packet, retransmit or terminate..
2015 payload_index = payload;
2021 if (p->header_length > 0)
2024 /* Determine the first page the payload isn't contained in. */
2025 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2026 if (p->payload_length > 0)
2027 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2033 /* Get header size in number of descriptors. */
2034 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2036 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2041 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2042 d[0].req_count = cpu_to_le16(8);
2044 header = (__le32 *) &d[1];
2045 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2046 IT_HEADER_TAG(p->tag) |
2047 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2048 IT_HEADER_CHANNEL(ctx->base.channel) |
2049 IT_HEADER_SPEED(ctx->base.speed));
2051 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2052 p->payload_length));
2055 if (p->header_length > 0) {
2056 d[2].req_count = cpu_to_le16(p->header_length);
2057 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2058 memcpy(&d[z], p->header, p->header_length);
2061 pd = d + z - payload_z;
2062 payload_end_index = payload_index + p->payload_length;
2063 for (i = 0; i < payload_z; i++) {
2064 page = payload_index >> PAGE_SHIFT;
2065 offset = payload_index & ~PAGE_MASK;
2066 next_page_index = (page + 1) << PAGE_SHIFT;
2068 min(next_page_index, payload_end_index) - payload_index;
2069 pd[i].req_count = cpu_to_le16(length);
2071 page_bus = page_private(buffer->pages[page]);
2072 pd[i].data_address = cpu_to_le32(page_bus + offset);
2074 payload_index += length;
2078 irq = DESCRIPTOR_IRQ_ALWAYS;
2080 irq = DESCRIPTOR_NO_IRQ;
2082 last = z == 2 ? d : d + z - 1;
2083 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2085 DESCRIPTOR_BRANCH_ALWAYS |
2088 context_append(&ctx->context, d, z, header_z);
2094 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2095 struct fw_iso_packet *packet,
2096 struct fw_iso_buffer *buffer,
2097 unsigned long payload)
2099 struct iso_context *ctx = container_of(base, struct iso_context, base);
2100 struct db_descriptor *db = NULL;
2101 struct descriptor *d;
2102 struct fw_iso_packet *p;
2103 dma_addr_t d_bus, page_bus;
2104 u32 z, header_z, length, rest;
2105 int page, offset, packet_count, header_size;
2108 * FIXME: Cycle lost behavior should be configurable: lose
2109 * packet, retransmit or terminate..
2116 * The OHCI controller puts the status word in the header
2117 * buffer too, so we need 4 extra bytes per packet.
2119 packet_count = p->header_length / ctx->base.header_size;
2120 header_size = packet_count * (ctx->base.header_size + 4);
2122 /* Get header size in number of descriptors. */
2123 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2124 page = payload >> PAGE_SHIFT;
2125 offset = payload & ~PAGE_MASK;
2126 rest = p->payload_length;
2128 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2130 d = context_get_descriptors(&ctx->context,
2131 z + header_z, &d_bus);
2135 db = (struct db_descriptor *) d;
2136 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2137 DESCRIPTOR_BRANCH_ALWAYS);
2138 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
2139 if (p->skip && rest == p->payload_length) {
2140 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2141 db->first_req_count = db->first_size;
2143 db->first_req_count = cpu_to_le16(header_size);
2145 db->first_res_count = db->first_req_count;
2146 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2148 if (p->skip && rest == p->payload_length)
2150 else if (offset + rest < PAGE_SIZE)
2153 length = PAGE_SIZE - offset;
2155 db->second_req_count = cpu_to_le16(length);
2156 db->second_res_count = db->second_req_count;
2157 page_bus = page_private(buffer->pages[page]);
2158 db->second_buffer = cpu_to_le32(page_bus + offset);
2160 if (p->interrupt && length == rest)
2161 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2163 context_append(&ctx->context, d, z, header_z);
2164 offset = (offset + length) & ~PAGE_MASK;
2174 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2175 struct fw_iso_packet *packet,
2176 struct fw_iso_buffer *buffer,
2177 unsigned long payload)
2179 struct iso_context *ctx = container_of(base, struct iso_context, base);
2180 struct descriptor *d = NULL, *pd = NULL;
2181 struct fw_iso_packet *p = packet;
2182 dma_addr_t d_bus, page_bus;
2183 u32 z, header_z, rest;
2185 int page, offset, packet_count, header_size, payload_per_buffer;
2188 * The OHCI controller puts the status word in the
2189 * buffer too, so we need 4 extra bytes per packet.
2191 packet_count = p->header_length / ctx->base.header_size;
2192 header_size = ctx->base.header_size + 4;
2194 /* Get header size in number of descriptors. */
2195 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2196 page = payload >> PAGE_SHIFT;
2197 offset = payload & ~PAGE_MASK;
2198 payload_per_buffer = p->payload_length / packet_count;
2200 for (i = 0; i < packet_count; i++) {
2201 /* d points to the header descriptor */
2202 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2203 d = context_get_descriptors(&ctx->context,
2204 z + header_z, &d_bus);
2208 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2209 DESCRIPTOR_INPUT_MORE);
2210 if (p->skip && i == 0)
2211 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2212 d->req_count = cpu_to_le16(header_size);
2213 d->res_count = d->req_count;
2214 d->transfer_status = 0;
2215 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2217 rest = payload_per_buffer;
2218 for (j = 1; j < z; j++) {
2220 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2221 DESCRIPTOR_INPUT_MORE);
2223 if (offset + rest < PAGE_SIZE)
2226 length = PAGE_SIZE - offset;
2227 pd->req_count = cpu_to_le16(length);
2228 pd->res_count = pd->req_count;
2229 pd->transfer_status = 0;
2231 page_bus = page_private(buffer->pages[page]);
2232 pd->data_address = cpu_to_le32(page_bus + offset);
2234 offset = (offset + length) & ~PAGE_MASK;
2239 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2240 DESCRIPTOR_INPUT_LAST |
2241 DESCRIPTOR_BRANCH_ALWAYS);
2242 if (p->interrupt && i == packet_count - 1)
2243 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2245 context_append(&ctx->context, d, z, header_z);
2252 ohci_queue_iso(struct fw_iso_context *base,
2253 struct fw_iso_packet *packet,
2254 struct fw_iso_buffer *buffer,
2255 unsigned long payload)
2257 struct iso_context *ctx = container_of(base, struct iso_context, base);
2258 unsigned long flags;
2261 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2262 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2263 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
2264 else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
2265 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
2268 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2271 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2276 static const struct fw_card_driver ohci_driver = {
2277 .name = ohci_driver_name,
2278 .enable = ohci_enable,
2279 .update_phy_reg = ohci_update_phy_reg,
2280 .set_config_rom = ohci_set_config_rom,
2281 .send_request = ohci_send_request,
2282 .send_response = ohci_send_response,
2283 .cancel_packet = ohci_cancel_packet,
2284 .enable_phys_dma = ohci_enable_phys_dma,
2285 .get_bus_time = ohci_get_bus_time,
2287 .allocate_iso_context = ohci_allocate_iso_context,
2288 .free_iso_context = ohci_free_iso_context,
2289 .queue_iso = ohci_queue_iso,
2290 .start_iso = ohci_start_iso,
2291 .stop_iso = ohci_stop_iso,
2294 #ifdef CONFIG_PPC_PMAC
2295 static void ohci_pmac_on(struct pci_dev *dev)
2297 if (machine_is(powermac)) {
2298 struct device_node *ofn = pci_device_to_OF_node(dev);
2301 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2302 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2307 static void ohci_pmac_off(struct pci_dev *dev)
2309 if (machine_is(powermac)) {
2310 struct device_node *ofn = pci_device_to_OF_node(dev);
2313 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2314 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2319 #define ohci_pmac_on(dev)
2320 #define ohci_pmac_off(dev)
2321 #endif /* CONFIG_PPC_PMAC */
2323 static int __devinit
2324 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2326 struct fw_ohci *ohci;
2327 u32 bus_options, max_receive, link_speed;
2332 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2334 fw_error("Could not malloc fw_ohci data.\n");
2338 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2342 err = pci_enable_device(dev);
2344 fw_error("Failed to enable OHCI hardware.\n");
2348 pci_set_master(dev);
2349 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2350 pci_set_drvdata(dev, ohci);
2352 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2353 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2354 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2356 spin_lock_init(&ohci->lock);
2358 tasklet_init(&ohci->bus_reset_tasklet,
2359 bus_reset_tasklet, (unsigned long)ohci);
2361 err = pci_request_region(dev, 0, ohci_driver_name);
2363 fw_error("MMIO resource unavailable\n");
2367 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2368 if (ohci->registers == NULL) {
2369 fw_error("Failed to remap registers\n");
2374 ar_context_init(&ohci->ar_request_ctx, ohci,
2375 OHCI1394_AsReqRcvContextControlSet);
2377 ar_context_init(&ohci->ar_response_ctx, ohci,
2378 OHCI1394_AsRspRcvContextControlSet);
2380 context_init(&ohci->at_request_ctx, ohci,
2381 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2383 context_init(&ohci->at_response_ctx, ohci,
2384 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2386 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2387 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2388 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2389 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2390 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2392 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2393 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2394 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2395 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2396 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2398 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2399 fw_error("Out of memory for it/ir contexts.\n");
2401 goto fail_registers;
2404 /* self-id dma buffer allocation */
2405 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2409 if (ohci->self_id_cpu == NULL) {
2410 fw_error("Out of memory for self ID buffer.\n");
2412 goto fail_registers;
2415 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2416 max_receive = (bus_options >> 12) & 0xf;
2417 link_speed = bus_options & 0x7;
2418 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2419 reg_read(ohci, OHCI1394_GUIDLo);
2421 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2425 ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2426 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2427 dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
2431 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2432 ohci->self_id_cpu, ohci->self_id_bus);
2434 kfree(ohci->it_context_list);
2435 kfree(ohci->ir_context_list);
2436 pci_iounmap(dev, ohci->registers);
2438 pci_release_region(dev, 0);
2440 pci_disable_device(dev);
2448 static void pci_remove(struct pci_dev *dev)
2450 struct fw_ohci *ohci;
2452 ohci = pci_get_drvdata(dev);
2453 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2455 fw_core_remove_card(&ohci->card);
2458 * FIXME: Fail all pending packets here, now that the upper
2459 * layers can't queue any more.
2462 software_reset(ohci);
2463 free_irq(dev->irq, ohci);
2464 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2465 ohci->self_id_cpu, ohci->self_id_bus);
2466 kfree(ohci->it_context_list);
2467 kfree(ohci->ir_context_list);
2468 pci_iounmap(dev, ohci->registers);
2469 pci_release_region(dev, 0);
2470 pci_disable_device(dev);
2474 fw_notify("Removed fw-ohci device.\n");
2478 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2480 struct fw_ohci *ohci = pci_get_drvdata(dev);
2483 software_reset(ohci);
2484 free_irq(dev->irq, ohci);
2485 err = pci_save_state(dev);
2487 fw_error("pci_save_state failed\n");
2490 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2492 fw_error("pci_set_power_state failed with %d\n", err);
2498 static int pci_resume(struct pci_dev *dev)
2500 struct fw_ohci *ohci = pci_get_drvdata(dev);
2504 pci_set_power_state(dev, PCI_D0);
2505 pci_restore_state(dev);
2506 err = pci_enable_device(dev);
2508 fw_error("pci_enable_device failed\n");
2512 return ohci_enable(&ohci->card, NULL, 0);
2516 static struct pci_device_id pci_table[] = {
2517 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2521 MODULE_DEVICE_TABLE(pci, pci_table);
2523 static struct pci_driver fw_ohci_pci_driver = {
2524 .name = ohci_driver_name,
2525 .id_table = pci_table,
2527 .remove = pci_remove,
2529 .resume = pci_resume,
2530 .suspend = pci_suspend,
2534 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2535 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2536 MODULE_LICENSE("GPL");
2538 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2539 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2540 MODULE_ALIAS("ohci1394");
2543 static int __init fw_ohci_init(void)
2545 return pci_register_driver(&fw_ohci_pci_driver);
2548 static void __exit fw_ohci_cleanup(void)
2550 pci_unregister_driver(&fw_ohci_pci_driver);
2553 module_init(fw_ohci_init);
2554 module_exit(fw_ohci_cleanup);