2 * Defines, structures, APIs for edac_core module
4 * (C) 2007 Linux Networx (http://lnxi.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
8 * Written by Thayne Harbaugh
9 * Based on work by Dan Hollis <goemon at anime dot net> and others.
10 * http://www.anime.net/~goemon/linux-ecc/
12 * NMI handling support added by
13 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
15 * Refactored for multi-source files:
16 * Doug Thompson <norsk5@xmission.com>
23 #include <linux/kernel.h>
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <linux/smp.h>
28 #include <linux/pci.h>
29 #include <linux/time.h>
30 #include <linux/nmi.h>
31 #include <linux/rcupdate.h>
32 #include <linux/completion.h>
33 #include <linux/kobject.h>
34 #include <linux/platform_device.h>
35 #include <linux/sysdev.h>
36 #include <linux/workqueue.h>
37 #include <linux/version.h>
39 #define EDAC_MC_LABEL_LEN 31
40 #define EDAC_DEVICE_NAME_LEN 31
41 #define EDAC_ATTRIB_VALUE_LEN 15
42 #define MC_PROC_NAME_MAX_LEN 7
45 #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
46 #else /* PAGE_SHIFT > 20 */
47 #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) )
50 #define edac_printk(level, prefix, fmt, arg...) \
51 printk(level "EDAC " prefix ": " fmt, ##arg)
53 #define edac_mc_printk(mci, level, fmt, arg...) \
54 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
56 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
57 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
59 /* edac_device printk */
60 #define edac_device_printk(ctl, level, fmt, arg...) \
61 printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
64 #define edac_pci_printk(ctl, level, fmt, arg...) \
65 printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
67 /* prefixes for edac_printk() and edac_mc_printk() */
69 #define EDAC_PCI "PCI"
70 #define EDAC_DEBUG "DEBUG"
72 #ifdef CONFIG_EDAC_DEBUG
73 extern int edac_debug_level;
75 #define edac_debug_printk(level, fmt, arg...) \
77 if (level <= edac_debug_level) \
78 edac_printk(KERN_EMERG, EDAC_DEBUG, fmt, ##arg); \
81 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
82 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
83 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
84 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
85 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
87 #else /* !CONFIG_EDAC_DEBUG */
89 #define debugf0( ... )
90 #define debugf1( ... )
91 #define debugf2( ... )
92 #define debugf3( ... )
93 #define debugf4( ... )
95 #endif /* !CONFIG_EDAC_DEBUG */
97 #define BIT(x) (1 << (x))
99 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
100 PCI_DEVICE_ID_ ## vend ## _ ## dev
102 #define dev_name(dev) (dev)->dev_name
112 DEV_X32, /* Do these parts exist? */
113 DEV_X64 /* Do these parts exist? */
116 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
117 #define DEV_FLAG_X1 BIT(DEV_X1)
118 #define DEV_FLAG_X2 BIT(DEV_X2)
119 #define DEV_FLAG_X4 BIT(DEV_X4)
120 #define DEV_FLAG_X8 BIT(DEV_X8)
121 #define DEV_FLAG_X16 BIT(DEV_X16)
122 #define DEV_FLAG_X32 BIT(DEV_X32)
123 #define DEV_FLAG_X64 BIT(DEV_X64)
127 MEM_EMPTY = 0, /* Empty csrow */
128 MEM_RESERVED, /* Reserved csrow type */
129 MEM_UNKNOWN, /* Unknown csrow type */
130 MEM_FPM, /* Fast page mode */
131 MEM_EDO, /* Extended data out */
132 MEM_BEDO, /* Burst Extended data out */
133 MEM_SDR, /* Single data rate SDRAM */
134 MEM_RDR, /* Registered single data rate SDRAM */
135 MEM_DDR, /* Double data rate SDRAM */
136 MEM_RDDR, /* Registered Double data rate SDRAM */
137 MEM_RMBS, /* Rambus DRAM */
138 MEM_DDR2, /* DDR2 RAM */
139 MEM_FB_DDR2, /* fully buffered DDR2 */
140 MEM_RDDR2, /* Registered DDR2 RAM */
143 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
144 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
145 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
146 #define MEM_FLAG_FPM BIT(MEM_FPM)
147 #define MEM_FLAG_EDO BIT(MEM_EDO)
148 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
149 #define MEM_FLAG_SDR BIT(MEM_SDR)
150 #define MEM_FLAG_RDR BIT(MEM_RDR)
151 #define MEM_FLAG_DDR BIT(MEM_DDR)
152 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
153 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
154 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
155 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
156 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
158 /* chipset Error Detection and Correction capabilities and mode */
160 EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
161 EDAC_NONE, /* Doesnt support ECC */
162 EDAC_RESERVED, /* Reserved ECC type */
163 EDAC_PARITY, /* Detects parity errors */
164 EDAC_EC, /* Error Checking - no correction */
165 EDAC_SECDED, /* Single bit error correction, Double detection */
166 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
167 EDAC_S4ECD4ED, /* Chipkill x4 devices */
168 EDAC_S8ECD8ED, /* Chipkill x8 devices */
169 EDAC_S16ECD16ED, /* Chipkill x16 devices */
172 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
173 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
174 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
175 #define EDAC_FLAG_EC BIT(EDAC_EC)
176 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
177 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
178 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
179 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
180 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
182 /* scrubbing capabilities */
184 SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
185 SCRUB_NONE, /* No scrubber */
186 SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
187 SCRUB_SW_SRC, /* Software scrub only errors */
188 SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
189 SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
190 SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
191 SCRUB_HW_SRC, /* Hardware scrub only errors */
192 SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
193 SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
196 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
197 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
198 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
199 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
200 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
201 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
202 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
203 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
205 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
207 /* EDAC internal operation states */
208 #define OP_ALLOC 0x100
209 #define OP_RUNNING_POLL 0x201
210 #define OP_RUNNING_INTERRUPT 0x202
211 #define OP_RUNNING_POLL_INTR 0x203
212 #define OP_OFFLINE 0x300
215 * There are several things to be aware of that aren't at all obvious:
218 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
220 * These are some of the many terms that are thrown about that don't always
221 * mean what people think they mean (Inconceivable!). In the interest of
222 * creating a common ground for discussion, terms and their definitions
223 * will be established.
225 * Memory devices: The individual chip on a memory stick. These devices
226 * commonly output 4 and 8 bits each. Grouping several
227 * of these in parallel provides 64 bits which is common
228 * for a memory stick.
230 * Memory Stick: A printed circuit board that agregates multiple
231 * memory devices in parallel. This is the atomic
232 * memory component that is purchaseable by Joe consumer
233 * and loaded into a memory socket.
235 * Socket: A physical connector on the motherboard that accepts
236 * a single memory stick.
238 * Channel: Set of memory devices on a memory stick that must be
239 * grouped in parallel with one or more additional
240 * channels from other memory sticks. This parallel
241 * grouping of the output from multiple channels are
242 * necessary for the smallest granularity of memory access.
243 * Some memory controllers are capable of single channel -
244 * which means that memory sticks can be loaded
245 * individually. Other memory controllers are only
246 * capable of dual channel - which means that memory
247 * sticks must be loaded as pairs (see "socket set").
249 * Chip-select row: All of the memory devices that are selected together.
250 * for a single, minimum grain of memory access.
251 * This selects all of the parallel memory devices across
252 * all of the parallel channels. Common chip-select rows
253 * for single channel are 64 bits, for dual channel 128
256 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
257 * Motherboards commonly drive two chip-select pins to
258 * a memory stick. A single-ranked stick, will occupy
259 * only one of those rows. The other will be unused.
261 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
262 * access different sets of memory devices. The two
263 * rows cannot be accessed concurrently.
265 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
266 * A double-sided stick has two chip-select rows which
267 * access different sets of memory devices. The two
268 * rows cannot be accessed concurrently. "Double-sided"
269 * is irrespective of the memory devices being mounted
270 * on both sides of the memory stick.
272 * Socket set: All of the memory sticks that are required for for
273 * a single memory access or all of the memory sticks
274 * spanned by a chip-select row. A single socket set
275 * has two chip-select rows and if double-sided sticks
276 * are used these will occupy those chip-select rows.
278 * Bank: This term is avoided because it is unclear when
279 * needing to distinguish between chip-select rows and
289 * STRUCTURE ORGANIZATION AND CHOICES
293 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
296 struct channel_info {
297 int chan_idx; /* channel index */
298 u32 ce_count; /* Correctable Errors for this CHANNEL */
299 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
300 struct csrow_info *csrow; /* the parent */
304 unsigned long first_page; /* first page number in dimm */
305 unsigned long last_page; /* last page number in dimm */
306 unsigned long page_mask; /* used for interleaving -
309 u32 nr_pages; /* number of pages in csrow */
310 u32 grain; /* granularity of reported error in bytes */
311 int csrow_idx; /* the chip-select row */
312 enum dev_type dtype; /* memory device type */
313 u32 ue_count; /* Uncorrectable Errors for this csrow */
314 u32 ce_count; /* Correctable Errors for this csrow */
315 enum mem_type mtype; /* memory csrow type */
316 enum edac_type edac_mode; /* EDAC mode for this csrow */
317 struct mem_ctl_info *mci; /* the parent */
319 struct kobject kobj; /* sysfs kobject for this csrow */
321 /* channel information for this csrow */
323 struct channel_info *channels;
326 /* mcidev_sysfs_attribute structure
327 * used for driver sysfs attributes and in mem_ctl_info
328 * sysfs top level entries
330 struct mcidev_sysfs_attribute {
331 struct attribute attr;
332 ssize_t (*show)(struct mem_ctl_info *,char *);
333 ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
336 /* MEMORY controller information structure
338 struct mem_ctl_info {
339 struct list_head link; /* for global list of mem_ctl_info structs */
340 unsigned long mtype_cap; /* memory types supported by mc */
341 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
342 unsigned long edac_cap; /* configuration capabilities - this is
343 * closely related to edac_ctl_cap. The
344 * difference is that the controller may be
345 * capable of s4ecd4ed which would be listed
346 * in edac_ctl_cap, but if channels aren't
347 * capable of s4ecd4ed then the edac_cap would
348 * not have that capability.
350 unsigned long scrub_cap; /* chipset scrub capabilities */
351 enum scrub_type scrub_mode; /* current scrub mode */
353 /* Translates sdram memory scrub rate given in bytes/sec to the
354 internal representation and configures whatever else needs
357 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
359 /* Get the current sdram memory scrub rate from the internal
360 representation and converts it to the closest matching
361 bandwith in bytes/sec.
363 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
366 /* pointer to edac checking routine */
367 void (*edac_check) (struct mem_ctl_info * mci);
370 * Remaps memory pages: controller pages to physical pages.
371 * For most MC's, this will be NULL.
373 /* FIXME - why not send the phys page to begin with? */
374 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
378 struct csrow_info *csrows;
380 * FIXME - what about controllers on other busses? - IDs must be
381 * unique. dev pointer should be sufficiently unique, but
382 * BUS:SLOT.FUNC numbers may not be unique.
385 const char *mod_name;
387 const char *ctl_name;
388 const char *dev_name;
389 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
391 u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
392 u32 ce_noinfo_count; /* Correctable Errors w/o info */
393 u32 ue_count; /* Total Uncorrectable Errors for this MC */
394 u32 ce_count; /* Total Correctable Errors for this MC */
395 unsigned long start_time; /* mci load start time (in jiffies) */
397 /* this stuff is for safe removal of mc devices from global list while
398 * NMI handlers may be traversing list
401 struct completion complete;
403 /* edac sysfs device control */
404 struct kobject edac_mci_kobj;
406 /* Additional top controller level attributes, but specified
407 * by the low level driver.
409 * Set by the low level driver to provide attributes at the
410 * controller level, same level as 'ue_count' and 'ce_count' above.
411 * An array of structures, NULL terminated
413 * If attributes are desired, then set to array of attributes
414 * If no attributes are desired, leave NULL
416 struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
418 /* work struct for this MC */
419 struct delayed_work work;
421 /* the internal state of this controller instance */
426 * The following are the structures to provide for a generic
427 * or abstract 'edac_device'. This set of structures and the
428 * code that implements the APIs for the same, provide for
429 * registering EDAC type devices which are NOT standard memory.
431 * CPU caches (L1 and L2)
434 * Fabric switch units
435 * PCIe interface controllers
436 * other EDAC/ECC type devices that can be monitored for
439 * It allows for a 2 level set of hiearchry. For example:
441 * cache could be composed of L1, L2 and L3 levels of cache.
442 * Each CPU core would have its own L1 cache, while sharing
443 * L2 and maybe L3 caches.
445 * View them arranged, via the sysfs presentation:
446 * /sys/devices/system/edac/..
448 * mc/ <existing memory device directory>
449 * cpu/cpu0/.. <L1 and L2 block directory>
454 * cpu/cpu1/.. <L1 and L2 block directory>
461 * the L1 and L2 directories would be "edac_device_block's"
464 struct edac_device_counter {
469 /* forward reference */
470 struct edac_device_ctl_info;
471 struct edac_device_block;
473 /* edac_dev_sysfs_attribute structure
474 * used for driver sysfs attributes in mem_ctl_info
475 * for extra controls and attributes:
476 * like high level error Injection controls
478 struct edac_dev_sysfs_attribute {
479 struct attribute attr;
480 ssize_t (*show)(struct edac_device_ctl_info *, char *);
481 ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
484 /* edac_dev_sysfs_block_attribute structure
485 * used in leaf 'block' nodes for adding controls/attributes
487 struct edac_dev_sysfs_block_attribute {
488 struct attribute attr;
489 ssize_t (*show)(struct kobject *, struct attribute *, char *);
490 ssize_t (*store)(struct kobject *, struct attribute *,
491 const char *, size_t);
492 struct edac_device_block *block;
499 /* device block control structure */
500 struct edac_device_block {
501 struct edac_device_instance *instance; /* Up Pointer */
502 char name[EDAC_DEVICE_NAME_LEN + 1];
504 struct edac_device_counter counters; /* basic UE and CE counters */
506 int nr_attribs; /* how many attributes */
508 /* this block's attributes, could be NULL */
509 struct edac_dev_sysfs_block_attribute *block_attributes;
511 /* edac sysfs device control */
513 struct completion kobj_complete;
516 /* device instance control structure */
517 struct edac_device_instance {
518 struct edac_device_ctl_info *ctl; /* Up pointer */
519 char name[EDAC_DEVICE_NAME_LEN + 4];
521 struct edac_device_counter counters; /* instance counters */
523 u32 nr_blocks; /* how many blocks */
524 struct edac_device_block *blocks; /* block array */
526 /* edac sysfs device control */
528 struct completion kobj_complete;
533 * Abstract edac_device control info structure
536 struct edac_device_ctl_info {
537 /* for global list of edac_device_ctl_info structs */
538 struct list_head link;
542 /* Per instance controls for this edac_device */
543 int log_ue; /* boolean for logging UEs */
544 int log_ce; /* boolean for logging CEs */
545 int panic_on_ue; /* boolean for panic'ing on an UE */
546 unsigned poll_msec; /* number of milliseconds to poll interval */
547 unsigned long delay; /* number of jiffies for poll_msec */
549 /* Additional top controller level attributes, but specified
550 * by the low level driver.
552 * Set by the low level driver to provide attributes at the
553 * controller level, same level as 'ue_count' and 'ce_count' above.
554 * An array of structures, NULL terminated
556 * If attributes are desired, then set to array of attributes
557 * If no attributes are desired, leave NULL
559 struct edac_dev_sysfs_attribute *sysfs_attributes;
561 /* pointer to main 'edac' class in sysfs */
562 struct sysdev_class *edac_class;
564 /* the internal state of this controller instance */
566 /* work struct for this instance */
567 struct delayed_work work;
569 /* pointer to edac polling checking routine:
570 * If NOT NULL: points to polling check routine
571 * If NULL: Then assumes INTERRUPT operation, where
572 * MC driver will receive events
574 void (*edac_check) (struct edac_device_ctl_info * edac_dev);
576 struct device *dev; /* pointer to device structure */
578 const char *mod_name; /* module name */
579 const char *ctl_name; /* edac controller name */
580 const char *dev_name; /* pci/platform/etc... name */
582 void *pvt_info; /* pointer to 'private driver' info */
584 unsigned long start_time; /* edac_device load start time (jiffies) */
586 /* these are for safe removal of mc devices from global list while
587 * NMI handlers may be traversing list
590 struct completion complete;
592 /* sysfs top name under 'edac' directory
599 char name[EDAC_DEVICE_NAME_LEN + 1];
601 /* Number of instances supported on this control structure
602 * and the array of those instances
605 struct edac_device_instance *instances;
607 /* Event counters for the this whole EDAC Device */
608 struct edac_device_counter counters;
610 /* edac sysfs device control for the 'name'
611 * device this structure controls
614 struct completion kobj_complete;
617 /* To get from the instance's wq to the beginning of the ctl structure */
618 #define to_edac_mem_ctl_work(w) \
619 container_of(w, struct mem_ctl_info, work)
621 #define to_edac_device_ctl_work(w) \
622 container_of(w,struct edac_device_ctl_info,work)
625 * The alloc() and free() functions for the 'edac_device' control info
626 * structure. A MC driver will allocate one of these for each edac_device
627 * it is going to control/register with the EDAC CORE.
629 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
630 unsigned sizeof_private,
631 char *edac_device_name, unsigned nr_instances,
632 char *edac_block_name, unsigned nr_blocks,
633 unsigned offset_value,
634 struct edac_dev_sysfs_block_attribute *block_attributes,
638 /* The offset value can be:
639 * -1 indicating no offset value
640 * 0 for zero-based block numbers
641 * 1 for 1-based block number
642 * other for other-based block number
644 #define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
646 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
650 struct edac_pci_counter {
656 * Abstract edac_pci control info structure
659 struct edac_pci_ctl_info {
660 /* for global list of edac_pci_ctl_info structs */
661 struct list_head link;
665 struct sysdev_class *edac_class; /* pointer to class */
667 /* the internal state of this controller instance */
669 /* work struct for this instance */
670 struct delayed_work work;
672 /* pointer to edac polling checking routine:
673 * If NOT NULL: points to polling check routine
674 * If NULL: Then assumes INTERRUPT operation, where
675 * MC driver will receive events
677 void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
679 struct device *dev; /* pointer to device structure */
681 const char *mod_name; /* module name */
682 const char *ctl_name; /* edac controller name */
683 const char *dev_name; /* pci/platform/etc... name */
685 void *pvt_info; /* pointer to 'private driver' info */
687 unsigned long start_time; /* edac_pci load start time (jiffies) */
689 /* these are for safe removal of devices from global list while
690 * NMI handlers may be traversing list
693 struct completion complete;
695 /* sysfs top name under 'edac' directory
702 char name[EDAC_DEVICE_NAME_LEN + 1];
704 /* Event counters for the this whole EDAC Device */
705 struct edac_pci_counter counters;
707 /* edac sysfs device control for the 'name'
708 * device this structure controls
711 struct completion kobj_complete;
714 #define to_edac_pci_ctl_work(w) \
715 container_of(w, struct edac_pci_ctl_info,work)
717 /* write all or some bits in a byte-register*/
718 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
724 pci_read_config_byte(pdev, offset, &buf);
730 pci_write_config_byte(pdev, offset, value);
733 /* write all or some bits in a word-register*/
734 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
737 if (mask != 0xffff) {
740 pci_read_config_word(pdev, offset, &buf);
746 pci_write_config_word(pdev, offset, value);
749 /* write all or some bits in a dword-register*/
750 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
753 if (mask != 0xffff) {
756 pci_read_config_dword(pdev, offset, &buf);
762 pci_write_config_dword(pdev, offset, value);
765 #endif /* CONFIG_PCI */
767 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
768 unsigned nr_chans, int edac_index);
769 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
770 extern void edac_mc_free(struct mem_ctl_info *mci);
771 extern struct mem_ctl_info *edac_mc_find(int idx);
772 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
773 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
777 * The no info errors are used when error overflows are reported.
778 * There are a limited number of error logging registers that can
779 * be exausted. When all registers are exhausted and an additional
780 * error occurs then an error overflow register records that an
781 * error occured and the type of error, but doesn't have any
782 * further information. The ce/ue versions make for cleaner
783 * reporting logic and function interface - reduces conditional
784 * statement clutter and extra function arguments.
786 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
787 unsigned long page_frame_number,
788 unsigned long offset_in_page,
789 unsigned long syndrome, int row, int channel,
791 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
793 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
794 unsigned long page_frame_number,
795 unsigned long offset_in_page, int row,
797 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
799 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
800 unsigned int channel0, unsigned int channel1,
802 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
803 unsigned int channel, char *msg);
808 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
809 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
810 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
811 int inst_nr, int block_nr, const char *msg);
812 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
813 int inst_nr, int block_nr, const char *msg);
818 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
819 const char *edac_pci_name);
821 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
823 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
824 unsigned long value);
826 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
827 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
829 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
831 const char *mod_name);
833 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
834 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
835 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
840 extern char *edac_op_state_to_string(int op_state);
842 #endif /* _EDAC_CORE_H_ */