2 * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
4 * Copyright (C) 2002-2006 Nokia Corporation. All rights reserved.
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #ifndef __OMAP_DSP_OMAP1_DSP_H
25 #define __OMAP_DSP_OMAP1_DSP_H
27 #ifdef CONFIG_ARCH_OMAP15XX
28 #define OMAP1510_DARAM_BASE (OMAP1510_DSP_BASE + 0x0)
29 #define OMAP1510_DARAM_SIZE 0x10000
30 #define OMAP1510_SARAM_BASE (OMAP1510_DSP_BASE + 0x10000)
31 #define OMAP1510_SARAM_SIZE 0x18000
34 #ifdef CONFIG_ARCH_OMAP16XX
35 #define OMAP16XX_DARAM_BASE (OMAP16XX_DSP_BASE + 0x0)
36 #define OMAP16XX_DARAM_SIZE 0x10000
37 #define OMAP16XX_SARAM_BASE (OMAP16XX_DSP_BASE + 0x10000)
38 #define OMAP16XX_SARAM_SIZE 0x18000
44 #define ARM_RSTCT1_SW_RST 0x0008
45 #define ARM_RSTCT1_DSP_RST 0x0004
46 #define ARM_RSTCT1_DSP_EN 0x0002
47 #define ARM_RSTCT1_ARM_RST 0x0001
52 #define MPUI_CTRL_WORDSWAP_MASK 0x00600000
53 #define MPUI_CTRL_WORDSWAP_ALL 0x00000000
54 #define MPUI_CTRL_WORDSWAP_NONAPI 0x00200000
55 #define MPUI_CTRL_WORDSWAP_API 0x00400000
56 #define MPUI_CTRL_WORDSWAP_NONE 0x00600000
57 #define MPUI_CTRL_AP_MASK 0x001c0000
58 #define MPUI_CTRL_AP_MDH 0x00000000
59 #define MPUI_CTRL_AP_MHD 0x00040000
60 #define MPUI_CTRL_AP_DMH 0x00080000
61 #define MPUI_CTRL_AP_HMD 0x000c0000
62 #define MPUI_CTRL_AP_DHM 0x00100000
63 #define MPUI_CTRL_AP_HDM 0x00140000
64 #define MPUI_CTRL_BYTESWAP_MASK 0x00030000
65 #define MPUI_CTRL_BYTESWAP_NONE 0x00000000
66 #define MPUI_CTRL_BYTESWAP_NONAPI 0x00010000
67 #define MPUI_CTRL_BYTESWAP_ALL 0x00020000
68 #define MPUI_CTRL_BYTESWAP_API 0x00030000
69 #define MPUI_CTRL_TIMEOUT_MASK 0x0000ff00
70 #define MPUI_CTRL_APIF_HNSTB_DIV_MASK 0x000000f0
71 #define MPUI_CTRL_S_NABORT_GL 0x00000008
72 #define MPUI_CTRL_S_NABORT_32BIT 0x00000004
73 #define MPUI_CTRL_EN_TIMEOUT 0x00000002
74 #define MPUI_CTRL_HF_MCUCLK 0x00000001
75 #define DSP_BOOT_CONFIG_DIRECT 0x00000000
76 #define DSP_BOOT_CONFIG_PSD_DIRECT 0x00000001
77 #define DSP_BOOT_CONFIG_IDLE 0x00000002
78 #define DSP_BOOT_CONFIG_DL16 0x00000003
79 #define DSP_BOOT_CONFIG_DL32 0x00000004
80 #define DSP_BOOT_CONFIG_MPUI 0x00000005
81 #define DSP_BOOT_CONFIG_INTERNAL 0x00000006
86 * pseudo direct: 0x080000
87 * MPUI: branch 0x010000
88 * internel: branch 0x024000
90 #define DSP_BOOT_ADR_DIRECT 0xffff00
91 #define DSP_BOOT_ADR_PSD_DIRECT 0x080000
92 #define DSP_BOOT_ADR_MPUI 0x010000
93 #define DSP_BOOT_ADR_INTERNAL 0x024000
98 #define TC_ENDIANISM_SWAP 0x00000002
99 #define TC_ENDIANISM_SWAP_WORD 0x00000002
100 #define TC_ENDIANISM_SWAP_BYTE 0x00000000
101 #define TC_ENDIANISM_EN 0x00000001
106 #define DSPREG_ICR_RESERVED_BITS 0xffc0
107 #define DSPREG_ICR_EMIF 0x0020
108 #define DSPREG_ICR_DPLL 0x0010
109 #define DSPREG_ICR_PER 0x0008
110 #define DSPREG_ICR_CACHE 0x0004
111 #define DSPREG_ICR_DMA 0x0002
112 #define DSPREG_ICR_CPU 0x0001
114 #endif /* __OMAP_DSP_OMAP1_DSP_H */