2 * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
4 * Copyright (C) 2002-2006 Nokia Corporation. All rights reserved.
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #ifndef __PLAT_OMAP_DSP_DSP_H
25 #define __PLAT_OMAP_DSP_DSP_H
27 #include "hardware_dsp.h"
28 #include <asm/arch/dsp_common.h>
29 #include <asm/arch/mmu.h>
32 #ifdef CONFIG_ARCH_OMAP2
33 #include "../../../arch/arm/mach-omap2/prm.h"
34 #include "../../../arch/arm/mach-omap2/prm_regbits_24xx.h"
35 #include "../../../arch/arm/mach-omap2/cm.h"
36 #include "../../../arch/arm/mach-omap2/cm_regbits_24xx.h"
40 * MAJOR device number: !! allocated arbitrary !!
42 #define OMAP_DSP_CTL_MAJOR 96
43 #define OMAP_DSP_TASK_MAJOR 97
45 #define OLD_BINARY_SUPPORT y
47 #ifdef OLD_BINARY_SUPPORT
48 #define MBREV_3_0 0x0017
49 #define MBREV_3_2 0x0018
52 #define DSP_INIT_PAGE 0xfff000
54 #ifdef CONFIG_ARCH_OMAP1
55 /* idle program will be placed at IDLEPG_BASE. */
56 #define IDLEPG_BASE 0xfffe00
57 #define IDLEPG_SIZE 0x100
58 #endif /* CONFIG_ARCH_OMAP1 */
60 /* timeout value for DSP response */
61 #define DSP_TIMEOUT (10 * HZ)
64 MEM_TYPE_CROSSING = -1,
72 typedef int __bitwise arm_dsp_dir_t;
73 #define DIR_A2D ((__force arm_dsp_dir_t) 1)
74 #define DIR_D2A ((__force arm_dsp_dir_t) 2)
80 CFGSTAT_RESUME, /* request only */
90 /* keep 2 entries for TID_FREE and TID_ANON */
91 #define TASKDEV_MAX 254
93 #define MK32(uw,lw) (((u32)(uw)) << 16 | (lw))
94 #define MKLONG(uw,lw) (((unsigned long)(uw)) << 16 | (lw))
95 #define MKVIRT(uw,lw) dspword_to_virt(MKLONG((uw), (lw)));
104 struct mem_sync_struct {
105 struct sync_seq *DARAM;
106 struct sync_seq *SARAM;
107 struct sync_seq *SDRAM;
110 /* struct mbcmd and union mbcmd_hw must be compatible */
118 #define MBCMD_INIT(h, l, d) { \
130 typedef u32 dsp_long_t; /* must have ability to carry TADD_ABORTADR */
132 extern void dsp_mbox_start(void);
133 extern void dsp_mbox_stop(void);
134 extern int dsp_mbox_config(void *p);
135 extern int sync_with_dsp(u16 *syncwd, u16 tid, int try_cnt);
136 extern int __dsp_mbcmd_send_exarg(struct mbcmd *mb, struct mb_exarg *arg,
138 #define dsp_mbcmd_send(mb) __dsp_mbcmd_send_exarg((mb), NULL, 0)
139 #define dsp_mbcmd_send_exarg(mb, arg) __dsp_mbcmd_send_exarg((mb), (arg), 0)
140 extern int dsp_mbcmd_send_and_wait_exarg(struct mbcmd *mb, struct mb_exarg *arg,
141 wait_queue_head_t *q);
142 #define dsp_mbcmd_send_and_wait(mb, q) \
143 dsp_mbcmd_send_and_wait_exarg((mb), NULL, (q))
145 static inline int __mbcompose_send_exarg(u8 cmd_h, u8 cmd_l, u16 data,
146 struct mb_exarg *arg,
149 struct mbcmd mb = MBCMD_INIT(cmd_h, cmd_l, data);
150 return __dsp_mbcmd_send_exarg(&mb, arg, recovery_flag);
152 #define mbcompose_send(cmd_h, cmd_l, data) \
153 __mbcompose_send_exarg(MBOX_CMD_DSP_##cmd_h, (cmd_l), (data), NULL, 0)
154 #define mbcompose_send_exarg(cmd_h, cmd_l, data, arg) \
155 __mbcompose_send_exarg(MBOX_CMD_DSP_##cmd_h, (cmd_l), (data), arg, 0)
156 #define mbcompose_send_recovery(cmd_h, cmd_l, data) \
157 __mbcompose_send_exarg(MBOX_CMD_DSP_##cmd_h, (cmd_l), (data), NULL, 1)
159 static inline int __mbcompose_send_and_wait_exarg(u8 cmd_h, u8 cmd_l,
161 struct mb_exarg *arg,
162 wait_queue_head_t *q)
164 struct mbcmd mb = MBCMD_INIT(cmd_h, cmd_l, data);
165 return dsp_mbcmd_send_and_wait_exarg(&mb, arg, q);
167 #define mbcompose_send_and_wait(cmd_h, cmd_l, data, q) \
168 __mbcompose_send_and_wait_exarg(MBOX_CMD_DSP_##cmd_h, (cmd_l), (data), \
170 #define mbcompose_send_and_wait_exarg(cmd_h, cmd_l, data, arg, q) \
171 __mbcompose_send_and_wait_exarg(MBOX_CMD_DSP_##cmd_h, (cmd_l), (data), \
174 extern struct ipbuf_head *bid_to_ipbuf(u16 bid);
175 extern void ipbuf_start(void);
176 extern void ipbuf_stop(void);
177 extern int ipbuf_config(u16 ln, u16 lsz, void *base);
178 extern int ipbuf_sys_config(void *p, arm_dsp_dir_t dir);
179 extern int ipbuf_p_validate(void *p, arm_dsp_dir_t dir);
180 extern struct ipbuf_head *get_free_ipbuf(u8 tid);
181 extern void release_ipbuf(struct ipbuf_head *ipb_h);
182 extern void balance_ipbuf(void);
183 extern void unuse_ipbuf(struct ipbuf_head *ipb_h);
184 extern void unuse_ipbuf_nowait(struct ipbuf_head *ipb_h);
186 #define release_ipbuf_pvt(ipbuf_pvt) \
188 (ipbuf_pvt)->s = TID_FREE; \
191 extern int mbox_revision;
193 extern int dsp_cfgstat_request(enum cfgstat_e st);
194 extern enum cfgstat_e dsp_cfgstat_get_stat(void);
195 extern int dsp_set_runlevel(u8 level);
197 extern int dsp_task_config_all(u8 n);
198 extern void dsp_task_unconfig_all(void);
199 extern u8 dsp_task_count(void);
200 extern int dsp_taskmod_busy(void);
201 extern int dsp_mkdev(char *name);
202 extern int dsp_rmdev(char *name);
203 extern int dsp_tadd_minor(unsigned char minor, dsp_long_t adr);
204 extern int dsp_tdel_minor(unsigned char minor);
205 extern int dsp_tkill_minor(unsigned char minor);
206 extern long taskdev_state_stale(unsigned char minor);
207 extern int dsp_dbg_config(u16 *buf, u16 sz, u16 lsz);
208 extern void dsp_dbg_stop(void);
210 extern int ipbuf_is_held(u8 tid, u16 bid);
212 extern int dsp_mem_sync_inc(void);
213 extern int dsp_mem_sync_config(struct mem_sync_struct *sync);
214 extern enum dsp_mem_type_e dsp_mem_type(void *vadr, size_t len);
215 extern int dsp_address_validate(void *p, size_t len, char *fmt, ...);
216 #ifdef CONFIG_ARCH_OMAP1
217 extern void dsp_mem_usecount_clear(void);
219 extern void exmap_use(void *vadr, size_t len);
220 extern void exmap_unuse(void *vadr, size_t len);
221 extern unsigned long dsp_virt_to_phys(void *vadr, size_t *len);
222 extern void dsp_mem_start(void);
223 extern void dsp_mem_stop(void);
225 extern void dsp_twch_start(void);
226 extern void dsp_twch_stop(void);
227 extern void dsp_twch_touch(void);
229 extern void dsp_err_start(void);
230 extern void dsp_err_stop(void);
231 extern void dsp_err_set(enum errcode_e code, unsigned long arg);
232 extern void dsp_err_clear(enum errcode_e code);
233 extern int dsp_err_isset(enum errcode_e code);
243 enum cmd_l_type_e cmd_l_type;
244 void (*handler)(struct mbcmd *mb);
247 extern const struct cmdinfo *cmdinfo[];
249 #define cmd_name(mb) (cmdinfo[(mb).cmd_h]->name)
250 extern char *subcmd_name(struct mbcmd *mb);
252 extern void mblog_add(struct mbcmd *mb, arm_dsp_dir_t dir);
254 extern struct omap_mmu dsp_mmu;
256 #define dsp_mem_enable(addr) omap_mmu_mem_enable(&dsp_mmu, (addr))
257 #define dsp_mem_disable(addr) omap_mmu_mem_disable(&dsp_mmu, (addr))
259 #define DSPSPACE_SIZE 0x1000000
261 #define omap_set_bit_regw(b,r) \
262 do { omap_writew(omap_readw(r) | (b), (r)); } while(0)
263 #define omap_clr_bit_regw(b,r) \
264 do { omap_writew(omap_readw(r) & ~(b), (r)); } while(0)
265 #define omap_set_bit_regl(b,r) \
266 do { omap_writel(omap_readl(r) | (b), (r)); } while(0)
267 #define omap_clr_bit_regl(b,r) \
268 do { omap_writel(omap_readl(r) & ~(b), (r)); } while(0)
269 #define omap_set_bits_regl(val,mask,r) \
270 do { omap_writel((omap_readl(r) & ~(mask)) | (val), (r)); } while(0)
272 #define dspword_to_virt(dw) ((void *)(dspmem_base + ((dw) << 1)))
273 #define dspbyte_to_virt(db) ((void *)(dspmem_base + (db)))
274 #define virt_to_dspword(va) \
275 ((dsp_long_t)(((unsigned long)(va) - dspmem_base) >> 1))
276 #define virt_to_dspbyte(va) \
277 ((dsp_long_t)((unsigned long)(va) - dspmem_base))
278 #define is_dsp_internal_mem(va) \
279 (((unsigned long)(va) >= dspmem_base) && \
280 ((unsigned long)(va) < dspmem_base + dspmem_size))
281 #define is_dspbyte_internal_mem(db) ((db) < dspmem_size)
282 #define is_dspword_internal_mem(dw) (((dw) << 1) < dspmem_size)
284 #ifdef CONFIG_ARCH_OMAP1
286 * MPUI byteswap/wordswap on/off
287 * default setting: wordswap = all, byteswap = APIMEM only
289 #define mpui_wordswap_on() \
290 omap_set_bits_regl(MPUI_CTRL_WORDSWAP_ALL, MPUI_CTRL_WORDSWAP_MASK, \
293 #define mpui_wordswap_off() \
294 omap_set_bits_regl(MPUI_CTRL_WORDSWAP_NONE, MPUI_CTRL_WORDSWAP_MASK, \
297 #define mpui_byteswap_on() \
298 omap_set_bits_regl(MPUI_CTRL_BYTESWAP_API, MPUI_CTRL_BYTESWAP_MASK, \
301 #define mpui_byteswap_off() \
302 omap_set_bits_regl(MPUI_CTRL_BYTESWAP_NONE, MPUI_CTRL_BYTESWAP_MASK, \
306 * TC wordswap on / off
308 #define tc_wordswap() \
310 omap_writel(TC_ENDIANISM_SWAP_WORD | TC_ENDIANISM_EN, \
314 #define tc_noswap() omap_clr_bit_regl(TC_ENDIANISM_EN, TC_ENDIANISM)
317 * enable priority registers, EMIF, MPUI control logic
319 #define __dsp_enable() omap_set_bit_regw(ARM_RSTCT1_DSP_RST, ARM_RSTCT1)
320 #define __dsp_disable() omap_clr_bit_regw(ARM_RSTCT1_DSP_RST, ARM_RSTCT1)
321 #define __dsp_run() omap_set_bit_regw(ARM_RSTCT1_DSP_EN, ARM_RSTCT1)
322 #define __dsp_reset() omap_clr_bit_regw(ARM_RSTCT1_DSP_EN, ARM_RSTCT1)
323 #endif /* CONFIG_ARCH_OMAP1 */
325 #ifdef CONFIG_ARCH_OMAP2
327 * PRCM / IPI control logic
329 * REVISIT: these macros should probably be static inline functions
331 #define __dsp_core_enable() \
332 do { prm_write_mod_reg(prm_read_mod_reg(OMAP24XX_DSP_MOD, RM_RSTCTRL) \
333 & ~OMAP24XX_RST1_DSP, OMAP24XX_DSP_MOD, RM_RSTCTRL); } while (0)
334 #define __dsp_core_disable() \
335 do { prm_write_mod_reg(prm_read_mod_reg(OMAP24XX_DSP_MOD, RM_RSTCTRL) \
336 | OMAP24XX_RST1_DSP, OMAP24XX_DSP_MOD, RM_RSTCTRL); } while (0)
337 #define __dsp_per_enable() \
338 do { prm_write_mod_reg(prm_read_mod_reg(OMAP24XX_DSP_MOD, RM_RSTCTRL) \
339 & ~OMAP24XX_RST2_DSP, OMAP24XX_DSP_MOD, RM_RSTCTRL); } while (0)
340 #define __dsp_per_disable() \
341 do { prm_write_mod_reg(prm_read_mod_reg(OMAP24XX_DSP_MOD, RM_RSTCTRL) \
342 | OMAP24XX_RST2_DSP, OMAP24XX_DSP_MOD, RM_RSTCTRL); } while (0)
343 #endif /* CONFIG_ARCH_OMAP2 */
345 #if defined(CONFIG_ARCH_OMAP1)
346 extern struct clk *dsp_ck_handle;
347 extern struct clk *api_ck_handle;
348 #elif defined(CONFIG_ARCH_OMAP2)
349 extern struct clk *dsp_fck_handle;
350 extern struct clk *dsp_ick_handle;
352 extern dsp_long_t dspmem_base, dspmem_size,
353 daram_base, daram_size,
354 saram_base, saram_size;
358 #ifdef CONFIG_ARCH_OMAP1
366 int dsp_set_rstvect(dsp_long_t adr);
367 dsp_long_t dsp_get_rstvect(void);
368 void dsp_set_idle_boot_base(dsp_long_t adr, size_t size);
369 void dsp_reset_idle_boot_base(void);
370 void dsp_cpustat_request(enum cpustat_e req);
371 enum cpustat_e dsp_cpustat_get_stat(void);
372 u16 dsp_cpustat_get_icrmask(void);
373 void dsp_cpustat_set_icrmask(u16 mask);
374 void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void));
375 void dsp_unregister_mem_cb(void);
377 #if defined(CONFIG_ARCH_OMAP1)
378 #define command_dvfs_stop(m) (0)
379 #define command_dvfs_start(m) (0)
380 #elif defined(CONFIG_ARCH_OMAP2)
381 #define command_dvfs_stop(m) \
382 (((m)->cmd_l == KFUNC_POWER) && ((m)->data == DVFS_STOP))
383 #define command_dvfs_start(m) \
384 (((m)->cmd_l == KFUNC_POWER) && ((m)->data == DVFS_START))
387 extern struct omap_dsp *omap_dsp;
389 extern int dsp_late_init(void);
391 #endif /* __PLAT_OMAP_DSP_DSP_H */