drivers/dma/iop-adma.c

   1 /*
   2  * offload engine driver for the Intel Xscale series of i/o processors
   3  * Copyright © 2006, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  */
  19
  20 /*
  21  * This driver supports the asynchrounous DMA copy and RAID engines available
  22  * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/async_tx.h>
  28 #include <linux/delay.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/memory.h>
  34 #include <linux/ioport.h>
  35
  36 #include <asm/arch/adma.h>
  37
  38 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
  39 #define to_iop_adma_device(dev) \
  40         container_of(dev, struct iop_adma_device, common)
  41 #define tx_to_iop_adma_slot(tx) \
  42         container_of(tx, struct iop_adma_desc_slot, async_tx)
  43
  44 /**
  45  * iop_adma_free_slots - flags descriptor slots for reuse
  46  * @slot: Slot to free
  47  * Caller must hold &iop_chan->lock while calling this function
  48  */
  49 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
  50 {
  51         int stride = slot->slots_per_op;
  52
  53         while (stride--) {
  54                 slot->slots_per_op = 0;
  55                 slot = list_entry(slot->slot_node.next,
  56                                 struct iop_adma_desc_slot,
  57                                 slot_node);
  58         }
  59 }
  60
  61 static dma_cookie_t
  62 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
  63         struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
  64 {
  65         BUG_ON(desc->async_tx.cookie < 0);
  66         if (desc->async_tx.cookie > 0) {
  67                 cookie = desc->async_tx.cookie;
  68                 desc->async_tx.cookie = 0;
  69
  70                 /* call the callback (must not sleep or submit new
  71                  * operations to this channel)
  72                  */
  73                 if (desc->async_tx.callback)
  74                         desc->async_tx.callback(
  75                                 desc->async_tx.callback_param);
  76
  77                 /* unmap dma addresses
  78                  * (unmap_single vs unmap_page?)
  79                  */
  80                 if (desc->group_head && desc->unmap_len) {
  81                         struct iop_adma_desc_slot *unmap = desc->group_head;
  82                         struct device *dev =
  83                                 &iop_chan->device->pdev->dev;
  84                         u32 len = unmap->unmap_len;
  85                         u32 src_cnt = unmap->unmap_src_cnt;
  86                         dma_addr_t addr = iop_desc_get_dest_addr(unmap,
  87                                 iop_chan);
  88
  89                         dma_unmap_page(dev, addr, len, DMA_FROM_DEVICE);
  90                         while (src_cnt--) {
  91                                 addr = iop_desc_get_src_addr(unmap,
  92                                                         iop_chan,
  93                                                         src_cnt);
  94                                 dma_unmap_page(dev, addr, len,
  95                                         DMA_TO_DEVICE);
  96                         }
  97                         desc->group_head = NULL;
  98                 }
  99         }
 100
 101         /* run dependent operations */
 102         async_tx_run_dependencies(&desc->async_tx);
 103
 104         return cookie;
 105 }
 106
 107 static int
 108 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
 109         struct iop_adma_chan *iop_chan)
 110 {
 111         /* the client is allowed to attach dependent operations
 112          * until 'ack' is set
 113          */
 114         if (!async_tx_test_ack(&desc->async_tx))
 115                 return 0;
 116
 117         /* leave the last descriptor in the chain
 118          * so we can append to it
 119          */
 120         if (desc->chain_node.next == &iop_chan->chain)
 121                 return 1;
 122
 123         dev_dbg(iop_chan->device->common.dev,
 124                 "\tfree slot: %d slots_per_op: %d\n",
 125                 desc->idx, desc->slots_per_op);
 126
 127         list_del(&desc->chain_node);
 128         iop_adma_free_slots(desc);
 129
 130         return 0;
 131 }
 132
 133 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
 134 {
 135         struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
 136         dma_cookie_t cookie = 0;
 137         u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
 138         int busy = iop_chan_is_busy(iop_chan);
 139         int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
 140
 141         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
 142         /* free completed slots from the chain starting with
 143          * the oldest descriptor
 144          */
 145         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
 146                                         chain_node) {
 147                 pr_debug("\tcookie: %d slot: %d busy: %d "
 148                         "this_desc: %#x next_desc: %#x ack: %d\n",
 149                         iter->async_tx.cookie, iter->idx, busy,
 150                         iter->async_tx.phys, iop_desc_get_next_desc(iter),
 151                         async_tx_test_ack(&iter->async_tx));
 152                 prefetch(_iter);
 153                 prefetch(&_iter->async_tx);
 154
 155                 /* do not advance past the current descriptor loaded into the
 156                  * hardware channel, subsequent descriptors are either in
 157                  * process or have not been submitted
 158                  */
 159                 if (seen_current)
 160                         break;
 161
 162                 /* stop the search if we reach the current descriptor and the
 163                  * channel is busy, or if it appears that the current descriptor
 164                  * needs to be re-read (i.e. has been appended to)
 165                  */
 166                 if (iter->async_tx.phys == current_desc) {
 167                         BUG_ON(seen_current++);
 168                         if (busy || iop_desc_get_next_desc(iter))
 169                                 break;
 170                 }
 171
 172                 /* detect the start of a group transaction */
 173                 if (!slot_cnt && !slots_per_op) {
 174                         slot_cnt = iter->slot_cnt;
 175                         slots_per_op = iter->slots_per_op;
 176                         if (slot_cnt <= slots_per_op) {
 177                                 slot_cnt = 0;
 178                                 slots_per_op = 0;
 179                         }
 180                 }
 181
 182                 if (slot_cnt) {
 183                         pr_debug("\tgroup++\n");
 184                         if (!grp_start)
 185                                 grp_start = iter;
 186                         slot_cnt -= slots_per_op;
 187                 }
 188
 189                 /* all the members of a group are complete */
 190                 if (slots_per_op != 0 && slot_cnt == 0) {
 191                         struct iop_adma_desc_slot *grp_iter, *_grp_iter;
 192                         int end_of_chain = 0;
 193                         pr_debug("\tgroup end\n");
 194
 195                         /* collect the total results */
 196                         if (grp_start->xor_check_result) {
 197                                 u32 zero_sum_result = 0;
 198                                 slot_cnt = grp_start->slot_cnt;
 199                                 grp_iter = grp_start;
 200
 201                                 list_for_each_entry_from(grp_iter,
 202                                         &iop_chan->chain, chain_node) {
 203                                         zero_sum_result |=
 204                                             iop_desc_get_zero_result(grp_iter);
 205                                             pr_debug("\titer%d result: %d\n",
 206                                             grp_iter->idx, zero_sum_result);
 207                                         slot_cnt -= slots_per_op;
 208                                         if (slot_cnt == 0)
 209                                                 break;
 210                                 }
 211                                 pr_debug("\tgrp_start->xor_check_result: %p\n",
 212                                         grp_start->xor_check_result);
 213                                 *grp_start->xor_check_result = zero_sum_result;
 214                         }
 215
 216                         /* clean up the group */
 217                         slot_cnt = grp_start->slot_cnt;
 218                         grp_iter = grp_start;
 219                         list_for_each_entry_safe_from(grp_iter, _grp_iter,
 220                                 &iop_chan->chain, chain_node) {
 221                                 cookie = iop_adma_run_tx_complete_actions(
 222                                         grp_iter, iop_chan, cookie);
 223
 224                                 slot_cnt -= slots_per_op;
 225                                 end_of_chain = iop_adma_clean_slot(grp_iter,
 226                                         iop_chan);
 227
 228                                 if (slot_cnt == 0 || end_of_chain)
 229                                         break;
 230                         }
 231
 232                         /* the group should be complete at this point */
 233                         BUG_ON(slot_cnt);
 234
 235                         slots_per_op = 0;
 236                         grp_start = NULL;
 237                         if (end_of_chain)
 238                                 break;
 239                         else
 240                                 continue;
 241                 } else if (slots_per_op) /* wait for group completion */
 242                         continue;
 243
 244                 /* write back zero sum results (single descriptor case) */
 245                 if (iter->xor_check_result && iter->async_tx.cookie)
 246                         *iter->xor_check_result =
 247                                 iop_desc_get_zero_result(iter);
 248
 249                 cookie = iop_adma_run_tx_complete_actions(
 250                                         iter, iop_chan, cookie);
 251
 252                 if (iop_adma_clean_slot(iter, iop_chan))
 253                         break;
 254         }
 255
 256         BUG_ON(!seen_current);
 257
 258         if (cookie > 0) {
 259                 iop_chan->completed_cookie = cookie;
 260                 pr_debug("\tcompleted cookie %d\n", cookie);
 261         }
 262 }
 263
 264 static void
 265 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
 266 {
 267         spin_lock_bh(&iop_chan->lock);
 268         __iop_adma_slot_cleanup(iop_chan);
 269         spin_unlock_bh(&iop_chan->lock);
 270 }
 271
 272 static void iop_adma_tasklet(unsigned long data)
 273 {
 274         struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
 275
 276         spin_lock(&iop_chan->lock);
 277         __iop_adma_slot_cleanup(iop_chan);
 278         spin_unlock(&iop_chan->lock);
 279 }
 280
 281 static struct iop_adma_desc_slot *
 282 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
 283                         int slots_per_op)
 284 {
 285         struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
 286         LIST_HEAD(chain);
 287         int slots_found, retry = 0;
 288
 289         /* start search from the last allocated descrtiptor
 290          * if a contiguous allocation can not be found start searching
 291          * from the beginning of the list
 292          */
 293 retry:
 294         slots_found = 0;
 295         if (retry == 0)
 296                 iter = iop_chan->last_used;
 297         else
 298                 iter = list_entry(&iop_chan->all_slots,
 299                         struct iop_adma_desc_slot,
 300                         slot_node);
 301
 302         list_for_each_entry_safe_continue(
 303                 iter, _iter, &iop_chan->all_slots, slot_node) {
 304                 prefetch(_iter);
 305                 prefetch(&_iter->async_tx);
 306                 if (iter->slots_per_op) {
 307                         /* give up after finding the first busy slot
 308                          * on the second pass through the list
 309                          */
 310                         if (retry)
 311                                 break;
 312
 313                         slots_found = 0;
 314                         continue;
 315                 }
 316
 317                 /* start the allocation if the slot is correctly aligned */
 318                 if (!slots_found++) {
 319                         if (iop_desc_is_aligned(iter, slots_per_op))
 320                                 alloc_start = iter;
 321                         else {
 322                                 slots_found = 0;
 323                                 continue;
 324                         }
 325                 }
 326
 327                 if (slots_found == num_slots) {
 328                         struct iop_adma_desc_slot *alloc_tail = NULL;
 329                         struct iop_adma_desc_slot *last_used = NULL;
 330                         iter = alloc_start;
 331                         while (num_slots) {
 332                                 int i;
 333                                 dev_dbg(iop_chan->device->common.dev,
 334                                         "allocated slot: %d "
 335                                         "(desc %p phys: %#x) slots_per_op %d\n",
 336                                         iter->idx, iter->hw_desc,
 337                                         iter->async_tx.phys, slots_per_op);
 338
 339                                 /* pre-ack all but the last descriptor */
 340                                 if (num_slots != slots_per_op)
 341                                         async_tx_ack(&iter->async_tx);
 342
 343                                 list_add_tail(&iter->chain_node, &chain);
 344                                 alloc_tail = iter;
 345                                 iter->async_tx.cookie = 0;
 346                                 iter->slot_cnt = num_slots;
 347                                 iter->xor_check_result = NULL;
 348                                 for (i = 0; i < slots_per_op; i++) {
 349                                         iter->slots_per_op = slots_per_op - i;
 350                                         last_used = iter;
 351                                         iter = list_entry(iter->slot_node.next,
 352                                                 struct iop_adma_desc_slot,
 353                                                 slot_node);
 354                                 }
 355                                 num_slots -= slots_per_op;
 356                         }
 357                         alloc_tail->group_head = alloc_start;
 358                         alloc_tail->async_tx.cookie = -EBUSY;
 359                         list_splice(&chain, &alloc_tail->async_tx.tx_list);
 360                         iop_chan->last_used = last_used;
 361                         iop_desc_clear_next_desc(alloc_start);
 362                         iop_desc_clear_next_desc(alloc_tail);
 363                         return alloc_tail;
 364                 }
 365         }
 366         if (!retry++)
 367                 goto retry;
 368
 369         /* try to free some slots if the allocation fails */
 370         tasklet_schedule(&iop_chan->irq_tasklet);
 371
 372         return NULL;
 373 }
 374
 375 static dma_cookie_t
 376 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
 377         struct iop_adma_desc_slot *desc)
 378 {
 379         dma_cookie_t cookie = iop_chan->common.cookie;
 380         cookie++;
 381         if (cookie < 0)
 382                 cookie = 1;
 383         iop_chan->common.cookie = desc->async_tx.cookie = cookie;
 384         return cookie;
 385 }
 386
 387 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
 388 {
 389         dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
 390                 iop_chan->pending);
 391
 392         if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
 393                 iop_chan->pending = 0;
 394                 iop_chan_append(iop_chan);
 395         }
 396 }
 397
 398 static dma_cookie_t
 399 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
 400 {
 401         struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
 402         struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
 403         struct iop_adma_desc_slot *grp_start, *old_chain_tail;
 404         int slot_cnt;
 405         int slots_per_op;
 406         dma_cookie_t cookie;
 407
 408         grp_start = sw_desc->group_head;
 409         slot_cnt = grp_start->slot_cnt;
 410         slots_per_op = grp_start->slots_per_op;
 411
 412         spin_lock_bh(&iop_chan->lock);
 413         cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
 414
 415         old_chain_tail = list_entry(iop_chan->chain.prev,
 416                 struct iop_adma_desc_slot, chain_node);
 417         list_splice_init(&sw_desc->async_tx.tx_list,
 418                          &old_chain_tail->chain_node);
 419
 420         /* fix up the hardware chain */
 421         iop_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
 422
 423         /* 1/ don't add pre-chained descriptors
 424          * 2/ dummy read to flush next_desc write
 425          */
 426         BUG_ON(iop_desc_get_next_desc(sw_desc));
 427
 428         /* increment the pending count by the number of slots
 429          * memcpy operations have a 1:1 (slot:operation) relation
 430          * other operations are heavier and will pop the threshold
 431          * more often.
 432          */
 433         iop_chan->pending += slot_cnt;
 434         iop_adma_check_threshold(iop_chan);
 435         spin_unlock_bh(&iop_chan->lock);
 436
 437         dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
 438                 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
 439
 440         return cookie;
 441 }
 442
 443 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
 444 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
 445
 446 /* returns the number of allocated descriptors */
 447 static int iop_adma_alloc_chan_resources(struct dma_chan *chan,
 448                                          struct dma_client *client)
 449 {
 450         char *hw_desc;
 451         int idx;
 452         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 453         struct iop_adma_desc_slot *slot = NULL;
 454         int init = iop_chan->slots_allocated ? 0 : 1;
 455         struct iop_adma_platform_data *plat_data =
 456                 iop_chan->device->pdev->dev.platform_data;
 457         int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
 458
 459         /* Allocate descriptor slots */
 460         do {
 461                 idx = iop_chan->slots_allocated;
 462                 if (idx == num_descs_in_pool)
 463                         break;
 464
 465                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 466                 if (!slot) {
 467                         printk(KERN_INFO "IOP ADMA Channel only initialized"
 468                                 " %d descriptor slots", idx);
 469                         break;
 470                 }
 471                 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
 472                 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
 473
 474                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
 475                 slot->async_tx.tx_submit = iop_adma_tx_submit;
 476                 INIT_LIST_HEAD(&slot->chain_node);
 477                 INIT_LIST_HEAD(&slot->slot_node);
 478                 INIT_LIST_HEAD(&slot->async_tx.tx_list);
 479                 hw_desc = (char *) iop_chan->device->dma_desc_pool;
 480                 slot->async_tx.phys =
 481                         (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
 482                 slot->idx = idx;
 483
 484                 spin_lock_bh(&iop_chan->lock);
 485                 iop_chan->slots_allocated++;
 486                 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
 487                 spin_unlock_bh(&iop_chan->lock);
 488         } while (iop_chan->slots_allocated < num_descs_in_pool);
 489
 490         if (idx && !iop_chan->last_used)
 491                 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
 492                                         struct iop_adma_desc_slot,
 493                                         slot_node);
 494
 495         dev_dbg(iop_chan->device->common.dev,
 496                 "allocated %d descriptor slots last_used: %p\n",
 497                 iop_chan->slots_allocated, iop_chan->last_used);
 498
 499         /* initialize the channel and the chain with a null operation */
 500         if (init) {
 501                 if (dma_has_cap(DMA_MEMCPY,
 502                         iop_chan->device->common.cap_mask))
 503                         iop_chan_start_null_memcpy(iop_chan);
 504                 else if (dma_has_cap(DMA_XOR,
 505                         iop_chan->device->common.cap_mask))
 506                         iop_chan_start_null_xor(iop_chan);
 507                 else
 508                         BUG();
 509         }
 510
 511         return (idx > 0) ? idx : -ENOMEM;
 512 }
 513
 514 static struct dma_async_tx_descriptor *
 515 iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
 516 {
 517         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 518         struct iop_adma_desc_slot *sw_desc, *grp_start;
 519         int slot_cnt, slots_per_op;
 520
 521         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
 522
 523         spin_lock_bh(&iop_chan->lock);
 524         slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
 525         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
 526         if (sw_desc) {
 527                 grp_start = sw_desc->group_head;
 528                 iop_desc_init_interrupt(grp_start, iop_chan);
 529                 grp_start->unmap_len = 0;
 530                 sw_desc->async_tx.flags = flags;
 531         }
 532         spin_unlock_bh(&iop_chan->lock);
 533
 534         return sw_desc ? &sw_desc->async_tx : NULL;
 535 }
 536
 537 static struct dma_async_tx_descriptor *
 538 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
 539                          dma_addr_t dma_src, size_t len, unsigned long flags)
 540 {
 541         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 542         struct iop_adma_desc_slot *sw_desc, *grp_start;
 543         int slot_cnt, slots_per_op;
 544
 545         if (unlikely(!len))
 546                 return NULL;
 547         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
 548
 549         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
 550                 __func__, len);
 551
 552         spin_lock_bh(&iop_chan->lock);
 553         slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
 554         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
 555         if (sw_desc) {
 556                 grp_start = sw_desc->group_head;
 557                 iop_desc_init_memcpy(grp_start, flags);
 558                 iop_desc_set_byte_count(grp_start, iop_chan, len);
 559                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
 560                 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
 561                 sw_desc->unmap_src_cnt = 1;
 562                 sw_desc->unmap_len = len;
 563                 sw_desc->async_tx.flags = flags;
 564         }
 565         spin_unlock_bh(&iop_chan->lock);
 566
 567         return sw_desc ? &sw_desc->async_tx : NULL;
 568 }
 569
 570 static struct dma_async_tx_descriptor *
 571 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
 572                          int value, size_t len, unsigned long flags)
 573 {
 574         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 575         struct iop_adma_desc_slot *sw_desc, *grp_start;
 576         int slot_cnt, slots_per_op;
 577
 578         if (unlikely(!len))
 579                 return NULL;
 580         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
 581
 582         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
 583                 __func__, len);
 584
 585         spin_lock_bh(&iop_chan->lock);
 586         slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
 587         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
 588         if (sw_desc) {
 589                 grp_start = sw_desc->group_head;
 590                 iop_desc_init_memset(grp_start, flags);
 591                 iop_desc_set_byte_count(grp_start, iop_chan, len);
 592                 iop_desc_set_block_fill_val(grp_start, value);
 593                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
 594                 sw_desc->unmap_src_cnt = 1;
 595                 sw_desc->unmap_len = len;
 596                 sw_desc->async_tx.flags = flags;
 597         }
 598         spin_unlock_bh(&iop_chan->lock);
 599
 600         return sw_desc ? &sw_desc->async_tx : NULL;
 601 }
 602
 603 static struct dma_async_tx_descriptor *
 604 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
 605                       dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
 606                       unsigned long flags)
 607 {
 608         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 609         struct iop_adma_desc_slot *sw_desc, *grp_start;
 610         int slot_cnt, slots_per_op;
 611
 612         if (unlikely(!len))
 613                 return NULL;
 614         BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
 615
 616         dev_dbg(iop_chan->device->common.dev,
 617                 "%s src_cnt: %d len: %u flags: %lx\n",
 618                 __func__, src_cnt, len, flags);
 619
 620         spin_lock_bh(&iop_chan->lock);
 621         slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
 622         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
 623         if (sw_desc) {
 624                 grp_start = sw_desc->group_head;
 625                 iop_desc_init_xor(grp_start, src_cnt, flags);
 626                 iop_desc_set_byte_count(grp_start, iop_chan, len);
 627                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
 628                 sw_desc->unmap_src_cnt = src_cnt;
 629                 sw_desc->unmap_len = len;
 630                 sw_desc->async_tx.flags = flags;
 631                 while (src_cnt--)
 632                         iop_desc_set_xor_src_addr(grp_start, src_cnt,
 633                                                   dma_src[src_cnt]);
 634         }
 635         spin_unlock_bh(&iop_chan->lock);
 636
 637         return sw_desc ? &sw_desc->async_tx : NULL;
 638 }
 639
 640 static struct dma_async_tx_descriptor *
 641 iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src,
 642                            unsigned int src_cnt, size_t len, u32 *result,
 643                            unsigned long flags)
 644 {
 645         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 646         struct iop_adma_desc_slot *sw_desc, *grp_start;
 647         int slot_cnt, slots_per_op;
 648
 649         if (unlikely(!len))
 650                 return NULL;
 651
 652         dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
 653                 __func__, src_cnt, len);
 654
 655         spin_lock_bh(&iop_chan->lock);
 656         slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
 657         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
 658         if (sw_desc) {
 659                 grp_start = sw_desc->group_head;
 660                 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
 661                 iop_desc_set_zero_sum_byte_count(grp_start, len);
 662                 grp_start->xor_check_result = result;
 663                 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
 664                         __func__, grp_start->xor_check_result);
 665                 sw_desc->unmap_src_cnt = src_cnt;
 666                 sw_desc->unmap_len = len;
 667                 sw_desc->async_tx.flags = flags;
 668                 while (src_cnt--)
 669                         iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
 670                                                        dma_src[src_cnt]);
 671         }
 672         spin_unlock_bh(&iop_chan->lock);
 673
 674         return sw_desc ? &sw_desc->async_tx : NULL;
 675 }
 676
 677 static void iop_adma_free_chan_resources(struct dma_chan *chan)
 678 {
 679         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 680         struct iop_adma_desc_slot *iter, *_iter;
 681         int in_use_descs = 0;
 682
 683         iop_adma_slot_cleanup(iop_chan);
 684
 685         spin_lock_bh(&iop_chan->lock);
 686         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
 687                                         chain_node) {
 688                 in_use_descs++;
 689                 list_del(&iter->chain_node);
 690         }
 691         list_for_each_entry_safe_reverse(
 692                 iter, _iter, &iop_chan->all_slots, slot_node) {
 693                 list_del(&iter->slot_node);
 694                 kfree(iter);
 695                 iop_chan->slots_allocated--;
 696         }
 697         iop_chan->last_used = NULL;
 698
 699         dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
 700                 __func__, iop_chan->slots_allocated);
 701         spin_unlock_bh(&iop_chan->lock);
 702
 703         /* one is ok since we left it on there on purpose */
 704         if (in_use_descs > 1)
 705                 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
 706                         in_use_descs - 1);
 707 }
 708
 709 /**
 710  * iop_adma_is_complete - poll the status of an ADMA transaction
 711  * @chan: ADMA channel handle
 712  * @cookie: ADMA transaction identifier
 713  */
 714 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
 715                                         dma_cookie_t cookie,
 716                                         dma_cookie_t *done,
 717                                         dma_cookie_t *used)
 718 {
 719         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 720         dma_cookie_t last_used;
 721         dma_cookie_t last_complete;
 722         enum dma_status ret;
 723
 724         last_used = chan->cookie;
 725         last_complete = iop_chan->completed_cookie;
 726
 727         if (done)
 728                 *done = last_complete;
 729         if (used)
 730                 *used = last_used;
 731
 732         ret = dma_async_is_complete(cookie, last_complete, last_used);
 733         if (ret == DMA_SUCCESS)
 734                 return ret;
 735
 736         iop_adma_slot_cleanup(iop_chan);
 737
 738         last_used = chan->cookie;
 739         last_complete = iop_chan->completed_cookie;
 740
 741         if (done)
 742                 *done = last_complete;
 743         if (used)
 744                 *used = last_used;
 745
 746         return dma_async_is_complete(cookie, last_complete, last_used);
 747 }
 748
 749 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
 750 {
 751         struct iop_adma_chan *chan = data;
 752
 753         dev_dbg(chan->device->common.dev, "%s\n", __func__);
 754
 755         tasklet_schedule(&chan->irq_tasklet);
 756
 757         iop_adma_device_clear_eot_status(chan);
 758
 759         return IRQ_HANDLED;
 760 }
 761
 762 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
 763 {
 764         struct iop_adma_chan *chan = data;
 765
 766         dev_dbg(chan->device->common.dev, "%s\n", __func__);
 767
 768         tasklet_schedule(&chan->irq_tasklet);
 769
 770         iop_adma_device_clear_eoc_status(chan);
 771
 772         return IRQ_HANDLED;
 773 }
 774
 775 static irqreturn_t iop_adma_err_handler(int irq, void *data)
 776 {
 777         struct iop_adma_chan *chan = data;
 778         unsigned long status = iop_chan_get_status(chan);
 779
 780         dev_printk(KERN_ERR, chan->device->common.dev,
 781                 "error ( %s%s%s%s%s%s%s)\n",
 782                 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
 783                 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
 784                 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
 785                 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
 786                 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
 787                 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
 788                 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
 789
 790         iop_adma_device_clear_err_status(chan);
 791
 792         BUG();
 793
 794         return IRQ_HANDLED;
 795 }
 796
 797 static void iop_adma_issue_pending(struct dma_chan *chan)
 798 {
 799         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
 800
 801         if (iop_chan->pending) {
 802                 iop_chan->pending = 0;
 803                 iop_chan_append(iop_chan);
 804         }
 805 }
 806
 807 /*
 808  * Perform a transaction to verify the HW works.
 809  */
 810 #define IOP_ADMA_TEST_SIZE 2000
 811
 812 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
 813 {
 814         int i;
 815         void *src, *dest;
 816         dma_addr_t src_dma, dest_dma;
 817         struct dma_chan *dma_chan;
 818         dma_cookie_t cookie;
 819         struct dma_async_tx_descriptor *tx;
 820         int err = 0;
 821         struct iop_adma_chan *iop_chan;
 822
 823         dev_dbg(device->common.dev, "%s\n", __func__);
 824
 825         src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
 826         if (!src)
 827                 return -ENOMEM;
 828         dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
 829         if (!dest) {
 830                 kfree(src);
 831                 return -ENOMEM;
 832         }
 833
 834         /* Fill in src buffer */
 835         for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
 836                 ((u8 *) src)[i] = (u8)i;
 837
 838         /* Start copy, using first DMA channel */
 839         dma_chan = container_of(device->common.channels.next,
 840                                 struct dma_chan,
 841                                 device_node);
 842         if (iop_adma_alloc_chan_resources(dma_chan, NULL) < 1) {
 843                 err = -ENODEV;
 844                 goto out;
 845         }
 846
 847         dest_dma = dma_map_single(dma_chan->device->dev, dest,
 848                                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
 849         src_dma = dma_map_single(dma_chan->device->dev, src,
 850                                 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
 851         tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
 852                                       IOP_ADMA_TEST_SIZE,
 853                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 854
 855         cookie = iop_adma_tx_submit(tx);
 856         iop_adma_issue_pending(dma_chan);
 857         msleep(1);
 858
 859         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
 860                         DMA_SUCCESS) {
 861                 dev_printk(KERN_ERR, dma_chan->device->dev,
 862                         "Self-test copy timed out, disabling\n");
 863                 err = -ENODEV;
 864                 goto free_resources;
 865         }
 866
 867         iop_chan = to_iop_adma_chan(dma_chan);
 868         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
 869                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
 870         if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
 871                 dev_printk(KERN_ERR, dma_chan->device->dev,
 872                         "Self-test copy failed compare, disabling\n");
 873                 err = -ENODEV;
 874                 goto free_resources;
 875         }
 876
 877 free_resources:
 878         iop_adma_free_chan_resources(dma_chan);
 879 out:
 880         kfree(src);
 881         kfree(dest);
 882         return err;
 883 }
 884
 885 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
 886 static int __devinit
 887 iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device)
 888 {
 889         int i, src_idx;
 890         struct page *dest;
 891         struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
 892         struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
 893         dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
 894         dma_addr_t dma_addr, dest_dma;
 895         struct dma_async_tx_descriptor *tx;
 896         struct dma_chan *dma_chan;
 897         dma_cookie_t cookie;
 898         u8 cmp_byte = 0;
 899         u32 cmp_word;
 900         u32 zero_sum_result;
 901         int err = 0;
 902         struct iop_adma_chan *iop_chan;
 903
 904         dev_dbg(device->common.dev, "%s\n", __func__);
 905
 906         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
 907                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
 908                 if (!xor_srcs[src_idx])
 909                         while (src_idx--) {
 910                                 __free_page(xor_srcs[src_idx]);
 911                                 return -ENOMEM;
 912                         }
 913         }
 914
 915         dest = alloc_page(GFP_KERNEL);
 916         if (!dest)
 917                 while (src_idx--) {
 918                         __free_page(xor_srcs[src_idx]);
 919                         return -ENOMEM;
 920                 }
 921
 922         /* Fill in src buffers */
 923         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
 924                 u8 *ptr = page_address(xor_srcs[src_idx]);
 925                 for (i = 0; i < PAGE_SIZE; i++)
 926                         ptr[i] = (1 << src_idx);
 927         }
 928
 929         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
 930                 cmp_byte ^= (u8) (1 << src_idx);
 931
 932         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
 933                         (cmp_byte << 8) | cmp_byte;
 934
 935         memset(page_address(dest), 0, PAGE_SIZE);
 936
 937         dma_chan = container_of(device->common.channels.next,
 938                                 struct dma_chan,
 939                                 device_node);
 940         if (iop_adma_alloc_chan_resources(dma_chan, NULL) < 1) {
 941                 err = -ENODEV;
 942                 goto out;
 943         }
 944
 945         /* test xor */
 946         dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
 947                                 PAGE_SIZE, DMA_FROM_DEVICE);
 948         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
 949                 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
 950                                            0, PAGE_SIZE, DMA_TO_DEVICE);
 951         tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
 952                                    IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
 953                                    DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 954
 955         cookie = iop_adma_tx_submit(tx);
 956         iop_adma_issue_pending(dma_chan);
 957         msleep(8);
 958
 959         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
 960                 DMA_SUCCESS) {
 961                 dev_printk(KERN_ERR, dma_chan->device->dev,
 962                         "Self-test xor timed out, disabling\n");
 963                 err = -ENODEV;
 964                 goto free_resources;
 965         }
 966
 967         iop_chan = to_iop_adma_chan(dma_chan);
 968         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
 969                 PAGE_SIZE, DMA_FROM_DEVICE);
 970         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
 971                 u32 *ptr = page_address(dest);
 972                 if (ptr[i] != cmp_word) {
 973                         dev_printk(KERN_ERR, dma_chan->device->dev,
 974                                 "Self-test xor failed compare, disabling\n");
 975                         err = -ENODEV;
 976                         goto free_resources;
 977                 }
 978         }
 979         dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
 980                 PAGE_SIZE, DMA_TO_DEVICE);
 981
 982         /* skip zero sum if the capability is not present */
 983         if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask))
 984                 goto free_resources;
 985
 986         /* zero sum the sources with the destintation page */
 987         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
 988                 zero_sum_srcs[i] = xor_srcs[i];
 989         zero_sum_srcs[i] = dest;
 990
 991         zero_sum_result = 1;
 992
 993         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
 994                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
 995                                            zero_sum_srcs[i], 0, PAGE_SIZE,
 996                                            DMA_TO_DEVICE);
 997         tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
 998                                         IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
 999                                         &zero_sum_result,
1000                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1001
1002         cookie = iop_adma_tx_submit(tx);
1003         iop_adma_issue_pending(dma_chan);
1004         msleep(8);
1005
1006         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1007                 dev_printk(KERN_ERR, dma_chan->device->dev,
1008                         "Self-test zero sum timed out, disabling\n");
1009                 err = -ENODEV;
1010                 goto free_resources;
1011         }
1012
1013         if (zero_sum_result != 0) {
1014                 dev_printk(KERN_ERR, dma_chan->device->dev,
1015                         "Self-test zero sum failed compare, disabling\n");
1016                 err = -ENODEV;
1017                 goto free_resources;
1018         }
1019
1020         /* test memset */
1021         dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1022                         PAGE_SIZE, DMA_FROM_DEVICE);
1023         tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1024                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1025
1026         cookie = iop_adma_tx_submit(tx);
1027         iop_adma_issue_pending(dma_chan);
1028         msleep(8);
1029
1030         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1031                 dev_printk(KERN_ERR, dma_chan->device->dev,
1032                         "Self-test memset timed out, disabling\n");
1033                 err = -ENODEV;
1034                 goto free_resources;
1035         }
1036
1037         for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1038                 u32 *ptr = page_address(dest);
1039                 if (ptr[i]) {
1040                         dev_printk(KERN_ERR, dma_chan->device->dev,
1041                                 "Self-test memset failed compare, disabling\n");
1042                         err = -ENODEV;
1043                         goto free_resources;
1044                 }
1045         }
1046
1047         /* test for non-zero parity sum */
1048         zero_sum_result = 0;
1049         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1050                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1051                                            zero_sum_srcs[i], 0, PAGE_SIZE,
1052                                            DMA_TO_DEVICE);
1053         tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1054                                         IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1055                                         &zero_sum_result,
1056                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1057
1058         cookie = iop_adma_tx_submit(tx);
1059         iop_adma_issue_pending(dma_chan);
1060         msleep(8);
1061
1062         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1063                 dev_printk(KERN_ERR, dma_chan->device->dev,
1064                         "Self-test non-zero sum timed out, disabling\n");
1065                 err = -ENODEV;
1066                 goto free_resources;
1067         }
1068
1069         if (zero_sum_result != 1) {
1070                 dev_printk(KERN_ERR, dma_chan->device->dev,
1071                         "Self-test non-zero sum failed compare, disabling\n");
1072                 err = -ENODEV;
1073                 goto free_resources;
1074         }
1075
1076 free_resources:
1077         iop_adma_free_chan_resources(dma_chan);
1078 out:
1079         src_idx = IOP_ADMA_NUM_SRC_TEST;
1080         while (src_idx--)
1081                 __free_page(xor_srcs[src_idx]);
1082         __free_page(dest);
1083         return err;
1084 }
1085
1086 static int __devexit iop_adma_remove(struct platform_device *dev)
1087 {
1088         struct iop_adma_device *device = platform_get_drvdata(dev);
1089         struct dma_chan *chan, *_chan;
1090         struct iop_adma_chan *iop_chan;
1091         int i;
1092         struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1093
1094         dma_async_device_unregister(&device->common);
1095
1096         for (i = 0; i < 3; i++) {
1097                 unsigned int irq;
1098                 irq = platform_get_irq(dev, i);
1099                 free_irq(irq, device);
1100         }
1101
1102         dma_free_coherent(&dev->dev, plat_data->pool_size,
1103                         device->dma_desc_pool_virt, device->dma_desc_pool);
1104
1105         do {
1106                 struct resource *res;
1107                 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1108                 release_mem_region(res->start, res->end - res->start);
1109         } while (0);
1110
1111         list_for_each_entry_safe(chan, _chan, &device->common.channels,
1112                                 device_node) {
1113                 iop_chan = to_iop_adma_chan(chan);
1114                 list_del(&chan->device_node);
1115                 kfree(iop_chan);
1116         }
1117         kfree(device);
1118
1119         return 0;
1120 }
1121
1122 static int __devinit iop_adma_probe(struct platform_device *pdev)
1123 {
1124         struct resource *res;
1125         int ret = 0, i;
1126         struct iop_adma_device *adev;
1127         struct iop_adma_chan *iop_chan;
1128         struct dma_device *dma_dev;
1129         struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1130
1131         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1132         if (!res)
1133                 return -ENODEV;
1134
1135         if (!devm_request_mem_region(&pdev->dev, res->start,
1136                                 res->end - res->start, pdev->name))
1137                 return -EBUSY;
1138
1139         adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1140         if (!adev)
1141                 return -ENOMEM;
1142         dma_dev = &adev->common;
1143
1144         /* allocate coherent memory for hardware descriptors
1145          * note: writecombine gives slightly better performance, but
1146          * requires that we explicitly flush the writes
1147          */
1148         if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1149                                         plat_data->pool_size,
1150                                         &adev->dma_desc_pool,
1151                                         GFP_KERNEL)) == NULL) {
1152                 ret = -ENOMEM;
1153                 goto err_free_adev;
1154         }
1155
1156         dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1157                 __func__, adev->dma_desc_pool_virt,
1158                 (void *) adev->dma_desc_pool);
1159
1160         adev->id = plat_data->hw_id;
1161
1162         /* discover transaction capabilites from the platform data */
1163         dma_dev->cap_mask = plat_data->cap_mask;
1164
1165         adev->pdev = pdev;
1166         platform_set_drvdata(pdev, adev);
1167
1168         INIT_LIST_HEAD(&dma_dev->channels);
1169
1170         /* set base routines */
1171         dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1172         dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1173         dma_dev->device_is_tx_complete = iop_adma_is_complete;
1174         dma_dev->device_issue_pending = iop_adma_issue_pending;
1175         dma_dev->dev = &pdev->dev;
1176
1177         /* set prep routines based on capability */
1178         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1179                 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1180         if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1181                 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1182         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1183                 dma_dev->max_xor = iop_adma_get_max_xor();
1184                 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1185         }
1186         if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask))
1187                 dma_dev->device_prep_dma_zero_sum =
1188                         iop_adma_prep_dma_zero_sum;
1189         if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1190                 dma_dev->device_prep_dma_interrupt =
1191                         iop_adma_prep_dma_interrupt;
1192
1193         iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1194         if (!iop_chan) {
1195                 ret = -ENOMEM;
1196                 goto err_free_dma;
1197         }
1198         iop_chan->device = adev;
1199
1200         iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1201                                         res->end - res->start);
1202         if (!iop_chan->mmr_base) {
1203                 ret = -ENOMEM;
1204                 goto err_free_iop_chan;
1205         }
1206         tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1207                 iop_chan);
1208
1209         /* clear errors before enabling interrupts */
1210         iop_adma_device_clear_err_status(iop_chan);
1211
1212         for (i = 0; i < 3; i++) {
1213                 irq_handler_t handler[] = { iop_adma_eot_handler,
1214                                         iop_adma_eoc_handler,
1215                                         iop_adma_err_handler };
1216                 int irq = platform_get_irq(pdev, i);
1217                 if (irq < 0) {
1218                         ret = -ENXIO;
1219                         goto err_free_iop_chan;
1220                 } else {
1221                         ret = devm_request_irq(&pdev->dev, irq,
1222                                         handler[i], 0, pdev->name, iop_chan);
1223                         if (ret)
1224                                 goto err_free_iop_chan;
1225                 }
1226         }
1227
1228         spin_lock_init(&iop_chan->lock);
1229         INIT_LIST_HEAD(&iop_chan->chain);
1230         INIT_LIST_HEAD(&iop_chan->all_slots);
1231         INIT_RCU_HEAD(&iop_chan->common.rcu);
1232         iop_chan->common.device = dma_dev;
1233         list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1234
1235         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1236                 ret = iop_adma_memcpy_self_test(adev);
1237                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1238                 if (ret)
1239                         goto err_free_iop_chan;
1240         }
1241
1242         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1243                 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1244                 ret = iop_adma_xor_zero_sum_self_test(adev);
1245                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1246                 if (ret)
1247                         goto err_free_iop_chan;
1248         }
1249
1250         dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1251           "( %s%s%s%s%s%s%s%s%s%s)\n",
1252           dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "",
1253           dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1254           dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "",
1255           dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1256           dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1257           dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "",
1258           dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)  ? "fill " : "",
1259           dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1260           dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1261           dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1262
1263         dma_async_device_register(dma_dev);
1264         goto out;
1265
1266  err_free_iop_chan:
1267         kfree(iop_chan);
1268  err_free_dma:
1269         dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1270                         adev->dma_desc_pool_virt, adev->dma_desc_pool);
1271  err_free_adev:
1272         kfree(adev);
1273  out:
1274         return ret;
1275 }
1276
1277 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1278 {
1279         struct iop_adma_desc_slot *sw_desc, *grp_start;
1280         dma_cookie_t cookie;
1281         int slot_cnt, slots_per_op;
1282
1283         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1284
1285         spin_lock_bh(&iop_chan->lock);
1286         slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1287         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1288         if (sw_desc) {
1289                 grp_start = sw_desc->group_head;
1290
1291                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1292                 async_tx_ack(&sw_desc->async_tx);
1293                 iop_desc_init_memcpy(grp_start, 0);
1294                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1295                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1296                 iop_desc_set_memcpy_src_addr(grp_start, 0);
1297
1298                 cookie = iop_chan->common.cookie;
1299                 cookie++;
1300                 if (cookie <= 1)
1301                         cookie = 2;
1302
1303                 /* initialize the completed cookie to be less than
1304                  * the most recently used cookie
1305                  */
1306                 iop_chan->completed_cookie = cookie - 1;
1307                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1308
1309                 /* channel should not be busy */
1310                 BUG_ON(iop_chan_is_busy(iop_chan));
1311
1312                 /* clear any prior error-status bits */
1313                 iop_adma_device_clear_err_status(iop_chan);
1314
1315                 /* disable operation */
1316                 iop_chan_disable(iop_chan);
1317
1318                 /* set the descriptor address */
1319                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1320
1321                 /* 1/ don't add pre-chained descriptors
1322                  * 2/ dummy read to flush next_desc write
1323                  */
1324                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1325
1326                 /* run the descriptor */
1327                 iop_chan_enable(iop_chan);
1328         } else
1329                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1330                          "failed to allocate null descriptor\n");
1331         spin_unlock_bh(&iop_chan->lock);
1332 }
1333
1334 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1335 {
1336         struct iop_adma_desc_slot *sw_desc, *grp_start;
1337         dma_cookie_t cookie;
1338         int slot_cnt, slots_per_op;
1339
1340         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1341
1342         spin_lock_bh(&iop_chan->lock);
1343         slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1344         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1345         if (sw_desc) {
1346                 grp_start = sw_desc->group_head;
1347                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1348                 async_tx_ack(&sw_desc->async_tx);
1349                 iop_desc_init_null_xor(grp_start, 2, 0);
1350                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1351                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1352                 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1353                 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1354
1355                 cookie = iop_chan->common.cookie;
1356                 cookie++;
1357                 if (cookie <= 1)
1358                         cookie = 2;
1359
1360                 /* initialize the completed cookie to be less than
1361                  * the most recently used cookie
1362                  */
1363                 iop_chan->completed_cookie = cookie - 1;
1364                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1365
1366                 /* channel should not be busy */
1367                 BUG_ON(iop_chan_is_busy(iop_chan));
1368
1369                 /* clear any prior error-status bits */
1370                 iop_adma_device_clear_err_status(iop_chan);
1371
1372                 /* disable operation */
1373                 iop_chan_disable(iop_chan);
1374
1375                 /* set the descriptor address */
1376                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1377
1378                 /* 1/ don't add pre-chained descriptors
1379                  * 2/ dummy read to flush next_desc write
1380                  */
1381                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1382
1383                 /* run the descriptor */
1384                 iop_chan_enable(iop_chan);
1385         } else
1386                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1387                         "failed to allocate null descriptor\n");
1388         spin_unlock_bh(&iop_chan->lock);
1389 }
1390
1391 MODULE_ALIAS("platform:iop-adma");
1392
1393 static struct platform_driver iop_adma_driver = {
1394         .probe          = iop_adma_probe,
1395         .remove         = iop_adma_remove,
1396         .driver         = {
1397                 .owner  = THIS_MODULE,
1398                 .name   = "iop-adma",
1399         },
1400 };
1401
1402 static int __init iop_adma_init (void)
1403 {
1404         return platform_driver_register(&iop_adma_driver);
1405 }
1406
1407 /* it's currently unsafe to unload this module */
1408 #if 0
1409 static void __exit iop_adma_exit (void)
1410 {
1411         platform_driver_unregister(&iop_adma_driver);
1412         return;
1413 }
1414 module_exit(iop_adma_exit);
1415 #endif
1416
1417 module_init(iop_adma_init);
1418
1419 MODULE_AUTHOR("Intel Corporation");
1420 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1421 MODULE_LICENSE("GPL");