drivers/dma/ioat_dma.c

   1 /*
   2  * Intel I/OAT DMA Linux driver
   3  * Copyright(c) 2004 - 2007 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  */
  22
  23 /*
  24  * This driver supports an Intel I/OAT DMA engine, which does asynchronous
  25  * copy operations.
  26  */
  27
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/dmaengine.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/workqueue.h>
  36 #include "ioatdma.h"
  37 #include "ioatdma_registers.h"
  38 #include "ioatdma_hw.h"
  39
  40 #define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common)
  41 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
  42 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
  43 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx)
  44
  45 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
  46 static int ioat_pending_level = 4;
  47 module_param(ioat_pending_level, int, 0644);
  48 MODULE_PARM_DESC(ioat_pending_level,
  49                  "high-water mark for pushing ioat descriptors (default: 4)");
  50
  51 #define RESET_DELAY  msecs_to_jiffies(100)
  52 #define WATCHDOG_DELAY  round_jiffies(msecs_to_jiffies(2000))
  53 static void ioat_dma_chan_reset_part2(struct work_struct *work);
  54 static void ioat_dma_chan_watchdog(struct work_struct *work);
  55
  56 /*
  57  * workaround for IOAT ver.3.0 null descriptor issue
  58  * (channel returns error when size is 0)
  59  */
  60 #define NULL_DESC_BUFFER_SIZE 1
  61
  62 /* internal functions */
  63 static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan);
  64 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan);
  65
  66 static struct ioat_desc_sw *
  67 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
  68 static struct ioat_desc_sw *
  69 ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
  70
  71 static inline struct ioat_dma_chan *ioat_lookup_chan_by_index(
  72                                                 struct ioatdma_device *device,
  73                                                 int index)
  74 {
  75         return device->idx[index];
  76 }
  77
  78 /**
  79  * ioat_dma_do_interrupt - handler used for single vector interrupt mode
  80  * @irq: interrupt id
  81  * @data: interrupt data
  82  */
  83 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
  84 {
  85         struct ioatdma_device *instance = data;
  86         struct ioat_dma_chan *ioat_chan;
  87         unsigned long attnstatus;
  88         int bit;
  89         u8 intrctrl;
  90
  91         intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
  92
  93         if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
  94                 return IRQ_NONE;
  95
  96         if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
  97                 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  98                 return IRQ_NONE;
  99         }
 100
 101         attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
 102         for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
 103                 ioat_chan = ioat_lookup_chan_by_index(instance, bit);
 104                 tasklet_schedule(&ioat_chan->cleanup_task);
 105         }
 106
 107         writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
 108         return IRQ_HANDLED;
 109 }
 110
 111 /**
 112  * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
 113  * @irq: interrupt id
 114  * @data: interrupt data
 115  */
 116 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
 117 {
 118         struct ioat_dma_chan *ioat_chan = data;
 119
 120         tasklet_schedule(&ioat_chan->cleanup_task);
 121
 122         return IRQ_HANDLED;
 123 }
 124
 125 static void ioat_dma_cleanup_tasklet(unsigned long data);
 126
 127 /**
 128  * ioat_dma_enumerate_channels - find and initialize the device's channels
 129  * @device: the device to be enumerated
 130  */
 131 static int ioat_dma_enumerate_channels(struct ioatdma_device *device)
 132 {
 133         u8 xfercap_scale;
 134         u32 xfercap;
 135         int i;
 136         struct ioat_dma_chan *ioat_chan;
 137
 138         /*
 139          * IOAT ver.3 workarounds
 140          */
 141         if (device->version == IOAT_VER_3_0) {
 142                 u32 chan_err_mask;
 143                 u16 dev_id;
 144                 u32 dmauncerrsts;
 145
 146                 /*
 147                  * Write CHANERRMSK_INT with 3E07h to mask out the errors
 148                  * that can cause stability issues for IOAT ver.3
 149                  */
 150                 chan_err_mask = 0x3E07;
 151                 pci_write_config_dword(device->pdev,
 152                         IOAT_PCI_CHANERRMASK_INT_OFFSET,
 153                         chan_err_mask);
 154
 155                 /*
 156                  * Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
 157                  * (workaround for spurious config parity error after restart)
 158                  */
 159                 pci_read_config_word(device->pdev,
 160                         IOAT_PCI_DEVICE_ID_OFFSET,
 161                         &dev_id);
 162                 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {
 163                         dmauncerrsts = 0x10;
 164                         pci_write_config_dword(device->pdev,
 165                                 IOAT_PCI_DMAUNCERRSTS_OFFSET,
 166                                 dmauncerrsts);
 167                 }
 168         }
 169
 170         device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
 171         xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
 172         xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
 173
 174 #if CONFIG_I7300_IDLE_IOAT_CHANNEL
 175         device->common.chancnt--;
 176 #endif
 177         for (i = 0; i < device->common.chancnt; i++) {
 178                 ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL);
 179                 if (!ioat_chan) {
 180                         device->common.chancnt = i;
 181                         break;
 182                 }
 183
 184                 ioat_chan->device = device;
 185                 ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1));
 186                 ioat_chan->xfercap = xfercap;
 187                 ioat_chan->desccount = 0;
 188                 INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2);
 189                 if (ioat_chan->device->version != IOAT_VER_1_2) {
 190                         writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE
 191                                         | IOAT_DMA_DCA_ANY_CPU,
 192                                 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
 193                 }
 194                 spin_lock_init(&ioat_chan->cleanup_lock);
 195                 spin_lock_init(&ioat_chan->desc_lock);
 196                 INIT_LIST_HEAD(&ioat_chan->free_desc);
 197                 INIT_LIST_HEAD(&ioat_chan->used_desc);
 198                 /* This should be made common somewhere in dmaengine.c */
 199                 ioat_chan->common.device = &device->common;
 200                 list_add_tail(&ioat_chan->common.device_node,
 201                               &device->common.channels);
 202                 device->idx[i] = ioat_chan;
 203                 tasklet_init(&ioat_chan->cleanup_task,
 204                              ioat_dma_cleanup_tasklet,
 205                              (unsigned long) ioat_chan);
 206                 tasklet_disable(&ioat_chan->cleanup_task);
 207         }
 208         return device->common.chancnt;
 209 }
 210
 211 /**
 212  * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
 213  *                                 descriptors to hw
 214  * @chan: DMA channel handle
 215  */
 216 static inline void __ioat1_dma_memcpy_issue_pending(
 217                                                 struct ioat_dma_chan *ioat_chan)
 218 {
 219         ioat_chan->pending = 0;
 220         writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET);
 221 }
 222
 223 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
 224 {
 225         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 226
 227         if (ioat_chan->pending > 0) {
 228                 spin_lock_bh(&ioat_chan->desc_lock);
 229                 __ioat1_dma_memcpy_issue_pending(ioat_chan);
 230                 spin_unlock_bh(&ioat_chan->desc_lock);
 231         }
 232 }
 233
 234 static inline void __ioat2_dma_memcpy_issue_pending(
 235                                                 struct ioat_dma_chan *ioat_chan)
 236 {
 237         ioat_chan->pending = 0;
 238         writew(ioat_chan->dmacount,
 239                ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
 240 }
 241
 242 static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan)
 243 {
 244         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 245
 246         if (ioat_chan->pending > 0) {
 247                 spin_lock_bh(&ioat_chan->desc_lock);
 248                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
 249                 spin_unlock_bh(&ioat_chan->desc_lock);
 250         }
 251 }
 252
 253
 254 /**
 255  * ioat_dma_chan_reset_part2 - reinit the channel after a reset
 256  */
 257 static void ioat_dma_chan_reset_part2(struct work_struct *work)
 258 {
 259         struct ioat_dma_chan *ioat_chan =
 260                 container_of(work, struct ioat_dma_chan, work.work);
 261         struct ioat_desc_sw *desc;
 262
 263         spin_lock_bh(&ioat_chan->cleanup_lock);
 264         spin_lock_bh(&ioat_chan->desc_lock);
 265
 266         ioat_chan->completion_virt->low = 0;
 267         ioat_chan->completion_virt->high = 0;
 268         ioat_chan->pending = 0;
 269
 270         /*
 271          * count the descriptors waiting, and be sure to do it
 272          * right for both the CB1 line and the CB2 ring
 273          */
 274         ioat_chan->dmacount = 0;
 275         if (ioat_chan->used_desc.prev) {
 276                 desc = to_ioat_desc(ioat_chan->used_desc.prev);
 277                 do {
 278                         ioat_chan->dmacount++;
 279                         desc = to_ioat_desc(desc->node.next);
 280                 } while (&desc->node != ioat_chan->used_desc.next);
 281         }
 282
 283         /*
 284          * write the new starting descriptor address
 285          * this puts channel engine into ARMED state
 286          */
 287         desc = to_ioat_desc(ioat_chan->used_desc.prev);
 288         switch (ioat_chan->device->version) {
 289         case IOAT_VER_1_2:
 290                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
 291                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
 292                 writel(((u64) desc->async_tx.phys) >> 32,
 293                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
 294
 295                 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
 296                         + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
 297                 break;
 298         case IOAT_VER_2_0:
 299                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
 300                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
 301                 writel(((u64) desc->async_tx.phys) >> 32,
 302                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
 303
 304                 /* tell the engine to go with what's left to be done */
 305                 writew(ioat_chan->dmacount,
 306                        ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
 307
 308                 break;
 309         }
 310         dev_err(&ioat_chan->device->pdev->dev,
 311                 "chan%d reset - %d descs waiting, %d total desc\n",
 312                 chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
 313
 314         spin_unlock_bh(&ioat_chan->desc_lock);
 315         spin_unlock_bh(&ioat_chan->cleanup_lock);
 316 }
 317
 318 /**
 319  * ioat_dma_reset_channel - restart a channel
 320  * @ioat_chan: IOAT DMA channel handle
 321  */
 322 static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan)
 323 {
 324         u32 chansts, chanerr;
 325
 326         if (!ioat_chan->used_desc.prev)
 327                 return;
 328
 329         chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
 330         chansts = (ioat_chan->completion_virt->low
 331                                         & IOAT_CHANSTS_DMA_TRANSFER_STATUS);
 332         if (chanerr) {
 333                 dev_err(&ioat_chan->device->pdev->dev,
 334                         "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
 335                         chan_num(ioat_chan), chansts, chanerr);
 336                 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
 337         }
 338
 339         /*
 340          * whack it upside the head with a reset
 341          * and wait for things to settle out.
 342          * force the pending count to a really big negative
 343          * to make sure no one forces an issue_pending
 344          * while we're waiting.
 345          */
 346
 347         spin_lock_bh(&ioat_chan->desc_lock);
 348         ioat_chan->pending = INT_MIN;
 349         writeb(IOAT_CHANCMD_RESET,
 350                ioat_chan->reg_base
 351                + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
 352         spin_unlock_bh(&ioat_chan->desc_lock);
 353
 354         /* schedule the 2nd half instead of sleeping a long time */
 355         schedule_delayed_work(&ioat_chan->work, RESET_DELAY);
 356 }
 357
 358 /**
 359  * ioat_dma_chan_watchdog - watch for stuck channels
 360  */
 361 static void ioat_dma_chan_watchdog(struct work_struct *work)
 362 {
 363         struct ioatdma_device *device =
 364                 container_of(work, struct ioatdma_device, work.work);
 365         struct ioat_dma_chan *ioat_chan;
 366         int i;
 367
 368         union {
 369                 u64 full;
 370                 struct {
 371                         u32 low;
 372                         u32 high;
 373                 };
 374         } completion_hw;
 375         unsigned long compl_desc_addr_hw;
 376
 377         for (i = 0; i < device->common.chancnt; i++) {
 378                 ioat_chan = ioat_lookup_chan_by_index(device, i);
 379
 380                 if (ioat_chan->device->version == IOAT_VER_1_2
 381                         /* have we started processing anything yet */
 382                     && ioat_chan->last_completion
 383                         /* have we completed any since last watchdog cycle? */
 384                     && (ioat_chan->last_completion ==
 385                                 ioat_chan->watchdog_completion)
 386                         /* has TCP stuck on one cookie since last watchdog? */
 387                     && (ioat_chan->watchdog_tcp_cookie ==
 388                                 ioat_chan->watchdog_last_tcp_cookie)
 389                     && (ioat_chan->watchdog_tcp_cookie !=
 390                                 ioat_chan->completed_cookie)
 391                         /* is there something in the chain to be processed? */
 392                         /* CB1 chain always has at least the last one processed */
 393                     && (ioat_chan->used_desc.prev != ioat_chan->used_desc.next)
 394                     && ioat_chan->pending == 0) {
 395
 396                         /*
 397                          * check CHANSTS register for completed
 398                          * descriptor address.
 399                          * if it is different than completion writeback,
 400                          * it is not zero
 401                          * and it has changed since the last watchdog
 402                          *     we can assume that channel
 403                          *     is still working correctly
 404                          *     and the problem is in completion writeback.
 405                          *     update completion writeback
 406                          *     with actual CHANSTS value
 407                          * else
 408                          *     try resetting the channel
 409                          */
 410
 411                         completion_hw.low = readl(ioat_chan->reg_base +
 412                                 IOAT_CHANSTS_OFFSET_LOW(ioat_chan->device->version));
 413                         completion_hw.high = readl(ioat_chan->reg_base +
 414                                 IOAT_CHANSTS_OFFSET_HIGH(ioat_chan->device->version));
 415 #if (BITS_PER_LONG == 64)
 416                         compl_desc_addr_hw =
 417                                 completion_hw.full
 418                                 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
 419 #else
 420                         compl_desc_addr_hw =
 421                                 completion_hw.low & IOAT_LOW_COMPLETION_MASK;
 422 #endif
 423
 424                         if ((compl_desc_addr_hw != 0)
 425                            && (compl_desc_addr_hw != ioat_chan->watchdog_completion)
 426                            && (compl_desc_addr_hw != ioat_chan->last_compl_desc_addr_hw)) {
 427                                 ioat_chan->last_compl_desc_addr_hw = compl_desc_addr_hw;
 428                                 ioat_chan->completion_virt->low = completion_hw.low;
 429                                 ioat_chan->completion_virt->high = completion_hw.high;
 430                         } else {
 431                                 ioat_dma_reset_channel(ioat_chan);
 432                                 ioat_chan->watchdog_completion = 0;
 433                                 ioat_chan->last_compl_desc_addr_hw = 0;
 434                         }
 435
 436                 /*
 437                  * for version 2.0 if there are descriptors yet to be processed
 438                  * and the last completed hasn't changed since the last watchdog
 439                  *      if they haven't hit the pending level
 440                  *          issue the pending to push them through
 441                  *      else
 442                  *          try resetting the channel
 443                  */
 444                 } else if (ioat_chan->device->version == IOAT_VER_2_0
 445                     && ioat_chan->used_desc.prev
 446                     && ioat_chan->last_completion
 447                     && ioat_chan->last_completion == ioat_chan->watchdog_completion) {
 448
 449                         if (ioat_chan->pending < ioat_pending_level)
 450                                 ioat2_dma_memcpy_issue_pending(&ioat_chan->common);
 451                         else {
 452                                 ioat_dma_reset_channel(ioat_chan);
 453                                 ioat_chan->watchdog_completion = 0;
 454                         }
 455                 } else {
 456                         ioat_chan->last_compl_desc_addr_hw = 0;
 457                         ioat_chan->watchdog_completion
 458                                         = ioat_chan->last_completion;
 459                 }
 460
 461                 ioat_chan->watchdog_last_tcp_cookie =
 462                         ioat_chan->watchdog_tcp_cookie;
 463         }
 464
 465         schedule_delayed_work(&device->work, WATCHDOG_DELAY);
 466 }
 467
 468 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 469 {
 470         struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
 471         struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
 472         struct ioat_desc_sw *prev, *new;
 473         struct ioat_dma_descriptor *hw;
 474         dma_cookie_t cookie;
 475         LIST_HEAD(new_chain);
 476         u32 copy;
 477         size_t len;
 478         dma_addr_t src, dst;
 479         unsigned long orig_flags;
 480         unsigned int desc_count = 0;
 481
 482         /* src and dest and len are stored in the initial descriptor */
 483         len = first->len;
 484         src = first->src;
 485         dst = first->dst;
 486         orig_flags = first->async_tx.flags;
 487         new = first;
 488
 489         spin_lock_bh(&ioat_chan->desc_lock);
 490         prev = to_ioat_desc(ioat_chan->used_desc.prev);
 491         prefetch(prev->hw);
 492         do {
 493                 copy = min_t(size_t, len, ioat_chan->xfercap);
 494
 495                 async_tx_ack(&new->async_tx);
 496
 497                 hw = new->hw;
 498                 hw->size = copy;
 499                 hw->ctl = 0;
 500                 hw->src_addr = src;
 501                 hw->dst_addr = dst;
 502                 hw->next = 0;
 503
 504                 /* chain together the physical address list for the HW */
 505                 wmb();
 506                 prev->hw->next = (u64) new->async_tx.phys;
 507
 508                 len -= copy;
 509                 dst += copy;
 510                 src += copy;
 511
 512                 list_add_tail(&new->node, &new_chain);
 513                 desc_count++;
 514                 prev = new;
 515         } while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan)));
 516
 517         if (!new) {
 518                 dev_err(&ioat_chan->device->pdev->dev,
 519                         "tx submit failed\n");
 520                 spin_unlock_bh(&ioat_chan->desc_lock);
 521                 return -ENOMEM;
 522         }
 523
 524         hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
 525         if (new->async_tx.callback) {
 526                 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
 527                 if (first != new) {
 528                         /* move callback into to last desc */
 529                         new->async_tx.callback = first->async_tx.callback;
 530                         new->async_tx.callback_param
 531                                         = first->async_tx.callback_param;
 532                         first->async_tx.callback = NULL;
 533                         first->async_tx.callback_param = NULL;
 534                 }
 535         }
 536
 537         new->tx_cnt = desc_count;
 538         new->async_tx.flags = orig_flags; /* client is in control of this ack */
 539
 540         /* store the original values for use in later cleanup */
 541         if (new != first) {
 542                 new->src = first->src;
 543                 new->dst = first->dst;
 544                 new->len = first->len;
 545         }
 546
 547         /* cookie incr and addition to used_list must be atomic */
 548         cookie = ioat_chan->common.cookie;
 549         cookie++;
 550         if (cookie < 0)
 551                 cookie = 1;
 552         ioat_chan->common.cookie = new->async_tx.cookie = cookie;
 553
 554         /* write address into NextDescriptor field of last desc in chain */
 555         to_ioat_desc(ioat_chan->used_desc.prev)->hw->next =
 556                                                         first->async_tx.phys;
 557         list_splice_tail(&new_chain, &ioat_chan->used_desc);
 558
 559         ioat_chan->dmacount += desc_count;
 560         ioat_chan->pending += desc_count;
 561         if (ioat_chan->pending >= ioat_pending_level)
 562                 __ioat1_dma_memcpy_issue_pending(ioat_chan);
 563         spin_unlock_bh(&ioat_chan->desc_lock);
 564
 565         return cookie;
 566 }
 567
 568 static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
 569 {
 570         struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
 571         struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
 572         struct ioat_desc_sw *new;
 573         struct ioat_dma_descriptor *hw;
 574         dma_cookie_t cookie;
 575         u32 copy;
 576         size_t len;
 577         dma_addr_t src, dst;
 578         unsigned long orig_flags;
 579         unsigned int desc_count = 0;
 580
 581         /* src and dest and len are stored in the initial descriptor */
 582         len = first->len;
 583         src = first->src;
 584         dst = first->dst;
 585         orig_flags = first->async_tx.flags;
 586         new = first;
 587
 588         /*
 589          * ioat_chan->desc_lock is still in force in version 2 path
 590          * it gets unlocked at end of this function
 591          */
 592         do {
 593                 copy = min_t(size_t, len, ioat_chan->xfercap);
 594
 595                 async_tx_ack(&new->async_tx);
 596
 597                 hw = new->hw;
 598                 hw->size = copy;
 599                 hw->ctl = 0;
 600                 hw->src_addr = src;
 601                 hw->dst_addr = dst;
 602
 603                 len -= copy;
 604                 dst += copy;
 605                 src += copy;
 606                 desc_count++;
 607         } while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan)));
 608
 609         if (!new) {
 610                 dev_err(&ioat_chan->device->pdev->dev,
 611                         "tx submit failed\n");
 612                 spin_unlock_bh(&ioat_chan->desc_lock);
 613                 return -ENOMEM;
 614         }
 615
 616         hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
 617         if (new->async_tx.callback) {
 618                 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
 619                 if (first != new) {
 620                         /* move callback into to last desc */
 621                         new->async_tx.callback = first->async_tx.callback;
 622                         new->async_tx.callback_param
 623                                         = first->async_tx.callback_param;
 624                         first->async_tx.callback = NULL;
 625                         first->async_tx.callback_param = NULL;
 626                 }
 627         }
 628
 629         new->tx_cnt = desc_count;
 630         new->async_tx.flags = orig_flags; /* client is in control of this ack */
 631
 632         /* store the original values for use in later cleanup */
 633         if (new != first) {
 634                 new->src = first->src;
 635                 new->dst = first->dst;
 636                 new->len = first->len;
 637         }
 638
 639         /* cookie incr and addition to used_list must be atomic */
 640         cookie = ioat_chan->common.cookie;
 641         cookie++;
 642         if (cookie < 0)
 643                 cookie = 1;
 644         ioat_chan->common.cookie = new->async_tx.cookie = cookie;
 645
 646         ioat_chan->dmacount += desc_count;
 647         ioat_chan->pending += desc_count;
 648         if (ioat_chan->pending >= ioat_pending_level)
 649                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
 650         spin_unlock_bh(&ioat_chan->desc_lock);
 651
 652         return cookie;
 653 }
 654
 655 /**
 656  * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
 657  * @ioat_chan: the channel supplying the memory pool for the descriptors
 658  * @flags: allocation flags
 659  */
 660 static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
 661                                         struct ioat_dma_chan *ioat_chan,
 662                                         gfp_t flags)
 663 {
 664         struct ioat_dma_descriptor *desc;
 665         struct ioat_desc_sw *desc_sw;
 666         struct ioatdma_device *ioatdma_device;
 667         dma_addr_t phys;
 668
 669         ioatdma_device = to_ioatdma_device(ioat_chan->common.device);
 670         desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
 671         if (unlikely(!desc))
 672                 return NULL;
 673
 674         desc_sw = kzalloc(sizeof(*desc_sw), flags);
 675         if (unlikely(!desc_sw)) {
 676                 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
 677                 return NULL;
 678         }
 679
 680         memset(desc, 0, sizeof(*desc));
 681         dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common);
 682         switch (ioat_chan->device->version) {
 683         case IOAT_VER_1_2:
 684                 desc_sw->async_tx.tx_submit = ioat1_tx_submit;
 685                 break;
 686         case IOAT_VER_2_0:
 687         case IOAT_VER_3_0:
 688                 desc_sw->async_tx.tx_submit = ioat2_tx_submit;
 689                 break;
 690         }
 691         INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
 692
 693         desc_sw->hw = desc;
 694         desc_sw->async_tx.phys = phys;
 695
 696         return desc_sw;
 697 }
 698
 699 static int ioat_initial_desc_count = 256;
 700 module_param(ioat_initial_desc_count, int, 0644);
 701 MODULE_PARM_DESC(ioat_initial_desc_count,
 702                  "initial descriptors per channel (default: 256)");
 703
 704 /**
 705  * ioat2_dma_massage_chan_desc - link the descriptors into a circle
 706  * @ioat_chan: the channel to be massaged
 707  */
 708 static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan)
 709 {
 710         struct ioat_desc_sw *desc, *_desc;
 711
 712         /* setup used_desc */
 713         ioat_chan->used_desc.next = ioat_chan->free_desc.next;
 714         ioat_chan->used_desc.prev = NULL;
 715
 716         /* pull free_desc out of the circle so that every node is a hw
 717          * descriptor, but leave it pointing to the list
 718          */
 719         ioat_chan->free_desc.prev->next = ioat_chan->free_desc.next;
 720         ioat_chan->free_desc.next->prev = ioat_chan->free_desc.prev;
 721
 722         /* circle link the hw descriptors */
 723         desc = to_ioat_desc(ioat_chan->free_desc.next);
 724         desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
 725         list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) {
 726                 desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
 727         }
 728 }
 729
 730 /**
 731  * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors
 732  * @chan: the channel to be filled out
 733  */
 734 static int ioat_dma_alloc_chan_resources(struct dma_chan *chan,
 735                                          struct dma_client *client)
 736 {
 737         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 738         struct ioat_desc_sw *desc;
 739         u16 chanctrl;
 740         u32 chanerr;
 741         int i;
 742         LIST_HEAD(tmp_list);
 743
 744         /* have we already been set up? */
 745         if (!list_empty(&ioat_chan->free_desc))
 746                 return ioat_chan->desccount;
 747
 748         /* Setup register to interrupt and write completion status on error */
 749         chanctrl = IOAT_CHANCTRL_ERR_INT_EN |
 750                 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
 751                 IOAT_CHANCTRL_ERR_COMPLETION_EN;
 752         writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
 753
 754         chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
 755         if (chanerr) {
 756                 dev_err(&ioat_chan->device->pdev->dev,
 757                         "CHANERR = %x, clearing\n", chanerr);
 758                 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
 759         }
 760
 761         /* Allocate descriptors */
 762         for (i = 0; i < ioat_initial_desc_count; i++) {
 763                 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
 764                 if (!desc) {
 765                         dev_err(&ioat_chan->device->pdev->dev,
 766                                 "Only %d initial descriptors\n", i);
 767                         break;
 768                 }
 769                 list_add_tail(&desc->node, &tmp_list);
 770         }
 771         spin_lock_bh(&ioat_chan->desc_lock);
 772         ioat_chan->desccount = i;
 773         list_splice(&tmp_list, &ioat_chan->free_desc);
 774         if (ioat_chan->device->version != IOAT_VER_1_2)
 775                 ioat2_dma_massage_chan_desc(ioat_chan);
 776         spin_unlock_bh(&ioat_chan->desc_lock);
 777
 778         /* allocate a completion writeback area */
 779         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
 780         ioat_chan->completion_virt =
 781                 pci_pool_alloc(ioat_chan->device->completion_pool,
 782                                GFP_KERNEL,
 783                                &ioat_chan->completion_addr);
 784         memset(ioat_chan->completion_virt, 0,
 785                sizeof(*ioat_chan->completion_virt));
 786         writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF,
 787                ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
 788         writel(((u64) ioat_chan->completion_addr) >> 32,
 789                ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
 790
 791         tasklet_enable(&ioat_chan->cleanup_task);
 792         ioat_dma_start_null_desc(ioat_chan);  /* give chain to dma device */
 793         return ioat_chan->desccount;
 794 }
 795
 796 /**
 797  * ioat_dma_free_chan_resources - release all the descriptors
 798  * @chan: the channel to be cleaned
 799  */
 800 static void ioat_dma_free_chan_resources(struct dma_chan *chan)
 801 {
 802         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 803         struct ioatdma_device *ioatdma_device = to_ioatdma_device(chan->device);
 804         struct ioat_desc_sw *desc, *_desc;
 805         int in_use_descs = 0;
 806
 807         tasklet_disable(&ioat_chan->cleanup_task);
 808         ioat_dma_memcpy_cleanup(ioat_chan);
 809
 810         /* Delay 100ms after reset to allow internal DMA logic to quiesce
 811          * before removing DMA descriptor resources.
 812          */
 813         writeb(IOAT_CHANCMD_RESET,
 814                ioat_chan->reg_base
 815                         + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
 816         mdelay(100);
 817
 818         spin_lock_bh(&ioat_chan->desc_lock);
 819         switch (ioat_chan->device->version) {
 820         case IOAT_VER_1_2:
 821                 list_for_each_entry_safe(desc, _desc,
 822                                          &ioat_chan->used_desc, node) {
 823                         in_use_descs++;
 824                         list_del(&desc->node);
 825                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 826                                       desc->async_tx.phys);
 827                         kfree(desc);
 828                 }
 829                 list_for_each_entry_safe(desc, _desc,
 830                                          &ioat_chan->free_desc, node) {
 831                         list_del(&desc->node);
 832                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 833                                       desc->async_tx.phys);
 834                         kfree(desc);
 835                 }
 836                 break;
 837         case IOAT_VER_2_0:
 838         case IOAT_VER_3_0:
 839                 list_for_each_entry_safe(desc, _desc,
 840                                          ioat_chan->free_desc.next, node) {
 841                         list_del(&desc->node);
 842                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 843                                       desc->async_tx.phys);
 844                         kfree(desc);
 845                 }
 846                 desc = to_ioat_desc(ioat_chan->free_desc.next);
 847                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 848                               desc->async_tx.phys);
 849                 kfree(desc);
 850                 INIT_LIST_HEAD(&ioat_chan->free_desc);
 851                 INIT_LIST_HEAD(&ioat_chan->used_desc);
 852                 break;
 853         }
 854         spin_unlock_bh(&ioat_chan->desc_lock);
 855
 856         pci_pool_free(ioatdma_device->completion_pool,
 857                       ioat_chan->completion_virt,
 858                       ioat_chan->completion_addr);
 859
 860         /* one is ok since we left it on there on purpose */
 861         if (in_use_descs > 1)
 862                 dev_err(&ioat_chan->device->pdev->dev,
 863                         "Freeing %d in use descriptors!\n",
 864                         in_use_descs - 1);
 865
 866         ioat_chan->last_completion = ioat_chan->completion_addr = 0;
 867         ioat_chan->pending = 0;
 868         ioat_chan->dmacount = 0;
 869         ioat_chan->watchdog_completion = 0;
 870         ioat_chan->last_compl_desc_addr_hw = 0;
 871         ioat_chan->watchdog_tcp_cookie =
 872                 ioat_chan->watchdog_last_tcp_cookie = 0;
 873 }
 874
 875 /**
 876  * ioat_dma_get_next_descriptor - return the next available descriptor
 877  * @ioat_chan: IOAT DMA channel handle
 878  *
 879  * Gets the next descriptor from the chain, and must be called with the
 880  * channel's desc_lock held.  Allocates more descriptors if the channel
 881  * has run out.
 882  */
 883 static struct ioat_desc_sw *
 884 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
 885 {
 886         struct ioat_desc_sw *new;
 887
 888         if (!list_empty(&ioat_chan->free_desc)) {
 889                 new = to_ioat_desc(ioat_chan->free_desc.next);
 890                 list_del(&new->node);
 891         } else {
 892                 /* try to get another desc */
 893                 new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
 894                 if (!new) {
 895                         dev_err(&ioat_chan->device->pdev->dev,
 896                                 "alloc failed\n");
 897                         return NULL;
 898                 }
 899         }
 900
 901         prefetch(new->hw);
 902         return new;
 903 }
 904
 905 static struct ioat_desc_sw *
 906 ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
 907 {
 908         struct ioat_desc_sw *new;
 909
 910         /*
 911          * used.prev points to where to start processing
 912          * used.next points to next free descriptor
 913          * if used.prev == NULL, there are none waiting to be processed
 914          * if used.next == used.prev.prev, there is only one free descriptor,
 915          *      and we need to use it to as a noop descriptor before
 916          *      linking in a new set of descriptors, since the device
 917          *      has probably already read the pointer to it
 918          */
 919         if (ioat_chan->used_desc.prev &&
 920             ioat_chan->used_desc.next == ioat_chan->used_desc.prev->prev) {
 921
 922                 struct ioat_desc_sw *desc;
 923                 struct ioat_desc_sw *noop_desc;
 924                 int i;
 925
 926                 /* set up the noop descriptor */
 927                 noop_desc = to_ioat_desc(ioat_chan->used_desc.next);
 928                 /* set size to non-zero value (channel returns error when size is 0) */
 929                 noop_desc->hw->size = NULL_DESC_BUFFER_SIZE;
 930                 noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL;
 931                 noop_desc->hw->src_addr = 0;
 932                 noop_desc->hw->dst_addr = 0;
 933
 934                 ioat_chan->used_desc.next = ioat_chan->used_desc.next->next;
 935                 ioat_chan->pending++;
 936                 ioat_chan->dmacount++;
 937
 938                 /* try to get a few more descriptors */
 939                 for (i = 16; i; i--) {
 940                         desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
 941                         if (!desc) {
 942                                 dev_err(&ioat_chan->device->pdev->dev,
 943                                         "alloc failed\n");
 944                                 break;
 945                         }
 946                         list_add_tail(&desc->node, ioat_chan->used_desc.next);
 947
 948                         desc->hw->next
 949                                 = to_ioat_desc(desc->node.next)->async_tx.phys;
 950                         to_ioat_desc(desc->node.prev)->hw->next
 951                                 = desc->async_tx.phys;
 952                         ioat_chan->desccount++;
 953                 }
 954
 955                 ioat_chan->used_desc.next = noop_desc->node.next;
 956         }
 957         new = to_ioat_desc(ioat_chan->used_desc.next);
 958         prefetch(new);
 959         ioat_chan->used_desc.next = new->node.next;
 960
 961         if (ioat_chan->used_desc.prev == NULL)
 962                 ioat_chan->used_desc.prev = &new->node;
 963
 964         prefetch(new->hw);
 965         return new;
 966 }
 967
 968 static struct ioat_desc_sw *ioat_dma_get_next_descriptor(
 969                                                 struct ioat_dma_chan *ioat_chan)
 970 {
 971         if (!ioat_chan)
 972                 return NULL;
 973
 974         switch (ioat_chan->device->version) {
 975         case IOAT_VER_1_2:
 976                 return ioat1_dma_get_next_descriptor(ioat_chan);
 977                 break;
 978         case IOAT_VER_2_0:
 979         case IOAT_VER_3_0:
 980                 return ioat2_dma_get_next_descriptor(ioat_chan);
 981                 break;
 982         }
 983         return NULL;
 984 }
 985
 986 static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy(
 987                                                 struct dma_chan *chan,
 988                                                 dma_addr_t dma_dest,
 989                                                 dma_addr_t dma_src,
 990                                                 size_t len,
 991                                                 unsigned long flags)
 992 {
 993         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 994         struct ioat_desc_sw *new;
 995
 996         spin_lock_bh(&ioat_chan->desc_lock);
 997         new = ioat_dma_get_next_descriptor(ioat_chan);
 998         spin_unlock_bh(&ioat_chan->desc_lock);
 999
1000         if (new) {
1001                 new->len = len;
1002                 new->dst = dma_dest;
1003                 new->src = dma_src;
1004                 new->async_tx.flags = flags;
1005                 return &new->async_tx;
1006         } else {
1007                 dev_err(&ioat_chan->device->pdev->dev,
1008                         "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
1009                         chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
1010                 return NULL;
1011         }
1012 }
1013
1014 static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy(
1015                                                 struct dma_chan *chan,
1016                                                 dma_addr_t dma_dest,
1017                                                 dma_addr_t dma_src,
1018                                                 size_t len,
1019                                                 unsigned long flags)
1020 {
1021         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1022         struct ioat_desc_sw *new;
1023
1024         spin_lock_bh(&ioat_chan->desc_lock);
1025         new = ioat2_dma_get_next_descriptor(ioat_chan);
1026
1027         /*
1028          * leave ioat_chan->desc_lock set in ioat 2 path
1029          * it will get unlocked at end of tx_submit
1030          */
1031
1032         if (new) {
1033                 new->len = len;
1034                 new->dst = dma_dest;
1035                 new->src = dma_src;
1036                 new->async_tx.flags = flags;
1037                 return &new->async_tx;
1038         } else {
1039                 spin_unlock_bh(&ioat_chan->desc_lock);
1040                 dev_err(&ioat_chan->device->pdev->dev,
1041                         "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
1042                         chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
1043                 return NULL;
1044         }
1045 }
1046
1047 static void ioat_dma_cleanup_tasklet(unsigned long data)
1048 {
1049         struct ioat_dma_chan *chan = (void *)data;
1050         ioat_dma_memcpy_cleanup(chan);
1051         writew(IOAT_CHANCTRL_INT_DISABLE,
1052                chan->reg_base + IOAT_CHANCTRL_OFFSET);
1053 }
1054
1055 static void
1056 ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc)
1057 {
1058         /*
1059          * yes we are unmapping both _page and _single
1060          * alloc'd regions with unmap_page. Is this
1061          * *really* that bad?
1062          */
1063         if (!(desc->async_tx.flags & DMA_COMPL_SKIP_DEST_UNMAP))
1064                 pci_unmap_page(ioat_chan->device->pdev,
1065                                 pci_unmap_addr(desc, dst),
1066                                 pci_unmap_len(desc, len),
1067                                 PCI_DMA_FROMDEVICE);
1068
1069         if (!(desc->async_tx.flags & DMA_COMPL_SKIP_SRC_UNMAP))
1070                 pci_unmap_page(ioat_chan->device->pdev,
1071                                 pci_unmap_addr(desc, src),
1072                                 pci_unmap_len(desc, len),
1073                                 PCI_DMA_TODEVICE);
1074 }
1075
1076 /**
1077  * ioat_dma_memcpy_cleanup - cleanup up finished descriptors
1078  * @chan: ioat channel to be cleaned up
1079  */
1080 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
1081 {
1082         unsigned long phys_complete;
1083         struct ioat_desc_sw *desc, *_desc;
1084         dma_cookie_t cookie = 0;
1085         unsigned long desc_phys;
1086         struct ioat_desc_sw *latest_desc;
1087
1088         prefetch(ioat_chan->completion_virt);
1089
1090         if (!spin_trylock_bh(&ioat_chan->cleanup_lock))
1091                 return;
1092
1093         /* The completion writeback can happen at any time,
1094            so reads by the driver need to be atomic operations
1095            The descriptor physical addresses are limited to 32-bits
1096            when the CPU can only do a 32-bit mov */
1097
1098 #if (BITS_PER_LONG == 64)
1099         phys_complete =
1100                 ioat_chan->completion_virt->full
1101                 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
1102 #else
1103         phys_complete =
1104                 ioat_chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
1105 #endif
1106
1107         if ((ioat_chan->completion_virt->full
1108                 & IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
1109                                 IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
1110                 dev_err(&ioat_chan->device->pdev->dev,
1111                         "Channel halted, chanerr = %x\n",
1112                         readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET));
1113
1114                 /* TODO do something to salvage the situation */
1115         }
1116
1117         if (phys_complete == ioat_chan->last_completion) {
1118                 spin_unlock_bh(&ioat_chan->cleanup_lock);
1119                 /*
1120                  * perhaps we're stuck so hard that the watchdog can't go off?
1121                  * try to catch it after 2 seconds
1122                  */
1123                 if (ioat_chan->device->version != IOAT_VER_3_0) {
1124                         if (time_after(jiffies,
1125                                        ioat_chan->last_completion_time + HZ*WATCHDOG_DELAY)) {
1126                                 ioat_dma_chan_watchdog(&(ioat_chan->device->work.work));
1127                                 ioat_chan->last_completion_time = jiffies;
1128                         }
1129                 }
1130                 return;
1131         }
1132         ioat_chan->last_completion_time = jiffies;
1133
1134         cookie = 0;
1135         if (!spin_trylock_bh(&ioat_chan->desc_lock)) {
1136                 spin_unlock_bh(&ioat_chan->cleanup_lock);
1137                 return;
1138         }
1139
1140         switch (ioat_chan->device->version) {
1141         case IOAT_VER_1_2:
1142                 list_for_each_entry_safe(desc, _desc,
1143                                          &ioat_chan->used_desc, node) {
1144
1145                         /*
1146                          * Incoming DMA requests may use multiple descriptors,
1147                          * due to exceeding xfercap, perhaps. If so, only the
1148                          * last one will have a cookie, and require unmapping.
1149                          */
1150                         if (desc->async_tx.cookie) {
1151                                 cookie = desc->async_tx.cookie;
1152                                 ioat_dma_unmap(ioat_chan, desc);
1153                                 if (desc->async_tx.callback) {
1154                                         desc->async_tx.callback(desc->async_tx.callback_param);
1155                                         desc->async_tx.callback = NULL;
1156                                 }
1157                         }
1158
1159                         if (desc->async_tx.phys != phys_complete) {
1160                                 /*
1161                                  * a completed entry, but not the last, so clean
1162                                  * up if the client is done with the descriptor
1163                                  */
1164                                 if (async_tx_test_ack(&desc->async_tx)) {
1165                                         list_del(&desc->node);
1166                                         list_add_tail(&desc->node,
1167                                                       &ioat_chan->free_desc);
1168                                 } else
1169                                         desc->async_tx.cookie = 0;
1170                         } else {
1171                                 /*
1172                                  * last used desc. Do not remove, so we can
1173                                  * append from it, but don't look at it next
1174                                  * time, either
1175                                  */
1176                                 desc->async_tx.cookie = 0;
1177
1178                                 /* TODO check status bits? */
1179                                 break;
1180                         }
1181                 }
1182                 break;
1183         case IOAT_VER_2_0:
1184         case IOAT_VER_3_0:
1185                 /* has some other thread has already cleaned up? */
1186                 if (ioat_chan->used_desc.prev == NULL)
1187                         break;
1188
1189                 /* work backwards to find latest finished desc */
1190                 desc = to_ioat_desc(ioat_chan->used_desc.next);
1191                 latest_desc = NULL;
1192                 do {
1193                         desc = to_ioat_desc(desc->node.prev);
1194                         desc_phys = (unsigned long)desc->async_tx.phys
1195                                        & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
1196                         if (desc_phys == phys_complete) {
1197                                 latest_desc = desc;
1198                                 break;
1199                         }
1200                 } while (&desc->node != ioat_chan->used_desc.prev);
1201
1202                 if (latest_desc != NULL) {
1203
1204                         /* work forwards to clear finished descriptors */
1205                         for (desc = to_ioat_desc(ioat_chan->used_desc.prev);
1206                              &desc->node != latest_desc->node.next &&
1207                              &desc->node != ioat_chan->used_desc.next;
1208                              desc = to_ioat_desc(desc->node.next)) {
1209                                 if (desc->async_tx.cookie) {
1210                                         cookie = desc->async_tx.cookie;
1211                                         desc->async_tx.cookie = 0;
1212                                         ioat_dma_unmap(ioat_chan, desc);
1213                                         if (desc->async_tx.callback) {
1214                                                 desc->async_tx.callback(desc->async_tx.callback_param);
1215                                                 desc->async_tx.callback = NULL;
1216                                         }
1217                                 }
1218                         }
1219
1220                         /* move used.prev up beyond those that are finished */
1221                         if (&desc->node == ioat_chan->used_desc.next)
1222                                 ioat_chan->used_desc.prev = NULL;
1223                         else
1224                                 ioat_chan->used_desc.prev = &desc->node;
1225                 }
1226                 break;
1227         }
1228
1229         spin_unlock_bh(&ioat_chan->desc_lock);
1230
1231         ioat_chan->last_completion = phys_complete;
1232         if (cookie != 0)
1233                 ioat_chan->completed_cookie = cookie;
1234
1235         spin_unlock_bh(&ioat_chan->cleanup_lock);
1236 }
1237
1238 /**
1239  * ioat_dma_is_complete - poll the status of a IOAT DMA transaction
1240  * @chan: IOAT DMA channel handle
1241  * @cookie: DMA transaction identifier
1242  * @done: if not %NULL, updated with last completed transaction
1243  * @used: if not %NULL, updated with last used transaction
1244  */
1245 static enum dma_status ioat_dma_is_complete(struct dma_chan *chan,
1246                                             dma_cookie_t cookie,
1247                                             dma_cookie_t *done,
1248                                             dma_cookie_t *used)
1249 {
1250         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1251         dma_cookie_t last_used;
1252         dma_cookie_t last_complete;
1253         enum dma_status ret;
1254
1255         last_used = chan->cookie;
1256         last_complete = ioat_chan->completed_cookie;
1257         ioat_chan->watchdog_tcp_cookie = cookie;
1258
1259         if (done)
1260                 *done = last_complete;
1261         if (used)
1262                 *used = last_used;
1263
1264         ret = dma_async_is_complete(cookie, last_complete, last_used);
1265         if (ret == DMA_SUCCESS)
1266                 return ret;
1267
1268         ioat_dma_memcpy_cleanup(ioat_chan);
1269
1270         last_used = chan->cookie;
1271         last_complete = ioat_chan->completed_cookie;
1272
1273         if (done)
1274                 *done = last_complete;
1275         if (used)
1276                 *used = last_used;
1277
1278         return dma_async_is_complete(cookie, last_complete, last_used);
1279 }
1280
1281 static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
1282 {
1283         struct ioat_desc_sw *desc;
1284
1285         spin_lock_bh(&ioat_chan->desc_lock);
1286
1287         desc = ioat_dma_get_next_descriptor(ioat_chan);
1288
1289         if (!desc) {
1290                 dev_err(&ioat_chan->device->pdev->dev,
1291                         "Unable to start null desc - get next desc failed\n");
1292                 spin_unlock_bh(&ioat_chan->desc_lock);
1293                 return;
1294         }
1295
1296         desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL
1297                                 | IOAT_DMA_DESCRIPTOR_CTL_INT_GN
1298                                 | IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
1299         /* set size to non-zero value (channel returns error when size is 0) */
1300         desc->hw->size = NULL_DESC_BUFFER_SIZE;
1301         desc->hw->src_addr = 0;
1302         desc->hw->dst_addr = 0;
1303         async_tx_ack(&desc->async_tx);
1304         switch (ioat_chan->device->version) {
1305         case IOAT_VER_1_2:
1306                 desc->hw->next = 0;
1307                 list_add_tail(&desc->node, &ioat_chan->used_desc);
1308
1309                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1310                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
1311                 writel(((u64) desc->async_tx.phys) >> 32,
1312                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
1313
1314                 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
1315                         + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
1316                 break;
1317         case IOAT_VER_2_0:
1318         case IOAT_VER_3_0:
1319                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1320                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
1321                 writel(((u64) desc->async_tx.phys) >> 32,
1322                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
1323
1324                 ioat_chan->dmacount++;
1325                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
1326                 break;
1327         }
1328         spin_unlock_bh(&ioat_chan->desc_lock);
1329 }
1330
1331 /*
1332  * Perform a IOAT transaction to verify the HW works.
1333  */
1334 #define IOAT_TEST_SIZE 2000
1335
1336 static void ioat_dma_test_callback(void *dma_async_param)
1337 {
1338         printk(KERN_ERR "ioatdma: ioat_dma_test_callback(%p)\n",
1339                 dma_async_param);
1340 }
1341
1342 /**
1343  * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
1344  * @device: device to be tested
1345  */
1346 static int ioat_dma_self_test(struct ioatdma_device *device)
1347 {
1348         int i;
1349         u8 *src;
1350         u8 *dest;
1351         struct dma_chan *dma_chan;
1352         struct dma_async_tx_descriptor *tx;
1353         dma_addr_t dma_dest, dma_src;
1354         dma_cookie_t cookie;
1355         int err = 0;
1356
1357         src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1358         if (!src)
1359                 return -ENOMEM;
1360         dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1361         if (!dest) {
1362                 kfree(src);
1363                 return -ENOMEM;
1364         }
1365
1366         /* Fill in src buffer */
1367         for (i = 0; i < IOAT_TEST_SIZE; i++)
1368                 src[i] = (u8)i;
1369
1370         /* Start copy, using first DMA channel */
1371         dma_chan = container_of(device->common.channels.next,
1372                                 struct dma_chan,
1373                                 device_node);
1374         if (device->common.device_alloc_chan_resources(dma_chan, NULL) < 1) {
1375                 dev_err(&device->pdev->dev,
1376                         "selftest cannot allocate chan resource\n");
1377                 err = -ENODEV;
1378                 goto out;
1379         }
1380
1381         dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE,
1382                                  DMA_TO_DEVICE);
1383         dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE,
1384                                   DMA_FROM_DEVICE);
1385         tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
1386                                                    IOAT_TEST_SIZE, 0);
1387         if (!tx) {
1388                 dev_err(&device->pdev->dev,
1389                         "Self-test prep failed, disabling\n");
1390                 err = -ENODEV;
1391                 goto free_resources;
1392         }
1393
1394         async_tx_ack(tx);
1395         tx->callback = ioat_dma_test_callback;
1396         tx->callback_param = (void *)0x8086;
1397         cookie = tx->tx_submit(tx);
1398         if (cookie < 0) {
1399                 dev_err(&device->pdev->dev,
1400                         "Self-test setup failed, disabling\n");
1401                 err = -ENODEV;
1402                 goto free_resources;
1403         }
1404         device->common.device_issue_pending(dma_chan);
1405         msleep(1);
1406
1407         if (device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL)
1408                                         != DMA_SUCCESS) {
1409                 dev_err(&device->pdev->dev,
1410                         "Self-test copy timed out, disabling\n");
1411                 err = -ENODEV;
1412                 goto free_resources;
1413         }
1414         if (memcmp(src, dest, IOAT_TEST_SIZE)) {
1415                 dev_err(&device->pdev->dev,
1416                         "Self-test copy failed compare, disabling\n");
1417                 err = -ENODEV;
1418                 goto free_resources;
1419         }
1420
1421 free_resources:
1422         device->common.device_free_chan_resources(dma_chan);
1423 out:
1424         kfree(src);
1425         kfree(dest);
1426         return err;
1427 }
1428
1429 static char ioat_interrupt_style[32] = "msix";
1430 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
1431                     sizeof(ioat_interrupt_style), 0644);
1432 MODULE_PARM_DESC(ioat_interrupt_style,
1433                  "set ioat interrupt style: msix (default), "
1434                  "msix-single-vector, msi, intx)");
1435
1436 /**
1437  * ioat_dma_setup_interrupts - setup interrupt handler
1438  * @device: ioat device
1439  */
1440 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
1441 {
1442         struct ioat_dma_chan *ioat_chan;
1443         int err, i, j, msixcnt;
1444         u8 intrctrl = 0;
1445
1446         if (!strcmp(ioat_interrupt_style, "msix"))
1447                 goto msix;
1448         if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
1449                 goto msix_single_vector;
1450         if (!strcmp(ioat_interrupt_style, "msi"))
1451                 goto msi;
1452         if (!strcmp(ioat_interrupt_style, "intx"))
1453                 goto intx;
1454         dev_err(&device->pdev->dev, "invalid ioat_interrupt_style %s\n",
1455                 ioat_interrupt_style);
1456         goto err_no_irq;
1457
1458 msix:
1459         /* The number of MSI-X vectors should equal the number of channels */
1460         msixcnt = device->common.chancnt;
1461         for (i = 0; i < msixcnt; i++)
1462                 device->msix_entries[i].entry = i;
1463
1464         err = pci_enable_msix(device->pdev, device->msix_entries, msixcnt);
1465         if (err < 0)
1466                 goto msi;
1467         if (err > 0)
1468                 goto msix_single_vector;
1469
1470         for (i = 0; i < msixcnt; i++) {
1471                 ioat_chan = ioat_lookup_chan_by_index(device, i);
1472                 err = request_irq(device->msix_entries[i].vector,
1473                                   ioat_dma_do_interrupt_msix,
1474                                   0, "ioat-msix", ioat_chan);
1475                 if (err) {
1476                         for (j = 0; j < i; j++) {
1477                                 ioat_chan =
1478                                         ioat_lookup_chan_by_index(device, j);
1479                                 free_irq(device->msix_entries[j].vector,
1480                                          ioat_chan);
1481                         }
1482                         goto msix_single_vector;
1483                 }
1484         }
1485         intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
1486         device->irq_mode = msix_multi_vector;
1487         goto done;
1488
1489 msix_single_vector:
1490         device->msix_entries[0].entry = 0;
1491         err = pci_enable_msix(device->pdev, device->msix_entries, 1);
1492         if (err)
1493                 goto msi;
1494
1495         err = request_irq(device->msix_entries[0].vector, ioat_dma_do_interrupt,
1496                           0, "ioat-msix", device);
1497         if (err) {
1498                 pci_disable_msix(device->pdev);
1499                 goto msi;
1500         }
1501         device->irq_mode = msix_single_vector;
1502         goto done;
1503
1504 msi:
1505         err = pci_enable_msi(device->pdev);
1506         if (err)
1507                 goto intx;
1508
1509         err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1510                           0, "ioat-msi", device);
1511         if (err) {
1512                 pci_disable_msi(device->pdev);
1513                 goto intx;
1514         }
1515         /*
1516          * CB 1.2 devices need a bit set in configuration space to enable MSI
1517          */
1518         if (device->version == IOAT_VER_1_2) {
1519                 u32 dmactrl;
1520                 pci_read_config_dword(device->pdev,
1521                                       IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1522                 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1523                 pci_write_config_dword(device->pdev,
1524                                        IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1525         }
1526         device->irq_mode = msi;
1527         goto done;
1528
1529 intx:
1530         err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1531                           IRQF_SHARED, "ioat-intx", device);
1532         if (err)
1533                 goto err_no_irq;
1534         device->irq_mode = intx;
1535
1536 done:
1537         intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
1538         writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
1539         return 0;
1540
1541 err_no_irq:
1542         /* Disable all interrupt generation */
1543         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1544         dev_err(&device->pdev->dev, "no usable interrupts\n");
1545         device->irq_mode = none;
1546         return -1;
1547 }
1548
1549 /**
1550  * ioat_dma_remove_interrupts - remove whatever interrupts were set
1551  * @device: ioat device
1552  */
1553 static void ioat_dma_remove_interrupts(struct ioatdma_device *device)
1554 {
1555         struct ioat_dma_chan *ioat_chan;
1556         int i;
1557
1558         /* Disable all interrupt generation */
1559         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1560
1561         switch (device->irq_mode) {
1562         case msix_multi_vector:
1563                 for (i = 0; i < device->common.chancnt; i++) {
1564                         ioat_chan = ioat_lookup_chan_by_index(device, i);
1565                         free_irq(device->msix_entries[i].vector, ioat_chan);
1566                 }
1567                 pci_disable_msix(device->pdev);
1568                 break;
1569         case msix_single_vector:
1570                 free_irq(device->msix_entries[0].vector, device);
1571                 pci_disable_msix(device->pdev);
1572                 break;
1573         case msi:
1574                 free_irq(device->pdev->irq, device);
1575                 pci_disable_msi(device->pdev);
1576                 break;
1577         case intx:
1578                 free_irq(device->pdev->irq, device);
1579                 break;
1580         case none:
1581                 dev_warn(&device->pdev->dev,
1582                          "call to %s without interrupts setup\n", __func__);
1583         }
1584         device->irq_mode = none;
1585 }
1586
1587 struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
1588                                       void __iomem *iobase)
1589 {
1590         int err;
1591         struct ioatdma_device *device;
1592
1593         device = kzalloc(sizeof(*device), GFP_KERNEL);
1594         if (!device) {
1595                 err = -ENOMEM;
1596                 goto err_kzalloc;
1597         }
1598         device->pdev = pdev;
1599         device->reg_base = iobase;
1600         device->version = readb(device->reg_base + IOAT_VER_OFFSET);
1601
1602         /* DMA coherent memory pool for DMA descriptor allocations */
1603         device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1604                                            sizeof(struct ioat_dma_descriptor),
1605                                            64, 0);
1606         if (!device->dma_pool) {
1607                 err = -ENOMEM;
1608                 goto err_dma_pool;
1609         }
1610
1611         device->completion_pool = pci_pool_create("completion_pool", pdev,
1612                                                   sizeof(u64), SMP_CACHE_BYTES,
1613                                                   SMP_CACHE_BYTES);
1614         if (!device->completion_pool) {
1615                 err = -ENOMEM;
1616                 goto err_completion_pool;
1617         }
1618
1619         INIT_LIST_HEAD(&device->common.channels);
1620         ioat_dma_enumerate_channels(device);
1621
1622         device->common.device_alloc_chan_resources =
1623                                                 ioat_dma_alloc_chan_resources;
1624         device->common.device_free_chan_resources =
1625                                                 ioat_dma_free_chan_resources;
1626         device->common.dev = &pdev->dev;
1627
1628         dma_cap_set(DMA_MEMCPY, device->common.cap_mask);
1629         device->common.device_is_tx_complete = ioat_dma_is_complete;
1630         switch (device->version) {
1631         case IOAT_VER_1_2:
1632                 device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1633                 device->common.device_issue_pending =
1634                                                 ioat1_dma_memcpy_issue_pending;
1635                 break;
1636         case IOAT_VER_2_0:
1637         case IOAT_VER_3_0:
1638                 device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy;
1639                 device->common.device_issue_pending =
1640                                                 ioat2_dma_memcpy_issue_pending;
1641                 break;
1642         }
1643
1644         dev_err(&device->pdev->dev,
1645                 "Intel(R) I/OAT DMA Engine found,"
1646                 " %d channels, device version 0x%02x, driver version %s\n",
1647                 device->common.chancnt, device->version, IOAT_DMA_VERSION);
1648
1649         err = ioat_dma_setup_interrupts(device);
1650         if (err)
1651                 goto err_setup_interrupts;
1652
1653         err = ioat_dma_self_test(device);
1654         if (err)
1655                 goto err_self_test;
1656
1657         ioat_set_tcp_copy_break(device);
1658
1659         dma_async_device_register(&device->common);
1660
1661         if (device->version != IOAT_VER_3_0) {
1662                 INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog);
1663                 schedule_delayed_work(&device->work,
1664                                       WATCHDOG_DELAY);
1665         }
1666
1667         return device;
1668
1669 err_self_test:
1670         ioat_dma_remove_interrupts(device);
1671 err_setup_interrupts:
1672         pci_pool_destroy(device->completion_pool);
1673 err_completion_pool:
1674         pci_pool_destroy(device->dma_pool);
1675 err_dma_pool:
1676         kfree(device);
1677 err_kzalloc:
1678         dev_err(&pdev->dev,
1679                 "Intel(R) I/OAT DMA Engine initialization failed\n");
1680         return NULL;
1681 }
1682
1683 void ioat_dma_remove(struct ioatdma_device *device)
1684 {
1685         struct dma_chan *chan, *_chan;
1686         struct ioat_dma_chan *ioat_chan;
1687
1688         ioat_dma_remove_interrupts(device);
1689
1690         dma_async_device_unregister(&device->common);
1691
1692         pci_pool_destroy(device->dma_pool);
1693         pci_pool_destroy(device->completion_pool);
1694
1695         iounmap(device->reg_base);
1696         pci_release_regions(device->pdev);
1697         pci_disable_device(device->pdev);
1698
1699         if (device->version != IOAT_VER_3_0) {
1700                 cancel_delayed_work(&device->work);
1701         }
1702
1703         list_for_each_entry_safe(chan, _chan,
1704                                  &device->common.channels, device_node) {
1705                 ioat_chan = to_ioat_chan(chan);
1706                 list_del(&chan->device_node);
1707                 kfree(ioat_chan);
1708         }
1709         kfree(device);
1710 }
1711