drivers/dma/fsldma.c

   1 /*
   2  * Freescale MPC85xx, MPC83xx DMA Engine support
   3  *
   4  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author:
   7  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
   8  *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
   9  *
  10  * Description:
  11  *   DMA engine driver for Freescale MPC8540 DMA controller, which is
  12  *   also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
  13  *   The support for MPC8349 DMA contorller is also added.
  14  *
  15  * This is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dmaengine.h>
  27 #include <linux/delay.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/dmapool.h>
  30 #include <linux/of_platform.h>
  31
  32 #include "fsldma.h"
  33
  34 static void dma_init(struct fsl_dma_chan *fsl_chan)
  35 {
  36         /* Reset the channel */
  37         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32);
  38
  39         switch (fsl_chan->feature & FSL_DMA_IP_MASK) {
  40         case FSL_DMA_IP_85XX:
  41                 /* Set the channel to below modes:
  42                  * EIE - Error interrupt enable
  43                  * EOSIE - End of segments interrupt enable (basic mode)
  44                  * EOLNIE - End of links interrupt enable
  45                  */
  46                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE
  47                                 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
  48                 break;
  49         case FSL_DMA_IP_83XX:
  50                 /* Set the channel to below modes:
  51                  * EOTIE - End-of-transfer interrupt enable
  52                  */
  53                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE,
  54                                 32);
  55                 break;
  56         }
  57
  58 }
  59
  60 static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val)
  61 {
  62         DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32);
  63 }
  64
  65 static u32 get_sr(struct fsl_dma_chan *fsl_chan)
  66 {
  67         return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32);
  68 }
  69
  70 static void set_desc_cnt(struct fsl_dma_chan *fsl_chan,
  71                                 struct fsl_dma_ld_hw *hw, u32 count)
  72 {
  73         hw->count = CPU_TO_DMA(fsl_chan, count, 32);
  74 }
  75
  76 static void set_desc_src(struct fsl_dma_chan *fsl_chan,
  77                                 struct fsl_dma_ld_hw *hw, dma_addr_t src)
  78 {
  79         u64 snoop_bits;
  80
  81         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
  82                 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
  83         hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64);
  84 }
  85
  86 static void set_desc_dest(struct fsl_dma_chan *fsl_chan,
  87                                 struct fsl_dma_ld_hw *hw, dma_addr_t dest)
  88 {
  89         u64 snoop_bits;
  90
  91         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
  92                 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
  93         hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64);
  94 }
  95
  96 static void set_desc_next(struct fsl_dma_chan *fsl_chan,
  97                                 struct fsl_dma_ld_hw *hw, dma_addr_t next)
  98 {
  99         u64 snoop_bits;
 100
 101         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
 102                 ? FSL_DMA_SNEN : 0;
 103         hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64);
 104 }
 105
 106 static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
 107 {
 108         DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64);
 109 }
 110
 111 static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan)
 112 {
 113         return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN;
 114 }
 115
 116 static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
 117 {
 118         DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64);
 119 }
 120
 121 static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan)
 122 {
 123         return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64);
 124 }
 125
 126 static int dma_is_idle(struct fsl_dma_chan *fsl_chan)
 127 {
 128         u32 sr = get_sr(fsl_chan);
 129         return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
 130 }
 131
 132 static void dma_start(struct fsl_dma_chan *fsl_chan)
 133 {
 134         u32 mr_set = 0;;
 135
 136         if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
 137                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
 138                 mr_set |= FSL_DMA_MR_EMP_EN;
 139         } else
 140                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 141                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 142                                 & ~FSL_DMA_MR_EMP_EN, 32);
 143
 144         if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
 145                 mr_set |= FSL_DMA_MR_EMS_EN;
 146         else
 147                 mr_set |= FSL_DMA_MR_CS;
 148
 149         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 150                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 151                         | mr_set, 32);
 152 }
 153
 154 static void dma_halt(struct fsl_dma_chan *fsl_chan)
 155 {
 156         int i = 0;
 157         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 158                 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA,
 159                 32);
 160         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 161                 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS
 162                 | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32);
 163
 164         while (!dma_is_idle(fsl_chan) && (i++ < 100))
 165                 udelay(10);
 166         if (i >= 100 && !dma_is_idle(fsl_chan))
 167                 dev_err(fsl_chan->dev, "DMA halt timeout!\n");
 168 }
 169
 170 static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
 171                         struct fsl_desc_sw *desc)
 172 {
 173         desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
 174                 DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL,
 175                 64);
 176 }
 177
 178 static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
 179                 struct fsl_desc_sw *new_desc)
 180 {
 181         struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev);
 182
 183         if (list_empty(&fsl_chan->ld_queue))
 184                 return;
 185
 186         /* Link to the new descriptor physical address and
 187          * Enable End-of-segment interrupt for
 188          * the last link descriptor.
 189          * (the previous node's next link descriptor)
 190          *
 191          * For FSL_DMA_IP_83xx, the snoop enable bit need be set.
 192          */
 193         queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
 194                         new_desc->async_tx.phys | FSL_DMA_EOSIE |
 195                         (((fsl_chan->feature & FSL_DMA_IP_MASK)
 196                                 == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64);
 197 }
 198
 199 /**
 200  * fsl_chan_set_src_loop_size - Set source address hold transfer size
 201  * @fsl_chan : Freescale DMA channel
 202  * @size     : Address loop size, 0 for disable loop
 203  *
 204  * The set source address hold transfer size. The source
 205  * address hold or loop transfer size is when the DMA transfer
 206  * data from source address (SA), if the loop size is 4, the DMA will
 207  * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
 208  * SA + 1 ... and so on.
 209  */
 210 static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
 211 {
 212         switch (size) {
 213         case 0:
 214                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 215                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
 216                         (~FSL_DMA_MR_SAHE), 32);
 217                 break;
 218         case 1:
 219         case 2:
 220         case 4:
 221         case 8:
 222                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 223                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
 224                         FSL_DMA_MR_SAHE | (__ilog2(size) << 14),
 225                         32);
 226                 break;
 227         }
 228 }
 229
 230 /**
 231  * fsl_chan_set_dest_loop_size - Set destination address hold transfer size
 232  * @fsl_chan : Freescale DMA channel
 233  * @size     : Address loop size, 0 for disable loop
 234  *
 235  * The set destination address hold transfer size. The destination
 236  * address hold or loop transfer size is when the DMA transfer
 237  * data to destination address (TA), if the loop size is 4, the DMA will
 238  * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
 239  * TA + 1 ... and so on.
 240  */
 241 static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
 242 {
 243         switch (size) {
 244         case 0:
 245                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 246                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
 247                         (~FSL_DMA_MR_DAHE), 32);
 248                 break;
 249         case 1:
 250         case 2:
 251         case 4:
 252         case 8:
 253                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 254                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
 255                         FSL_DMA_MR_DAHE | (__ilog2(size) << 16),
 256                         32);
 257                 break;
 258         }
 259 }
 260
 261 /**
 262  * fsl_chan_toggle_ext_pause - Toggle channel external pause status
 263  * @fsl_chan : Freescale DMA channel
 264  * @size     : Pause control size, 0 for disable external pause control.
 265  *             The maximum is 1024.
 266  *
 267  * The Freescale DMA channel can be controlled by the external
 268  * signal DREQ#. The pause control size is how many bytes are allowed
 269  * to transfer before pausing the channel, after which a new assertion
 270  * of DREQ# resumes channel operation.
 271  */
 272 static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size)
 273 {
 274         if (size > 1024)
 275                 return;
 276
 277         if (size) {
 278                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 279                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 280                                 | ((__ilog2(size) << 24) & 0x0f000000),
 281                         32);
 282                 fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
 283         } else
 284                 fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
 285 }
 286
 287 /**
 288  * fsl_chan_toggle_ext_start - Toggle channel external start status
 289  * @fsl_chan : Freescale DMA channel
 290  * @enable   : 0 is disabled, 1 is enabled.
 291  *
 292  * If enable the external start, the channel can be started by an
 293  * external DMA start pin. So the dma_start() does not start the
 294  * transfer immediately. The DMA channel will wait for the
 295  * control pin asserted.
 296  */
 297 static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable)
 298 {
 299         if (enable)
 300                 fsl_chan->feature |= FSL_DMA_CHAN_START_EXT;
 301         else
 302                 fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT;
 303 }
 304
 305 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 306 {
 307         struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
 308         struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
 309         unsigned long flags;
 310         dma_cookie_t cookie;
 311
 312         /* cookie increment and adding to ld_queue must be atomic */
 313         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 314
 315         cookie = fsl_chan->common.cookie;
 316         cookie++;
 317         if (cookie < 0)
 318                 cookie = 1;
 319         desc->async_tx.cookie = cookie;
 320         fsl_chan->common.cookie = desc->async_tx.cookie;
 321
 322         append_ld_queue(fsl_chan, desc);
 323         list_splice_init(&desc->async_tx.tx_list, fsl_chan->ld_queue.prev);
 324
 325         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 326
 327         return cookie;
 328 }
 329
 330 /**
 331  * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
 332  * @fsl_chan : Freescale DMA channel
 333  *
 334  * Return - The descriptor allocated. NULL for failed.
 335  */
 336 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
 337                                         struct fsl_dma_chan *fsl_chan)
 338 {
 339         dma_addr_t pdesc;
 340         struct fsl_desc_sw *desc_sw;
 341
 342         desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc);
 343         if (desc_sw) {
 344                 memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
 345                 dma_async_tx_descriptor_init(&desc_sw->async_tx,
 346                                                 &fsl_chan->common);
 347                 desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
 348                 INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
 349                 desc_sw->async_tx.phys = pdesc;
 350         }
 351
 352         return desc_sw;
 353 }
 354
 355
 356 /**
 357  * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
 358  * @fsl_chan : Freescale DMA channel
 359  *
 360  * This function will create a dma pool for descriptor allocation.
 361  *
 362  * Return - The number of descriptors allocated.
 363  */
 364 static int fsl_dma_alloc_chan_resources(struct dma_chan *chan)
 365 {
 366         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 367         LIST_HEAD(tmp_list);
 368
 369         /* We need the descriptor to be aligned to 32bytes
 370          * for meeting FSL DMA specification requirement.
 371          */
 372         fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
 373                         fsl_chan->dev, sizeof(struct fsl_desc_sw),
 374                         32, 0);
 375         if (!fsl_chan->desc_pool) {
 376                 dev_err(fsl_chan->dev, "No memory for channel %d "
 377                         "descriptor dma pool.\n", fsl_chan->id);
 378                 return 0;
 379         }
 380
 381         return 1;
 382 }
 383
 384 /**
 385  * fsl_dma_free_chan_resources - Free all resources of the channel.
 386  * @fsl_chan : Freescale DMA channel
 387  */
 388 static void fsl_dma_free_chan_resources(struct dma_chan *chan)
 389 {
 390         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 391         struct fsl_desc_sw *desc, *_desc;
 392         unsigned long flags;
 393
 394         dev_dbg(fsl_chan->dev, "Free all channel resources.\n");
 395         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 396         list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
 397 #ifdef FSL_DMA_LD_DEBUG
 398                 dev_dbg(fsl_chan->dev,
 399                                 "LD %p will be released.\n", desc);
 400 #endif
 401                 list_del(&desc->node);
 402                 /* free link descriptor */
 403                 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
 404         }
 405         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 406         dma_pool_destroy(fsl_chan->desc_pool);
 407 }
 408
 409 static struct dma_async_tx_descriptor *
 410 fsl_dma_prep_interrupt(struct dma_chan *chan)
 411 {
 412         struct fsl_dma_chan *fsl_chan;
 413         struct fsl_desc_sw *new;
 414
 415         if (!chan)
 416                 return NULL;
 417
 418         fsl_chan = to_fsl_chan(chan);
 419
 420         new = fsl_dma_alloc_descriptor(fsl_chan);
 421         if (!new) {
 422                 dev_err(fsl_chan->dev, "No free memory for link descriptor\n");
 423                 return NULL;
 424         }
 425
 426         new->async_tx.cookie = -EBUSY;
 427         new->async_tx.ack = 0;
 428
 429         /* Set End-of-link to the last link descriptor of new list*/
 430         set_ld_eol(fsl_chan, new);
 431
 432         return &new->async_tx;
 433 }
 434
 435 static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
 436         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
 437         size_t len, unsigned long flags)
 438 {
 439         struct fsl_dma_chan *fsl_chan;
 440         struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
 441         size_t copy;
 442         LIST_HEAD(link_chain);
 443
 444         if (!chan)
 445                 return NULL;
 446
 447         if (!len)
 448                 return NULL;
 449
 450         fsl_chan = to_fsl_chan(chan);
 451
 452         do {
 453
 454                 /* Allocate the link descriptor from DMA pool */
 455                 new = fsl_dma_alloc_descriptor(fsl_chan);
 456                 if (!new) {
 457                         dev_err(fsl_chan->dev,
 458                                         "No free memory for link descriptor\n");
 459                         return NULL;
 460                 }
 461 #ifdef FSL_DMA_LD_DEBUG
 462                 dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
 463 #endif
 464
 465                 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
 466
 467                 set_desc_cnt(fsl_chan, &new->hw, copy);
 468                 set_desc_src(fsl_chan, &new->hw, dma_src);
 469                 set_desc_dest(fsl_chan, &new->hw, dma_dest);
 470
 471                 if (!first)
 472                         first = new;
 473                 else
 474                         set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys);
 475
 476                 new->async_tx.cookie = 0;
 477                 new->async_tx.ack = 1;
 478
 479                 prev = new;
 480                 len -= copy;
 481                 dma_src += copy;
 482                 dma_dest += copy;
 483
 484                 /* Insert the link descriptor to the LD ring */
 485                 list_add_tail(&new->node, &first->async_tx.tx_list);
 486         } while (len);
 487
 488         new->async_tx.ack = 0; /* client is in control of this ack */
 489         new->async_tx.cookie = -EBUSY;
 490
 491         /* Set End-of-link to the last link descriptor of new list*/
 492         set_ld_eol(fsl_chan, new);
 493
 494         return first ? &first->async_tx : NULL;
 495 }
 496
 497 /**
 498  * fsl_dma_update_completed_cookie - Update the completed cookie.
 499  * @fsl_chan : Freescale DMA channel
 500  */
 501 static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan)
 502 {
 503         struct fsl_desc_sw *cur_desc, *desc;
 504         dma_addr_t ld_phy;
 505
 506         ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK;
 507
 508         if (ld_phy) {
 509                 cur_desc = NULL;
 510                 list_for_each_entry(desc, &fsl_chan->ld_queue, node)
 511                         if (desc->async_tx.phys == ld_phy) {
 512                                 cur_desc = desc;
 513                                 break;
 514                         }
 515
 516                 if (cur_desc && cur_desc->async_tx.cookie) {
 517                         if (dma_is_idle(fsl_chan))
 518                                 fsl_chan->completed_cookie =
 519                                         cur_desc->async_tx.cookie;
 520                         else
 521                                 fsl_chan->completed_cookie =
 522                                         cur_desc->async_tx.cookie - 1;
 523                 }
 524         }
 525 }
 526
 527 /**
 528  * fsl_chan_ld_cleanup - Clean up link descriptors
 529  * @fsl_chan : Freescale DMA channel
 530  *
 531  * This function clean up the ld_queue of DMA channel.
 532  * If 'in_intr' is set, the function will move the link descriptor to
 533  * the recycle list. Otherwise, free it directly.
 534  */
 535 static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan)
 536 {
 537         struct fsl_desc_sw *desc, *_desc;
 538         unsigned long flags;
 539
 540         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 541
 542         fsl_dma_update_completed_cookie(fsl_chan);
 543         dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n",
 544                         fsl_chan->completed_cookie);
 545         list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
 546                 dma_async_tx_callback callback;
 547                 void *callback_param;
 548
 549                 if (dma_async_is_complete(desc->async_tx.cookie,
 550                             fsl_chan->completed_cookie, fsl_chan->common.cookie)
 551                                 == DMA_IN_PROGRESS)
 552                         break;
 553
 554                 callback = desc->async_tx.callback;
 555                 callback_param = desc->async_tx.callback_param;
 556
 557                 /* Remove from ld_queue list */
 558                 list_del(&desc->node);
 559
 560                 dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n",
 561                                 desc);
 562                 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
 563
 564                 /* Run the link descriptor callback function */
 565                 if (callback) {
 566                         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 567                         dev_dbg(fsl_chan->dev, "link descriptor %p callback\n",
 568                                         desc);
 569                         callback(callback_param);
 570                         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 571                 }
 572         }
 573         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 574 }
 575
 576 /**
 577  * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue.
 578  * @fsl_chan : Freescale DMA channel
 579  */
 580 static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
 581 {
 582         struct list_head *ld_node;
 583         dma_addr_t next_dest_addr;
 584         unsigned long flags;
 585
 586         if (!dma_is_idle(fsl_chan))
 587                 return;
 588
 589         dma_halt(fsl_chan);
 590
 591         /* If there are some link descriptors
 592          * not transfered in queue. We need to start it.
 593          */
 594         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 595
 596         /* Find the first un-transfer desciptor */
 597         for (ld_node = fsl_chan->ld_queue.next;
 598                 (ld_node != &fsl_chan->ld_queue)
 599                         && (dma_async_is_complete(
 600                                 to_fsl_desc(ld_node)->async_tx.cookie,
 601                                 fsl_chan->completed_cookie,
 602                                 fsl_chan->common.cookie) == DMA_SUCCESS);
 603                 ld_node = ld_node->next);
 604
 605         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 606
 607         if (ld_node != &fsl_chan->ld_queue) {
 608                 /* Get the ld start address from ld_queue */
 609                 next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
 610                 dev_dbg(fsl_chan->dev, "xfer LDs staring from %p\n",
 611                                 (void *)next_dest_addr);
 612                 set_cdar(fsl_chan, next_dest_addr);
 613                 dma_start(fsl_chan);
 614         } else {
 615                 set_cdar(fsl_chan, 0);
 616                 set_ndar(fsl_chan, 0);
 617         }
 618 }
 619
 620 /**
 621  * fsl_dma_memcpy_issue_pending - Issue the DMA start command
 622  * @fsl_chan : Freescale DMA channel
 623  */
 624 static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan)
 625 {
 626         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 627
 628 #ifdef FSL_DMA_LD_DEBUG
 629         struct fsl_desc_sw *ld;
 630         unsigned long flags;
 631
 632         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 633         if (list_empty(&fsl_chan->ld_queue)) {
 634                 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 635                 return;
 636         }
 637
 638         dev_dbg(fsl_chan->dev, "--memcpy issue--\n");
 639         list_for_each_entry(ld, &fsl_chan->ld_queue, node) {
 640                 int i;
 641                 dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n",
 642                                 fsl_chan->id, ld->async_tx.phys);
 643                 for (i = 0; i < 8; i++)
 644                         dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n",
 645                                         i, *(((u32 *)&ld->hw) + i));
 646         }
 647         dev_dbg(fsl_chan->dev, "----------------\n");
 648         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 649 #endif
 650
 651         fsl_chan_xfer_ld_queue(fsl_chan);
 652 }
 653
 654 static void fsl_dma_dependency_added(struct dma_chan *chan)
 655 {
 656         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 657
 658         fsl_chan_ld_cleanup(fsl_chan);
 659 }
 660
 661 /**
 662  * fsl_dma_is_complete - Determine the DMA status
 663  * @fsl_chan : Freescale DMA channel
 664  */
 665 static enum dma_status fsl_dma_is_complete(struct dma_chan *chan,
 666                                         dma_cookie_t cookie,
 667                                         dma_cookie_t *done,
 668                                         dma_cookie_t *used)
 669 {
 670         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 671         dma_cookie_t last_used;
 672         dma_cookie_t last_complete;
 673
 674         fsl_chan_ld_cleanup(fsl_chan);
 675
 676         last_used = chan->cookie;
 677         last_complete = fsl_chan->completed_cookie;
 678
 679         if (done)
 680                 *done = last_complete;
 681
 682         if (used)
 683                 *used = last_used;
 684
 685         return dma_async_is_complete(cookie, last_complete, last_used);
 686 }
 687
 688 static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
 689 {
 690         struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
 691         u32 stat;
 692
 693         stat = get_sr(fsl_chan);
 694         dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n",
 695                                                 fsl_chan->id, stat);
 696         set_sr(fsl_chan, stat);         /* Clear the event register */
 697
 698         stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
 699         if (!stat)
 700                 return IRQ_NONE;
 701
 702         if (stat & FSL_DMA_SR_TE)
 703                 dev_err(fsl_chan->dev, "Transfer Error!\n");
 704
 705         /* If the link descriptor segment transfer finishes,
 706          * we will recycle the used descriptor.
 707          */
 708         if (stat & FSL_DMA_SR_EOSI) {
 709                 dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
 710                 dev_dbg(fsl_chan->dev, "event: clndar %p, nlndar %p\n",
 711                         (void *)get_cdar(fsl_chan), (void *)get_ndar(fsl_chan));
 712                 stat &= ~FSL_DMA_SR_EOSI;
 713         }
 714
 715         /* If it current transfer is the end-of-transfer,
 716          * we should clear the Channel Start bit for
 717          * prepare next transfer.
 718          */
 719         if (stat & (FSL_DMA_SR_EOLNI | FSL_DMA_SR_EOCDI)) {
 720                 dev_dbg(fsl_chan->dev, "event: End-of-link INT\n");
 721                 stat &= ~FSL_DMA_SR_EOLNI;
 722                 fsl_chan_xfer_ld_queue(fsl_chan);
 723         }
 724
 725         if (stat)
 726                 dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n",
 727                                         stat);
 728
 729         dev_dbg(fsl_chan->dev, "event: Exit\n");
 730         tasklet_schedule(&fsl_chan->tasklet);
 731         return IRQ_HANDLED;
 732 }
 733
 734 static irqreturn_t fsl_dma_do_interrupt(int irq, void *data)
 735 {
 736         struct fsl_dma_device *fdev = (struct fsl_dma_device *)data;
 737         u32 gsr;
 738         int ch_nr;
 739
 740         gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base)
 741                         : in_le32(fdev->reg_base);
 742         ch_nr = (32 - ffs(gsr)) / 8;
 743
 744         return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq,
 745                         fdev->chan[ch_nr]) : IRQ_NONE;
 746 }
 747
 748 static void dma_do_tasklet(unsigned long data)
 749 {
 750         struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
 751         fsl_chan_ld_cleanup(fsl_chan);
 752 }
 753
 754 #ifdef FSL_DMA_CALLBACKTEST
 755 static void fsl_dma_callback_test(struct fsl_dma_chan *fsl_chan)
 756 {
 757         if (fsl_chan)
 758                 dev_info(fsl_chan->dev, "selftest: callback is ok!\n");
 759 }
 760 #endif
 761
 762 #ifdef CONFIG_FSL_DMA_SELFTEST
 763 static int fsl_dma_self_test(struct fsl_dma_chan *fsl_chan)
 764 {
 765         struct dma_chan *chan;
 766         int err = 0;
 767         dma_addr_t dma_dest, dma_src;
 768         dma_cookie_t cookie;
 769         u8 *src, *dest;
 770         int i;
 771         size_t test_size;
 772         struct dma_async_tx_descriptor *tx1, *tx2, *tx3;
 773
 774         test_size = 4096;
 775
 776         src = kmalloc(test_size * 2, GFP_KERNEL);
 777         if (!src) {
 778                 dev_err(fsl_chan->dev,
 779                                 "selftest: Cannot alloc memory for test!\n");
 780                 err = -ENOMEM;
 781                 goto out;
 782         }
 783
 784         dest = src + test_size;
 785
 786         for (i = 0; i < test_size; i++)
 787                 src[i] = (u8) i;
 788
 789         chan = &fsl_chan->common;
 790
 791         if (fsl_dma_alloc_chan_resources(chan) < 1) {
 792                 dev_err(fsl_chan->dev,
 793                                 "selftest: Cannot alloc resources for DMA\n");
 794                 err = -ENODEV;
 795                 goto out;
 796         }
 797
 798         /* TX 1 */
 799         dma_src = dma_map_single(fsl_chan->dev, src, test_size / 2,
 800                                  DMA_TO_DEVICE);
 801         dma_dest = dma_map_single(fsl_chan->dev, dest, test_size / 2,
 802                                   DMA_FROM_DEVICE);
 803         tx1 = fsl_dma_prep_memcpy(chan, dma_dest, dma_src, test_size / 2, 0);
 804         async_tx_ack(tx1);
 805
 806         cookie = fsl_dma_tx_submit(tx1);
 807         fsl_dma_memcpy_issue_pending(chan);
 808         msleep(2);
 809
 810         if (fsl_dma_is_complete(chan, cookie, NULL, NULL) != DMA_SUCCESS) {
 811                 dev_err(fsl_chan->dev, "selftest: Time out!\n");
 812                 err = -ENODEV;
 813                 goto out;
 814         }
 815
 816         /* Test free and re-alloc channel resources */
 817         fsl_dma_free_chan_resources(chan);
 818
 819         if (fsl_dma_alloc_chan_resources(chan) < 1) {
 820                 dev_err(fsl_chan->dev,
 821                                 "selftest: Cannot alloc resources for DMA\n");
 822                 err = -ENODEV;
 823                 goto free_resources;
 824         }
 825
 826         /* Continue to test
 827          * TX 2
 828          */
 829         dma_src = dma_map_single(fsl_chan->dev, src + test_size / 2,
 830                                         test_size / 4, DMA_TO_DEVICE);
 831         dma_dest = dma_map_single(fsl_chan->dev, dest + test_size / 2,
 832                                         test_size / 4, DMA_FROM_DEVICE);
 833         tx2 = fsl_dma_prep_memcpy(chan, dma_dest, dma_src, test_size / 4, 0);
 834         async_tx_ack(tx2);
 835
 836         /* TX 3 */
 837         dma_src = dma_map_single(fsl_chan->dev, src + test_size * 3 / 4,
 838                                         test_size / 4, DMA_TO_DEVICE);
 839         dma_dest = dma_map_single(fsl_chan->dev, dest + test_size * 3 / 4,
 840                                         test_size / 4, DMA_FROM_DEVICE);
 841         tx3 = fsl_dma_prep_memcpy(chan, dma_dest, dma_src, test_size / 4, 0);
 842         async_tx_ack(tx3);
 843
 844         /* Test exchanging the prepared tx sort */
 845         cookie = fsl_dma_tx_submit(tx3);
 846         cookie = fsl_dma_tx_submit(tx2);
 847
 848 #ifdef FSL_DMA_CALLBACKTEST
 849         if (dma_has_cap(DMA_INTERRUPT, ((struct fsl_dma_device *)
 850             dev_get_drvdata(fsl_chan->dev->parent))->common.cap_mask)) {
 851                 tx3->callback = fsl_dma_callback_test;
 852                 tx3->callback_param = fsl_chan;
 853         }
 854 #endif
 855         fsl_dma_memcpy_issue_pending(chan);
 856         msleep(2);
 857
 858         if (fsl_dma_is_complete(chan, cookie, NULL, NULL) != DMA_SUCCESS) {
 859                 dev_err(fsl_chan->dev, "selftest: Time out!\n");
 860                 err = -ENODEV;
 861                 goto free_resources;
 862         }
 863
 864         err = memcmp(src, dest, test_size);
 865         if (err) {
 866                 for (i = 0; (*(src + i) == *(dest + i)) && (i < test_size);
 867                                 i++);
 868                 dev_err(fsl_chan->dev, "selftest: Test failed, data %d/%ld is "
 869                                 "error! src 0x%x, dest 0x%x\n",
 870                                 i, (long)test_size, *(src + i), *(dest + i));
 871         }
 872
 873 free_resources:
 874         fsl_dma_free_chan_resources(chan);
 875 out:
 876         kfree(src);
 877         return err;
 878 }
 879 #endif
 880
 881 static int __devinit of_fsl_dma_chan_probe(struct of_device *dev,
 882                         const struct of_device_id *match)
 883 {
 884         struct fsl_dma_device *fdev;
 885         struct fsl_dma_chan *new_fsl_chan;
 886         int err;
 887
 888         fdev = dev_get_drvdata(dev->dev.parent);
 889         BUG_ON(!fdev);
 890
 891         /* alloc channel */
 892         new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL);
 893         if (!new_fsl_chan) {
 894                 dev_err(&dev->dev, "No free memory for allocating "
 895                                 "dma channels!\n");
 896                 err = -ENOMEM;
 897                 goto err;
 898         }
 899
 900         /* get dma channel register base */
 901         err = of_address_to_resource(dev->node, 0, &new_fsl_chan->reg);
 902         if (err) {
 903                 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
 904                                 dev->node->full_name);
 905                 goto err;
 906         }
 907
 908         new_fsl_chan->feature = *(u32 *)match->data;
 909
 910         if (!fdev->feature)
 911                 fdev->feature = new_fsl_chan->feature;
 912
 913         /* If the DMA device's feature is different than its channels',
 914          * report the bug.
 915          */
 916         WARN_ON(fdev->feature != new_fsl_chan->feature);
 917
 918         new_fsl_chan->dev = &dev->dev;
 919         new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start,
 920                         new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
 921
 922         new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
 923         if (new_fsl_chan->id > FSL_DMA_MAX_CHANS_PER_DEVICE) {
 924                 dev_err(&dev->dev, "There is no %d channel!\n",
 925                                 new_fsl_chan->id);
 926                 err = -EINVAL;
 927                 goto err;
 928         }
 929         fdev->chan[new_fsl_chan->id] = new_fsl_chan;
 930         tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet,
 931                         (unsigned long)new_fsl_chan);
 932
 933         /* Init the channel */
 934         dma_init(new_fsl_chan);
 935
 936         /* Clear cdar registers */
 937         set_cdar(new_fsl_chan, 0);
 938
 939         switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) {
 940         case FSL_DMA_IP_85XX:
 941                 new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start;
 942                 new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
 943         case FSL_DMA_IP_83XX:
 944                 new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size;
 945                 new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size;
 946         }
 947
 948         spin_lock_init(&new_fsl_chan->desc_lock);
 949         INIT_LIST_HEAD(&new_fsl_chan->ld_queue);
 950
 951         new_fsl_chan->common.device = &fdev->common;
 952
 953         /* Add the channel to DMA device channel list */
 954         list_add_tail(&new_fsl_chan->common.device_node,
 955                         &fdev->common.channels);
 956         fdev->common.chancnt++;
 957
 958         new_fsl_chan->irq = irq_of_parse_and_map(dev->node, 0);
 959         if (new_fsl_chan->irq != NO_IRQ) {
 960                 err = request_irq(new_fsl_chan->irq,
 961                                         &fsl_dma_chan_do_interrupt, IRQF_SHARED,
 962                                         "fsldma-channel", new_fsl_chan);
 963                 if (err) {
 964                         dev_err(&dev->dev, "DMA channel %s request_irq error "
 965                                 "with return %d\n", dev->node->full_name, err);
 966                         goto err;
 967                 }
 968         }
 969
 970 #ifdef CONFIG_FSL_DMA_SELFTEST
 971         err = fsl_dma_self_test(new_fsl_chan);
 972         if (err)
 973                 goto err;
 974 #endif
 975
 976         dev_info(&dev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id,
 977                                 match->compatible, new_fsl_chan->irq);
 978
 979         return 0;
 980 err:
 981         dma_halt(new_fsl_chan);
 982         iounmap(new_fsl_chan->reg_base);
 983         free_irq(new_fsl_chan->irq, new_fsl_chan);
 984         list_del(&new_fsl_chan->common.device_node);
 985         kfree(new_fsl_chan);
 986         return err;
 987 }
 988
 989 const u32 mpc8540_dma_ip_feature = FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN;
 990 const u32 mpc8349_dma_ip_feature = FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN;
 991
 992 static struct of_device_id of_fsl_dma_chan_ids[] = {
 993         {
 994                 .compatible = "fsl,mpc8540-dma-channel",
 995                 .data = (void *)&mpc8540_dma_ip_feature,
 996         },
 997         {
 998                 .compatible = "fsl,mpc8349-dma-channel",
 999                 .data = (void *)&mpc8349_dma_ip_feature,
1000         },
1001         {}
1002 };
1003
1004 static struct of_platform_driver of_fsl_dma_chan_driver = {
1005         .name = "of-fsl-dma-channel",
1006         .match_table = of_fsl_dma_chan_ids,
1007         .probe = of_fsl_dma_chan_probe,
1008 };
1009
1010 static __init int of_fsl_dma_chan_init(void)
1011 {
1012         return of_register_platform_driver(&of_fsl_dma_chan_driver);
1013 }
1014
1015 static int __devinit of_fsl_dma_probe(struct of_device *dev,
1016                         const struct of_device_id *match)
1017 {
1018         int err;
1019         unsigned int irq;
1020         struct fsl_dma_device *fdev;
1021
1022         fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL);
1023         if (!fdev) {
1024                 dev_err(&dev->dev, "No enough memory for 'priv'\n");
1025                 err = -ENOMEM;
1026                 goto err;
1027         }
1028         fdev->dev = &dev->dev;
1029         INIT_LIST_HEAD(&fdev->common.channels);
1030
1031         /* get DMA controller register base */
1032         err = of_address_to_resource(dev->node, 0, &fdev->reg);
1033         if (err) {
1034                 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1035                                 dev->node->full_name);
1036                 goto err;
1037         }
1038
1039         dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
1040                         "controller at %p...\n",
1041                         match->compatible, (void *)fdev->reg.start);
1042         fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
1043                                                 - fdev->reg.start + 1);
1044
1045         dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1046         dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
1047         fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1048         fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
1049         fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
1050         fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1051         fdev->common.device_is_tx_complete = fsl_dma_is_complete;
1052         fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
1053         fdev->common.device_dependency_added = fsl_dma_dependency_added;
1054         fdev->common.dev = &dev->dev;
1055
1056         irq = irq_of_parse_and_map(dev->node, 0);
1057         if (irq != NO_IRQ) {
1058                 err = request_irq(irq, &fsl_dma_do_interrupt, IRQF_SHARED,
1059                                         "fsldma-device", fdev);
1060                 if (err) {
1061                         dev_err(&dev->dev, "DMA device request_irq error "
1062                                 "with return %d\n", err);
1063                         goto err;
1064                 }
1065         }
1066
1067         dev_set_drvdata(&(dev->dev), fdev);
1068         of_platform_bus_probe(dev->node, of_fsl_dma_chan_ids, &dev->dev);
1069
1070         dma_async_device_register(&fdev->common);
1071         return 0;
1072
1073 err:
1074         iounmap(fdev->reg_base);
1075         kfree(fdev);
1076         return err;
1077 }
1078
1079 static struct of_device_id of_fsl_dma_ids[] = {
1080         { .compatible = "fsl,mpc8540-dma", },
1081         { .compatible = "fsl,mpc8349-dma", },
1082         {}
1083 };
1084
1085 static struct of_platform_driver of_fsl_dma_driver = {
1086         .name = "of-fsl-dma",
1087         .match_table = of_fsl_dma_ids,
1088         .probe = of_fsl_dma_probe,
1089 };
1090
1091 static __init int of_fsl_dma_init(void)
1092 {
1093         return of_register_platform_driver(&of_fsl_dma_driver);
1094 }
1095
1096 subsys_initcall(of_fsl_dma_chan_init);
1097 subsys_initcall(of_fsl_dma_init);