drivers/dma/fsldma.c

   1 /*
   2  * Freescale MPC85xx, MPC83xx DMA Engine support
   3  *
   4  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author:
   7  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
   8  *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
   9  *
  10  * Description:
  11  *   DMA engine driver for Freescale MPC8540 DMA controller, which is
  12  *   also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
  13  *   The support for MPC8349 DMA contorller is also added.
  14  *
  15  * This is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dmaengine.h>
  27 #include <linux/delay.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/dmapool.h>
  30 #include <linux/of_platform.h>
  31
  32 #include "fsldma.h"
  33
  34 static void dma_init(struct fsl_dma_chan *fsl_chan)
  35 {
  36         /* Reset the channel */
  37         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32);
  38
  39         switch (fsl_chan->feature & FSL_DMA_IP_MASK) {
  40         case FSL_DMA_IP_85XX:
  41                 /* Set the channel to below modes:
  42                  * EIE - Error interrupt enable
  43                  * EOSIE - End of segments interrupt enable (basic mode)
  44                  * EOLNIE - End of links interrupt enable
  45                  */
  46                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE
  47                                 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
  48                 break;
  49         case FSL_DMA_IP_83XX:
  50                 /* Set the channel to below modes:
  51                  * EOTIE - End-of-transfer interrupt enable
  52                  */
  53                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE,
  54                                 32);
  55                 break;
  56         }
  57
  58 }
  59
  60 static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val)
  61 {
  62         DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32);
  63 }
  64
  65 static u32 get_sr(struct fsl_dma_chan *fsl_chan)
  66 {
  67         return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32);
  68 }
  69
  70 static void set_desc_cnt(struct fsl_dma_chan *fsl_chan,
  71                                 struct fsl_dma_ld_hw *hw, u32 count)
  72 {
  73         hw->count = CPU_TO_DMA(fsl_chan, count, 32);
  74 }
  75
  76 static void set_desc_src(struct fsl_dma_chan *fsl_chan,
  77                                 struct fsl_dma_ld_hw *hw, dma_addr_t src)
  78 {
  79         u64 snoop_bits;
  80
  81         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
  82                 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
  83         hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64);
  84 }
  85
  86 static void set_desc_dest(struct fsl_dma_chan *fsl_chan,
  87                                 struct fsl_dma_ld_hw *hw, dma_addr_t dest)
  88 {
  89         u64 snoop_bits;
  90
  91         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
  92                 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
  93         hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64);
  94 }
  95
  96 static void set_desc_next(struct fsl_dma_chan *fsl_chan,
  97                                 struct fsl_dma_ld_hw *hw, dma_addr_t next)
  98 {
  99         u64 snoop_bits;
 100
 101         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
 102                 ? FSL_DMA_SNEN : 0;
 103         hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64);
 104 }
 105
 106 static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
 107 {
 108         DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64);
 109 }
 110
 111 static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan)
 112 {
 113         return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN;
 114 }
 115
 116 static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
 117 {
 118         DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64);
 119 }
 120
 121 static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan)
 122 {
 123         return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64);
 124 }
 125
 126 static u32 get_bcr(struct fsl_dma_chan *fsl_chan)
 127 {
 128         return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32);
 129 }
 130
 131 static int dma_is_idle(struct fsl_dma_chan *fsl_chan)
 132 {
 133         u32 sr = get_sr(fsl_chan);
 134         return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
 135 }
 136
 137 static void dma_start(struct fsl_dma_chan *fsl_chan)
 138 {
 139         u32 mr_set = 0;;
 140
 141         if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
 142                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
 143                 mr_set |= FSL_DMA_MR_EMP_EN;
 144         } else
 145                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 146                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 147                                 & ~FSL_DMA_MR_EMP_EN, 32);
 148
 149         if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
 150                 mr_set |= FSL_DMA_MR_EMS_EN;
 151         else
 152                 mr_set |= FSL_DMA_MR_CS;
 153
 154         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 155                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 156                         | mr_set, 32);
 157 }
 158
 159 static void dma_halt(struct fsl_dma_chan *fsl_chan)
 160 {
 161         int i;
 162
 163         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 164                 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA,
 165                 32);
 166         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 167                 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS
 168                 | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32);
 169
 170         for (i = 0; i < 100; i++) {
 171                 if (dma_is_idle(fsl_chan))
 172                         break;
 173                 udelay(10);
 174         }
 175         if (i >= 100 && !dma_is_idle(fsl_chan))
 176                 dev_err(fsl_chan->dev, "DMA halt timeout!\n");
 177 }
 178
 179 static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
 180                         struct fsl_desc_sw *desc)
 181 {
 182         desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
 183                 DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL,
 184                 64);
 185 }
 186
 187 static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
 188                 struct fsl_desc_sw *new_desc)
 189 {
 190         struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev);
 191
 192         if (list_empty(&fsl_chan->ld_queue))
 193                 return;
 194
 195         /* Link to the new descriptor physical address and
 196          * Enable End-of-segment interrupt for
 197          * the last link descriptor.
 198          * (the previous node's next link descriptor)
 199          *
 200          * For FSL_DMA_IP_83xx, the snoop enable bit need be set.
 201          */
 202         queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
 203                         new_desc->async_tx.phys | FSL_DMA_EOSIE |
 204                         (((fsl_chan->feature & FSL_DMA_IP_MASK)
 205                                 == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64);
 206 }
 207
 208 /**
 209  * fsl_chan_set_src_loop_size - Set source address hold transfer size
 210  * @fsl_chan : Freescale DMA channel
 211  * @size     : Address loop size, 0 for disable loop
 212  *
 213  * The set source address hold transfer size. The source
 214  * address hold or loop transfer size is when the DMA transfer
 215  * data from source address (SA), if the loop size is 4, the DMA will
 216  * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
 217  * SA + 1 ... and so on.
 218  */
 219 static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
 220 {
 221         switch (size) {
 222         case 0:
 223                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 224                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
 225                         (~FSL_DMA_MR_SAHE), 32);
 226                 break;
 227         case 1:
 228         case 2:
 229         case 4:
 230         case 8:
 231                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 232                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
 233                         FSL_DMA_MR_SAHE | (__ilog2(size) << 14),
 234                         32);
 235                 break;
 236         }
 237 }
 238
 239 /**
 240  * fsl_chan_set_dest_loop_size - Set destination address hold transfer size
 241  * @fsl_chan : Freescale DMA channel
 242  * @size     : Address loop size, 0 for disable loop
 243  *
 244  * The set destination address hold transfer size. The destination
 245  * address hold or loop transfer size is when the DMA transfer
 246  * data to destination address (TA), if the loop size is 4, the DMA will
 247  * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
 248  * TA + 1 ... and so on.
 249  */
 250 static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
 251 {
 252         switch (size) {
 253         case 0:
 254                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 255                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
 256                         (~FSL_DMA_MR_DAHE), 32);
 257                 break;
 258         case 1:
 259         case 2:
 260         case 4:
 261         case 8:
 262                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 263                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
 264                         FSL_DMA_MR_DAHE | (__ilog2(size) << 16),
 265                         32);
 266                 break;
 267         }
 268 }
 269
 270 /**
 271  * fsl_chan_toggle_ext_pause - Toggle channel external pause status
 272  * @fsl_chan : Freescale DMA channel
 273  * @size     : Pause control size, 0 for disable external pause control.
 274  *             The maximum is 1024.
 275  *
 276  * The Freescale DMA channel can be controlled by the external
 277  * signal DREQ#. The pause control size is how many bytes are allowed
 278  * to transfer before pausing the channel, after which a new assertion
 279  * of DREQ# resumes channel operation.
 280  */
 281 static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size)
 282 {
 283         if (size > 1024)
 284                 return;
 285
 286         if (size) {
 287                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 288                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 289                                 | ((__ilog2(size) << 24) & 0x0f000000),
 290                         32);
 291                 fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
 292         } else
 293                 fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
 294 }
 295
 296 /**
 297  * fsl_chan_toggle_ext_start - Toggle channel external start status
 298  * @fsl_chan : Freescale DMA channel
 299  * @enable   : 0 is disabled, 1 is enabled.
 300  *
 301  * If enable the external start, the channel can be started by an
 302  * external DMA start pin. So the dma_start() does not start the
 303  * transfer immediately. The DMA channel will wait for the
 304  * control pin asserted.
 305  */
 306 static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable)
 307 {
 308         if (enable)
 309                 fsl_chan->feature |= FSL_DMA_CHAN_START_EXT;
 310         else
 311                 fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT;
 312 }
 313
 314 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 315 {
 316         struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
 317         struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
 318         unsigned long flags;
 319         dma_cookie_t cookie;
 320
 321         /* cookie increment and adding to ld_queue must be atomic */
 322         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 323
 324         cookie = fsl_chan->common.cookie;
 325         cookie++;
 326         if (cookie < 0)
 327                 cookie = 1;
 328         desc->async_tx.cookie = cookie;
 329         fsl_chan->common.cookie = desc->async_tx.cookie;
 330
 331         append_ld_queue(fsl_chan, desc);
 332         list_splice_init(&desc->async_tx.tx_list, fsl_chan->ld_queue.prev);
 333
 334         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 335
 336         return cookie;
 337 }
 338
 339 /**
 340  * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
 341  * @fsl_chan : Freescale DMA channel
 342  *
 343  * Return - The descriptor allocated. NULL for failed.
 344  */
 345 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
 346                                         struct fsl_dma_chan *fsl_chan)
 347 {
 348         dma_addr_t pdesc;
 349         struct fsl_desc_sw *desc_sw;
 350
 351         desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc);
 352         if (desc_sw) {
 353                 memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
 354                 dma_async_tx_descriptor_init(&desc_sw->async_tx,
 355                                                 &fsl_chan->common);
 356                 desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
 357                 INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
 358                 desc_sw->async_tx.phys = pdesc;
 359         }
 360
 361         return desc_sw;
 362 }
 363
 364
 365 /**
 366  * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
 367  * @fsl_chan : Freescale DMA channel
 368  *
 369  * This function will create a dma pool for descriptor allocation.
 370  *
 371  * Return - The number of descriptors allocated.
 372  */
 373 static int fsl_dma_alloc_chan_resources(struct dma_chan *chan)
 374 {
 375         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 376
 377         /* Has this channel already been allocated? */
 378         if (fsl_chan->desc_pool)
 379                 return 1;
 380
 381         /* We need the descriptor to be aligned to 32bytes
 382          * for meeting FSL DMA specification requirement.
 383          */
 384         fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
 385                         fsl_chan->dev, sizeof(struct fsl_desc_sw),
 386                         32, 0);
 387         if (!fsl_chan->desc_pool) {
 388                 dev_err(fsl_chan->dev, "No memory for channel %d "
 389                         "descriptor dma pool.\n", fsl_chan->id);
 390                 return 0;
 391         }
 392
 393         return 1;
 394 }
 395
 396 /**
 397  * fsl_dma_free_chan_resources - Free all resources of the channel.
 398  * @fsl_chan : Freescale DMA channel
 399  */
 400 static void fsl_dma_free_chan_resources(struct dma_chan *chan)
 401 {
 402         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 403         struct fsl_desc_sw *desc, *_desc;
 404         unsigned long flags;
 405
 406         dev_dbg(fsl_chan->dev, "Free all channel resources.\n");
 407         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 408         list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
 409 #ifdef FSL_DMA_LD_DEBUG
 410                 dev_dbg(fsl_chan->dev,
 411                                 "LD %p will be released.\n", desc);
 412 #endif
 413                 list_del(&desc->node);
 414                 /* free link descriptor */
 415                 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
 416         }
 417         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 418         dma_pool_destroy(fsl_chan->desc_pool);
 419
 420         fsl_chan->desc_pool = NULL;
 421 }
 422
 423 static struct dma_async_tx_descriptor *
 424 fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
 425 {
 426         struct fsl_dma_chan *fsl_chan;
 427         struct fsl_desc_sw *new;
 428
 429         if (!chan)
 430                 return NULL;
 431
 432         fsl_chan = to_fsl_chan(chan);
 433
 434         new = fsl_dma_alloc_descriptor(fsl_chan);
 435         if (!new) {
 436                 dev_err(fsl_chan->dev, "No free memory for link descriptor\n");
 437                 return NULL;
 438         }
 439
 440         new->async_tx.cookie = -EBUSY;
 441         new->async_tx.flags = flags;
 442
 443         /* Insert the link descriptor to the LD ring */
 444         list_add_tail(&new->node, &new->async_tx.tx_list);
 445
 446         /* Set End-of-link to the last link descriptor of new list*/
 447         set_ld_eol(fsl_chan, new);
 448
 449         return &new->async_tx;
 450 }
 451
 452 static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
 453         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
 454         size_t len, unsigned long flags)
 455 {
 456         struct fsl_dma_chan *fsl_chan;
 457         struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
 458         size_t copy;
 459         LIST_HEAD(link_chain);
 460
 461         if (!chan)
 462                 return NULL;
 463
 464         if (!len)
 465                 return NULL;
 466
 467         fsl_chan = to_fsl_chan(chan);
 468
 469         do {
 470
 471                 /* Allocate the link descriptor from DMA pool */
 472                 new = fsl_dma_alloc_descriptor(fsl_chan);
 473                 if (!new) {
 474                         dev_err(fsl_chan->dev,
 475                                         "No free memory for link descriptor\n");
 476                         return NULL;
 477                 }
 478 #ifdef FSL_DMA_LD_DEBUG
 479                 dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
 480 #endif
 481
 482                 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
 483
 484                 set_desc_cnt(fsl_chan, &new->hw, copy);
 485                 set_desc_src(fsl_chan, &new->hw, dma_src);
 486                 set_desc_dest(fsl_chan, &new->hw, dma_dest);
 487
 488                 if (!first)
 489                         first = new;
 490                 else
 491                         set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys);
 492
 493                 new->async_tx.cookie = 0;
 494                 async_tx_ack(&new->async_tx);
 495
 496                 prev = new;
 497                 len -= copy;
 498                 dma_src += copy;
 499                 dma_dest += copy;
 500
 501                 /* Insert the link descriptor to the LD ring */
 502                 list_add_tail(&new->node, &first->async_tx.tx_list);
 503         } while (len);
 504
 505         new->async_tx.flags = flags; /* client is in control of this ack */
 506         new->async_tx.cookie = -EBUSY;
 507
 508         /* Set End-of-link to the last link descriptor of new list*/
 509         set_ld_eol(fsl_chan, new);
 510
 511         return first ? &first->async_tx : NULL;
 512 }
 513
 514 /**
 515  * fsl_dma_update_completed_cookie - Update the completed cookie.
 516  * @fsl_chan : Freescale DMA channel
 517  */
 518 static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan)
 519 {
 520         struct fsl_desc_sw *cur_desc, *desc;
 521         dma_addr_t ld_phy;
 522
 523         ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK;
 524
 525         if (ld_phy) {
 526                 cur_desc = NULL;
 527                 list_for_each_entry(desc, &fsl_chan->ld_queue, node)
 528                         if (desc->async_tx.phys == ld_phy) {
 529                                 cur_desc = desc;
 530                                 break;
 531                         }
 532
 533                 if (cur_desc && cur_desc->async_tx.cookie) {
 534                         if (dma_is_idle(fsl_chan))
 535                                 fsl_chan->completed_cookie =
 536                                         cur_desc->async_tx.cookie;
 537                         else
 538                                 fsl_chan->completed_cookie =
 539                                         cur_desc->async_tx.cookie - 1;
 540                 }
 541         }
 542 }
 543
 544 /**
 545  * fsl_chan_ld_cleanup - Clean up link descriptors
 546  * @fsl_chan : Freescale DMA channel
 547  *
 548  * This function clean up the ld_queue of DMA channel.
 549  * If 'in_intr' is set, the function will move the link descriptor to
 550  * the recycle list. Otherwise, free it directly.
 551  */
 552 static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan)
 553 {
 554         struct fsl_desc_sw *desc, *_desc;
 555         unsigned long flags;
 556
 557         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 558
 559         dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n",
 560                         fsl_chan->completed_cookie);
 561         list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
 562                 dma_async_tx_callback callback;
 563                 void *callback_param;
 564
 565                 if (dma_async_is_complete(desc->async_tx.cookie,
 566                             fsl_chan->completed_cookie, fsl_chan->common.cookie)
 567                                 == DMA_IN_PROGRESS)
 568                         break;
 569
 570                 callback = desc->async_tx.callback;
 571                 callback_param = desc->async_tx.callback_param;
 572
 573                 /* Remove from ld_queue list */
 574                 list_del(&desc->node);
 575
 576                 dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n",
 577                                 desc);
 578                 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
 579
 580                 /* Run the link descriptor callback function */
 581                 if (callback) {
 582                         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 583                         dev_dbg(fsl_chan->dev, "link descriptor %p callback\n",
 584                                         desc);
 585                         callback(callback_param);
 586                         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 587                 }
 588         }
 589         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 590 }
 591
 592 /**
 593  * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue.
 594  * @fsl_chan : Freescale DMA channel
 595  */
 596 static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
 597 {
 598         struct list_head *ld_node;
 599         dma_addr_t next_dest_addr;
 600         unsigned long flags;
 601
 602         if (!dma_is_idle(fsl_chan))
 603                 return;
 604
 605         dma_halt(fsl_chan);
 606
 607         /* If there are some link descriptors
 608          * not transfered in queue. We need to start it.
 609          */
 610         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 611
 612         /* Find the first un-transfer desciptor */
 613         for (ld_node = fsl_chan->ld_queue.next;
 614                 (ld_node != &fsl_chan->ld_queue)
 615                         && (dma_async_is_complete(
 616                                 to_fsl_desc(ld_node)->async_tx.cookie,
 617                                 fsl_chan->completed_cookie,
 618                                 fsl_chan->common.cookie) == DMA_SUCCESS);
 619                 ld_node = ld_node->next);
 620
 621         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 622
 623         if (ld_node != &fsl_chan->ld_queue) {
 624                 /* Get the ld start address from ld_queue */
 625                 next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
 626                 dev_dbg(fsl_chan->dev, "xfer LDs staring from %p\n",
 627                                 (void *)next_dest_addr);
 628                 set_cdar(fsl_chan, next_dest_addr);
 629                 dma_start(fsl_chan);
 630         } else {
 631                 set_cdar(fsl_chan, 0);
 632                 set_ndar(fsl_chan, 0);
 633         }
 634 }
 635
 636 /**
 637  * fsl_dma_memcpy_issue_pending - Issue the DMA start command
 638  * @fsl_chan : Freescale DMA channel
 639  */
 640 static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan)
 641 {
 642         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 643
 644 #ifdef FSL_DMA_LD_DEBUG
 645         struct fsl_desc_sw *ld;
 646         unsigned long flags;
 647
 648         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 649         if (list_empty(&fsl_chan->ld_queue)) {
 650                 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 651                 return;
 652         }
 653
 654         dev_dbg(fsl_chan->dev, "--memcpy issue--\n");
 655         list_for_each_entry(ld, &fsl_chan->ld_queue, node) {
 656                 int i;
 657                 dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n",
 658                                 fsl_chan->id, ld->async_tx.phys);
 659                 for (i = 0; i < 8; i++)
 660                         dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n",
 661                                         i, *(((u32 *)&ld->hw) + i));
 662         }
 663         dev_dbg(fsl_chan->dev, "----------------\n");
 664         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 665 #endif
 666
 667         fsl_chan_xfer_ld_queue(fsl_chan);
 668 }
 669
 670 /**
 671  * fsl_dma_is_complete - Determine the DMA status
 672  * @fsl_chan : Freescale DMA channel
 673  */
 674 static enum dma_status fsl_dma_is_complete(struct dma_chan *chan,
 675                                         dma_cookie_t cookie,
 676                                         dma_cookie_t *done,
 677                                         dma_cookie_t *used)
 678 {
 679         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 680         dma_cookie_t last_used;
 681         dma_cookie_t last_complete;
 682
 683         fsl_chan_ld_cleanup(fsl_chan);
 684
 685         last_used = chan->cookie;
 686         last_complete = fsl_chan->completed_cookie;
 687
 688         if (done)
 689                 *done = last_complete;
 690
 691         if (used)
 692                 *used = last_used;
 693
 694         return dma_async_is_complete(cookie, last_complete, last_used);
 695 }
 696
 697 static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
 698 {
 699         struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
 700         u32 stat;
 701         int update_cookie = 0;
 702         int xfer_ld_q = 0;
 703
 704         stat = get_sr(fsl_chan);
 705         dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n",
 706                                                 fsl_chan->id, stat);
 707         set_sr(fsl_chan, stat);         /* Clear the event register */
 708
 709         stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
 710         if (!stat)
 711                 return IRQ_NONE;
 712
 713         if (stat & FSL_DMA_SR_TE)
 714                 dev_err(fsl_chan->dev, "Transfer Error!\n");
 715
 716         /* Programming Error
 717          * The DMA_INTERRUPT async_tx is a NULL transfer, which will
 718          * triger a PE interrupt.
 719          */
 720         if (stat & FSL_DMA_SR_PE) {
 721                 dev_dbg(fsl_chan->dev, "event: Programming Error INT\n");
 722                 if (get_bcr(fsl_chan) == 0) {
 723                         /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
 724                          * Now, update the completed cookie, and continue the
 725                          * next uncompleted transfer.
 726                          */
 727                         update_cookie = 1;
 728                         xfer_ld_q = 1;
 729                 }
 730                 stat &= ~FSL_DMA_SR_PE;
 731         }
 732
 733         /* If the link descriptor segment transfer finishes,
 734          * we will recycle the used descriptor.
 735          */
 736         if (stat & FSL_DMA_SR_EOSI) {
 737                 dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
 738                 dev_dbg(fsl_chan->dev, "event: clndar %p, nlndar %p\n",
 739                         (void *)get_cdar(fsl_chan), (void *)get_ndar(fsl_chan));
 740                 stat &= ~FSL_DMA_SR_EOSI;
 741                 update_cookie = 1;
 742         }
 743
 744         /* For MPC8349, EOCDI event need to update cookie
 745          * and start the next transfer if it exist.
 746          */
 747         if (stat & FSL_DMA_SR_EOCDI) {
 748                 dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n");
 749                 stat &= ~FSL_DMA_SR_EOCDI;
 750                 update_cookie = 1;
 751                 xfer_ld_q = 1;
 752         }
 753
 754         /* If it current transfer is the end-of-transfer,
 755          * we should clear the Channel Start bit for
 756          * prepare next transfer.
 757          */
 758         if (stat & FSL_DMA_SR_EOLNI) {
 759                 dev_dbg(fsl_chan->dev, "event: End-of-link INT\n");
 760                 stat &= ~FSL_DMA_SR_EOLNI;
 761                 xfer_ld_q = 1;
 762         }
 763
 764         if (update_cookie)
 765                 fsl_dma_update_completed_cookie(fsl_chan);
 766         if (xfer_ld_q)
 767                 fsl_chan_xfer_ld_queue(fsl_chan);
 768         if (stat)
 769                 dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n",
 770                                         stat);
 771
 772         dev_dbg(fsl_chan->dev, "event: Exit\n");
 773         tasklet_schedule(&fsl_chan->tasklet);
 774         return IRQ_HANDLED;
 775 }
 776
 777 static irqreturn_t fsl_dma_do_interrupt(int irq, void *data)
 778 {
 779         struct fsl_dma_device *fdev = (struct fsl_dma_device *)data;
 780         u32 gsr;
 781         int ch_nr;
 782
 783         gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base)
 784                         : in_le32(fdev->reg_base);
 785         ch_nr = (32 - ffs(gsr)) / 8;
 786
 787         return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq,
 788                         fdev->chan[ch_nr]) : IRQ_NONE;
 789 }
 790
 791 static void dma_do_tasklet(unsigned long data)
 792 {
 793         struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
 794         fsl_chan_ld_cleanup(fsl_chan);
 795 }
 796
 797 static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev,
 798         struct device_node *node, u32 feature, const char *compatible)
 799 {
 800         struct fsl_dma_chan *new_fsl_chan;
 801         int err;
 802
 803         /* alloc channel */
 804         new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL);
 805         if (!new_fsl_chan) {
 806                 dev_err(fdev->dev, "No free memory for allocating "
 807                                 "dma channels!\n");
 808                 return -ENOMEM;
 809         }
 810
 811         /* get dma channel register base */
 812         err = of_address_to_resource(node, 0, &new_fsl_chan->reg);
 813         if (err) {
 814                 dev_err(fdev->dev, "Can't get %s property 'reg'\n",
 815                                 node->full_name);
 816                 goto err_no_reg;
 817         }
 818
 819         new_fsl_chan->feature = feature;
 820
 821         if (!fdev->feature)
 822                 fdev->feature = new_fsl_chan->feature;
 823
 824         /* If the DMA device's feature is different than its channels',
 825          * report the bug.
 826          */
 827         WARN_ON(fdev->feature != new_fsl_chan->feature);
 828
 829         new_fsl_chan->dev = fdev->dev;
 830         new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start,
 831                         new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
 832
 833         new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
 834         if (new_fsl_chan->id > FSL_DMA_MAX_CHANS_PER_DEVICE) {
 835                 dev_err(fdev->dev, "There is no %d channel!\n",
 836                                 new_fsl_chan->id);
 837                 err = -EINVAL;
 838                 goto err_no_chan;
 839         }
 840         fdev->chan[new_fsl_chan->id] = new_fsl_chan;
 841         tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet,
 842                         (unsigned long)new_fsl_chan);
 843
 844         /* Init the channel */
 845         dma_init(new_fsl_chan);
 846
 847         /* Clear cdar registers */
 848         set_cdar(new_fsl_chan, 0);
 849
 850         switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) {
 851         case FSL_DMA_IP_85XX:
 852                 new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start;
 853                 new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
 854         case FSL_DMA_IP_83XX:
 855                 new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size;
 856                 new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size;
 857         }
 858
 859         spin_lock_init(&new_fsl_chan->desc_lock);
 860         INIT_LIST_HEAD(&new_fsl_chan->ld_queue);
 861
 862         new_fsl_chan->common.device = &fdev->common;
 863
 864         /* Add the channel to DMA device channel list */
 865         list_add_tail(&new_fsl_chan->common.device_node,
 866                         &fdev->common.channels);
 867         fdev->common.chancnt++;
 868
 869         new_fsl_chan->irq = irq_of_parse_and_map(node, 0);
 870         if (new_fsl_chan->irq != NO_IRQ) {
 871                 err = request_irq(new_fsl_chan->irq,
 872                                         &fsl_dma_chan_do_interrupt, IRQF_SHARED,
 873                                         "fsldma-channel", new_fsl_chan);
 874                 if (err) {
 875                         dev_err(fdev->dev, "DMA channel %s request_irq error "
 876                                 "with return %d\n", node->full_name, err);
 877                         goto err_no_irq;
 878                 }
 879         }
 880
 881         dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id,
 882                  compatible,
 883                  new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq);
 884
 885         return 0;
 886
 887 err_no_irq:
 888         list_del(&new_fsl_chan->common.device_node);
 889 err_no_chan:
 890         iounmap(new_fsl_chan->reg_base);
 891 err_no_reg:
 892         kfree(new_fsl_chan);
 893         return err;
 894 }
 895
 896 static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan)
 897 {
 898         if (fchan->irq != NO_IRQ)
 899                 free_irq(fchan->irq, fchan);
 900         list_del(&fchan->common.device_node);
 901         iounmap(fchan->reg_base);
 902         kfree(fchan);
 903 }
 904
 905 static int __devinit of_fsl_dma_probe(struct of_device *dev,
 906                         const struct of_device_id *match)
 907 {
 908         int err;
 909         struct fsl_dma_device *fdev;
 910         struct device_node *child;
 911
 912         fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL);
 913         if (!fdev) {
 914                 dev_err(&dev->dev, "No enough memory for 'priv'\n");
 915                 return -ENOMEM;
 916         }
 917         fdev->dev = &dev->dev;
 918         INIT_LIST_HEAD(&fdev->common.channels);
 919
 920         /* get DMA controller register base */
 921         err = of_address_to_resource(dev->node, 0, &fdev->reg);
 922         if (err) {
 923                 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
 924                                 dev->node->full_name);
 925                 goto err_no_reg;
 926         }
 927
 928         dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
 929                         "controller at %p...\n",
 930                         match->compatible, (void *)fdev->reg.start);
 931         fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
 932                                                 - fdev->reg.start + 1);
 933
 934         dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
 935         dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
 936         fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
 937         fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
 938         fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
 939         fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
 940         fdev->common.device_is_tx_complete = fsl_dma_is_complete;
 941         fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
 942         fdev->common.dev = &dev->dev;
 943
 944         fdev->irq = irq_of_parse_and_map(dev->node, 0);
 945         if (fdev->irq != NO_IRQ) {
 946                 err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED,
 947                                         "fsldma-device", fdev);
 948                 if (err) {
 949                         dev_err(&dev->dev, "DMA device request_irq error "
 950                                 "with return %d\n", err);
 951                         goto err;
 952                 }
 953         }
 954
 955         dev_set_drvdata(&(dev->dev), fdev);
 956
 957         /* We cannot use of_platform_bus_probe() because there is no
 958          * of_platform_bus_remove.  Instead, we manually instantiate every DMA
 959          * channel object.
 960          */
 961         for_each_child_of_node(dev->node, child) {
 962                 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel"))
 963                         fsl_dma_chan_probe(fdev, child,
 964                                 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
 965                                 "fsl,eloplus-dma-channel");
 966                 if (of_device_is_compatible(child, "fsl,elo-dma-channel"))
 967                         fsl_dma_chan_probe(fdev, child,
 968                                 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
 969                                 "fsl,elo-dma-channel");
 970         }
 971
 972         dma_async_device_register(&fdev->common);
 973         return 0;
 974
 975 err:
 976         iounmap(fdev->reg_base);
 977 err_no_reg:
 978         kfree(fdev);
 979         return err;
 980 }
 981
 982 static int of_fsl_dma_remove(struct of_device *of_dev)
 983 {
 984         struct fsl_dma_device *fdev;
 985         unsigned int i;
 986
 987         fdev = dev_get_drvdata(&of_dev->dev);
 988
 989         dma_async_device_unregister(&fdev->common);
 990
 991         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++)
 992                 if (fdev->chan[i])
 993                         fsl_dma_chan_remove(fdev->chan[i]);
 994
 995         if (fdev->irq != NO_IRQ)
 996                 free_irq(fdev->irq, fdev);
 997
 998         iounmap(fdev->reg_base);
 999
1000         kfree(fdev);
1001         dev_set_drvdata(&of_dev->dev, NULL);
1002
1003         return 0;
1004 }
1005
1006 static struct of_device_id of_fsl_dma_ids[] = {
1007         { .compatible = "fsl,eloplus-dma", },
1008         { .compatible = "fsl,elo-dma", },
1009         {}
1010 };
1011
1012 static struct of_platform_driver of_fsl_dma_driver = {
1013         .name = "fsl-elo-dma",
1014         .match_table = of_fsl_dma_ids,
1015         .probe = of_fsl_dma_probe,
1016         .remove = of_fsl_dma_remove,
1017 };
1018
1019 static __init int of_fsl_dma_init(void)
1020 {
1021         int ret;
1022
1023         pr_info("Freescale Elo / Elo Plus DMA driver\n");
1024
1025         ret = of_register_platform_driver(&of_fsl_dma_driver);
1026         if (ret)
1027                 pr_err("fsldma: failed to register platform driver\n");
1028
1029         return ret;
1030 }
1031
1032 static void __exit of_fsl_dma_exit(void)
1033 {
1034         of_unregister_platform_driver(&of_fsl_dma_driver);
1035 }
1036
1037 subsys_initcall(of_fsl_dma_init);
1038 module_exit(of_fsl_dma_exit);
1039
1040 MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
1041 MODULE_LICENSE("GPL");