drivers/char/tpm/tpm_tis.c

   1 /*
   2  * Copyright (C) 2005, 2006 IBM Corporation
   3  *
   4  * Authors:
   5  * Leendert van Doorn <leendert@watson.ibm.com>
   6  * Kylene Hall <kjhall@us.ibm.com>
   7  *
   8  * Device driver for TCG/TCPA TPM (trusted platform module).
   9  * Specifications at www.trustedcomputinggroup.org
  10  *
  11  * This device driver implements the TPM interface as defined in
  12  * the TCG TPM Interface Spec version 1.2, revision 1.0.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation, version 2 of the
  17  * License.
  18  */
  19 #include <linux/pnp.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/wait.h>
  22 #include "tpm.h"
  23
  24 #define TPM_HEADER_SIZE 10
  25
  26 enum tis_access {
  27         TPM_ACCESS_VALID = 0x80,
  28         TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
  29         TPM_ACCESS_REQUEST_PENDING = 0x04,
  30         TPM_ACCESS_REQUEST_USE = 0x02,
  31 };
  32
  33 enum tis_status {
  34         TPM_STS_VALID = 0x80,
  35         TPM_STS_COMMAND_READY = 0x40,
  36         TPM_STS_GO = 0x20,
  37         TPM_STS_DATA_AVAIL = 0x10,
  38         TPM_STS_DATA_EXPECT = 0x08,
  39 };
  40
  41 enum tis_int_flags {
  42         TPM_GLOBAL_INT_ENABLE = 0x80000000,
  43         TPM_INTF_BURST_COUNT_STATIC = 0x100,
  44         TPM_INTF_CMD_READY_INT = 0x080,
  45         TPM_INTF_INT_EDGE_FALLING = 0x040,
  46         TPM_INTF_INT_EDGE_RISING = 0x020,
  47         TPM_INTF_INT_LEVEL_LOW = 0x010,
  48         TPM_INTF_INT_LEVEL_HIGH = 0x008,
  49         TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
  50         TPM_INTF_STS_VALID_INT = 0x002,
  51         TPM_INTF_DATA_AVAIL_INT = 0x001,
  52 };
  53
  54 enum tis_defaults {
  55         TIS_MEM_BASE = 0xFED4000,
  56         TIS_MEM_LEN = 0x5000,
  57         TIS_SHORT_TIMEOUT = 750, /* ms */
  58         TIS_LONG_TIMEOUT = 2000, /* 2 sec */
  59 };
  60
  61 #define TPM_ACCESS(l)                   (0x0000 | ((l) << 12))
  62 #define TPM_INT_ENABLE(l)               (0x0008 | ((l) << 12))
  63 #define TPM_INT_VECTOR(l)               (0x000C | ((l) << 12))
  64 #define TPM_INT_STATUS(l)               (0x0010 | ((l) << 12))
  65 #define TPM_INTF_CAPS(l)                (0x0014 | ((l) << 12))
  66 #define TPM_STS(l)                      (0x0018 | ((l) << 12))
  67 #define TPM_DATA_FIFO(l)                (0x0024 | ((l) << 12))
  68
  69 #define TPM_DID_VID(l)                  (0x0F00 | ((l) << 12))
  70 #define TPM_RID(l)                      (0x0F04 | ((l) << 12))
  71
  72 static LIST_HEAD(tis_chips);
  73 static DEFINE_SPINLOCK(tis_lock);
  74
  75 static int check_locality(struct tpm_chip *chip, int l)
  76 {
  77         if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
  78              (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
  79             (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
  80                 return chip->vendor.locality = l;
  81
  82         return -1;
  83 }
  84
  85 static void release_locality(struct tpm_chip *chip, int l, int force)
  86 {
  87         if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
  88                       (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
  89             (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID))
  90                 iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
  91                          chip->vendor.iobase + TPM_ACCESS(l));
  92 }
  93
  94 static int request_locality(struct tpm_chip *chip, int l)
  95 {
  96         unsigned long stop;
  97         long rc;
  98
  99         if (check_locality(chip, l) >= 0)
 100                 return l;
 101
 102         iowrite8(TPM_ACCESS_REQUEST_USE,
 103                  chip->vendor.iobase + TPM_ACCESS(l));
 104
 105         if (chip->vendor.irq) {
 106                 rc = wait_event_interruptible_timeout(chip->vendor.int_queue,
 107                                                       (check_locality
 108                                                        (chip, l) >= 0),
 109                                                       chip->vendor.timeout_a);
 110                 if (rc > 0)
 111                         return l;
 112
 113         } else {
 114                 /* wait for burstcount */
 115                 stop = jiffies + chip->vendor.timeout_a;
 116                 do {
 117                         if (check_locality(chip, l) >= 0)
 118                                 return l;
 119                         msleep(TPM_TIMEOUT);
 120                 }
 121                 while (time_before(jiffies, stop));
 122         }
 123         return -1;
 124 }
 125
 126 static u8 tpm_tis_status(struct tpm_chip *chip)
 127 {
 128         return ioread8(chip->vendor.iobase +
 129                        TPM_STS(chip->vendor.locality));
 130 }
 131
 132 static void tpm_tis_ready(struct tpm_chip *chip)
 133 {
 134         /* this causes the current command to be aborted */
 135         iowrite8(TPM_STS_COMMAND_READY,
 136                  chip->vendor.iobase + TPM_STS(chip->vendor.locality));
 137 }
 138
 139 static int get_burstcount(struct tpm_chip *chip)
 140 {
 141         unsigned long stop;
 142         int burstcnt;
 143
 144         /* wait for burstcount */
 145         /* which timeout value, spec has 2 answers (c & d) */
 146         stop = jiffies + chip->vendor.timeout_d;
 147         do {
 148                 burstcnt = ioread8(chip->vendor.iobase +
 149                                    TPM_STS(chip->vendor.locality) + 1);
 150                 burstcnt += ioread8(chip->vendor.iobase +
 151                                     TPM_STS(chip->vendor.locality) +
 152                                     2) << 8;
 153                 if (burstcnt)
 154                         return burstcnt;
 155                 msleep(TPM_TIMEOUT);
 156         } while (time_before(jiffies, stop));
 157         return -EBUSY;
 158 }
 159
 160 static int wait_for_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout,
 161                          wait_queue_head_t *queue)
 162 {
 163         unsigned long stop;
 164         long rc;
 165         u8 status;
 166
 167         /* check current status */
 168         status = tpm_tis_status(chip);
 169         if ((status & mask) == mask)
 170                 return 0;
 171
 172         if (chip->vendor.irq) {
 173                 rc = wait_event_interruptible_timeout(*queue,
 174                                                       ((tpm_tis_status
 175                                                         (chip) & mask) ==
 176                                                        mask), timeout);
 177                 if (rc > 0)
 178                         return 0;
 179         } else {
 180                 stop = jiffies + timeout;
 181                 do {
 182                         msleep(TPM_TIMEOUT);
 183                         status = tpm_tis_status(chip);
 184                         if ((status & mask) == mask)
 185                                 return 0;
 186                 } while (time_before(jiffies, stop));
 187         }
 188         return -ETIME;
 189 }
 190
 191 static int recv_data(struct tpm_chip *chip, u8 * buf, size_t count)
 192 {
 193         int size = 0, burstcnt;
 194         while (size < count &&
 195                wait_for_stat(chip,
 196                              TPM_STS_DATA_AVAIL | TPM_STS_VALID,
 197                              chip->vendor.timeout_c,
 198                              &chip->vendor.read_queue)
 199                == 0) {
 200                 burstcnt = get_burstcount(chip);
 201                 for (; burstcnt > 0 && size < count; burstcnt--)
 202                         buf[size++] = ioread8(chip->vendor.iobase +
 203                                               TPM_DATA_FIFO(chip->vendor.
 204                                                             locality));
 205         }
 206         return size;
 207 }
 208
 209 static int tpm_tis_recv(struct tpm_chip *chip, u8 * buf, size_t count)
 210 {
 211         int size = 0;
 212         int expected, status;
 213
 214         if (count < TPM_HEADER_SIZE) {
 215                 size = -EIO;
 216                 goto out;
 217         }
 218
 219         /* read first 10 bytes, including tag, paramsize, and result */
 220         if ((size =
 221              recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) {
 222                 dev_err(chip->dev, "Unable to read header\n");
 223                 goto out;
 224         }
 225
 226         expected = be32_to_cpu(*(__be32 *) (buf + 2));
 227         if (expected > count) {
 228                 size = -EIO;
 229                 goto out;
 230         }
 231
 232         if ((size +=
 233              recv_data(chip, &buf[TPM_HEADER_SIZE],
 234                        expected - TPM_HEADER_SIZE)) < expected) {
 235                 dev_err(chip->dev, "Unable to read remainder of result\n");
 236                 size = -ETIME;
 237                 goto out;
 238         }
 239
 240         wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
 241                       &chip->vendor.int_queue);
 242         status = tpm_tis_status(chip);
 243         if (status & TPM_STS_DATA_AVAIL) {      /* retry? */
 244                 dev_err(chip->dev, "Error left over data\n");
 245                 size = -EIO;
 246                 goto out;
 247         }
 248
 249 out:
 250         tpm_tis_ready(chip);
 251         release_locality(chip, chip->vendor.locality, 0);
 252         return size;
 253 }
 254
 255 /*
 256  * If interrupts are used (signaled by an irq set in the vendor structure)
 257  * tpm.c can skip polling for the data to be available as the interrupt is
 258  * waited for here
 259  */
 260 static int tpm_tis_send(struct tpm_chip *chip, u8 * buf, size_t len)
 261 {
 262         int rc, status, burstcnt;
 263         size_t count = 0;
 264         u32 ordinal;
 265
 266         if (request_locality(chip, 0) < 0)
 267                 return -EBUSY;
 268
 269         status = tpm_tis_status(chip);
 270         if ((status & TPM_STS_COMMAND_READY) == 0) {
 271                 tpm_tis_ready(chip);
 272                 if (wait_for_stat
 273                     (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b,
 274                      &chip->vendor.int_queue) < 0) {
 275                         rc = -ETIME;
 276                         goto out_err;
 277                 }
 278         }
 279
 280         while (count < len - 1) {
 281                 burstcnt = get_burstcount(chip);
 282                 for (; burstcnt > 0 && count < len - 1; burstcnt--) {
 283                         iowrite8(buf[count], chip->vendor.iobase +
 284                                  TPM_DATA_FIFO(chip->vendor.locality));
 285                         count++;
 286                 }
 287
 288                 wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
 289                               &chip->vendor.int_queue);
 290                 status = tpm_tis_status(chip);
 291                 if ((status & TPM_STS_DATA_EXPECT) == 0) {
 292                         rc = -EIO;
 293                         goto out_err;
 294                 }
 295         }
 296
 297         /* write last byte */
 298         iowrite8(buf[count],
 299                  chip->vendor.iobase +
 300                  TPM_DATA_FIFO(chip->vendor.locality));
 301         wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
 302                       &chip->vendor.int_queue);
 303         status = tpm_tis_status(chip);
 304         if ((status & TPM_STS_DATA_EXPECT) != 0) {
 305                 rc = -EIO;
 306                 goto out_err;
 307         }
 308
 309         /* go and do it */
 310         iowrite8(TPM_STS_GO,
 311                  chip->vendor.iobase + TPM_STS(chip->vendor.locality));
 312
 313         if (chip->vendor.irq) {
 314                 ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
 315                 if (wait_for_stat
 316                     (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID,
 317                      tpm_calc_ordinal_duration(chip, ordinal),
 318                      &chip->vendor.read_queue) < 0) {
 319                         rc = -ETIME;
 320                         goto out_err;
 321                 }
 322         }
 323         return len;
 324 out_err:
 325         tpm_tis_ready(chip);
 326         release_locality(chip, chip->vendor.locality, 0);
 327         return rc;
 328 }
 329
 330 static struct file_operations tis_ops = {
 331         .owner = THIS_MODULE,
 332         .llseek = no_llseek,
 333         .open = tpm_open,
 334         .read = tpm_read,
 335         .write = tpm_write,
 336         .release = tpm_release,
 337 };
 338
 339 static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
 340 static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
 341 static DEVICE_ATTR(enabled, S_IRUGO, tpm_show_enabled, NULL);
 342 static DEVICE_ATTR(active, S_IRUGO, tpm_show_active, NULL);
 343 static DEVICE_ATTR(owned, S_IRUGO, tpm_show_owned, NULL);
 344 static DEVICE_ATTR(temp_deactivated, S_IRUGO, tpm_show_temp_deactivated,
 345                    NULL);
 346 static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps_1_2, NULL);
 347 static DEVICE_ATTR(cancel, S_IWUSR | S_IWGRP, NULL, tpm_store_cancel);
 348
 349 static struct attribute *tis_attrs[] = {
 350         &dev_attr_pubek.attr,
 351         &dev_attr_pcrs.attr,
 352         &dev_attr_enabled.attr,
 353         &dev_attr_active.attr,
 354         &dev_attr_owned.attr,
 355         &dev_attr_temp_deactivated.attr,
 356         &dev_attr_caps.attr,
 357         &dev_attr_cancel.attr, NULL,
 358 };
 359
 360 static struct attribute_group tis_attr_grp = {
 361         .attrs = tis_attrs
 362 };
 363
 364 static struct tpm_vendor_specific tpm_tis = {
 365         .status = tpm_tis_status,
 366         .recv = tpm_tis_recv,
 367         .send = tpm_tis_send,
 368         .cancel = tpm_tis_ready,
 369         .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
 370         .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
 371         .req_canceled = TPM_STS_COMMAND_READY,
 372         .attr_group = &tis_attr_grp,
 373         .miscdev = {
 374                     .fops = &tis_ops,},
 375 };
 376
 377 static irqreturn_t tis_int_probe(int irq, void *dev_id, struct pt_regs
 378                                  *regs)
 379 {
 380         struct tpm_chip *chip = (struct tpm_chip *) dev_id;
 381         u32 interrupt;
 382
 383         interrupt = ioread32(chip->vendor.iobase +
 384                              TPM_INT_STATUS(chip->vendor.locality));
 385
 386         if (interrupt == 0)
 387                 return IRQ_NONE;
 388
 389         chip->vendor.irq = irq;
 390
 391         /* Clear interrupts handled with TPM_EOI */
 392         iowrite32(interrupt,
 393                   chip->vendor.iobase +
 394                   TPM_INT_STATUS(chip->vendor.locality));
 395         return IRQ_HANDLED;
 396 }
 397
 398 static irqreturn_t tis_int_handler(int irq, void *dev_id, struct pt_regs
 399                                    *regs)
 400 {
 401         struct tpm_chip *chip = (struct tpm_chip *) dev_id;
 402         u32 interrupt;
 403         int i;
 404
 405         interrupt = ioread32(chip->vendor.iobase +
 406                              TPM_INT_STATUS(chip->vendor.locality));
 407
 408         if (interrupt == 0)
 409                 return IRQ_NONE;
 410
 411         if (interrupt & TPM_INTF_DATA_AVAIL_INT)
 412                 wake_up_interruptible(&chip->vendor.read_queue);
 413         if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
 414                 for (i = 0; i < 5; i++)
 415                         if (check_locality(chip, i) >= 0)
 416                                 break;
 417         if (interrupt &
 418             (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
 419              TPM_INTF_CMD_READY_INT))
 420                 wake_up_interruptible(&chip->vendor.int_queue);
 421
 422         /* Clear interrupts handled with TPM_EOI */
 423         iowrite32(interrupt,
 424                   chip->vendor.iobase +
 425                   TPM_INT_STATUS(chip->vendor.locality));
 426         return IRQ_HANDLED;
 427 }
 428
 429 static int __devinit tpm_tis_pnp_init(struct pnp_dev
 430                                       *pnp_dev, const struct
 431                                       pnp_device_id
 432                                       *pnp_id)
 433 {
 434         u32 vendor, intfcaps, intmask;
 435         int rc, i;
 436         unsigned long start, len;
 437         struct tpm_chip *chip;
 438
 439         start = pnp_mem_start(pnp_dev, 0);
 440         len = pnp_mem_len(pnp_dev, 0);
 441
 442         if (!start)
 443                 start = TIS_MEM_BASE;
 444         if (!len)
 445                 len = TIS_MEM_LEN;
 446
 447         if (!(chip = tpm_register_hardware(&pnp_dev->dev, &tpm_tis)))
 448                 return -ENODEV;
 449
 450         chip->vendor.iobase = ioremap(start, len);
 451         if (!chip->vendor.iobase) {
 452                 rc = -EIO;
 453                 goto out_err;
 454         }
 455
 456         vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
 457         if ((vendor & 0xFFFF) == 0xFFFF) {
 458                 rc = -ENODEV;
 459                 goto out_err;
 460         }
 461
 462         /* Default timeouts */
 463         chip->vendor.timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
 464         chip->vendor.timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT);
 465         chip->vendor.timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
 466         chip->vendor.timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
 467
 468         dev_info(&pnp_dev->dev,
 469                  "1.2 TPM (device-id 0x%X, rev-id %d)\n",
 470                  vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
 471
 472         /* Figure out the capabilities */
 473         intfcaps =
 474             ioread32(chip->vendor.iobase +
 475                      TPM_INTF_CAPS(chip->vendor.locality));
 476         dev_dbg(&pnp_dev->dev, "TPM interface capabilities (0x%x):\n",
 477                 intfcaps);
 478         if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
 479                 dev_dbg(&pnp_dev->dev, "\tBurst Count Static\n");
 480         if (intfcaps & TPM_INTF_CMD_READY_INT)
 481                 dev_dbg(&pnp_dev->dev, "\tCommand Ready Int Support\n");
 482         if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
 483                 dev_dbg(&pnp_dev->dev, "\tInterrupt Edge Falling\n");
 484         if (intfcaps & TPM_INTF_INT_EDGE_RISING)
 485                 dev_dbg(&pnp_dev->dev, "\tInterrupt Edge Rising\n");
 486         if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
 487                 dev_dbg(&pnp_dev->dev, "\tInterrupt Level Low\n");
 488         if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
 489                 dev_dbg(&pnp_dev->dev, "\tInterrupt Level High\n");
 490         if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
 491                 dev_dbg(&pnp_dev->dev, "\tLocality Change Int Support\n");
 492         if (intfcaps & TPM_INTF_STS_VALID_INT)
 493                 dev_dbg(&pnp_dev->dev, "\tSts Valid Int Support\n");
 494         if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
 495                 dev_dbg(&pnp_dev->dev, "\tData Avail Int Support\n");
 496
 497         if (request_locality(chip, 0) != 0) {
 498                 rc = -ENODEV;
 499                 goto out_err;
 500         }
 501
 502         /* INTERRUPT Setup */
 503         init_waitqueue_head(&chip->vendor.read_queue);
 504         init_waitqueue_head(&chip->vendor.int_queue);
 505
 506         intmask =
 507             ioread32(chip->vendor.iobase +
 508                      TPM_INT_ENABLE(chip->vendor.locality));
 509
 510         intmask |= TPM_INTF_CMD_READY_INT
 511             | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
 512             | TPM_INTF_STS_VALID_INT;
 513
 514         iowrite32(intmask,
 515                   chip->vendor.iobase +
 516                   TPM_INT_ENABLE(chip->vendor.locality));
 517
 518         chip->vendor.irq =
 519             ioread8(chip->vendor.iobase +
 520                     TPM_INT_VECTOR(chip->vendor.locality));
 521
 522         for (i = 3; i < 16 && chip->vendor.irq == 0; i++) {
 523                 iowrite8(i,
 524                          chip->vendor.iobase +
 525                          TPM_INT_VECTOR(chip->vendor.locality));
 526                 if (request_irq
 527                     (i, tis_int_probe, SA_SHIRQ,
 528                      chip->vendor.miscdev.name, chip) != 0) {
 529                         dev_info(chip->dev,
 530                                  "Unable to request irq: %d for probe\n",
 531                                  i);
 532                         continue;
 533                 }
 534
 535                 /* Clear all existing */
 536                 iowrite32(ioread32
 537                           (chip->vendor.iobase +
 538                            TPM_INT_STATUS(chip->vendor.locality)),
 539                           chip->vendor.iobase +
 540                           TPM_INT_STATUS(chip->vendor.locality));
 541
 542                 /* Turn on */
 543                 iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
 544                           chip->vendor.iobase +
 545                           TPM_INT_ENABLE(chip->vendor.locality));
 546
 547                 /* Generate Interrupts */
 548                 tpm_gen_interrupt(chip);
 549
 550                 /* Turn off */
 551                 iowrite32(intmask,
 552                           chip->vendor.iobase +
 553                           TPM_INT_ENABLE(chip->vendor.locality));
 554                 free_irq(i, chip);
 555         }
 556         if (chip->vendor.irq) {
 557                 iowrite8(chip->vendor.irq,
 558                          chip->vendor.iobase +
 559                          TPM_INT_VECTOR(chip->vendor.locality));
 560                 if (request_irq
 561                     (chip->vendor.irq, tis_int_handler, SA_SHIRQ,
 562                      chip->vendor.miscdev.name, chip) != 0) {
 563                         dev_info(chip->dev,
 564                                  "Unable to request irq: %d for use\n", i);
 565                         chip->vendor.irq = 0;
 566                 } else {
 567                         /* Clear all existing */
 568                         iowrite32(ioread32
 569                                   (chip->vendor.iobase +
 570                                    TPM_INT_STATUS(chip->vendor.locality)),
 571                                   chip->vendor.iobase +
 572                                   TPM_INT_STATUS(chip->vendor.locality));
 573
 574                         /* Turn on */
 575                         iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
 576                                   chip->vendor.iobase +
 577                                   TPM_INT_ENABLE(chip->vendor.locality));
 578                 }
 579         }
 580
 581         INIT_LIST_HEAD(&chip->vendor.list);
 582         spin_lock(&tis_lock);
 583         list_add(&chip->vendor.list, &tis_chips);
 584         spin_unlock(&tis_lock);
 585
 586         tpm_get_timeouts(chip);
 587         tpm_continue_selftest(chip);
 588
 589         return 0;
 590 out_err:
 591         if (chip->vendor.iobase)
 592                 iounmap(chip->vendor.iobase);
 593         tpm_remove_hardware(chip->dev);
 594         return rc;
 595 }
 596
 597 static int tpm_tis_pnp_suspend(struct pnp_dev *dev, pm_message_t msg)
 598 {
 599         return tpm_pm_suspend(&dev->dev, msg);
 600 }
 601
 602 static int tpm_tis_pnp_resume(struct pnp_dev *dev)
 603 {
 604         return tpm_pm_resume(&dev->dev);
 605 }
 606
 607 static struct pnp_device_id tpm_pnp_tbl[] __devinitdata = {
 608         {"PNP0C31", 0},         /* TPM */
 609         {"", 0}
 610 };
 611
 612 static struct pnp_driver tis_pnp_driver = {
 613         .name = "tpm_tis",
 614         .id_table = tpm_pnp_tbl,
 615         .probe = tpm_tis_pnp_init,
 616         .suspend = tpm_tis_pnp_suspend,
 617         .resume = tpm_tis_pnp_resume,
 618 };
 619
 620 static int __init init_tis(void)
 621 {
 622         return pnp_register_driver(&tis_pnp_driver);
 623 }
 624
 625 static void __exit cleanup_tis(void)
 626 {
 627         struct tpm_vendor_specific *i, *j;
 628         struct tpm_chip *chip;
 629         spin_lock(&tis_lock);
 630         list_for_each_entry_safe(i, j, &tis_chips, list) {
 631                 chip = to_tpm_chip(i);
 632                 iowrite32(~TPM_GLOBAL_INT_ENABLE &
 633                           ioread32(chip->vendor.iobase +
 634                                    TPM_INT_ENABLE(chip->vendor.
 635                                                   locality)),
 636                           chip->vendor.iobase +
 637                           TPM_INT_ENABLE(chip->vendor.locality));
 638                 release_locality(chip, chip->vendor.locality, 1);
 639                 if (chip->vendor.irq)
 640                         free_irq(chip->vendor.irq, chip);
 641                 iounmap(i->iobase);
 642                 list_del(&i->list);
 643                 tpm_remove_hardware(chip->dev);
 644         }
 645         spin_unlock(&tis_lock);
 646         pnp_unregister_driver(&tis_pnp_driver);
 647 }
 648
 649 module_init(init_tis);
 650 module_exit(cleanup_tis);
 651 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
 652 MODULE_DESCRIPTION("TPM Driver");
 653 MODULE_VERSION("2.0");
 654 MODULE_LICENSE("GPL");