drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/config.h>
  38 #include <linux/module.h>
  39 #include <linux/errno.h>
  40 #include <linux/signal.h>
  41 #include <linux/sched.h>
  42 #include <linux/timer.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/pci.h>
  45 #include <linux/tty.h>
  46 #include <linux/tty_flip.h>
  47 #include <linux/serial.h>
  48 #include <linux/major.h>
  49 #include <linux/string.h>
  50 #include <linux/fcntl.h>
  51 #include <linux/ptrace.h>
  52 #include <linux/ioport.h>
  53 #include <linux/mm.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <linux/delay.h>
  59 #include <linux/ioctl.h>
  60
  61 #include <asm/system.h>
  62 #include <asm/io.h>
  63 #include <asm/irq.h>
  64 #include <asm/dma.h>
  65 #include <linux/bitops.h>
  66 #include <asm/types.h>
  67 #include <linux/termios.h>
  68 #include <linux/workqueue.h>
  69 #include <linux/hdlc.h>
  70
  71 #ifdef CONFIG_HDLC_MODULE
  72 #define CONFIG_HDLC 1
  73 #endif
  74
  75 #define GET_USER(error,value,addr) error = get_user(value,addr)
  76 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  77 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  78 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  79
  80 #include <asm/uaccess.h>
  81
  82 #include "linux/synclink.h"
  83
  84 static MGSL_PARAMS default_params = {
  85         MGSL_MODE_HDLC,                 /* unsigned long mode */
  86         0,                              /* unsigned char loopback; */
  87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89         0,                              /* unsigned long clock_speed; */
  90         0xff,                           /* unsigned char addr_filter; */
  91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94         9600,                           /* unsigned long data_rate; */
  95         8,                              /* unsigned char data_bits; */
  96         1,                              /* unsigned char stop_bits; */
  97         ASYNC_PARITY_NONE               /* unsigned char parity; */
  98 };
  99
 100 /* size in bytes of DMA data buffers */
 101 #define SCABUFSIZE      1024
 102 #define SCA_MEM_SIZE    0x40000
 103 #define SCA_BASE_SIZE   512
 104 #define SCA_REG_SIZE    16
 105 #define SCA_MAX_PORTS   4
 106 #define SCAMAXDESC      128
 107
 108 #define BUFFERLISTSIZE  4096
 109
 110 /* SCA-I style DMA buffer descriptor */
 111 typedef struct _SCADESC
 112 {
 113         u16     next;           /* lower l6 bits of next descriptor addr */
 114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115         u8      buf_base;       /* upper 8 bits of buffer addr */
 116         u8      pad1;
 117         u16     length;         /* length of buffer */
 118         u8      status;         /* status of buffer */
 119         u8      pad2;
 120 } SCADESC, *PSCADESC;
 121
 122 typedef struct _SCADESC_EX
 123 {
 124         /* device driver bookkeeping section */
 125         char    *virt_addr;     /* virtual address of data buffer */
 126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127 } SCADESC_EX, *PSCADESC_EX;
 128
 129 /* The queue of BH actions to be performed */
 130
 131 #define BH_RECEIVE  1
 132 #define BH_TRANSMIT 2
 133 #define BH_STATUS   4
 134
 135 #define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 138
 139 struct  _input_signal_events {
 140         int     ri_up;
 141         int     ri_down;
 142         int     dsr_up;
 143         int     dsr_down;
 144         int     dcd_up;
 145         int     dcd_down;
 146         int     cts_up;
 147         int     cts_down;
 148 };
 149
 150 /*
 151  * Device instance data structure
 152  */
 153 typedef struct _synclinkmp_info {
 154         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 155         int                     magic;
 156         int                     flags;
 157         int                     count;          /* count of opens */
 158         int                     line;
 159         unsigned short          close_delay;
 160         unsigned short          closing_wait;   /* time to wait before closing */
 161
 162         struct mgsl_icount      icount;
 163
 164         struct tty_struct       *tty;
 165         int                     timeout;
 166         int                     x_char;         /* xon/xoff character */
 167         int                     blocked_open;   /* # of blocked opens */
 168         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 169         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 170         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 171         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 172         unsigned char           *tx_buf;
 173         int                     tx_put;
 174         int                     tx_get;
 175         int                     tx_count;
 176
 177         wait_queue_head_t       open_wait;
 178         wait_queue_head_t       close_wait;
 179
 180         wait_queue_head_t       status_event_wait_q;
 181         wait_queue_head_t       event_wait_q;
 182         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 183         struct _synclinkmp_info *next_device;   /* device list link */
 184         struct timer_list       status_timer;   /* input signal status check timer */
 185
 186         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 187         struct work_struct task;                        /* task structure for scheduling bh */
 188
 189         u32 max_frame_size;                     /* as set by device config */
 190
 191         u32 pending_bh;
 192
 193         int bh_running;                         /* Protection from multiple */
 194         int isr_overflow;
 195         int bh_requested;
 196
 197         int dcd_chkcount;                       /* check counts to prevent */
 198         int cts_chkcount;                       /* too many IRQs if a signal */
 199         int dsr_chkcount;                       /* is floating */
 200         int ri_chkcount;
 201
 202         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 203         unsigned long buffer_list_phys;
 204
 205         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 206         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 207         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 208         unsigned int current_rx_buf;
 209
 210         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 211         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 212         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 213         unsigned int last_tx_buf;
 214
 215         unsigned char *tmp_rx_buf;
 216         unsigned int tmp_rx_buf_count;
 217
 218         int rx_enabled;
 219         int rx_overflow;
 220
 221         int tx_enabled;
 222         int tx_active;
 223         u32 idle_mode;
 224
 225         unsigned char ie0_value;
 226         unsigned char ie1_value;
 227         unsigned char ie2_value;
 228         unsigned char ctrlreg_value;
 229         unsigned char old_signals;
 230
 231         char device_name[25];                   /* device instance name */
 232
 233         int port_count;
 234         int adapter_num;
 235         int port_num;
 236
 237         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 238
 239         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 240
 241         unsigned int irq_level;                 /* interrupt level */
 242         unsigned long irq_flags;
 243         int irq_requested;                      /* nonzero if IRQ requested */
 244
 245         MGSL_PARAMS params;                     /* communications parameters */
 246
 247         unsigned char serial_signals;           /* current serial signal states */
 248
 249         int irq_occurred;                       /* for diagnostics use */
 250         unsigned int init_error;                /* Initialization startup error */
 251
 252         u32 last_mem_alloc;
 253         unsigned char* memory_base;             /* shared memory address (PCI only) */
 254         u32 phys_memory_base;
 255         int shared_mem_requested;
 256
 257         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 258         u32 phys_sca_base;
 259         u32 sca_offset;
 260         int sca_base_requested;
 261
 262         unsigned char* lcr_base;                /* local config registers (PCI only) */
 263         u32 phys_lcr_base;
 264         u32 lcr_offset;
 265         int lcr_mem_requested;
 266
 267         unsigned char* statctrl_base;           /* status/control register memory */
 268         u32 phys_statctrl_base;
 269         u32 statctrl_offset;
 270         int sca_statctrl_requested;
 271
 272         u32 misc_ctrl_value;
 273         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 274         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 275         BOOLEAN drop_rts_on_tx_done;
 276
 277         struct  _input_signal_events    input_signal_events;
 278
 279         /* SPPP/Cisco HDLC device parts */
 280         int netcount;
 281         int dosyncppp;
 282         spinlock_t netlock;
 283
 284 #ifdef CONFIG_HDLC
 285         struct net_device *netdev;
 286 #endif
 287
 288 } SLMP_INFO;
 289
 290 #define MGSL_MAGIC 0x5401
 291
 292 /*
 293  * define serial signal status change macros
 294  */
 295 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 296 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 297 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 298 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 299
 300 /* Common Register macros */
 301 #define LPR     0x00
 302 #define PABR0   0x02
 303 #define PABR1   0x03
 304 #define WCRL    0x04
 305 #define WCRM    0x05
 306 #define WCRH    0x06
 307 #define DPCR    0x08
 308 #define DMER    0x09
 309 #define ISR0    0x10
 310 #define ISR1    0x11
 311 #define ISR2    0x12
 312 #define IER0    0x14
 313 #define IER1    0x15
 314 #define IER2    0x16
 315 #define ITCR    0x18
 316 #define INTVR   0x1a
 317 #define IMVR    0x1c
 318
 319 /* MSCI Register macros */
 320 #define TRB     0x20
 321 #define TRBL    0x20
 322 #define TRBH    0x21
 323 #define SR0     0x22
 324 #define SR1     0x23
 325 #define SR2     0x24
 326 #define SR3     0x25
 327 #define FST     0x26
 328 #define IE0     0x28
 329 #define IE1     0x29
 330 #define IE2     0x2a
 331 #define FIE     0x2b
 332 #define CMD     0x2c
 333 #define MD0     0x2e
 334 #define MD1     0x2f
 335 #define MD2     0x30
 336 #define CTL     0x31
 337 #define SA0     0x32
 338 #define SA1     0x33
 339 #define IDL     0x34
 340 #define TMC     0x35
 341 #define RXS     0x36
 342 #define TXS     0x37
 343 #define TRC0    0x38
 344 #define TRC1    0x39
 345 #define RRC     0x3a
 346 #define CST0    0x3c
 347 #define CST1    0x3d
 348
 349 /* Timer Register Macros */
 350 #define TCNT    0x60
 351 #define TCNTL   0x60
 352 #define TCNTH   0x61
 353 #define TCONR   0x62
 354 #define TCONRL  0x62
 355 #define TCONRH  0x63
 356 #define TMCS    0x64
 357 #define TEPR    0x65
 358
 359 /* DMA Controller Register macros */
 360 #define DARL    0x80
 361 #define DARH    0x81
 362 #define DARB    0x82
 363 #define BAR     0x80
 364 #define BARL    0x80
 365 #define BARH    0x81
 366 #define BARB    0x82
 367 #define SAR     0x84
 368 #define SARL    0x84
 369 #define SARH    0x85
 370 #define SARB    0x86
 371 #define CPB     0x86
 372 #define CDA     0x88
 373 #define CDAL    0x88
 374 #define CDAH    0x89
 375 #define EDA     0x8a
 376 #define EDAL    0x8a
 377 #define EDAH    0x8b
 378 #define BFL     0x8c
 379 #define BFLL    0x8c
 380 #define BFLH    0x8d
 381 #define BCR     0x8e
 382 #define BCRL    0x8e
 383 #define BCRH    0x8f
 384 #define DSR     0x90
 385 #define DMR     0x91
 386 #define FCT     0x93
 387 #define DIR     0x94
 388 #define DCMD    0x95
 389
 390 /* combine with timer or DMA register address */
 391 #define TIMER0  0x00
 392 #define TIMER1  0x08
 393 #define TIMER2  0x10
 394 #define TIMER3  0x18
 395 #define RXDMA   0x00
 396 #define TXDMA   0x20
 397
 398 /* SCA Command Codes */
 399 #define NOOP            0x00
 400 #define TXRESET         0x01
 401 #define TXENABLE        0x02
 402 #define TXDISABLE       0x03
 403 #define TXCRCINIT       0x04
 404 #define TXCRCEXCL       0x05
 405 #define TXEOM           0x06
 406 #define TXABORT         0x07
 407 #define MPON            0x08
 408 #define TXBUFCLR        0x09
 409 #define RXRESET         0x11
 410 #define RXENABLE        0x12
 411 #define RXDISABLE       0x13
 412 #define RXCRCINIT       0x14
 413 #define RXREJECT        0x15
 414 #define SEARCHMP        0x16
 415 #define RXCRCEXCL       0x17
 416 #define RXCRCCALC       0x18
 417 #define CHRESET         0x21
 418 #define HUNT            0x31
 419
 420 /* DMA command codes */
 421 #define SWABORT         0x01
 422 #define FEICLEAR        0x02
 423
 424 /* IE0 */
 425 #define TXINTE          BIT7
 426 #define RXINTE          BIT6
 427 #define TXRDYE          BIT1
 428 #define RXRDYE          BIT0
 429
 430 /* IE1 & SR1 */
 431 #define UDRN    BIT7
 432 #define IDLE    BIT6
 433 #define SYNCD   BIT4
 434 #define FLGD    BIT4
 435 #define CCTS    BIT3
 436 #define CDCD    BIT2
 437 #define BRKD    BIT1
 438 #define ABTD    BIT1
 439 #define GAPD    BIT1
 440 #define BRKE    BIT0
 441 #define IDLD    BIT0
 442
 443 /* IE2 & SR2 */
 444 #define EOM     BIT7
 445 #define PMP     BIT6
 446 #define SHRT    BIT6
 447 #define PE      BIT5
 448 #define ABT     BIT5
 449 #define FRME    BIT4
 450 #define RBIT    BIT4
 451 #define OVRN    BIT3
 452 #define CRCE    BIT2
 453
 454
 455 /*
 456  * Global linked list of SyncLink devices
 457  */
 458 static SLMP_INFO *synclinkmp_device_list = NULL;
 459 static int synclinkmp_adapter_count = -1;
 460 static int synclinkmp_device_count = 0;
 461
 462 /*
 463  * Set this param to non-zero to load eax with the
 464  * .text section address and breakpoint on module load.
 465  * This is useful for use with gdb and add-symbol-file command.
 466  */
 467 static int break_on_load=0;
 468
 469 /*
 470  * Driver major number, defaults to zero to get auto
 471  * assigned major number. May be forced as module parameter.
 472  */
 473 static int ttymajor=0;
 474
 475 /*
 476  * Array of user specified options for ISA adapters.
 477  */
 478 static int debug_level = 0;
 479 static int maxframe[MAX_DEVICES] = {0,};
 480 static int dosyncppp[MAX_DEVICES] = {0,};
 481
 482 module_param(break_on_load, bool, 0);
 483 module_param(ttymajor, int, 0);
 484 module_param(debug_level, int, 0);
 485 module_param_array(maxframe, int, NULL, 0);
 486 module_param_array(dosyncppp, int, NULL, 0);
 487
 488 static char *driver_name = "SyncLink MultiPort driver";
 489 static char *driver_version = "$Revision: 4.38 $";
 490
 491 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 492 static void synclinkmp_remove_one(struct pci_dev *dev);
 493
 494 static struct pci_device_id synclinkmp_pci_tbl[] = {
 495         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 496         { 0, }, /* terminate list */
 497 };
 498 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 499
 500 MODULE_LICENSE("GPL");
 501
 502 static struct pci_driver synclinkmp_pci_driver = {
 503         .name           = "synclinkmp",
 504         .id_table       = synclinkmp_pci_tbl,
 505         .probe          = synclinkmp_init_one,
 506         .remove         = __devexit_p(synclinkmp_remove_one),
 507 };
 508
 509
 510 static struct tty_driver *serial_driver;
 511
 512 /* number of characters left in xmit buffer before we ask for more */
 513 #define WAKEUP_CHARS 256
 514
 515
 516 /* tty callbacks */
 517
 518 static int  open(struct tty_struct *tty, struct file * filp);
 519 static void close(struct tty_struct *tty, struct file * filp);
 520 static void hangup(struct tty_struct *tty);
 521 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 522
 523 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 524 static void put_char(struct tty_struct *tty, unsigned char ch);
 525 static void send_xchar(struct tty_struct *tty, char ch);
 526 static void wait_until_sent(struct tty_struct *tty, int timeout);
 527 static int  write_room(struct tty_struct *tty);
 528 static void flush_chars(struct tty_struct *tty);
 529 static void flush_buffer(struct tty_struct *tty);
 530 static void tx_hold(struct tty_struct *tty);
 531 static void tx_release(struct tty_struct *tty);
 532
 533 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 534 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 535 static int  chars_in_buffer(struct tty_struct *tty);
 536 static void throttle(struct tty_struct * tty);
 537 static void unthrottle(struct tty_struct * tty);
 538 static void set_break(struct tty_struct *tty, int break_state);
 539
 540 #ifdef CONFIG_HDLC
 541 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 542 static void hdlcdev_tx_done(SLMP_INFO *info);
 543 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 544 static int  hdlcdev_init(SLMP_INFO *info);
 545 static void hdlcdev_exit(SLMP_INFO *info);
 546 #endif
 547
 548 /* ioctl handlers */
 549
 550 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 551 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 552 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 553 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 554 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 555 static int  tx_enable(SLMP_INFO *info, int enable);
 556 static int  tx_abort(SLMP_INFO *info);
 557 static int  rx_enable(SLMP_INFO *info, int enable);
 558 static int  modem_input_wait(SLMP_INFO *info,int arg);
 559 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 560 static int  tiocmget(struct tty_struct *tty, struct file *file);
 561 static int  tiocmset(struct tty_struct *tty, struct file *file,
 562                      unsigned int set, unsigned int clear);
 563 static void set_break(struct tty_struct *tty, int break_state);
 564
 565 static void add_device(SLMP_INFO *info);
 566 static void device_init(int adapter_num, struct pci_dev *pdev);
 567 static int  claim_resources(SLMP_INFO *info);
 568 static void release_resources(SLMP_INFO *info);
 569
 570 static int  startup(SLMP_INFO *info);
 571 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 572 static void shutdown(SLMP_INFO *info);
 573 static void program_hw(SLMP_INFO *info);
 574 static void change_params(SLMP_INFO *info);
 575
 576 static int  init_adapter(SLMP_INFO *info);
 577 static int  register_test(SLMP_INFO *info);
 578 static int  irq_test(SLMP_INFO *info);
 579 static int  loopback_test(SLMP_INFO *info);
 580 static int  adapter_test(SLMP_INFO *info);
 581 static int  memory_test(SLMP_INFO *info);
 582
 583 static void reset_adapter(SLMP_INFO *info);
 584 static void reset_port(SLMP_INFO *info);
 585 static void async_mode(SLMP_INFO *info);
 586 static void hdlc_mode(SLMP_INFO *info);
 587
 588 static void rx_stop(SLMP_INFO *info);
 589 static void rx_start(SLMP_INFO *info);
 590 static void rx_reset_buffers(SLMP_INFO *info);
 591 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 592 static int  rx_get_frame(SLMP_INFO *info);
 593
 594 static void tx_start(SLMP_INFO *info);
 595 static void tx_stop(SLMP_INFO *info);
 596 static void tx_load_fifo(SLMP_INFO *info);
 597 static void tx_set_idle(SLMP_INFO *info);
 598 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 599
 600 static void get_signals(SLMP_INFO *info);
 601 static void set_signals(SLMP_INFO *info);
 602 static void enable_loopback(SLMP_INFO *info, int enable);
 603 static void set_rate(SLMP_INFO *info, u32 data_rate);
 604
 605 static int  bh_action(SLMP_INFO *info);
 606 static void bh_handler(void* Context);
 607 static void bh_receive(SLMP_INFO *info);
 608 static void bh_transmit(SLMP_INFO *info);
 609 static void bh_status(SLMP_INFO *info);
 610 static void isr_timer(SLMP_INFO *info);
 611 static void isr_rxint(SLMP_INFO *info);
 612 static void isr_rxrdy(SLMP_INFO *info);
 613 static void isr_txint(SLMP_INFO *info);
 614 static void isr_txrdy(SLMP_INFO *info);
 615 static void isr_rxdmaok(SLMP_INFO *info);
 616 static void isr_rxdmaerror(SLMP_INFO *info);
 617 static void isr_txdmaok(SLMP_INFO *info);
 618 static void isr_txdmaerror(SLMP_INFO *info);
 619 static void isr_io_pin(SLMP_INFO *info, u16 status);
 620
 621 static int  alloc_dma_bufs(SLMP_INFO *info);
 622 static void free_dma_bufs(SLMP_INFO *info);
 623 static int  alloc_buf_list(SLMP_INFO *info);
 624 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 625 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 626 static void free_tmp_rx_buf(SLMP_INFO *info);
 627
 628 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 629 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 630 static void tx_timeout(unsigned long context);
 631 static void status_timeout(unsigned long context);
 632
 633 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 634 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 635 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 636 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 637 static unsigned char read_status_reg(SLMP_INFO * info);
 638 static void write_control_reg(SLMP_INFO * info);
 639
 640
 641 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 642 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 643 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 644
 645 static u32 misc_ctrl_value = 0x007e4040;
 646 static u32 lcr1_brdr_value = 0x00800028;
 647
 648 static u32 read_ahead_count = 8;
 649
 650 /* DPCR, DMA Priority Control
 651  *
 652  * 07..05  Not used, must be 0
 653  * 04      BRC, bus release condition: 0=all transfers complete
 654  *              1=release after 1 xfer on all channels
 655  * 03      CCC, channel change condition: 0=every cycle
 656  *              1=after each channel completes all xfers
 657  * 02..00  PR<2..0>, priority 100=round robin
 658  *
 659  * 00000100 = 0x00
 660  */
 661 static unsigned char dma_priority = 0x04;
 662
 663 // Number of bytes that can be written to shared RAM
 664 // in a single write operation
 665 static u32 sca_pci_load_interval = 64;
 666
 667 /*
 668  * 1st function defined in .text section. Calling this function in
 669  * init_module() followed by a breakpoint allows a remote debugger
 670  * (gdb) to get the .text address for the add-symbol-file command.
 671  * This allows remote debugging of dynamically loadable modules.
 672  */
 673 static void* synclinkmp_get_text_ptr(void);
 674 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 675
 676 static inline int sanity_check(SLMP_INFO *info,
 677                                char *name, const char *routine)
 678 {
 679 #ifdef SANITY_CHECK
 680         static const char *badmagic =
 681                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 682         static const char *badinfo =
 683                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 684
 685         if (!info) {
 686                 printk(badinfo, name, routine);
 687                 return 1;
 688         }
 689         if (info->magic != MGSL_MAGIC) {
 690                 printk(badmagic, name, routine);
 691                 return 1;
 692         }
 693 #else
 694         if (!info)
 695                 return 1;
 696 #endif
 697         return 0;
 698 }
 699
 700 /**
 701  * line discipline callback wrappers
 702  *
 703  * The wrappers maintain line discipline references
 704  * while calling into the line discipline.
 705  *
 706  * ldisc_receive_buf  - pass receive data to line discipline
 707  */
 708
 709 static void ldisc_receive_buf(struct tty_struct *tty,
 710                               const __u8 *data, char *flags, int count)
 711 {
 712         struct tty_ldisc *ld;
 713         if (!tty)
 714                 return;
 715         ld = tty_ldisc_ref(tty);
 716         if (ld) {
 717                 if (ld->receive_buf)
 718                         ld->receive_buf(tty, data, flags, count);
 719                 tty_ldisc_deref(ld);
 720         }
 721 }
 722
 723 /* tty callbacks */
 724
 725 /* Called when a port is opened.  Init and enable port.
 726  */
 727 static int open(struct tty_struct *tty, struct file *filp)
 728 {
 729         SLMP_INFO *info;
 730         int retval, line;
 731         unsigned long flags;
 732
 733         line = tty->index;
 734         if ((line < 0) || (line >= synclinkmp_device_count)) {
 735                 printk("%s(%d): open with invalid line #%d.\n",
 736                         __FILE__,__LINE__,line);
 737                 return -ENODEV;
 738         }
 739
 740         info = synclinkmp_device_list;
 741         while(info && info->line != line)
 742                 info = info->next_device;
 743         if (sanity_check(info, tty->name, "open"))
 744                 return -ENODEV;
 745         if ( info->init_error ) {
 746                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 747                         __FILE__,__LINE__,info->device_name,info->init_error);
 748                 return -ENODEV;
 749         }
 750
 751         tty->driver_data = info;
 752         info->tty = tty;
 753
 754         if (debug_level >= DEBUG_LEVEL_INFO)
 755                 printk("%s(%d):%s open(), old ref count = %d\n",
 756                          __FILE__,__LINE__,tty->driver->name, info->count);
 757
 758         /* If port is closing, signal caller to try again */
 759         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 760                 if (info->flags & ASYNC_CLOSING)
 761                         interruptible_sleep_on(&info->close_wait);
 762                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 763                         -EAGAIN : -ERESTARTSYS);
 764                 goto cleanup;
 765         }
 766
 767         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 768
 769         spin_lock_irqsave(&info->netlock, flags);
 770         if (info->netcount) {
 771                 retval = -EBUSY;
 772                 spin_unlock_irqrestore(&info->netlock, flags);
 773                 goto cleanup;
 774         }
 775         info->count++;
 776         spin_unlock_irqrestore(&info->netlock, flags);
 777
 778         if (info->count == 1) {
 779                 /* 1st open on this device, init hardware */
 780                 retval = startup(info);
 781                 if (retval < 0)
 782                         goto cleanup;
 783         }
 784
 785         retval = block_til_ready(tty, filp, info);
 786         if (retval) {
 787                 if (debug_level >= DEBUG_LEVEL_INFO)
 788                         printk("%s(%d):%s block_til_ready() returned %d\n",
 789                                  __FILE__,__LINE__, info->device_name, retval);
 790                 goto cleanup;
 791         }
 792
 793         if (debug_level >= DEBUG_LEVEL_INFO)
 794                 printk("%s(%d):%s open() success\n",
 795                          __FILE__,__LINE__, info->device_name);
 796         retval = 0;
 797
 798 cleanup:
 799         if (retval) {
 800                 if (tty->count == 1)
 801                         info->tty = NULL; /* tty layer will release tty struct */
 802                 if(info->count)
 803                         info->count--;
 804         }
 805
 806         return retval;
 807 }
 808
 809 /* Called when port is closed. Wait for remaining data to be
 810  * sent. Disable port and free resources.
 811  */
 812 static void close(struct tty_struct *tty, struct file *filp)
 813 {
 814         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 815
 816         if (sanity_check(info, tty->name, "close"))
 817                 return;
 818
 819         if (debug_level >= DEBUG_LEVEL_INFO)
 820                 printk("%s(%d):%s close() entry, count=%d\n",
 821                          __FILE__,__LINE__, info->device_name, info->count);
 822
 823         if (!info->count)
 824                 return;
 825
 826         if (tty_hung_up_p(filp))
 827                 goto cleanup;
 828
 829         if ((tty->count == 1) && (info->count != 1)) {
 830                 /*
 831                  * tty->count is 1 and the tty structure will be freed.
 832                  * info->count should be one in this case.
 833                  * if it's not, correct it so that the port is shutdown.
 834                  */
 835                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 836                        "info->count is %d\n",
 837                          __FILE__,__LINE__, info->device_name, info->count);
 838                 info->count = 1;
 839         }
 840
 841         info->count--;
 842
 843         /* if at least one open remaining, leave hardware active */
 844         if (info->count)
 845                 goto cleanup;
 846
 847         info->flags |= ASYNC_CLOSING;
 848
 849         /* set tty->closing to notify line discipline to
 850          * only process XON/XOFF characters. Only the N_TTY
 851          * discipline appears to use this (ppp does not).
 852          */
 853         tty->closing = 1;
 854
 855         /* wait for transmit data to clear all layers */
 856
 857         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 858                 if (debug_level >= DEBUG_LEVEL_INFO)
 859                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 860                                  __FILE__,__LINE__, info->device_name );
 861                 tty_wait_until_sent(tty, info->closing_wait);
 862         }
 863
 864         if (info->flags & ASYNC_INITIALIZED)
 865                 wait_until_sent(tty, info->timeout);
 866
 867         if (tty->driver->flush_buffer)
 868                 tty->driver->flush_buffer(tty);
 869
 870         tty_ldisc_flush(tty);
 871
 872         shutdown(info);
 873
 874         tty->closing = 0;
 875         info->tty = NULL;
 876
 877         if (info->blocked_open) {
 878                 if (info->close_delay) {
 879                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 880                 }
 881                 wake_up_interruptible(&info->open_wait);
 882         }
 883
 884         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 885
 886         wake_up_interruptible(&info->close_wait);
 887
 888 cleanup:
 889         if (debug_level >= DEBUG_LEVEL_INFO)
 890                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 891                         tty->driver->name, info->count);
 892 }
 893
 894 /* Called by tty_hangup() when a hangup is signaled.
 895  * This is the same as closing all open descriptors for the port.
 896  */
 897 static void hangup(struct tty_struct *tty)
 898 {
 899         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 900
 901         if (debug_level >= DEBUG_LEVEL_INFO)
 902                 printk("%s(%d):%s hangup()\n",
 903                          __FILE__,__LINE__, info->device_name );
 904
 905         if (sanity_check(info, tty->name, "hangup"))
 906                 return;
 907
 908         flush_buffer(tty);
 909         shutdown(info);
 910
 911         info->count = 0;
 912         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 913         info->tty = NULL;
 914
 915         wake_up_interruptible(&info->open_wait);
 916 }
 917
 918 /* Set new termios settings
 919  */
 920 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 921 {
 922         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 923         unsigned long flags;
 924
 925         if (debug_level >= DEBUG_LEVEL_INFO)
 926                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 927                         tty->driver->name );
 928
 929         /* just return if nothing has changed */
 930         if ((tty->termios->c_cflag == old_termios->c_cflag)
 931             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 932                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 933           return;
 934
 935         change_params(info);
 936
 937         /* Handle transition to B0 status */
 938         if (old_termios->c_cflag & CBAUD &&
 939             !(tty->termios->c_cflag & CBAUD)) {
 940                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 941                 spin_lock_irqsave(&info->lock,flags);
 942                 set_signals(info);
 943                 spin_unlock_irqrestore(&info->lock,flags);
 944         }
 945
 946         /* Handle transition away from B0 status */
 947         if (!(old_termios->c_cflag & CBAUD) &&
 948             tty->termios->c_cflag & CBAUD) {
 949                 info->serial_signals |= SerialSignal_DTR;
 950                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 951                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 952                         info->serial_signals |= SerialSignal_RTS;
 953                 }
 954                 spin_lock_irqsave(&info->lock,flags);
 955                 set_signals(info);
 956                 spin_unlock_irqrestore(&info->lock,flags);
 957         }
 958
 959         /* Handle turning off CRTSCTS */
 960         if (old_termios->c_cflag & CRTSCTS &&
 961             !(tty->termios->c_cflag & CRTSCTS)) {
 962                 tty->hw_stopped = 0;
 963                 tx_release(tty);
 964         }
 965 }
 966
 967 /* Send a block of data
 968  *
 969  * Arguments:
 970  *
 971  *      tty             pointer to tty information structure
 972  *      buf             pointer to buffer containing send data
 973  *      count           size of send data in bytes
 974  *
 975  * Return Value:        number of characters written
 976  */
 977 static int write(struct tty_struct *tty,
 978                  const unsigned char *buf, int count)
 979 {
 980         int     c, ret = 0;
 981         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 982         unsigned long flags;
 983
 984         if (debug_level >= DEBUG_LEVEL_INFO)
 985                 printk("%s(%d):%s write() count=%d\n",
 986                        __FILE__,__LINE__,info->device_name,count);
 987
 988         if (sanity_check(info, tty->name, "write"))
 989                 goto cleanup;
 990
 991         if (!tty || !info->tx_buf)
 992                 goto cleanup;
 993
 994         if (info->params.mode == MGSL_MODE_HDLC) {
 995                 if (count > info->max_frame_size) {
 996                         ret = -EIO;
 997                         goto cleanup;
 998                 }
 999                 if (info->tx_active)
1000                         goto cleanup;
1001                 if (info->tx_count) {
1002                         /* send accumulated data from send_char() calls */
1003                         /* as frame and wait before accepting more data. */
1004                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1005                         goto start;
1006                 }
1007                 ret = info->tx_count = count;
1008                 tx_load_dma_buffer(info, buf, count);
1009                 goto start;
1010         }
1011
1012         for (;;) {
1013                 c = min_t(int, count,
1014                         min(info->max_frame_size - info->tx_count - 1,
1015                             info->max_frame_size - info->tx_put));
1016                 if (c <= 0)
1017                         break;
1018
1019                 memcpy(info->tx_buf + info->tx_put, buf, c);
1020
1021                 spin_lock_irqsave(&info->lock,flags);
1022                 info->tx_put += c;
1023                 if (info->tx_put >= info->max_frame_size)
1024                         info->tx_put -= info->max_frame_size;
1025                 info->tx_count += c;
1026                 spin_unlock_irqrestore(&info->lock,flags);
1027
1028                 buf += c;
1029                 count -= c;
1030                 ret += c;
1031         }
1032
1033         if (info->params.mode == MGSL_MODE_HDLC) {
1034                 if (count) {
1035                         ret = info->tx_count = 0;
1036                         goto cleanup;
1037                 }
1038                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1039         }
1040 start:
1041         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1042                 spin_lock_irqsave(&info->lock,flags);
1043                 if (!info->tx_active)
1044                         tx_start(info);
1045                 spin_unlock_irqrestore(&info->lock,flags);
1046         }
1047
1048 cleanup:
1049         if (debug_level >= DEBUG_LEVEL_INFO)
1050                 printk( "%s(%d):%s write() returning=%d\n",
1051                         __FILE__,__LINE__,info->device_name,ret);
1052         return ret;
1053 }
1054
1055 /* Add a character to the transmit buffer.
1056  */
1057 static void put_char(struct tty_struct *tty, unsigned char ch)
1058 {
1059         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1060         unsigned long flags;
1061
1062         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1063                 printk( "%s(%d):%s put_char(%d)\n",
1064                         __FILE__,__LINE__,info->device_name,ch);
1065         }
1066
1067         if (sanity_check(info, tty->name, "put_char"))
1068                 return;
1069
1070         if (!tty || !info->tx_buf)
1071                 return;
1072
1073         spin_lock_irqsave(&info->lock,flags);
1074
1075         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1076              !info->tx_active ) {
1077
1078                 if (info->tx_count < info->max_frame_size - 1) {
1079                         info->tx_buf[info->tx_put++] = ch;
1080                         if (info->tx_put >= info->max_frame_size)
1081                                 info->tx_put -= info->max_frame_size;
1082                         info->tx_count++;
1083                 }
1084         }
1085
1086         spin_unlock_irqrestore(&info->lock,flags);
1087 }
1088
1089 /* Send a high-priority XON/XOFF character
1090  */
1091 static void send_xchar(struct tty_struct *tty, char ch)
1092 {
1093         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1094         unsigned long flags;
1095
1096         if (debug_level >= DEBUG_LEVEL_INFO)
1097                 printk("%s(%d):%s send_xchar(%d)\n",
1098                          __FILE__,__LINE__, info->device_name, ch );
1099
1100         if (sanity_check(info, tty->name, "send_xchar"))
1101                 return;
1102
1103         info->x_char = ch;
1104         if (ch) {
1105                 /* Make sure transmit interrupts are on */
1106                 spin_lock_irqsave(&info->lock,flags);
1107                 if (!info->tx_enabled)
1108                         tx_start(info);
1109                 spin_unlock_irqrestore(&info->lock,flags);
1110         }
1111 }
1112
1113 /* Wait until the transmitter is empty.
1114  */
1115 static void wait_until_sent(struct tty_struct *tty, int timeout)
1116 {
1117         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1118         unsigned long orig_jiffies, char_time;
1119
1120         if (!info )
1121                 return;
1122
1123         if (debug_level >= DEBUG_LEVEL_INFO)
1124                 printk("%s(%d):%s wait_until_sent() entry\n",
1125                          __FILE__,__LINE__, info->device_name );
1126
1127         if (sanity_check(info, tty->name, "wait_until_sent"))
1128                 return;
1129
1130         if (!(info->flags & ASYNC_INITIALIZED))
1131                 goto exit;
1132
1133         orig_jiffies = jiffies;
1134
1135         /* Set check interval to 1/5 of estimated time to
1136          * send a character, and make it at least 1. The check
1137          * interval should also be less than the timeout.
1138          * Note: use tight timings here to satisfy the NIST-PCTS.
1139          */
1140
1141         if ( info->params.data_rate ) {
1142                 char_time = info->timeout/(32 * 5);
1143                 if (!char_time)
1144                         char_time++;
1145         } else
1146                 char_time = 1;
1147
1148         if (timeout)
1149                 char_time = min_t(unsigned long, char_time, timeout);
1150
1151         if ( info->params.mode == MGSL_MODE_HDLC ) {
1152                 while (info->tx_active) {
1153                         msleep_interruptible(jiffies_to_msecs(char_time));
1154                         if (signal_pending(current))
1155                                 break;
1156                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1157                                 break;
1158                 }
1159         } else {
1160                 //TODO: determine if there is something similar to USC16C32
1161                 //      TXSTATUS_ALL_SENT status
1162                 while ( info->tx_active && info->tx_enabled) {
1163                         msleep_interruptible(jiffies_to_msecs(char_time));
1164                         if (signal_pending(current))
1165                                 break;
1166                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1167                                 break;
1168                 }
1169         }
1170
1171 exit:
1172         if (debug_level >= DEBUG_LEVEL_INFO)
1173                 printk("%s(%d):%s wait_until_sent() exit\n",
1174                          __FILE__,__LINE__, info->device_name );
1175 }
1176
1177 /* Return the count of free bytes in transmit buffer
1178  */
1179 static int write_room(struct tty_struct *tty)
1180 {
1181         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1182         int ret;
1183
1184         if (sanity_check(info, tty->name, "write_room"))
1185                 return 0;
1186
1187         if (info->params.mode == MGSL_MODE_HDLC) {
1188                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1189         } else {
1190                 ret = info->max_frame_size - info->tx_count - 1;
1191                 if (ret < 0)
1192                         ret = 0;
1193         }
1194
1195         if (debug_level >= DEBUG_LEVEL_INFO)
1196                 printk("%s(%d):%s write_room()=%d\n",
1197                        __FILE__, __LINE__, info->device_name, ret);
1198
1199         return ret;
1200 }
1201
1202 /* enable transmitter and send remaining buffered characters
1203  */
1204 static void flush_chars(struct tty_struct *tty)
1205 {
1206         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1207         unsigned long flags;
1208
1209         if ( debug_level >= DEBUG_LEVEL_INFO )
1210                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1211                         __FILE__,__LINE__,info->device_name,info->tx_count);
1212
1213         if (sanity_check(info, tty->name, "flush_chars"))
1214                 return;
1215
1216         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1217             !info->tx_buf)
1218                 return;
1219
1220         if ( debug_level >= DEBUG_LEVEL_INFO )
1221                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1222                         __FILE__,__LINE__,info->device_name );
1223
1224         spin_lock_irqsave(&info->lock,flags);
1225
1226         if (!info->tx_active) {
1227                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1228                         info->tx_count ) {
1229                         /* operating in synchronous (frame oriented) mode */
1230                         /* copy data from circular tx_buf to */
1231                         /* transmit DMA buffer. */
1232                         tx_load_dma_buffer(info,
1233                                  info->tx_buf,info->tx_count);
1234                 }
1235                 tx_start(info);
1236         }
1237
1238         spin_unlock_irqrestore(&info->lock,flags);
1239 }
1240
1241 /* Discard all data in the send buffer
1242  */
1243 static void flush_buffer(struct tty_struct *tty)
1244 {
1245         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1246         unsigned long flags;
1247
1248         if (debug_level >= DEBUG_LEVEL_INFO)
1249                 printk("%s(%d):%s flush_buffer() entry\n",
1250                          __FILE__,__LINE__, info->device_name );
1251
1252         if (sanity_check(info, tty->name, "flush_buffer"))
1253                 return;
1254
1255         spin_lock_irqsave(&info->lock,flags);
1256         info->tx_count = info->tx_put = info->tx_get = 0;
1257         del_timer(&info->tx_timer);
1258         spin_unlock_irqrestore(&info->lock,flags);
1259
1260         wake_up_interruptible(&tty->write_wait);
1261         tty_wakeup(tty);
1262 }
1263
1264 /* throttle (stop) transmitter
1265  */
1266 static void tx_hold(struct tty_struct *tty)
1267 {
1268         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1269         unsigned long flags;
1270
1271         if (sanity_check(info, tty->name, "tx_hold"))
1272                 return;
1273
1274         if ( debug_level >= DEBUG_LEVEL_INFO )
1275                 printk("%s(%d):%s tx_hold()\n",
1276                         __FILE__,__LINE__,info->device_name);
1277
1278         spin_lock_irqsave(&info->lock,flags);
1279         if (info->tx_enabled)
1280                 tx_stop(info);
1281         spin_unlock_irqrestore(&info->lock,flags);
1282 }
1283
1284 /* release (start) transmitter
1285  */
1286 static void tx_release(struct tty_struct *tty)
1287 {
1288         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1289         unsigned long flags;
1290
1291         if (sanity_check(info, tty->name, "tx_release"))
1292                 return;
1293
1294         if ( debug_level >= DEBUG_LEVEL_INFO )
1295                 printk("%s(%d):%s tx_release()\n",
1296                         __FILE__,__LINE__,info->device_name);
1297
1298         spin_lock_irqsave(&info->lock,flags);
1299         if (!info->tx_enabled)
1300                 tx_start(info);
1301         spin_unlock_irqrestore(&info->lock,flags);
1302 }
1303
1304 /* Service an IOCTL request
1305  *
1306  * Arguments:
1307  *
1308  *      tty     pointer to tty instance data
1309  *      file    pointer to associated file object for device
1310  *      cmd     IOCTL command code
1311  *      arg     command argument/context
1312  *
1313  * Return Value:        0 if success, otherwise error code
1314  */
1315 static int ioctl(struct tty_struct *tty, struct file *file,
1316                  unsigned int cmd, unsigned long arg)
1317 {
1318         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1319         int error;
1320         struct mgsl_icount cnow;        /* kernel counter temps */
1321         struct serial_icounter_struct __user *p_cuser;  /* user space */
1322         unsigned long flags;
1323         void __user *argp = (void __user *)arg;
1324
1325         if (debug_level >= DEBUG_LEVEL_INFO)
1326                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1327                         info->device_name, cmd );
1328
1329         if (sanity_check(info, tty->name, "ioctl"))
1330                 return -ENODEV;
1331
1332         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1333             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1334                 if (tty->flags & (1 << TTY_IO_ERROR))
1335                     return -EIO;
1336         }
1337
1338         switch (cmd) {
1339         case MGSL_IOCGPARAMS:
1340                 return get_params(info, argp);
1341         case MGSL_IOCSPARAMS:
1342                 return set_params(info, argp);
1343         case MGSL_IOCGTXIDLE:
1344                 return get_txidle(info, argp);
1345         case MGSL_IOCSTXIDLE:
1346                 return set_txidle(info, (int)arg);
1347         case MGSL_IOCTXENABLE:
1348                 return tx_enable(info, (int)arg);
1349         case MGSL_IOCRXENABLE:
1350                 return rx_enable(info, (int)arg);
1351         case MGSL_IOCTXABORT:
1352                 return tx_abort(info);
1353         case MGSL_IOCGSTATS:
1354                 return get_stats(info, argp);
1355         case MGSL_IOCWAITEVENT:
1356                 return wait_mgsl_event(info, argp);
1357         case MGSL_IOCLOOPTXDONE:
1358                 return 0; // TODO: Not supported, need to document
1359                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1360                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1361                  */
1362         case TIOCMIWAIT:
1363                 return modem_input_wait(info,(int)arg);
1364
1365                 /*
1366                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1367                  * Return: write counters to the user passed counter struct
1368                  * NB: both 1->0 and 0->1 transitions are counted except for
1369                  *     RI where only 0->1 is counted.
1370                  */
1371         case TIOCGICOUNT:
1372                 spin_lock_irqsave(&info->lock,flags);
1373                 cnow = info->icount;
1374                 spin_unlock_irqrestore(&info->lock,flags);
1375                 p_cuser = argp;
1376                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1377                 if (error) return error;
1378                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1379                 if (error) return error;
1380                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1381                 if (error) return error;
1382                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1383                 if (error) return error;
1384                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1385                 if (error) return error;
1386                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1387                 if (error) return error;
1388                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1389                 if (error) return error;
1390                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1391                 if (error) return error;
1392                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1393                 if (error) return error;
1394                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1395                 if (error) return error;
1396                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1397                 if (error) return error;
1398                 return 0;
1399         default:
1400                 return -ENOIOCTLCMD;
1401         }
1402         return 0;
1403 }
1404
1405 /*
1406  * /proc fs routines....
1407  */
1408
1409 static inline int line_info(char *buf, SLMP_INFO *info)
1410 {
1411         char    stat_buf[30];
1412         int     ret;
1413         unsigned long flags;
1414
1415         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1416                        "\tIRQ=%d MaxFrameSize=%u\n",
1417                 info->device_name,
1418                 info->phys_sca_base,
1419                 info->phys_memory_base,
1420                 info->phys_statctrl_base,
1421                 info->phys_lcr_base,
1422                 info->irq_level,
1423                 info->max_frame_size );
1424
1425         /* output current serial signal states */
1426         spin_lock_irqsave(&info->lock,flags);
1427         get_signals(info);
1428         spin_unlock_irqrestore(&info->lock,flags);
1429
1430         stat_buf[0] = 0;
1431         stat_buf[1] = 0;
1432         if (info->serial_signals & SerialSignal_RTS)
1433                 strcat(stat_buf, "|RTS");
1434         if (info->serial_signals & SerialSignal_CTS)
1435                 strcat(stat_buf, "|CTS");
1436         if (info->serial_signals & SerialSignal_DTR)
1437                 strcat(stat_buf, "|DTR");
1438         if (info->serial_signals & SerialSignal_DSR)
1439                 strcat(stat_buf, "|DSR");
1440         if (info->serial_signals & SerialSignal_DCD)
1441                 strcat(stat_buf, "|CD");
1442         if (info->serial_signals & SerialSignal_RI)
1443                 strcat(stat_buf, "|RI");
1444
1445         if (info->params.mode == MGSL_MODE_HDLC) {
1446                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1447                               info->icount.txok, info->icount.rxok);
1448                 if (info->icount.txunder)
1449                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1450                 if (info->icount.txabort)
1451                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1452                 if (info->icount.rxshort)
1453                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1454                 if (info->icount.rxlong)
1455                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1456                 if (info->icount.rxover)
1457                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1458                 if (info->icount.rxcrc)
1459                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1460         } else {
1461                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1462                               info->icount.tx, info->icount.rx);
1463                 if (info->icount.frame)
1464                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1465                 if (info->icount.parity)
1466                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1467                 if (info->icount.brk)
1468                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1469                 if (info->icount.overrun)
1470                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1471         }
1472
1473         /* Append serial signal status to end */
1474         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1475
1476         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1477          info->tx_active,info->bh_requested,info->bh_running,
1478          info->pending_bh);
1479
1480         return ret;
1481 }
1482
1483 /* Called to print information about devices
1484  */
1485 int read_proc(char *page, char **start, off_t off, int count,
1486               int *eof, void *data)
1487 {
1488         int len = 0, l;
1489         off_t   begin = 0;
1490         SLMP_INFO *info;
1491
1492         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1493
1494         info = synclinkmp_device_list;
1495         while( info ) {
1496                 l = line_info(page + len, info);
1497                 len += l;
1498                 if (len+begin > off+count)
1499                         goto done;
1500                 if (len+begin < off) {
1501                         begin += len;
1502                         len = 0;
1503                 }
1504                 info = info->next_device;
1505         }
1506
1507         *eof = 1;
1508 done:
1509         if (off >= len+begin)
1510                 return 0;
1511         *start = page + (off-begin);
1512         return ((count < begin+len-off) ? count : begin+len-off);
1513 }
1514
1515 /* Return the count of bytes in transmit buffer
1516  */
1517 static int chars_in_buffer(struct tty_struct *tty)
1518 {
1519         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1520
1521         if (sanity_check(info, tty->name, "chars_in_buffer"))
1522                 return 0;
1523
1524         if (debug_level >= DEBUG_LEVEL_INFO)
1525                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1526                        __FILE__, __LINE__, info->device_name, info->tx_count);
1527
1528         return info->tx_count;
1529 }
1530
1531 /* Signal remote device to throttle send data (our receive data)
1532  */
1533 static void throttle(struct tty_struct * tty)
1534 {
1535         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1536         unsigned long flags;
1537
1538         if (debug_level >= DEBUG_LEVEL_INFO)
1539                 printk("%s(%d):%s throttle() entry\n",
1540                          __FILE__,__LINE__, info->device_name );
1541
1542         if (sanity_check(info, tty->name, "throttle"))
1543                 return;
1544
1545         if (I_IXOFF(tty))
1546                 send_xchar(tty, STOP_CHAR(tty));
1547
1548         if (tty->termios->c_cflag & CRTSCTS) {
1549                 spin_lock_irqsave(&info->lock,flags);
1550                 info->serial_signals &= ~SerialSignal_RTS;
1551                 set_signals(info);
1552                 spin_unlock_irqrestore(&info->lock,flags);
1553         }
1554 }
1555
1556 /* Signal remote device to stop throttling send data (our receive data)
1557  */
1558 static void unthrottle(struct tty_struct * tty)
1559 {
1560         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1561         unsigned long flags;
1562
1563         if (debug_level >= DEBUG_LEVEL_INFO)
1564                 printk("%s(%d):%s unthrottle() entry\n",
1565                          __FILE__,__LINE__, info->device_name );
1566
1567         if (sanity_check(info, tty->name, "unthrottle"))
1568                 return;
1569
1570         if (I_IXOFF(tty)) {
1571                 if (info->x_char)
1572                         info->x_char = 0;
1573                 else
1574                         send_xchar(tty, START_CHAR(tty));
1575         }
1576
1577         if (tty->termios->c_cflag & CRTSCTS) {
1578                 spin_lock_irqsave(&info->lock,flags);
1579                 info->serial_signals |= SerialSignal_RTS;
1580                 set_signals(info);
1581                 spin_unlock_irqrestore(&info->lock,flags);
1582         }
1583 }
1584
1585 /* set or clear transmit break condition
1586  * break_state  -1=set break condition, 0=clear
1587  */
1588 static void set_break(struct tty_struct *tty, int break_state)
1589 {
1590         unsigned char RegValue;
1591         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1592         unsigned long flags;
1593
1594         if (debug_level >= DEBUG_LEVEL_INFO)
1595                 printk("%s(%d):%s set_break(%d)\n",
1596                          __FILE__,__LINE__, info->device_name, break_state);
1597
1598         if (sanity_check(info, tty->name, "set_break"))
1599                 return;
1600
1601         spin_lock_irqsave(&info->lock,flags);
1602         RegValue = read_reg(info, CTL);
1603         if (break_state == -1)
1604                 RegValue |= BIT3;
1605         else
1606                 RegValue &= ~BIT3;
1607         write_reg(info, CTL, RegValue);
1608         spin_unlock_irqrestore(&info->lock,flags);
1609 }
1610
1611 #ifdef CONFIG_HDLC
1612
1613 /**
1614  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1615  * set encoding and frame check sequence (FCS) options
1616  *
1617  * dev       pointer to network device structure
1618  * encoding  serial encoding setting
1619  * parity    FCS setting
1620  *
1621  * returns 0 if success, otherwise error code
1622  */
1623 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1624                           unsigned short parity)
1625 {
1626         SLMP_INFO *info = dev_to_port(dev);
1627         unsigned char  new_encoding;
1628         unsigned short new_crctype;
1629
1630         /* return error if TTY interface open */
1631         if (info->count)
1632                 return -EBUSY;
1633
1634         switch (encoding)
1635         {
1636         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1637         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1638         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1639         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1640         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1641         default: return -EINVAL;
1642         }
1643
1644         switch (parity)
1645         {
1646         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1647         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1648         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1649         default: return -EINVAL;
1650         }
1651
1652         info->params.encoding = new_encoding;
1653         info->params.crc_type = new_crctype;;
1654
1655         /* if network interface up, reprogram hardware */
1656         if (info->netcount)
1657                 program_hw(info);
1658
1659         return 0;
1660 }
1661
1662 /**
1663  * called by generic HDLC layer to send frame
1664  *
1665  * skb  socket buffer containing HDLC frame
1666  * dev  pointer to network device structure
1667  *
1668  * returns 0 if success, otherwise error code
1669  */
1670 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1671 {
1672         SLMP_INFO *info = dev_to_port(dev);
1673         struct net_device_stats *stats = hdlc_stats(dev);
1674         unsigned long flags;
1675
1676         if (debug_level >= DEBUG_LEVEL_INFO)
1677                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1678
1679         /* stop sending until this frame completes */
1680         netif_stop_queue(dev);
1681
1682         /* copy data to device buffers */
1683         info->tx_count = skb->len;
1684         tx_load_dma_buffer(info, skb->data, skb->len);
1685
1686         /* update network statistics */
1687         stats->tx_packets++;
1688         stats->tx_bytes += skb->len;
1689
1690         /* done with socket buffer, so free it */
1691         dev_kfree_skb(skb);
1692
1693         /* save start time for transmit timeout detection */
1694         dev->trans_start = jiffies;
1695
1696         /* start hardware transmitter if necessary */
1697         spin_lock_irqsave(&info->lock,flags);
1698         if (!info->tx_active)
1699                 tx_start(info);
1700         spin_unlock_irqrestore(&info->lock,flags);
1701
1702         return 0;
1703 }
1704
1705 /**
1706  * called by network layer when interface enabled
1707  * claim resources and initialize hardware
1708  *
1709  * dev  pointer to network device structure
1710  *
1711  * returns 0 if success, otherwise error code
1712  */
1713 static int hdlcdev_open(struct net_device *dev)
1714 {
1715         SLMP_INFO *info = dev_to_port(dev);
1716         int rc;
1717         unsigned long flags;
1718
1719         if (debug_level >= DEBUG_LEVEL_INFO)
1720                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1721
1722         /* generic HDLC layer open processing */
1723         if ((rc = hdlc_open(dev)))
1724                 return rc;
1725
1726         /* arbitrate between network and tty opens */
1727         spin_lock_irqsave(&info->netlock, flags);
1728         if (info->count != 0 || info->netcount != 0) {
1729                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1730                 spin_unlock_irqrestore(&info->netlock, flags);
1731                 return -EBUSY;
1732         }
1733         info->netcount=1;
1734         spin_unlock_irqrestore(&info->netlock, flags);
1735
1736         /* claim resources and init adapter */
1737         if ((rc = startup(info)) != 0) {
1738                 spin_lock_irqsave(&info->netlock, flags);
1739                 info->netcount=0;
1740                 spin_unlock_irqrestore(&info->netlock, flags);
1741                 return rc;
1742         }
1743
1744         /* assert DTR and RTS, apply hardware settings */
1745         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1746         program_hw(info);
1747
1748         /* enable network layer transmit */
1749         dev->trans_start = jiffies;
1750         netif_start_queue(dev);
1751
1752         /* inform generic HDLC layer of current DCD status */
1753         spin_lock_irqsave(&info->lock, flags);
1754         get_signals(info);
1755         spin_unlock_irqrestore(&info->lock, flags);
1756         hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
1757
1758         return 0;
1759 }
1760
1761 /**
1762  * called by network layer when interface is disabled
1763  * shutdown hardware and release resources
1764  *
1765  * dev  pointer to network device structure
1766  *
1767  * returns 0 if success, otherwise error code
1768  */
1769 static int hdlcdev_close(struct net_device *dev)
1770 {
1771         SLMP_INFO *info = dev_to_port(dev);
1772         unsigned long flags;
1773
1774         if (debug_level >= DEBUG_LEVEL_INFO)
1775                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1776
1777         netif_stop_queue(dev);
1778
1779         /* shutdown adapter and release resources */
1780         shutdown(info);
1781
1782         hdlc_close(dev);
1783
1784         spin_lock_irqsave(&info->netlock, flags);
1785         info->netcount=0;
1786         spin_unlock_irqrestore(&info->netlock, flags);
1787
1788         return 0;
1789 }
1790
1791 /**
1792  * called by network layer to process IOCTL call to network device
1793  *
1794  * dev  pointer to network device structure
1795  * ifr  pointer to network interface request structure
1796  * cmd  IOCTL command code
1797  *
1798  * returns 0 if success, otherwise error code
1799  */
1800 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1801 {
1802         const size_t size = sizeof(sync_serial_settings);
1803         sync_serial_settings new_line;
1804         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1805         SLMP_INFO *info = dev_to_port(dev);
1806         unsigned int flags;
1807
1808         if (debug_level >= DEBUG_LEVEL_INFO)
1809                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1810
1811         /* return error if TTY interface open */
1812         if (info->count)
1813                 return -EBUSY;
1814
1815         if (cmd != SIOCWANDEV)
1816                 return hdlc_ioctl(dev, ifr, cmd);
1817
1818         switch(ifr->ifr_settings.type) {
1819         case IF_GET_IFACE: /* return current sync_serial_settings */
1820
1821                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1822                 if (ifr->ifr_settings.size < size) {
1823                         ifr->ifr_settings.size = size; /* data size wanted */
1824                         return -ENOBUFS;
1825                 }
1826
1827                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1828                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1829                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1830                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1831
1832                 switch (flags){
1833                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1834                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1835                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1836                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1837                 default: new_line.clock_type = CLOCK_DEFAULT;
1838                 }
1839
1840                 new_line.clock_rate = info->params.clock_speed;
1841                 new_line.loopback   = info->params.loopback ? 1:0;
1842
1843                 if (copy_to_user(line, &new_line, size))
1844                         return -EFAULT;
1845                 return 0;
1846
1847         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1848
1849                 if(!capable(CAP_NET_ADMIN))
1850                         return -EPERM;
1851                 if (copy_from_user(&new_line, line, size))
1852                         return -EFAULT;
1853
1854                 switch (new_line.clock_type)
1855                 {
1856                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1857                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1858                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1859                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1860                 case CLOCK_DEFAULT:  flags = info->params.flags &
1861                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1862                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1863                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1864                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1865                 default: return -EINVAL;
1866                 }
1867
1868                 if (new_line.loopback != 0 && new_line.loopback != 1)
1869                         return -EINVAL;
1870
1871                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1872                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1873                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1874                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1875                 info->params.flags |= flags;
1876
1877                 info->params.loopback = new_line.loopback;
1878
1879                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1880                         info->params.clock_speed = new_line.clock_rate;
1881                 else
1882                         info->params.clock_speed = 0;
1883
1884                 /* if network interface up, reprogram hardware */
1885                 if (info->netcount)
1886                         program_hw(info);
1887                 return 0;
1888
1889         default:
1890                 return hdlc_ioctl(dev, ifr, cmd);
1891         }
1892 }
1893
1894 /**
1895  * called by network layer when transmit timeout is detected
1896  *
1897  * dev  pointer to network device structure
1898  */
1899 static void hdlcdev_tx_timeout(struct net_device *dev)
1900 {
1901         SLMP_INFO *info = dev_to_port(dev);
1902         struct net_device_stats *stats = hdlc_stats(dev);
1903         unsigned long flags;
1904
1905         if (debug_level >= DEBUG_LEVEL_INFO)
1906                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1907
1908         stats->tx_errors++;
1909         stats->tx_aborted_errors++;
1910
1911         spin_lock_irqsave(&info->lock,flags);
1912         tx_stop(info);
1913         spin_unlock_irqrestore(&info->lock,flags);
1914
1915         netif_wake_queue(dev);
1916 }
1917
1918 /**
1919  * called by device driver when transmit completes
1920  * reenable network layer transmit if stopped
1921  *
1922  * info  pointer to device instance information
1923  */
1924 static void hdlcdev_tx_done(SLMP_INFO *info)
1925 {
1926         if (netif_queue_stopped(info->netdev))
1927                 netif_wake_queue(info->netdev);
1928 }
1929
1930 /**
1931  * called by device driver when frame received
1932  * pass frame to network layer
1933  *
1934  * info  pointer to device instance information
1935  * buf   pointer to buffer contianing frame data
1936  * size  count of data bytes in buf
1937  */
1938 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1939 {
1940         struct sk_buff *skb = dev_alloc_skb(size);
1941         struct net_device *dev = info->netdev;
1942         struct net_device_stats *stats = hdlc_stats(dev);
1943
1944         if (debug_level >= DEBUG_LEVEL_INFO)
1945                 printk("hdlcdev_rx(%s)\n",dev->name);
1946
1947         if (skb == NULL) {
1948                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1949                 stats->rx_dropped++;
1950                 return;
1951         }
1952
1953         memcpy(skb_put(skb, size),buf,size);
1954
1955         skb->protocol = hdlc_type_trans(skb, info->netdev);
1956
1957         stats->rx_packets++;
1958         stats->rx_bytes += size;
1959
1960         netif_rx(skb);
1961
1962         info->netdev->last_rx = jiffies;
1963 }
1964
1965 /**
1966  * called by device driver when adding device instance
1967  * do generic HDLC initialization
1968  *
1969  * info  pointer to device instance information
1970  *
1971  * returns 0 if success, otherwise error code
1972  */
1973 static int hdlcdev_init(SLMP_INFO *info)
1974 {
1975         int rc;
1976         struct net_device *dev;
1977         hdlc_device *hdlc;
1978
1979         /* allocate and initialize network and HDLC layer objects */
1980
1981         if (!(dev = alloc_hdlcdev(info))) {
1982                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1983                 return -ENOMEM;
1984         }
1985
1986         /* for network layer reporting purposes only */
1987         dev->mem_start = info->phys_sca_base;
1988         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1989         dev->irq       = info->irq_level;
1990
1991         /* network layer callbacks and settings */
1992         dev->do_ioctl       = hdlcdev_ioctl;
1993         dev->open           = hdlcdev_open;
1994         dev->stop           = hdlcdev_close;
1995         dev->tx_timeout     = hdlcdev_tx_timeout;
1996         dev->watchdog_timeo = 10*HZ;
1997         dev->tx_queue_len   = 50;
1998
1999         /* generic HDLC layer callbacks and settings */
2000         hdlc         = dev_to_hdlc(dev);
2001         hdlc->attach = hdlcdev_attach;
2002         hdlc->xmit   = hdlcdev_xmit;
2003
2004         /* register objects with HDLC layer */
2005         if ((rc = register_hdlc_device(dev))) {
2006                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2007                 free_netdev(dev);
2008                 return rc;
2009         }
2010
2011         info->netdev = dev;
2012         return 0;
2013 }
2014
2015 /**
2016  * called by device driver when removing device instance
2017  * do generic HDLC cleanup
2018  *
2019  * info  pointer to device instance information
2020  */
2021 static void hdlcdev_exit(SLMP_INFO *info)
2022 {
2023         unregister_hdlc_device(info->netdev);
2024         free_netdev(info->netdev);
2025         info->netdev = NULL;
2026 }
2027
2028 #endif /* CONFIG_HDLC */
2029
2030
2031 /* Return next bottom half action to perform.
2032  * Return Value:        BH action code or 0 if nothing to do.
2033  */
2034 int bh_action(SLMP_INFO *info)
2035 {
2036         unsigned long flags;
2037         int rc = 0;
2038
2039         spin_lock_irqsave(&info->lock,flags);
2040
2041         if (info->pending_bh & BH_RECEIVE) {
2042                 info->pending_bh &= ~BH_RECEIVE;
2043                 rc = BH_RECEIVE;
2044         } else if (info->pending_bh & BH_TRANSMIT) {
2045                 info->pending_bh &= ~BH_TRANSMIT;
2046                 rc = BH_TRANSMIT;
2047         } else if (info->pending_bh & BH_STATUS) {
2048                 info->pending_bh &= ~BH_STATUS;
2049                 rc = BH_STATUS;
2050         }
2051
2052         if (!rc) {
2053                 /* Mark BH routine as complete */
2054                 info->bh_running   = 0;
2055                 info->bh_requested = 0;
2056         }
2057
2058         spin_unlock_irqrestore(&info->lock,flags);
2059
2060         return rc;
2061 }
2062
2063 /* Perform bottom half processing of work items queued by ISR.
2064  */
2065 void bh_handler(void* Context)
2066 {
2067         SLMP_INFO *info = (SLMP_INFO*)Context;
2068         int action;
2069
2070         if (!info)
2071                 return;
2072
2073         if ( debug_level >= DEBUG_LEVEL_BH )
2074                 printk( "%s(%d):%s bh_handler() entry\n",
2075                         __FILE__,__LINE__,info->device_name);
2076
2077         info->bh_running = 1;
2078
2079         while((action = bh_action(info)) != 0) {
2080
2081                 /* Process work item */
2082                 if ( debug_level >= DEBUG_LEVEL_BH )
2083                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2084                                 __FILE__,__LINE__,info->device_name, action);
2085
2086                 switch (action) {
2087
2088                 case BH_RECEIVE:
2089                         bh_receive(info);
2090                         break;
2091                 case BH_TRANSMIT:
2092                         bh_transmit(info);
2093                         break;
2094                 case BH_STATUS:
2095                         bh_status(info);
2096                         break;
2097                 default:
2098                         /* unknown work item ID */
2099                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2100                                 __FILE__,__LINE__,info->device_name,action);
2101                         break;
2102                 }
2103         }
2104
2105         if ( debug_level >= DEBUG_LEVEL_BH )
2106                 printk( "%s(%d):%s bh_handler() exit\n",
2107                         __FILE__,__LINE__,info->device_name);
2108 }
2109
2110 void bh_receive(SLMP_INFO *info)
2111 {
2112         if ( debug_level >= DEBUG_LEVEL_BH )
2113                 printk( "%s(%d):%s bh_receive()\n",
2114                         __FILE__,__LINE__,info->device_name);
2115
2116         while( rx_get_frame(info) );
2117 }
2118
2119 void bh_transmit(SLMP_INFO *info)
2120 {
2121         struct tty_struct *tty = info->tty;
2122
2123         if ( debug_level >= DEBUG_LEVEL_BH )
2124                 printk( "%s(%d):%s bh_transmit() entry\n",
2125                         __FILE__,__LINE__,info->device_name);
2126
2127         if (tty) {
2128                 tty_wakeup(tty);
2129                 wake_up_interruptible(&tty->write_wait);
2130         }
2131 }
2132
2133 void bh_status(SLMP_INFO *info)
2134 {
2135         if ( debug_level >= DEBUG_LEVEL_BH )
2136                 printk( "%s(%d):%s bh_status() entry\n",
2137                         __FILE__,__LINE__,info->device_name);
2138
2139         info->ri_chkcount = 0;
2140         info->dsr_chkcount = 0;
2141         info->dcd_chkcount = 0;
2142         info->cts_chkcount = 0;
2143 }
2144
2145 void isr_timer(SLMP_INFO * info)
2146 {
2147         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2148
2149         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2150         write_reg(info, IER2, 0);
2151
2152         /* TMCS, Timer Control/Status Register
2153          *
2154          * 07      CMF, Compare match flag (read only) 1=match
2155          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2156          * 05      Reserved, must be 0
2157          * 04      TME, Timer Enable
2158          * 03..00  Reserved, must be 0
2159          *
2160          * 0000 0000
2161          */
2162         write_reg(info, (unsigned char)(timer + TMCS), 0);
2163
2164         info->irq_occurred = TRUE;
2165
2166         if ( debug_level >= DEBUG_LEVEL_ISR )
2167                 printk("%s(%d):%s isr_timer()\n",
2168                         __FILE__,__LINE__,info->device_name);
2169 }
2170
2171 void isr_rxint(SLMP_INFO * info)
2172 {
2173         struct tty_struct *tty = info->tty;
2174         struct  mgsl_icount *icount = &info->icount;
2175         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2176         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2177
2178         /* clear status bits */
2179         if (status)
2180                 write_reg(info, SR1, status);
2181
2182         if (status2)
2183                 write_reg(info, SR2, status2);
2184
2185         if ( debug_level >= DEBUG_LEVEL_ISR )
2186                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2187                         __FILE__,__LINE__,info->device_name,status,status2);
2188
2189         if (info->params.mode == MGSL_MODE_ASYNC) {
2190                 if (status & BRKD) {
2191                         icount->brk++;
2192
2193                         /* process break detection if tty control
2194                          * is not set to ignore it
2195                          */
2196                         if ( tty ) {
2197                                 if (!(status & info->ignore_status_mask1)) {
2198                                         if (info->read_status_mask1 & BRKD) {
2199                                                 *tty->flip.flag_buf_ptr = TTY_BREAK;
2200                                                 if (info->flags & ASYNC_SAK)
2201                                                         do_SAK(tty);
2202                                         }
2203                                 }
2204                         }
2205                 }
2206         }
2207         else {
2208                 if (status & (FLGD|IDLD)) {
2209                         if (status & FLGD)
2210                                 info->icount.exithunt++;
2211                         else if (status & IDLD)
2212                                 info->icount.rxidle++;
2213                         wake_up_interruptible(&info->event_wait_q);
2214                 }
2215         }
2216
2217         if (status & CDCD) {
2218                 /* simulate a common modem status change interrupt
2219                  * for our handler
2220                  */
2221                 get_signals( info );
2222                 isr_io_pin(info,
2223                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2224         }
2225 }
2226
2227 /*
2228  * handle async rx data interrupts
2229  */
2230 void isr_rxrdy(SLMP_INFO * info)
2231 {
2232         u16 status;
2233         unsigned char DataByte;
2234         struct tty_struct *tty = info->tty;
2235         struct  mgsl_icount *icount = &info->icount;
2236
2237         if ( debug_level >= DEBUG_LEVEL_ISR )
2238                 printk("%s(%d):%s isr_rxrdy\n",
2239                         __FILE__,__LINE__,info->device_name);
2240
2241         while((status = read_reg(info,CST0)) & BIT0)
2242         {
2243                 DataByte = read_reg(info,TRB);
2244
2245                 if ( tty ) {
2246                         if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2247                                 continue;
2248
2249                         *tty->flip.char_buf_ptr = DataByte;
2250                         *tty->flip.flag_buf_ptr = 0;
2251                 }
2252
2253                 icount->rx++;
2254
2255                 if ( status & (PE + FRME + OVRN) ) {
2256                         printk("%s(%d):%s rxerr=%04X\n",
2257                                 __FILE__,__LINE__,info->device_name,status);
2258
2259                         /* update error statistics */
2260                         if (status & PE)
2261                                 icount->parity++;
2262                         else if (status & FRME)
2263                                 icount->frame++;
2264                         else if (status & OVRN)
2265                                 icount->overrun++;
2266
2267                         /* discard char if tty control flags say so */
2268                         if (status & info->ignore_status_mask2)
2269                                 continue;
2270
2271                         status &= info->read_status_mask2;
2272
2273                         if ( tty ) {
2274                                 if (status & PE)
2275                                         *tty->flip.flag_buf_ptr = TTY_PARITY;
2276                                 else if (status & FRME)
2277                                         *tty->flip.flag_buf_ptr = TTY_FRAME;
2278                                 if (status & OVRN) {
2279                                         /* Overrun is special, since it's
2280                                          * reported immediately, and doesn't
2281                                          * affect the current character
2282                                          */
2283                                         if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2284                                                 tty->flip.count++;
2285                                                 tty->flip.flag_buf_ptr++;
2286                                                 tty->flip.char_buf_ptr++;
2287                                                 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2288                                         }
2289                                 }
2290                         }
2291                 }       /* end of if (error) */
2292
2293                 if ( tty ) {
2294                         tty->flip.flag_buf_ptr++;
2295                         tty->flip.char_buf_ptr++;
2296                         tty->flip.count++;
2297                 }
2298         }
2299
2300         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2301                 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2302                         __FILE__,__LINE__,info->device_name,
2303                         tty ? tty->flip.count : 0);
2304                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2305                         __FILE__,__LINE__,info->device_name,
2306                         icount->rx,icount->brk,icount->parity,
2307                         icount->frame,icount->overrun);
2308         }
2309
2310         if ( tty && tty->flip.count )
2311                 tty_flip_buffer_push(tty);
2312 }
2313
2314 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2315 {
2316         if ( debug_level >= DEBUG_LEVEL_ISR )
2317                 printk("%s(%d):%s isr_txeom status=%02x\n",
2318                         __FILE__,__LINE__,info->device_name,status);
2319
2320         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2321         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2322         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2323
2324         if (status & UDRN) {
2325                 write_reg(info, CMD, TXRESET);
2326                 write_reg(info, CMD, TXENABLE);
2327         } else
2328                 write_reg(info, CMD, TXBUFCLR);
2329
2330         /* disable and clear tx interrupts */
2331         info->ie0_value &= ~TXRDYE;
2332         info->ie1_value &= ~(IDLE + UDRN);
2333         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2334         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2335
2336         if ( info->tx_active ) {
2337                 if (info->params.mode != MGSL_MODE_ASYNC) {
2338                         if (status & UDRN)
2339                                 info->icount.txunder++;
2340                         else if (status & IDLE)
2341                                 info->icount.txok++;
2342                 }
2343
2344                 info->tx_active = 0;
2345                 info->tx_count = info->tx_put = info->tx_get = 0;
2346
2347                 del_timer(&info->tx_timer);
2348
2349                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2350                         info->serial_signals &= ~SerialSignal_RTS;
2351                         info->drop_rts_on_tx_done = 0;
2352                         set_signals(info);
2353                 }
2354
2355 #ifdef CONFIG_HDLC
2356                 if (info->netcount)
2357                         hdlcdev_tx_done(info);
2358                 else
2359 #endif
2360                 {
2361                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2362                                 tx_stop(info);
2363                                 return;
2364                         }
2365                         info->pending_bh |= BH_TRANSMIT;
2366                 }
2367         }
2368 }
2369
2370
2371 /*
2372  * handle tx status interrupts
2373  */
2374 void isr_txint(SLMP_INFO * info)
2375 {
2376         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2377
2378         /* clear status bits */
2379         write_reg(info, SR1, status);
2380
2381         if ( debug_level >= DEBUG_LEVEL_ISR )
2382                 printk("%s(%d):%s isr_txint status=%02x\n",
2383                         __FILE__,__LINE__,info->device_name,status);
2384
2385         if (status & (UDRN + IDLE))
2386                 isr_txeom(info, status);
2387
2388         if (status & CCTS) {
2389                 /* simulate a common modem status change interrupt
2390                  * for our handler
2391                  */
2392                 get_signals( info );
2393                 isr_io_pin(info,
2394                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2395
2396         }
2397 }
2398
2399 /*
2400  * handle async tx data interrupts
2401  */
2402 void isr_txrdy(SLMP_INFO * info)
2403 {
2404         if ( debug_level >= DEBUG_LEVEL_ISR )
2405                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2406                         __FILE__,__LINE__,info->device_name,info->tx_count);
2407
2408         if (info->params.mode != MGSL_MODE_ASYNC) {
2409                 /* disable TXRDY IRQ, enable IDLE IRQ */
2410                 info->ie0_value &= ~TXRDYE;
2411                 info->ie1_value |= IDLE;
2412                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2413                 return;
2414         }
2415
2416         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2417                 tx_stop(info);
2418                 return;
2419         }
2420
2421         if ( info->tx_count )
2422                 tx_load_fifo( info );
2423         else {
2424                 info->tx_active = 0;
2425                 info->ie0_value &= ~TXRDYE;
2426                 write_reg(info, IE0, info->ie0_value);
2427         }
2428
2429         if (info->tx_count < WAKEUP_CHARS)
2430                 info->pending_bh |= BH_TRANSMIT;
2431 }
2432
2433 void isr_rxdmaok(SLMP_INFO * info)
2434 {
2435         /* BIT7 = EOT (end of transfer)
2436          * BIT6 = EOM (end of message/frame)
2437          */
2438         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2439
2440         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2441         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2442
2443         if ( debug_level >= DEBUG_LEVEL_ISR )
2444                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2445                         __FILE__,__LINE__,info->device_name,status);
2446
2447         info->pending_bh |= BH_RECEIVE;
2448 }
2449
2450 void isr_rxdmaerror(SLMP_INFO * info)
2451 {
2452         /* BIT5 = BOF (buffer overflow)
2453          * BIT4 = COF (counter overflow)
2454          */
2455         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2456
2457         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2458         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2459
2460         if ( debug_level >= DEBUG_LEVEL_ISR )
2461                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2462                         __FILE__,__LINE__,info->device_name,status);
2463
2464         info->rx_overflow = TRUE;
2465         info->pending_bh |= BH_RECEIVE;
2466 }
2467
2468 void isr_txdmaok(SLMP_INFO * info)
2469 {
2470         unsigned char status_reg1 = read_reg(info, SR1);
2471
2472         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2473         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2474         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2475
2476         if ( debug_level >= DEBUG_LEVEL_ISR )
2477                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2478                         __FILE__,__LINE__,info->device_name,status_reg1);
2479
2480         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2481         write_reg16(info, TRC0, 0);
2482         info->ie0_value |= TXRDYE;
2483         write_reg(info, IE0, info->ie0_value);
2484 }
2485
2486 void isr_txdmaerror(SLMP_INFO * info)
2487 {
2488         /* BIT5 = BOF (buffer overflow)
2489          * BIT4 = COF (counter overflow)
2490          */
2491         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2492
2493         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2494         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2495
2496         if ( debug_level >= DEBUG_LEVEL_ISR )
2497                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2498                         __FILE__,__LINE__,info->device_name,status);
2499 }
2500
2501 /* handle input serial signal changes
2502  */
2503 void isr_io_pin( SLMP_INFO *info, u16 status )
2504 {
2505         struct  mgsl_icount *icount;
2506
2507         if ( debug_level >= DEBUG_LEVEL_ISR )
2508                 printk("%s(%d):isr_io_pin status=%04X\n",
2509                         __FILE__,__LINE__,status);
2510
2511         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2512                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2513                 icount = &info->icount;
2514                 /* update input line counters */
2515                 if (status & MISCSTATUS_RI_LATCHED) {
2516                         icount->rng++;
2517                         if ( status & SerialSignal_RI )
2518                                 info->input_signal_events.ri_up++;
2519                         else
2520                                 info->input_signal_events.ri_down++;
2521                 }
2522                 if (status & MISCSTATUS_DSR_LATCHED) {
2523                         icount->dsr++;
2524                         if ( status & SerialSignal_DSR )
2525                                 info->input_signal_events.dsr_up++;
2526                         else
2527                                 info->input_signal_events.dsr_down++;
2528                 }
2529                 if (status & MISCSTATUS_DCD_LATCHED) {
2530                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2531                                 info->ie1_value &= ~CDCD;
2532                                 write_reg(info, IE1, info->ie1_value);
2533                         }
2534                         icount->dcd++;
2535                         if (status & SerialSignal_DCD) {
2536                                 info->input_signal_events.dcd_up++;
2537                         } else
2538                                 info->input_signal_events.dcd_down++;
2539 #ifdef CONFIG_HDLC
2540                         if (info->netcount)
2541                                 hdlc_set_carrier(status & SerialSignal_DCD, info->netdev);
2542 #endif
2543                 }
2544                 if (status & MISCSTATUS_CTS_LATCHED)
2545                 {
2546                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2547                                 info->ie1_value &= ~CCTS;
2548                                 write_reg(info, IE1, info->ie1_value);
2549                         }
2550                         icount->cts++;
2551                         if ( status & SerialSignal_CTS )
2552                                 info->input_signal_events.cts_up++;
2553                         else
2554                                 info->input_signal_events.cts_down++;
2555                 }
2556                 wake_up_interruptible(&info->status_event_wait_q);
2557                 wake_up_interruptible(&info->event_wait_q);
2558
2559                 if ( (info->flags & ASYNC_CHECK_CD) &&
2560                      (status & MISCSTATUS_DCD_LATCHED) ) {
2561                         if ( debug_level >= DEBUG_LEVEL_ISR )
2562                                 printk("%s CD now %s...", info->device_name,
2563                                        (status & SerialSignal_DCD) ? "on" : "off");
2564                         if (status & SerialSignal_DCD)
2565                                 wake_up_interruptible(&info->open_wait);
2566                         else {
2567                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2568                                         printk("doing serial hangup...");
2569                                 if (info->tty)
2570                                         tty_hangup(info->tty);
2571                         }
2572                 }
2573
2574                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2575                      (status & MISCSTATUS_CTS_LATCHED) ) {
2576                         if ( info->tty ) {
2577                                 if (info->tty->hw_stopped) {
2578                                         if (status & SerialSignal_CTS) {
2579                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2580                                                         printk("CTS tx start...");
2581                                                 info->tty->hw_stopped = 0;
2582                                                 tx_start(info);
2583                                                 info->pending_bh |= BH_TRANSMIT;
2584                                                 return;
2585                                         }
2586                                 } else {
2587                                         if (!(status & SerialSignal_CTS)) {
2588                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2589                                                         printk("CTS tx stop...");
2590                                                 info->tty->hw_stopped = 1;
2591                                                 tx_stop(info);
2592                                         }
2593                                 }
2594                         }
2595                 }
2596         }
2597
2598         info->pending_bh |= BH_STATUS;
2599 }
2600
2601 /* Interrupt service routine entry point.
2602  *
2603  * Arguments:
2604  *      irq             interrupt number that caused interrupt
2605  *      dev_id          device ID supplied during interrupt registration
2606  *      regs            interrupted processor context
2607  */
2608 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2609                                         struct pt_regs *regs)
2610 {
2611         SLMP_INFO * info;
2612         unsigned char status, status0, status1=0;
2613         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2614         unsigned char timerstatus0, timerstatus1=0;
2615         unsigned char shift;
2616         unsigned int i;
2617         unsigned short tmp;
2618
2619         if ( debug_level >= DEBUG_LEVEL_ISR )
2620                 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2621                         __FILE__,__LINE__,irq);
2622
2623         info = (SLMP_INFO *)dev_id;
2624         if (!info)
2625                 return IRQ_NONE;
2626
2627         spin_lock(&info->lock);
2628
2629         for(;;) {
2630
2631                 /* get status for SCA0 (ports 0-1) */
2632                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2633                 status0 = (unsigned char)tmp;
2634                 dmastatus0 = (unsigned char)(tmp>>8);
2635                 timerstatus0 = read_reg(info, ISR2);
2636
2637                 if ( debug_level >= DEBUG_LEVEL_ISR )
2638                         printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2639                                 __FILE__,__LINE__,info->device_name,
2640                                 status0,dmastatus0,timerstatus0);
2641
2642                 if (info->port_count == 4) {
2643                         /* get status for SCA1 (ports 2-3) */
2644                         tmp = read_reg16(info->port_array[2], ISR0);
2645                         status1 = (unsigned char)tmp;
2646                         dmastatus1 = (unsigned char)(tmp>>8);
2647                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2648
2649                         if ( debug_level >= DEBUG_LEVEL_ISR )
2650                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2651                                         __FILE__,__LINE__,info->device_name,
2652                                         status1,dmastatus1,timerstatus1);
2653                 }
2654
2655                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2656                          !status1 && !dmastatus1 && !timerstatus1)
2657                         break;
2658
2659                 for(i=0; i < info->port_count ; i++) {
2660                         if (info->port_array[i] == NULL)
2661                                 continue;
2662                         if (i < 2) {
2663                                 status = status0;
2664                                 dmastatus = dmastatus0;
2665                         } else {
2666                                 status = status1;
2667                                 dmastatus = dmastatus1;
2668                         }
2669
2670                         shift = i & 1 ? 4 :0;
2671
2672                         if (status & BIT0 << shift)
2673                                 isr_rxrdy(info->port_array[i]);
2674                         if (status & BIT1 << shift)
2675                                 isr_txrdy(info->port_array[i]);
2676                         if (status & BIT2 << shift)
2677                                 isr_rxint(info->port_array[i]);
2678                         if (status & BIT3 << shift)
2679                                 isr_txint(info->port_array[i]);
2680
2681                         if (dmastatus & BIT0 << shift)
2682                                 isr_rxdmaerror(info->port_array[i]);
2683                         if (dmastatus & BIT1 << shift)
2684                                 isr_rxdmaok(info->port_array[i]);
2685                         if (dmastatus & BIT2 << shift)
2686                                 isr_txdmaerror(info->port_array[i]);
2687                         if (dmastatus & BIT3 << shift)
2688                                 isr_txdmaok(info->port_array[i]);
2689                 }
2690
2691                 if (timerstatus0 & (BIT5 | BIT4))
2692                         isr_timer(info->port_array[0]);
2693                 if (timerstatus0 & (BIT7 | BIT6))
2694                         isr_timer(info->port_array[1]);
2695                 if (timerstatus1 & (BIT5 | BIT4))
2696                         isr_timer(info->port_array[2]);
2697                 if (timerstatus1 & (BIT7 | BIT6))
2698                         isr_timer(info->port_array[3]);
2699         }
2700
2701         for(i=0; i < info->port_count ; i++) {
2702                 SLMP_INFO * port = info->port_array[i];
2703
2704                 /* Request bottom half processing if there's something
2705                  * for it to do and the bh is not already running.
2706                  *
2707                  * Note: startup adapter diags require interrupts.
2708                  * do not request bottom half processing if the
2709                  * device is not open in a normal mode.
2710                  */
2711                 if ( port && (port->count || port->netcount) &&
2712                      port->pending_bh && !port->bh_running &&
2713                      !port->bh_requested ) {
2714                         if ( debug_level >= DEBUG_LEVEL_ISR )
2715                                 printk("%s(%d):%s queueing bh task.\n",
2716                                         __FILE__,__LINE__,port->device_name);
2717                         schedule_work(&port->task);
2718                         port->bh_requested = 1;
2719                 }
2720         }
2721
2722         spin_unlock(&info->lock);
2723
2724         if ( debug_level >= DEBUG_LEVEL_ISR )
2725                 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2726                         __FILE__,__LINE__,irq);
2727         return IRQ_HANDLED;
2728 }
2729
2730 /* Initialize and start device.
2731  */
2732 static int startup(SLMP_INFO * info)
2733 {
2734         if ( debug_level >= DEBUG_LEVEL_INFO )
2735                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2736
2737         if (info->flags & ASYNC_INITIALIZED)
2738                 return 0;
2739
2740         if (!info->tx_buf) {
2741                 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2742                 if (!info->tx_buf) {
2743                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2744                                 __FILE__,__LINE__,info->device_name);
2745                         return -ENOMEM;
2746                 }
2747         }
2748
2749         info->pending_bh = 0;
2750
2751         /* program hardware for current parameters */
2752         reset_port(info);
2753
2754         change_params(info);
2755
2756         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
2757         add_timer(&info->status_timer);
2758
2759         if (info->tty)
2760                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2761
2762         info->flags |= ASYNC_INITIALIZED;
2763
2764         return 0;
2765 }
2766
2767 /* Called by close() and hangup() to shutdown hardware
2768  */
2769 static void shutdown(SLMP_INFO * info)
2770 {
2771         unsigned long flags;
2772
2773         if (!(info->flags & ASYNC_INITIALIZED))
2774                 return;
2775
2776         if (debug_level >= DEBUG_LEVEL_INFO)
2777                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2778                          __FILE__,__LINE__, info->device_name );
2779
2780         /* clear status wait queue because status changes */
2781         /* can't happen after shutting down the hardware */
2782         wake_up_interruptible(&info->status_event_wait_q);
2783         wake_up_interruptible(&info->event_wait_q);
2784
2785         del_timer(&info->tx_timer);
2786         del_timer(&info->status_timer);
2787
2788         if (info->tx_buf) {
2789                 kfree(info->tx_buf);
2790                 info->tx_buf = NULL;
2791         }
2792
2793         spin_lock_irqsave(&info->lock,flags);
2794
2795         reset_port(info);
2796
2797         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2798                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2799                 set_signals(info);
2800         }
2801
2802         spin_unlock_irqrestore(&info->lock,flags);
2803
2804         if (info->tty)
2805                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2806
2807         info->flags &= ~ASYNC_INITIALIZED;
2808 }
2809
2810 static void program_hw(SLMP_INFO *info)
2811 {
2812         unsigned long flags;
2813
2814         spin_lock_irqsave(&info->lock,flags);
2815
2816         rx_stop(info);
2817         tx_stop(info);
2818
2819         info->tx_count = info->tx_put = info->tx_get = 0;
2820
2821         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2822                 hdlc_mode(info);
2823         else
2824                 async_mode(info);
2825
2826         set_signals(info);
2827
2828         info->dcd_chkcount = 0;
2829         info->cts_chkcount = 0;
2830         info->ri_chkcount = 0;
2831         info->dsr_chkcount = 0;
2832
2833         info->ie1_value |= (CDCD|CCTS);
2834         write_reg(info, IE1, info->ie1_value);
2835
2836         get_signals(info);
2837
2838         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2839                 rx_start(info);
2840
2841         spin_unlock_irqrestore(&info->lock,flags);
2842 }
2843
2844 /* Reconfigure adapter based on new parameters
2845  */
2846 static void change_params(SLMP_INFO *info)
2847 {
2848         unsigned cflag;
2849         int bits_per_char;
2850
2851         if (!info->tty || !info->tty->termios)
2852                 return;
2853
2854         if (debug_level >= DEBUG_LEVEL_INFO)
2855                 printk("%s(%d):%s change_params()\n",
2856                          __FILE__,__LINE__, info->device_name );
2857
2858         cflag = info->tty->termios->c_cflag;
2859
2860         /* if B0 rate (hangup) specified then negate DTR and RTS */
2861         /* otherwise assert DTR and RTS */
2862         if (cflag & CBAUD)
2863                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2864         else
2865                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2866
2867         /* byte size and parity */
2868
2869         switch (cflag & CSIZE) {
2870               case CS5: info->params.data_bits = 5; break;
2871               case CS6: info->params.data_bits = 6; break;
2872               case CS7: info->params.data_bits = 7; break;
2873               case CS8: info->params.data_bits = 8; break;
2874               /* Never happens, but GCC is too dumb to figure it out */
2875               default:  info->params.data_bits = 7; break;
2876               }
2877
2878         if (cflag & CSTOPB)
2879                 info->params.stop_bits = 2;
2880         else
2881                 info->params.stop_bits = 1;
2882
2883         info->params.parity = ASYNC_PARITY_NONE;
2884         if (cflag & PARENB) {
2885                 if (cflag & PARODD)
2886                         info->params.parity = ASYNC_PARITY_ODD;
2887                 else
2888                         info->params.parity = ASYNC_PARITY_EVEN;
2889 #ifdef CMSPAR
2890                 if (cflag & CMSPAR)
2891                         info->params.parity = ASYNC_PARITY_SPACE;
2892 #endif
2893         }
2894
2895         /* calculate number of jiffies to transmit a full
2896          * FIFO (32 bytes) at specified data rate
2897          */
2898         bits_per_char = info->params.data_bits +
2899                         info->params.stop_bits + 1;
2900
2901         /* if port data rate is set to 460800 or less then
2902          * allow tty settings to override, otherwise keep the
2903          * current data rate.
2904          */
2905         if (info->params.data_rate <= 460800) {
2906                 info->params.data_rate = tty_get_baud_rate(info->tty);
2907         }
2908
2909         if ( info->params.data_rate ) {
2910                 info->timeout = (32*HZ*bits_per_char) /
2911                                 info->params.data_rate;
2912         }
2913         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2914
2915         if (cflag & CRTSCTS)
2916                 info->flags |= ASYNC_CTS_FLOW;
2917         else
2918                 info->flags &= ~ASYNC_CTS_FLOW;
2919
2920         if (cflag & CLOCAL)
2921                 info->flags &= ~ASYNC_CHECK_CD;
2922         else
2923                 info->flags |= ASYNC_CHECK_CD;
2924
2925         /* process tty input control flags */
2926
2927         info->read_status_mask2 = OVRN;
2928         if (I_INPCK(info->tty))
2929                 info->read_status_mask2 |= PE | FRME;
2930         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2931                 info->read_status_mask1 |= BRKD;
2932         if (I_IGNPAR(info->tty))
2933                 info->ignore_status_mask2 |= PE | FRME;
2934         if (I_IGNBRK(info->tty)) {
2935                 info->ignore_status_mask1 |= BRKD;
2936                 /* If ignoring parity and break indicators, ignore
2937                  * overruns too.  (For real raw support).
2938                  */
2939                 if (I_IGNPAR(info->tty))
2940                         info->ignore_status_mask2 |= OVRN;
2941         }
2942
2943         program_hw(info);
2944 }
2945
2946 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2947 {
2948         int err;
2949
2950         if (debug_level >= DEBUG_LEVEL_INFO)
2951                 printk("%s(%d):%s get_params()\n",
2952                          __FILE__,__LINE__, info->device_name);
2953
2954         COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2955         if (err) {
2956                 if ( debug_level >= DEBUG_LEVEL_INFO )
2957                         printk( "%s(%d):%s get_stats() user buffer copy failed\n",
2958                                 __FILE__,__LINE__,info->device_name);
2959                 return -EFAULT;
2960         }
2961
2962         return 0;
2963 }
2964
2965 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2966 {
2967         int err;
2968         if (debug_level >= DEBUG_LEVEL_INFO)
2969                 printk("%s(%d):%s get_params()\n",
2970                          __FILE__,__LINE__, info->device_name);
2971
2972         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2973         if (err) {
2974                 if ( debug_level >= DEBUG_LEVEL_INFO )
2975                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2976                                 __FILE__,__LINE__,info->device_name);
2977                 return -EFAULT;
2978         }
2979
2980         return 0;
2981 }
2982
2983 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2984 {
2985         unsigned long flags;
2986         MGSL_PARAMS tmp_params;
2987         int err;
2988
2989         if (debug_level >= DEBUG_LEVEL_INFO)
2990                 printk("%s(%d):%s set_params\n",
2991                         __FILE__,__LINE__,info->device_name );
2992         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2993         if (err) {
2994                 if ( debug_level >= DEBUG_LEVEL_INFO )
2995                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2996                                 __FILE__,__LINE__,info->device_name);
2997                 return -EFAULT;
2998         }
2999
3000         spin_lock_irqsave(&info->lock,flags);
3001         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
3002         spin_unlock_irqrestore(&info->lock,flags);
3003
3004         change_params(info);
3005
3006         return 0;
3007 }
3008
3009 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
3010 {
3011         int err;
3012
3013         if (debug_level >= DEBUG_LEVEL_INFO)
3014                 printk("%s(%d):%s get_txidle()=%d\n",
3015                          __FILE__,__LINE__, info->device_name, info->idle_mode);
3016
3017         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3018         if (err) {
3019                 if ( debug_level >= DEBUG_LEVEL_INFO )
3020                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3021                                 __FILE__,__LINE__,info->device_name);
3022                 return -EFAULT;
3023         }
3024
3025         return 0;
3026 }
3027
3028 static int set_txidle(SLMP_INFO * info, int idle_mode)
3029 {
3030         unsigned long flags;
3031
3032         if (debug_level >= DEBUG_LEVEL_INFO)
3033                 printk("%s(%d):%s set_txidle(%d)\n",
3034                         __FILE__,__LINE__,info->device_name, idle_mode );
3035
3036         spin_lock_irqsave(&info->lock,flags);
3037         info->idle_mode = idle_mode;
3038         tx_set_idle( info );
3039         spin_unlock_irqrestore(&info->lock,flags);
3040         return 0;
3041 }
3042
3043 static int tx_enable(SLMP_INFO * info, int enable)
3044 {
3045         unsigned long flags;
3046
3047         if (debug_level >= DEBUG_LEVEL_INFO)
3048                 printk("%s(%d):%s tx_enable(%d)\n",
3049                         __FILE__,__LINE__,info->device_name, enable);
3050
3051         spin_lock_irqsave(&info->lock,flags);
3052         if ( enable ) {
3053                 if ( !info->tx_enabled ) {
3054                         tx_start(info);
3055                 }
3056         } else {
3057                 if ( info->tx_enabled )
3058                         tx_stop(info);
3059         }
3060         spin_unlock_irqrestore(&info->lock,flags);
3061         return 0;
3062 }
3063
3064 /* abort send HDLC frame
3065  */
3066 static int tx_abort(SLMP_INFO * info)
3067 {
3068         unsigned long flags;
3069
3070         if (debug_level >= DEBUG_LEVEL_INFO)
3071                 printk("%s(%d):%s tx_abort()\n",
3072                         __FILE__,__LINE__,info->device_name);
3073
3074         spin_lock_irqsave(&info->lock,flags);
3075         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3076                 info->ie1_value &= ~UDRN;
3077                 info->ie1_value |= IDLE;
3078                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3079                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3080
3081                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3082                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3083
3084                 write_reg(info, CMD, TXABORT);
3085         }
3086         spin_unlock_irqrestore(&info->lock,flags);
3087         return 0;
3088 }
3089
3090 static int rx_enable(SLMP_INFO * info, int enable)
3091 {
3092         unsigned long flags;
3093
3094         if (debug_level >= DEBUG_LEVEL_INFO)
3095                 printk("%s(%d):%s rx_enable(%d)\n",
3096                         __FILE__,__LINE__,info->device_name,enable);
3097
3098         spin_lock_irqsave(&info->lock,flags);
3099         if ( enable ) {
3100                 if ( !info->rx_enabled )
3101                         rx_start(info);
3102         } else {
3103                 if ( info->rx_enabled )
3104                         rx_stop(info);
3105         }
3106         spin_unlock_irqrestore(&info->lock,flags);
3107         return 0;
3108 }
3109
3110 /* wait for specified event to occur
3111  */
3112 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3113 {
3114         unsigned long flags;
3115         int s;
3116         int rc=0;
3117         struct mgsl_icount cprev, cnow;
3118         int events;
3119         int mask;
3120         struct  _input_signal_events oldsigs, newsigs;
3121         DECLARE_WAITQUEUE(wait, current);
3122
3123         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3124         if (rc) {
3125                 return  -EFAULT;
3126         }
3127
3128         if (debug_level >= DEBUG_LEVEL_INFO)
3129                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3130                         __FILE__,__LINE__,info->device_name,mask);
3131
3132         spin_lock_irqsave(&info->lock,flags);
3133
3134         /* return immediately if state matches requested events */
3135         get_signals(info);
3136         s = info->serial_signals;
3137
3138         events = mask &
3139                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3140                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3141                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3142                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3143         if (events) {
3144                 spin_unlock_irqrestore(&info->lock,flags);
3145                 goto exit;
3146         }
3147
3148         /* save current irq counts */
3149         cprev = info->icount;
3150         oldsigs = info->input_signal_events;
3151
3152         /* enable hunt and idle irqs if needed */
3153         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3154                 unsigned char oldval = info->ie1_value;
3155                 unsigned char newval = oldval +
3156                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3157                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3158                 if ( oldval != newval ) {
3159                         info->ie1_value = newval;
3160                         write_reg(info, IE1, info->ie1_value);
3161                 }
3162         }
3163
3164         set_current_state(TASK_INTERRUPTIBLE);
3165         add_wait_queue(&info->event_wait_q, &wait);
3166
3167         spin_unlock_irqrestore(&info->lock,flags);
3168
3169         for(;;) {
3170                 schedule();
3171                 if (signal_pending(current)) {
3172                         rc = -ERESTARTSYS;
3173                         break;
3174                 }
3175
3176                 /* get current irq counts */
3177                 spin_lock_irqsave(&info->lock,flags);
3178                 cnow = info->icount;
3179                 newsigs = info->input_signal_events;
3180                 set_current_state(TASK_INTERRUPTIBLE);
3181                 spin_unlock_irqrestore(&info->lock,flags);
3182
3183                 /* if no change, wait aborted for some reason */
3184                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3185                     newsigs.dsr_down == oldsigs.dsr_down &&
3186                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3187                     newsigs.dcd_down == oldsigs.dcd_down &&
3188                     newsigs.cts_up   == oldsigs.cts_up   &&
3189                     newsigs.cts_down == oldsigs.cts_down &&
3190                     newsigs.ri_up    == oldsigs.ri_up    &&
3191                     newsigs.ri_down  == oldsigs.ri_down  &&
3192                     cnow.exithunt    == cprev.exithunt   &&
3193                     cnow.rxidle      == cprev.rxidle) {
3194                         rc = -EIO;
3195                         break;
3196                 }
3197
3198                 events = mask &
3199                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3200                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3201                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3202                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3203                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3204                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3205                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3206                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3207                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3208                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3209                 if (events)
3210                         break;
3211
3212                 cprev = cnow;
3213                 oldsigs = newsigs;
3214         }
3215
3216         remove_wait_queue(&info->event_wait_q, &wait);
3217         set_current_state(TASK_RUNNING);
3218
3219
3220         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3221                 spin_lock_irqsave(&info->lock,flags);
3222                 if (!waitqueue_active(&info->event_wait_q)) {
3223                         /* disable enable exit hunt mode/idle rcvd IRQs */
3224                         info->ie1_value &= ~(FLGD|IDLD);
3225                         write_reg(info, IE1, info->ie1_value);
3226                 }
3227                 spin_unlock_irqrestore(&info->lock,flags);
3228         }
3229 exit:
3230         if ( rc == 0 )
3231                 PUT_USER(rc, events, mask_ptr);
3232
3233         return rc;
3234 }
3235
3236 static int modem_input_wait(SLMP_INFO *info,int arg)
3237 {
3238         unsigned long flags;
3239         int rc;
3240         struct mgsl_icount cprev, cnow;
3241         DECLARE_WAITQUEUE(wait, current);
3242
3243         /* save current irq counts */
3244         spin_lock_irqsave(&info->lock,flags);
3245         cprev = info->icount;
3246         add_wait_queue(&info->status_event_wait_q, &wait);
3247         set_current_state(TASK_INTERRUPTIBLE);
3248         spin_unlock_irqrestore(&info->lock,flags);
3249
3250         for(;;) {
3251                 schedule();
3252                 if (signal_pending(current)) {
3253                         rc = -ERESTARTSYS;
3254                         break;
3255                 }
3256
3257                 /* get new irq counts */
3258                 spin_lock_irqsave(&info->lock,flags);
3259                 cnow = info->icount;
3260                 set_current_state(TASK_INTERRUPTIBLE);
3261                 spin_unlock_irqrestore(&info->lock,flags);
3262
3263                 /* if no change, wait aborted for some reason */
3264                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3265                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3266                         rc = -EIO;
3267                         break;
3268                 }
3269
3270                 /* check for change in caller specified modem input */
3271                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3272                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3273                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3274                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3275                         rc = 0;
3276                         break;
3277                 }
3278
3279                 cprev = cnow;
3280         }
3281         remove_wait_queue(&info->status_event_wait_q, &wait);
3282         set_current_state(TASK_RUNNING);
3283         return rc;
3284 }
3285
3286 /* return the state of the serial control and status signals
3287  */
3288 static int tiocmget(struct tty_struct *tty, struct file *file)
3289 {
3290         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3291         unsigned int result;
3292         unsigned long flags;
3293
3294         spin_lock_irqsave(&info->lock,flags);
3295         get_signals(info);
3296         spin_unlock_irqrestore(&info->lock,flags);
3297
3298         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3299                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3300                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3301                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3302                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3303                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3304
3305         if (debug_level >= DEBUG_LEVEL_INFO)
3306                 printk("%s(%d):%s tiocmget() value=%08X\n",
3307                          __FILE__,__LINE__, info->device_name, result );
3308         return result;
3309 }
3310
3311 /* set modem control signals (DTR/RTS)
3312  */
3313 static int tiocmset(struct tty_struct *tty, struct file *file,
3314                     unsigned int set, unsigned int clear)
3315 {
3316         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3317         unsigned long flags;
3318
3319         if (debug_level >= DEBUG_LEVEL_INFO)
3320                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3321                         __FILE__,__LINE__,info->device_name, set, clear);
3322
3323         if (set & TIOCM_RTS)
3324                 info->serial_signals |= SerialSignal_RTS;
3325         if (set & TIOCM_DTR)
3326                 info->serial_signals |= SerialSignal_DTR;
3327         if (clear & TIOCM_RTS)
3328                 info->serial_signals &= ~SerialSignal_RTS;
3329         if (clear & TIOCM_DTR)
3330                 info->serial_signals &= ~SerialSignal_DTR;
3331
3332         spin_lock_irqsave(&info->lock,flags);
3333         set_signals(info);
3334         spin_unlock_irqrestore(&info->lock,flags);
3335
3336         return 0;
3337 }
3338
3339
3340
3341 /* Block the current process until the specified port is ready to open.
3342  */
3343 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3344                            SLMP_INFO *info)
3345 {
3346         DECLARE_WAITQUEUE(wait, current);
3347         int             retval;
3348         int             do_clocal = 0, extra_count = 0;
3349         unsigned long   flags;
3350
3351         if (debug_level >= DEBUG_LEVEL_INFO)
3352                 printk("%s(%d):%s block_til_ready()\n",
3353                          __FILE__,__LINE__, tty->driver->name );
3354
3355         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3356                 /* nonblock mode is set or port is not enabled */
3357                 /* just verify that callout device is not active */
3358                 info->flags |= ASYNC_NORMAL_ACTIVE;
3359                 return 0;
3360         }
3361
3362         if (tty->termios->c_cflag & CLOCAL)
3363                 do_clocal = 1;
3364
3365         /* Wait for carrier detect and the line to become
3366          * free (i.e., not in use by the callout).  While we are in
3367          * this loop, info->count is dropped by one, so that
3368          * close() knows when to free things.  We restore it upon
3369          * exit, either normal or abnormal.
3370          */
3371
3372         retval = 0;
3373         add_wait_queue(&info->open_wait, &wait);
3374
3375         if (debug_level >= DEBUG_LEVEL_INFO)
3376                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3377                          __FILE__,__LINE__, tty->driver->name, info->count );
3378
3379         spin_lock_irqsave(&info->lock, flags);
3380         if (!tty_hung_up_p(filp)) {
3381                 extra_count = 1;
3382                 info->count--;
3383         }
3384         spin_unlock_irqrestore(&info->lock, flags);
3385         info->blocked_open++;
3386
3387         while (1) {
3388                 if ((tty->termios->c_cflag & CBAUD)) {
3389                         spin_lock_irqsave(&info->lock,flags);
3390                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3391                         set_signals(info);
3392                         spin_unlock_irqrestore(&info->lock,flags);
3393                 }
3394
3395                 set_current_state(TASK_INTERRUPTIBLE);
3396
3397                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3398                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3399                                         -EAGAIN : -ERESTARTSYS;
3400                         break;
3401                 }
3402
3403                 spin_lock_irqsave(&info->lock,flags);
3404                 get_signals(info);
3405                 spin_unlock_irqrestore(&info->lock,flags);
3406
3407                 if (!(info->flags & ASYNC_CLOSING) &&
3408                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3409                         break;
3410                 }
3411
3412                 if (signal_pending(current)) {
3413                         retval = -ERESTARTSYS;
3414                         break;
3415                 }
3416
3417                 if (debug_level >= DEBUG_LEVEL_INFO)
3418                         printk("%s(%d):%s block_til_ready() count=%d\n",
3419                                  __FILE__,__LINE__, tty->driver->name, info->count );
3420
3421                 schedule();
3422         }
3423
3424         set_current_state(TASK_RUNNING);
3425         remove_wait_queue(&info->open_wait, &wait);
3426
3427         if (extra_count)
3428                 info->count++;
3429         info->blocked_open--;
3430
3431         if (debug_level >= DEBUG_LEVEL_INFO)
3432                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3433                          __FILE__,__LINE__, tty->driver->name, info->count );
3434
3435         if (!retval)
3436                 info->flags |= ASYNC_NORMAL_ACTIVE;
3437
3438         return retval;
3439 }
3440
3441 int alloc_dma_bufs(SLMP_INFO *info)
3442 {
3443         unsigned short BuffersPerFrame;
3444         unsigned short BufferCount;
3445
3446         // Force allocation to start at 64K boundary for each port.
3447         // This is necessary because *all* buffer descriptors for a port
3448         // *must* be in the same 64K block. All descriptors on a port
3449         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3450         // into the CBP register.
3451         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3452
3453         /* Calculate the number of DMA buffers necessary to hold the */
3454         /* largest allowable frame size. Note: If the max frame size is */
3455         /* not an even multiple of the DMA buffer size then we need to */
3456         /* round the buffer count per frame up one. */
3457
3458         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3459         if ( info->max_frame_size % SCABUFSIZE )
3460                 BuffersPerFrame++;
3461
3462         /* calculate total number of data buffers (SCABUFSIZE) possible
3463          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3464          * for the descriptor list (BUFFERLISTSIZE).
3465          */
3466         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3467
3468         /* limit number of buffers to maximum amount of descriptors */
3469         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3470                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3471
3472         /* use enough buffers to transmit one max size frame */
3473         info->tx_buf_count = BuffersPerFrame + 1;
3474
3475         /* never use more than half the available buffers for transmit */
3476         if (info->tx_buf_count > (BufferCount/2))
3477                 info->tx_buf_count = BufferCount/2;
3478
3479         if (info->tx_buf_count > SCAMAXDESC)
3480                 info->tx_buf_count = SCAMAXDESC;
3481
3482         /* use remaining buffers for receive */
3483         info->rx_buf_count = BufferCount - info->tx_buf_count;
3484
3485         if (info->rx_buf_count > SCAMAXDESC)
3486                 info->rx_buf_count = SCAMAXDESC;
3487
3488         if ( debug_level >= DEBUG_LEVEL_INFO )
3489                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3490                         __FILE__,__LINE__, info->device_name,
3491                         info->tx_buf_count,info->rx_buf_count);
3492
3493         if ( alloc_buf_list( info ) < 0 ||
3494                 alloc_frame_bufs(info,
3495                                         info->rx_buf_list,
3496                                         info->rx_buf_list_ex,
3497                                         info->rx_buf_count) < 0 ||
3498                 alloc_frame_bufs(info,
3499                                         info->tx_buf_list,
3500                                         info->tx_buf_list_ex,
3501                                         info->tx_buf_count) < 0 ||
3502                 alloc_tmp_rx_buf(info) < 0 ) {
3503                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3504                         __FILE__,__LINE__, info->device_name);
3505                 return -ENOMEM;
3506         }
3507
3508         rx_reset_buffers( info );
3509
3510         return 0;
3511 }
3512
3513 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3514  */
3515 int alloc_buf_list(SLMP_INFO *info)
3516 {
3517         unsigned int i;
3518
3519         /* build list in adapter shared memory */
3520         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3521         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3522         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3523
3524         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3525
3526         /* Save virtual address pointers to the receive and */
3527         /* transmit buffer lists. (Receive 1st). These pointers will */
3528         /* be used by the processor to access the lists. */
3529         info->rx_buf_list = (SCADESC *)info->buffer_list;
3530
3531         info->tx_buf_list = (SCADESC *)info->buffer_list;
3532         info->tx_buf_list += info->rx_buf_count;
3533
3534         /* Build links for circular buffer entry lists (tx and rx)
3535          *
3536          * Note: links are physical addresses read by the SCA device
3537          * to determine the next buffer entry to use.
3538          */
3539
3540         for ( i = 0; i < info->rx_buf_count; i++ ) {
3541                 /* calculate and store physical address of this buffer entry */
3542                 info->rx_buf_list_ex[i].phys_entry =
3543                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3544
3545                 /* calculate and store physical address of */
3546                 /* next entry in cirular list of entries */
3547                 info->rx_buf_list[i].next = info->buffer_list_phys;
3548                 if ( i < info->rx_buf_count - 1 )
3549                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3550
3551                 info->rx_buf_list[i].length = SCABUFSIZE;
3552         }
3553
3554         for ( i = 0; i < info->tx_buf_count; i++ ) {
3555                 /* calculate and store physical address of this buffer entry */
3556                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3557                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3558
3559                 /* calculate and store physical address of */
3560                 /* next entry in cirular list of entries */
3561
3562                 info->tx_buf_list[i].next = info->buffer_list_phys +
3563                         info->rx_buf_count * sizeof(SCADESC);
3564
3565                 if ( i < info->tx_buf_count - 1 )
3566                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3567         }
3568
3569         return 0;
3570 }
3571
3572 /* Allocate the frame DMA buffers used by the specified buffer list.
3573  */
3574 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3575 {
3576         int i;
3577         unsigned long phys_addr;
3578
3579         for ( i = 0; i < count; i++ ) {
3580                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3581                 phys_addr = info->port_array[0]->last_mem_alloc;
3582                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3583
3584                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3585                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3586         }
3587
3588         return 0;
3589 }
3590
3591 void free_dma_bufs(SLMP_INFO *info)
3592 {
3593         info->buffer_list = NULL;
3594         info->rx_buf_list = NULL;
3595         info->tx_buf_list = NULL;
3596 }
3597
3598 /* allocate buffer large enough to hold max_frame_size.
3599  * This buffer is used to pass an assembled frame to the line discipline.
3600  */
3601 int alloc_tmp_rx_buf(SLMP_INFO *info)
3602 {
3603         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3604         if (info->tmp_rx_buf == NULL)
3605                 return -ENOMEM;
3606         return 0;
3607 }
3608
3609 void free_tmp_rx_buf(SLMP_INFO *info)
3610 {
3611         if (info->tmp_rx_buf)
3612                 kfree(info->tmp_rx_buf);
3613         info->tmp_rx_buf = NULL;
3614 }
3615
3616 int claim_resources(SLMP_INFO *info)
3617 {
3618         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3619                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3620                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3621                 info->init_error = DiagStatus_AddressConflict;
3622                 goto errout;
3623         }
3624         else
3625                 info->shared_mem_requested = 1;
3626
3627         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3628                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3629                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3630                 info->init_error = DiagStatus_AddressConflict;
3631                 goto errout;
3632         }
3633         else
3634                 info->lcr_mem_requested = 1;
3635
3636         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3637                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3638                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3639                 info->init_error = DiagStatus_AddressConflict;
3640                 goto errout;
3641         }
3642         else
3643                 info->sca_base_requested = 1;
3644
3645         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3646                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3647                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3648                 info->init_error = DiagStatus_AddressConflict;
3649                 goto errout;
3650         }
3651         else
3652                 info->sca_statctrl_requested = 1;
3653
3654         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3655         if (!info->memory_base) {
3656                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3657                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3658                 info->init_error = DiagStatus_CantAssignPciResources;
3659                 goto errout;
3660         }
3661
3662         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3663         if (!info->lcr_base) {
3664                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3665                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3666                 info->init_error = DiagStatus_CantAssignPciResources;
3667                 goto errout;
3668         }
3669         info->lcr_base += info->lcr_offset;
3670
3671         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3672         if (!info->sca_base) {
3673                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3674                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3675                 info->init_error = DiagStatus_CantAssignPciResources;
3676                 goto errout;
3677         }
3678         info->sca_base += info->sca_offset;
3679
3680         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3681         if (!info->statctrl_base) {
3682                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3683                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3684                 info->init_error = DiagStatus_CantAssignPciResources;
3685                 goto errout;
3686         }
3687         info->statctrl_base += info->statctrl_offset;
3688
3689         if ( !memory_test(info) ) {
3690                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3691                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3692                 info->init_error = DiagStatus_MemoryError;
3693                 goto errout;
3694         }
3695
3696         return 0;
3697
3698 errout:
3699         release_resources( info );
3700         return -ENODEV;
3701 }
3702
3703 void release_resources(SLMP_INFO *info)
3704 {
3705         if ( debug_level >= DEBUG_LEVEL_INFO )
3706                 printk( "%s(%d):%s release_resources() entry\n",
3707                         __FILE__,__LINE__,info->device_name );
3708
3709         if ( info->irq_requested ) {
3710                 free_irq(info->irq_level, info);
3711                 info->irq_requested = 0;
3712         }
3713
3714         if ( info->shared_mem_requested ) {
3715                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3716                 info->shared_mem_requested = 0;
3717         }
3718         if ( info->lcr_mem_requested ) {
3719                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3720                 info->lcr_mem_requested = 0;
3721         }
3722         if ( info->sca_base_requested ) {
3723                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3724                 info->sca_base_requested = 0;
3725         }
3726         if ( info->sca_statctrl_requested ) {
3727                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3728                 info->sca_statctrl_requested = 0;
3729         }
3730
3731         if (info->memory_base){
3732                 iounmap(info->memory_base);
3733                 info->memory_base = NULL;
3734         }
3735
3736         if (info->sca_base) {
3737                 iounmap(info->sca_base - info->sca_offset);
3738                 info->sca_base=NULL;
3739         }
3740
3741         if (info->statctrl_base) {
3742                 iounmap(info->statctrl_base - info->statctrl_offset);
3743                 info->statctrl_base=NULL;
3744         }
3745
3746         if (info->lcr_base){
3747                 iounmap(info->lcr_base - info->lcr_offset);
3748                 info->lcr_base = NULL;
3749         }
3750
3751         if ( debug_level >= DEBUG_LEVEL_INFO )
3752                 printk( "%s(%d):%s release_resources() exit\n",
3753                         __FILE__,__LINE__,info->device_name );
3754 }
3755
3756 /* Add the specified device instance data structure to the
3757  * global linked list of devices and increment the device count.
3758  */
3759 void add_device(SLMP_INFO *info)
3760 {
3761         info->next_device = NULL;
3762         info->line = synclinkmp_device_count;
3763         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3764
3765         if (info->line < MAX_DEVICES) {
3766                 if (maxframe[info->line])
3767                         info->max_frame_size = maxframe[info->line];
3768                 info->dosyncppp = dosyncppp[info->line];
3769         }
3770
3771         synclinkmp_device_count++;
3772
3773         if ( !synclinkmp_device_list )
3774                 synclinkmp_device_list = info;
3775         else {
3776                 SLMP_INFO *current_dev = synclinkmp_device_list;
3777                 while( current_dev->next_device )
3778                         current_dev = current_dev->next_device;
3779                 current_dev->next_device = info;
3780         }
3781
3782         if ( info->max_frame_size < 4096 )
3783                 info->max_frame_size = 4096;
3784         else if ( info->max_frame_size > 65535 )
3785                 info->max_frame_size = 65535;
3786
3787         printk( "SyncLink MultiPort %s: "
3788                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3789                 info->device_name,
3790                 info->phys_sca_base,
3791                 info->phys_memory_base,
3792                 info->phys_statctrl_base,
3793                 info->phys_lcr_base,
3794                 info->irq_level,
3795                 info->max_frame_size );
3796
3797 #ifdef CONFIG_HDLC
3798         hdlcdev_init(info);
3799 #endif
3800 }
3801
3802 /* Allocate and initialize a device instance structure
3803  *
3804  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3805  */
3806 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3807 {
3808         SLMP_INFO *info;
3809
3810         info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3811                  GFP_KERNEL);
3812
3813         if (!info) {
3814                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3815                         __FILE__,__LINE__, adapter_num, port_num);
3816         } else {
3817                 memset(info, 0, sizeof(SLMP_INFO));
3818                 info->magic = MGSL_MAGIC;
3819                 INIT_WORK(&info->task, bh_handler, info);
3820                 info->max_frame_size = 4096;
3821                 info->close_delay = 5*HZ/10;
3822                 info->closing_wait = 30*HZ;
3823                 init_waitqueue_head(&info->open_wait);
3824                 init_waitqueue_head(&info->close_wait);
3825                 init_waitqueue_head(&info->status_event_wait_q);
3826                 init_waitqueue_head(&info->event_wait_q);
3827                 spin_lock_init(&info->netlock);
3828                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3829                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3830                 info->adapter_num = adapter_num;
3831                 info->port_num = port_num;
3832
3833                 /* Copy configuration info to device instance data */
3834                 info->irq_level = pdev->irq;
3835                 info->phys_lcr_base = pci_resource_start(pdev,0);
3836                 info->phys_sca_base = pci_resource_start(pdev,2);
3837                 info->phys_memory_base = pci_resource_start(pdev,3);
3838                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3839
3840                 /* Because veremap only works on page boundaries we must map
3841                  * a larger area than is actually implemented for the LCR
3842                  * memory range. We map a full page starting at the page boundary.
3843                  */
3844                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3845                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3846
3847                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3848                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3849
3850                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3851                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3852
3853                 info->bus_type = MGSL_BUS_TYPE_PCI;
3854                 info->irq_flags = SA_SHIRQ;
3855
3856                 init_timer(&info->tx_timer);
3857                 info->tx_timer.data = (unsigned long)info;
3858                 info->tx_timer.function = tx_timeout;
3859
3860                 init_timer(&info->status_timer);
3861                 info->status_timer.data = (unsigned long)info;
3862                 info->status_timer.function = status_timeout;
3863
3864                 /* Store the PCI9050 misc control register value because a flaw
3865                  * in the PCI9050 prevents LCR registers from being read if
3866                  * BIOS assigns an LCR base address with bit 7 set.
3867                  *
3868                  * Only the misc control register is accessed for which only
3869                  * write access is needed, so set an initial value and change
3870                  * bits to the device instance data as we write the value
3871                  * to the actual misc control register.
3872                  */
3873                 info->misc_ctrl_value = 0x087e4546;
3874
3875                 /* initial port state is unknown - if startup errors
3876                  * occur, init_error will be set to indicate the
3877                  * problem. Once the port is fully initialized,
3878                  * this value will be set to 0 to indicate the
3879                  * port is available.
3880                  */
3881                 info->init_error = -1;
3882         }
3883
3884         return info;
3885 }
3886
3887 void device_init(int adapter_num, struct pci_dev *pdev)
3888 {
3889         SLMP_INFO *port_array[SCA_MAX_PORTS];
3890         int port;
3891
3892         /* allocate device instances for up to SCA_MAX_PORTS devices */
3893         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3894                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3895                 if( port_array[port] == NULL ) {
3896                         for ( --port; port >= 0; --port )
3897                                 kfree(port_array[port]);
3898                         return;
3899                 }
3900         }
3901
3902         /* give copy of port_array to all ports and add to device list  */
3903         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3904                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3905                 add_device( port_array[port] );
3906                 spin_lock_init(&port_array[port]->lock);
3907         }
3908
3909         /* Allocate and claim adapter resources */
3910         if ( !claim_resources(port_array[0]) ) {
3911
3912                 alloc_dma_bufs(port_array[0]);
3913
3914                 /* copy resource information from first port to others */
3915                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3916                         port_array[port]->lock  = port_array[0]->lock;
3917                         port_array[port]->irq_level     = port_array[0]->irq_level;
3918                         port_array[port]->memory_base   = port_array[0]->memory_base;
3919                         port_array[port]->sca_base      = port_array[0]->sca_base;
3920                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3921                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3922                         alloc_dma_bufs(port_array[port]);
3923                 }
3924
3925                 if ( request_irq(port_array[0]->irq_level,
3926                                         synclinkmp_interrupt,
3927                                         port_array[0]->irq_flags,
3928                                         port_array[0]->device_name,
3929                                         port_array[0]) < 0 ) {
3930                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3931                                 __FILE__,__LINE__,
3932                                 port_array[0]->device_name,
3933                                 port_array[0]->irq_level );
3934                 }
3935                 else {
3936                         port_array[0]->irq_requested = 1;
3937                         adapter_test(port_array[0]);
3938                 }
3939         }
3940 }
3941
3942 static struct tty_operations ops = {
3943         .open = open,
3944         .close = close,
3945         .write = write,
3946         .put_char = put_char,
3947         .flush_chars = flush_chars,
3948         .write_room = write_room,
3949         .chars_in_buffer = chars_in_buffer,
3950         .flush_buffer = flush_buffer,
3951         .ioctl = ioctl,
3952         .throttle = throttle,
3953         .unthrottle = unthrottle,
3954         .send_xchar = send_xchar,
3955         .break_ctl = set_break,
3956         .wait_until_sent = wait_until_sent,
3957         .read_proc = read_proc,
3958         .set_termios = set_termios,
3959         .stop = tx_hold,
3960         .start = tx_release,
3961         .hangup = hangup,
3962         .tiocmget = tiocmget,
3963         .tiocmset = tiocmset,
3964 };
3965
3966 static void synclinkmp_cleanup(void)
3967 {
3968         int rc;
3969         SLMP_INFO *info;
3970         SLMP_INFO *tmp;
3971
3972         printk("Unloading %s %s\n", driver_name, driver_version);
3973
3974         if (serial_driver) {
3975                 if ((rc = tty_unregister_driver(serial_driver)))
3976                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3977                                __FILE__,__LINE__,rc);
3978                 put_tty_driver(serial_driver);
3979         }
3980
3981         /* reset devices */
3982         info = synclinkmp_device_list;
3983         while(info) {
3984                 reset_port(info);
3985                 info = info->next_device;
3986         }
3987
3988         /* release devices */
3989         info = synclinkmp_device_list;
3990         while(info) {
3991 #ifdef CONFIG_HDLC
3992                 hdlcdev_exit(info);
3993 #endif
3994                 free_dma_bufs(info);
3995                 free_tmp_rx_buf(info);
3996                 if ( info->port_num == 0 ) {
3997                         if (info->sca_base)
3998                                 write_reg(info, LPR, 1); /* set low power mode */
3999                         release_resources(info);
4000                 }
4001                 tmp = info;
4002                 info = info->next_device;
4003                 kfree(tmp);
4004         }
4005
4006         pci_unregister_driver(&synclinkmp_pci_driver);
4007 }
4008
4009 /* Driver initialization entry point.
4010  */
4011
4012 static int __init synclinkmp_init(void)
4013 {
4014         int rc;
4015
4016         if (break_on_load) {
4017                 synclinkmp_get_text_ptr();
4018                 BREAKPOINT();
4019         }
4020
4021         printk("%s %s\n", driver_name, driver_version);
4022
4023         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4024                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4025                 return rc;
4026         }
4027
4028         serial_driver = alloc_tty_driver(128);
4029         if (!serial_driver) {
4030                 rc = -ENOMEM;
4031                 goto error;
4032         }
4033
4034         /* Initialize the tty_driver structure */
4035
4036         serial_driver->owner = THIS_MODULE;
4037         serial_driver->driver_name = "synclinkmp";
4038         serial_driver->name = "ttySLM";
4039         serial_driver->major = ttymajor;
4040         serial_driver->minor_start = 64;
4041         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4042         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4043         serial_driver->init_termios = tty_std_termios;
4044         serial_driver->init_termios.c_cflag =
4045                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4046         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4047         tty_set_operations(serial_driver, &ops);
4048         if ((rc = tty_register_driver(serial_driver)) < 0) {
4049                 printk("%s(%d):Couldn't register serial driver\n",
4050                         __FILE__,__LINE__);
4051                 put_tty_driver(serial_driver);
4052                 serial_driver = NULL;
4053                 goto error;
4054         }
4055
4056         printk("%s %s, tty major#%d\n",
4057                 driver_name, driver_version,
4058                 serial_driver->major);
4059
4060         return 0;
4061
4062 error:
4063         synclinkmp_cleanup();
4064         return rc;
4065 }
4066
4067 static void __exit synclinkmp_exit(void)
4068 {
4069         synclinkmp_cleanup();
4070 }
4071
4072 module_init(synclinkmp_init);
4073 module_exit(synclinkmp_exit);
4074
4075 /* Set the port for internal loopback mode.
4076  * The TxCLK and RxCLK signals are generated from the BRG and
4077  * the TxD is looped back to the RxD internally.
4078  */
4079 void enable_loopback(SLMP_INFO *info, int enable)
4080 {
4081         if (enable) {
4082                 /* MD2 (Mode Register 2)
4083                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4084                  */
4085                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4086
4087                 /* degate external TxC clock source */
4088                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4089                 write_control_reg(info);
4090
4091                 /* RXS/TXS (Rx/Tx clock source)
4092                  * 07      Reserved, must be 0
4093                  * 06..04  Clock Source, 100=BRG
4094                  * 03..00  Clock Divisor, 0000=1
4095                  */
4096                 write_reg(info, RXS, 0x40);
4097                 write_reg(info, TXS, 0x40);
4098
4099         } else {
4100                 /* MD2 (Mode Register 2)
4101                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4102                  */
4103                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4104
4105                 /* RXS/TXS (Rx/Tx clock source)
4106                  * 07      Reserved, must be 0
4107                  * 06..04  Clock Source, 000=RxC/TxC Pin
4108                  * 03..00  Clock Divisor, 0000=1
4109                  */
4110                 write_reg(info, RXS, 0x00);
4111                 write_reg(info, TXS, 0x00);
4112         }
4113
4114         /* set LinkSpeed if available, otherwise default to 2Mbps */
4115         if (info->params.clock_speed)
4116                 set_rate(info, info->params.clock_speed);
4117         else
4118                 set_rate(info, 3686400);
4119 }
4120
4121 /* Set the baud rate register to the desired speed
4122  *
4123  *      data_rate       data rate of clock in bits per second
4124  *                      A data rate of 0 disables the AUX clock.
4125  */
4126 void set_rate( SLMP_INFO *info, u32 data_rate )
4127 {
4128         u32 TMCValue;
4129         unsigned char BRValue;
4130         u32 Divisor=0;
4131
4132         /* fBRG = fCLK/(TMC * 2^BR)
4133          */
4134         if (data_rate != 0) {
4135                 Divisor = 14745600/data_rate;
4136                 if (!Divisor)
4137                         Divisor = 1;
4138
4139                 TMCValue = Divisor;
4140
4141                 BRValue = 0;
4142                 if (TMCValue != 1 && TMCValue != 2) {
4143                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4144                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4145                          * 50/50 duty cycle.
4146                          */
4147                         BRValue = 1;
4148                         TMCValue >>= 1;
4149                 }
4150
4151                 /* while TMCValue is too big for TMC register, divide
4152                  * by 2 and increment BR exponent.
4153                  */
4154                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4155                         TMCValue >>= 1;
4156
4157                 write_reg(info, TXS,
4158                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4159                 write_reg(info, RXS,
4160                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4161                 write_reg(info, TMC, (unsigned char)TMCValue);
4162         }
4163         else {
4164                 write_reg(info, TXS,0);
4165                 write_reg(info, RXS,0);
4166                 write_reg(info, TMC, 0);
4167         }
4168 }
4169
4170 /* Disable receiver
4171  */
4172 void rx_stop(SLMP_INFO *info)
4173 {
4174         if (debug_level >= DEBUG_LEVEL_ISR)
4175                 printk("%s(%d):%s rx_stop()\n",
4176                          __FILE__,__LINE__, info->device_name );
4177
4178         write_reg(info, CMD, RXRESET);
4179
4180         info->ie0_value &= ~RXRDYE;
4181         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4182
4183         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4184         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4185         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4186
4187         info->rx_enabled = 0;
4188         info->rx_overflow = 0;
4189 }
4190
4191 /* enable the receiver
4192  */
4193 void rx_start(SLMP_INFO *info)
4194 {
4195         int i;
4196
4197         if (debug_level >= DEBUG_LEVEL_ISR)
4198                 printk("%s(%d):%s rx_start()\n",
4199                          __FILE__,__LINE__, info->device_name );
4200
4201         write_reg(info, CMD, RXRESET);
4202
4203         if ( info->params.mode == MGSL_MODE_HDLC ) {
4204                 /* HDLC, disabe IRQ on rxdata */
4205                 info->ie0_value &= ~RXRDYE;
4206                 write_reg(info, IE0, info->ie0_value);
4207
4208                 /* Reset all Rx DMA buffers and program rx dma */
4209                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4210                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4211
4212                 for (i = 0; i < info->rx_buf_count; i++) {
4213                         info->rx_buf_list[i].status = 0xff;
4214
4215                         // throttle to 4 shared memory writes at a time to prevent
4216                         // hogging local bus (keep latency time for DMA requests low).
4217                         if (!(i % 4))
4218                                 read_status_reg(info);
4219                 }
4220                 info->current_rx_buf = 0;
4221
4222                 /* set current/1st descriptor address */
4223                 write_reg16(info, RXDMA + CDA,
4224                         info->rx_buf_list_ex[0].phys_entry);
4225
4226                 /* set new last rx descriptor address */
4227                 write_reg16(info, RXDMA + EDA,
4228                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4229
4230                 /* set buffer length (shared by all rx dma data buffers) */
4231                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4232
4233                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4234                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4235         } else {
4236                 /* async, enable IRQ on rxdata */
4237                 info->ie0_value |= RXRDYE;
4238                 write_reg(info, IE0, info->ie0_value);
4239         }
4240
4241         write_reg(info, CMD, RXENABLE);
4242
4243         info->rx_overflow = FALSE;
4244         info->rx_enabled = 1;
4245 }
4246
4247 /* Enable the transmitter and send a transmit frame if
4248  * one is loaded in the DMA buffers.
4249  */
4250 void tx_start(SLMP_INFO *info)
4251 {
4252         if (debug_level >= DEBUG_LEVEL_ISR)
4253                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4254                          __FILE__,__LINE__, info->device_name,info->tx_count );
4255
4256         if (!info->tx_enabled ) {
4257                 write_reg(info, CMD, TXRESET);
4258                 write_reg(info, CMD, TXENABLE);
4259                 info->tx_enabled = TRUE;
4260         }
4261
4262         if ( info->tx_count ) {
4263
4264                 /* If auto RTS enabled and RTS is inactive, then assert */
4265                 /* RTS and set a flag indicating that the driver should */
4266                 /* negate RTS when the transmission completes. */
4267
4268                 info->drop_rts_on_tx_done = 0;
4269
4270                 if (info->params.mode != MGSL_MODE_ASYNC) {
4271
4272                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4273                                 get_signals( info );
4274                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4275                                         info->serial_signals |= SerialSignal_RTS;
4276                                         set_signals( info );
4277                                         info->drop_rts_on_tx_done = 1;
4278                                 }
4279                         }
4280
4281                         write_reg16(info, TRC0,
4282                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4283
4284                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4285                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4286
4287                         /* set TX CDA (current descriptor address) */
4288                         write_reg16(info, TXDMA + CDA,
4289                                 info->tx_buf_list_ex[0].phys_entry);
4290
4291                         /* set TX EDA (last descriptor address) */
4292                         write_reg16(info, TXDMA + EDA,
4293                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4294
4295                         /* enable underrun IRQ */
4296                         info->ie1_value &= ~IDLE;
4297                         info->ie1_value |= UDRN;
4298                         write_reg(info, IE1, info->ie1_value);
4299                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4300
4301                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4302                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4303
4304                         info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
4305                         add_timer(&info->tx_timer);
4306                 }
4307                 else {
4308                         tx_load_fifo(info);
4309                         /* async, enable IRQ on txdata */
4310                         info->ie0_value |= TXRDYE;
4311                         write_reg(info, IE0, info->ie0_value);
4312                 }
4313
4314                 info->tx_active = 1;
4315         }
4316 }
4317
4318 /* stop the transmitter and DMA
4319  */
4320 void tx_stop( SLMP_INFO *info )
4321 {
4322         if (debug_level >= DEBUG_LEVEL_ISR)
4323                 printk("%s(%d):%s tx_stop()\n",
4324                          __FILE__,__LINE__, info->device_name );
4325
4326         del_timer(&info->tx_timer);
4327
4328         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4329         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4330
4331         write_reg(info, CMD, TXRESET);
4332
4333         info->ie1_value &= ~(UDRN + IDLE);
4334         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4335         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4336
4337         info->ie0_value &= ~TXRDYE;
4338         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4339
4340         info->tx_enabled = 0;
4341         info->tx_active  = 0;
4342 }
4343
4344 /* Fill the transmit FIFO until the FIFO is full or
4345  * there is no more data to load.
4346  */
4347 void tx_load_fifo(SLMP_INFO *info)
4348 {
4349         u8 TwoBytes[2];
4350
4351         /* do nothing is now tx data available and no XON/XOFF pending */
4352
4353         if ( !info->tx_count && !info->x_char )
4354                 return;
4355
4356         /* load the Transmit FIFO until FIFOs full or all data sent */
4357
4358         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4359
4360                 /* there is more space in the transmit FIFO and */
4361                 /* there is more data in transmit buffer */
4362
4363                 if ( (info->tx_count > 1) && !info->x_char ) {
4364                         /* write 16-bits */
4365                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4366                         if (info->tx_get >= info->max_frame_size)
4367                                 info->tx_get -= info->max_frame_size;
4368                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4369                         if (info->tx_get >= info->max_frame_size)
4370                                 info->tx_get -= info->max_frame_size;
4371
4372                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4373
4374                         info->tx_count -= 2;
4375                         info->icount.tx += 2;
4376                 } else {
4377                         /* only 1 byte left to transmit or 1 FIFO slot left */
4378
4379                         if (info->x_char) {
4380                                 /* transmit pending high priority char */
4381                                 write_reg(info, TRB, info->x_char);
4382                                 info->x_char = 0;
4383                         } else {
4384                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4385                                 if (info->tx_get >= info->max_frame_size)
4386                                         info->tx_get -= info->max_frame_size;
4387                                 info->tx_count--;
4388                         }
4389                         info->icount.tx++;
4390                 }
4391         }
4392 }
4393
4394 /* Reset a port to a known state
4395  */
4396 void reset_port(SLMP_INFO *info)
4397 {
4398         if (info->sca_base) {
4399
4400                 tx_stop(info);
4401                 rx_stop(info);
4402
4403                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4404                 set_signals(info);
4405
4406                 /* disable all port interrupts */
4407                 info->ie0_value = 0;
4408                 info->ie1_value = 0;
4409                 info->ie2_value = 0;
4410                 write_reg(info, IE0, info->ie0_value);
4411                 write_reg(info, IE1, info->ie1_value);
4412                 write_reg(info, IE2, info->ie2_value);
4413
4414                 write_reg(info, CMD, CHRESET);
4415         }
4416 }
4417
4418 /* Reset all the ports to a known state.
4419  */
4420 void reset_adapter(SLMP_INFO *info)
4421 {
4422         int i;
4423
4424         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4425                 if (info->port_array[i])
4426                         reset_port(info->port_array[i]);
4427         }
4428 }
4429
4430 /* Program port for asynchronous communications.
4431  */
4432 void async_mode(SLMP_INFO *info)
4433 {
4434
4435         unsigned char RegValue;
4436
4437         tx_stop(info);
4438         rx_stop(info);
4439
4440         /* MD0, Mode Register 0
4441          *
4442          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4443          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4444          * 03      Reserved, must be 0
4445          * 02      CRCCC, CRC Calculation, 0=disabled
4446          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4447          *
4448          * 0000 0000
4449          */
4450         RegValue = 0x00;
4451         if (info->params.stop_bits != 1)
4452                 RegValue |= BIT1;
4453         write_reg(info, MD0, RegValue);
4454
4455         /* MD1, Mode Register 1
4456          *
4457          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4458          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4459          * 03..02  RXCHR<1..0>, rx char size
4460          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4461          *
4462          * 0100 0000
4463          */
4464         RegValue = 0x40;
4465         switch (info->params.data_bits) {
4466         case 7: RegValue |= BIT4 + BIT2; break;
4467         case 6: RegValue |= BIT5 + BIT3; break;
4468         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4469         }
4470         if (info->params.parity != ASYNC_PARITY_NONE) {
4471                 RegValue |= BIT1;
4472                 if (info->params.parity == ASYNC_PARITY_ODD)
4473                         RegValue |= BIT0;
4474         }
4475         write_reg(info, MD1, RegValue);
4476
4477         /* MD2, Mode Register 2
4478          *
4479          * 07..02  Reserved, must be 0
4480          * 01..00  CNCT<1..0> Channel connection, 0=normal
4481          *
4482          * 0000 0000
4483          */
4484         RegValue = 0x00;
4485         write_reg(info, MD2, RegValue);
4486
4487         /* RXS, Receive clock source
4488          *
4489          * 07      Reserved, must be 0
4490          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4491          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4492          */
4493         RegValue=BIT6;
4494         write_reg(info, RXS, RegValue);
4495
4496         /* TXS, Transmit clock source
4497          *
4498          * 07      Reserved, must be 0
4499          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4500          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4501          */
4502         RegValue=BIT6;
4503         write_reg(info, TXS, RegValue);
4504
4505         /* Control Register
4506          *
4507          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4508          */
4509         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4510         write_control_reg(info);
4511
4512         tx_set_idle(info);
4513
4514         /* RRC Receive Ready Control 0
4515          *
4516          * 07..05  Reserved, must be 0
4517          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4518          */
4519         write_reg(info, RRC, 0x00);
4520
4521         /* TRC0 Transmit Ready Control 0
4522          *
4523          * 07..05  Reserved, must be 0
4524          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4525          */
4526         write_reg(info, TRC0, 0x10);
4527
4528         /* TRC1 Transmit Ready Control 1
4529          *
4530          * 07..05  Reserved, must be 0
4531          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4532          */
4533         write_reg(info, TRC1, 0x1e);
4534
4535         /* CTL, MSCI control register
4536          *
4537          * 07..06  Reserved, set to 0
4538          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4539          * 04      IDLC, idle control, 0=mark 1=idle register
4540          * 03      BRK, break, 0=off 1 =on (async)
4541          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4542          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4543          * 00      RTS, RTS output control, 0=active 1=inactive
4544          *
4545          * 0001 0001
4546          */
4547         RegValue = 0x10;
4548         if (!(info->serial_signals & SerialSignal_RTS))
4549                 RegValue |= 0x01;
4550         write_reg(info, CTL, RegValue);
4551
4552         /* enable status interrupts */
4553         info->ie0_value |= TXINTE + RXINTE;
4554         write_reg(info, IE0, info->ie0_value);
4555
4556         /* enable break detect interrupt */
4557         info->ie1_value = BRKD;
4558         write_reg(info, IE1, info->ie1_value);
4559
4560         /* enable rx overrun interrupt */
4561         info->ie2_value = OVRN;
4562         write_reg(info, IE2, info->ie2_value);
4563
4564         set_rate( info, info->params.data_rate * 16 );
4565
4566         if (info->params.loopback)
4567                 enable_loopback(info,1);
4568 }
4569
4570 /* Program the SCA for HDLC communications.
4571  */
4572 void hdlc_mode(SLMP_INFO *info)
4573 {
4574         unsigned char RegValue;
4575         u32 DpllDivisor;
4576
4577         // Can't use DPLL because SCA outputs recovered clock on RxC when
4578         // DPLL mode selected. This causes output contention with RxC receiver.
4579         // Use of DPLL would require external hardware to disable RxC receiver
4580         // when DPLL mode selected.
4581         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4582
4583         /* disable DMA interrupts */
4584         write_reg(info, TXDMA + DIR, 0);
4585         write_reg(info, RXDMA + DIR, 0);
4586
4587         /* MD0, Mode Register 0
4588          *
4589          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4590          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4591          * 03      Reserved, must be 0
4592          * 02      CRCCC, CRC Calculation, 1=enabled
4593          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4594          * 00      CRC0, CRC initial value, 1 = all 1s
4595          *
4596          * 1000 0001
4597          */
4598         RegValue = 0x81;
4599         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4600                 RegValue |= BIT4;
4601         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4602                 RegValue |= BIT4;
4603         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4604                 RegValue |= BIT2 + BIT1;
4605         write_reg(info, MD0, RegValue);
4606
4607         /* MD1, Mode Register 1
4608          *
4609          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4610          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4611          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4612          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4613          *
4614          * 0000 0000
4615          */
4616         RegValue = 0x00;
4617         write_reg(info, MD1, RegValue);
4618
4619         /* MD2, Mode Register 2
4620          *
4621          * 07      NRZFM, 0=NRZ, 1=FM
4622          * 06..05  CODE<1..0> Encoding, 00=NRZ
4623          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4624          * 02      Reserved, must be 0
4625          * 01..00  CNCT<1..0> Channel connection, 0=normal
4626          *
4627          * 0000 0000
4628          */
4629         RegValue = 0x00;
4630         switch(info->params.encoding) {
4631         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4632         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4633         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4634         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4635 #if 0
4636         case HDLC_ENCODING_NRZB:                                        /* not supported */
4637         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4638         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4639 #endif
4640         }
4641         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4642                 DpllDivisor = 16;
4643                 RegValue |= BIT3;
4644         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4645                 DpllDivisor = 8;
4646         } else {
4647                 DpllDivisor = 32;
4648                 RegValue |= BIT4;
4649         }
4650         write_reg(info, MD2, RegValue);
4651
4652
4653         /* RXS, Receive clock source
4654          *
4655          * 07      Reserved, must be 0
4656          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4657          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4658          */
4659         RegValue=0;
4660         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4661                 RegValue |= BIT6;
4662         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4663                 RegValue |= BIT6 + BIT5;
4664         write_reg(info, RXS, RegValue);
4665
4666         /* TXS, Transmit clock source
4667          *
4668          * 07      Reserved, must be 0
4669          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4670          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4671          */
4672         RegValue=0;
4673         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4674                 RegValue |= BIT6;
4675         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4676                 RegValue |= BIT6 + BIT5;
4677         write_reg(info, TXS, RegValue);
4678
4679         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4680                 set_rate(info, info->params.clock_speed * DpllDivisor);
4681         else
4682                 set_rate(info, info->params.clock_speed);
4683
4684         /* GPDATA (General Purpose I/O Data Register)
4685          *
4686          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4687          */
4688         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4689                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4690         else
4691                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4692         write_control_reg(info);
4693
4694         /* RRC Receive Ready Control 0
4695          *
4696          * 07..05  Reserved, must be 0
4697          * 04..00  RRC<4..0> Rx FIFO trigger active
4698          */
4699         write_reg(info, RRC, rx_active_fifo_level);
4700
4701         /* TRC0 Transmit Ready Control 0
4702          *
4703          * 07..05  Reserved, must be 0
4704          * 04..00  TRC<4..0> Tx FIFO trigger active
4705          */
4706         write_reg(info, TRC0, tx_active_fifo_level);
4707
4708         /* TRC1 Transmit Ready Control 1
4709          *
4710          * 07..05  Reserved, must be 0
4711          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4712          */
4713         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4714
4715         /* DMR, DMA Mode Register
4716          *
4717          * 07..05  Reserved, must be 0
4718          * 04      TMOD, Transfer Mode: 1=chained-block
4719          * 03      Reserved, must be 0
4720          * 02      NF, Number of Frames: 1=multi-frame
4721          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4722          * 00      Reserved, must be 0
4723          *
4724          * 0001 0100
4725          */
4726         write_reg(info, TXDMA + DMR, 0x14);
4727         write_reg(info, RXDMA + DMR, 0x14);
4728
4729         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4730         write_reg(info, RXDMA + CPB,
4731                 (unsigned char)(info->buffer_list_phys >> 16));
4732
4733         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4734         write_reg(info, TXDMA + CPB,
4735                 (unsigned char)(info->buffer_list_phys >> 16));
4736
4737         /* enable status interrupts. other code enables/disables
4738          * the individual sources for these two interrupt classes.
4739          */
4740         info->ie0_value |= TXINTE + RXINTE;
4741         write_reg(info, IE0, info->ie0_value);
4742
4743         /* CTL, MSCI control register
4744          *
4745          * 07..06  Reserved, set to 0
4746          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4747          * 04      IDLC, idle control, 0=mark 1=idle register
4748          * 03      BRK, break, 0=off 1 =on (async)
4749          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4750          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4751          * 00      RTS, RTS output control, 0=active 1=inactive
4752          *
4753          * 0001 0001
4754          */
4755         RegValue = 0x10;
4756         if (!(info->serial_signals & SerialSignal_RTS))
4757                 RegValue |= 0x01;
4758         write_reg(info, CTL, RegValue);
4759
4760         /* preamble not supported ! */
4761
4762         tx_set_idle(info);
4763         tx_stop(info);
4764         rx_stop(info);
4765
4766         set_rate(info, info->params.clock_speed);
4767
4768         if (info->params.loopback)
4769                 enable_loopback(info,1);
4770 }
4771
4772 /* Set the transmit HDLC idle mode
4773  */
4774 void tx_set_idle(SLMP_INFO *info)
4775 {
4776         unsigned char RegValue = 0xff;
4777
4778         /* Map API idle mode to SCA register bits */
4779         switch(info->idle_mode) {
4780         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4781         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4782         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4783         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4784         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4785         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4786         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4787         }
4788
4789         write_reg(info, IDL, RegValue);
4790 }
4791
4792 /* Query the adapter for the state of the V24 status (input) signals.
4793  */
4794 void get_signals(SLMP_INFO *info)
4795 {
4796         u16 status = read_reg(info, SR3);
4797         u16 gpstatus = read_status_reg(info);
4798         u16 testbit;
4799
4800         /* clear all serial signals except DTR and RTS */
4801         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4802
4803         /* set serial signal bits to reflect MISR */
4804
4805         if (!(status & BIT3))
4806                 info->serial_signals |= SerialSignal_CTS;
4807
4808         if ( !(status & BIT2))
4809                 info->serial_signals |= SerialSignal_DCD;
4810
4811         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4812         if (!(gpstatus & testbit))
4813                 info->serial_signals |= SerialSignal_RI;
4814
4815         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4816         if (!(gpstatus & testbit))
4817                 info->serial_signals |= SerialSignal_DSR;
4818 }
4819
4820 /* Set the state of DTR and RTS based on contents of
4821  * serial_signals member of device context.
4822  */
4823 void set_signals(SLMP_INFO *info)
4824 {
4825         unsigned char RegValue;
4826         u16 EnableBit;
4827
4828         RegValue = read_reg(info, CTL);
4829         if (info->serial_signals & SerialSignal_RTS)
4830                 RegValue &= ~BIT0;
4831         else
4832                 RegValue |= BIT0;
4833         write_reg(info, CTL, RegValue);
4834
4835         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4836         EnableBit = BIT1 << (info->port_num*2);
4837         if (info->serial_signals & SerialSignal_DTR)
4838                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4839         else
4840                 info->port_array[0]->ctrlreg_value |= EnableBit;
4841         write_control_reg(info);
4842 }
4843
4844 /*******************/
4845 /* DMA Buffer Code */
4846 /*******************/
4847
4848 /* Set the count for all receive buffers to SCABUFSIZE
4849  * and set the current buffer to the first buffer. This effectively
4850  * makes all buffers free and discards any data in buffers.
4851  */
4852 void rx_reset_buffers(SLMP_INFO *info)
4853 {
4854         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4855 }
4856
4857 /* Free the buffers used by a received frame
4858  *
4859  * info   pointer to device instance data
4860  * first  index of 1st receive buffer of frame
4861  * last   index of last receive buffer of frame
4862  */
4863 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4864 {
4865         int done = 0;
4866
4867         while(!done) {
4868                 /* reset current buffer for reuse */
4869                 info->rx_buf_list[first].status = 0xff;
4870
4871                 if (first == last) {
4872                         done = 1;
4873                         /* set new last rx descriptor address */
4874                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4875                 }
4876
4877                 first++;
4878                 if (first == info->rx_buf_count)
4879                         first = 0;
4880         }
4881
4882         /* set current buffer to next buffer after last buffer of frame */
4883         info->current_rx_buf = first;
4884 }
4885
4886 /* Return a received frame from the receive DMA buffers.
4887  * Only frames received without errors are returned.
4888  *
4889  * Return Value:        1 if frame returned, otherwise 0
4890  */
4891 int rx_get_frame(SLMP_INFO *info)
4892 {
4893         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4894         unsigned short status;
4895         unsigned int framesize = 0;
4896         int ReturnCode = 0;
4897         unsigned long flags;
4898         struct tty_struct *tty = info->tty;
4899         unsigned char addr_field = 0xff;
4900         SCADESC *desc;
4901         SCADESC_EX *desc_ex;
4902
4903 CheckAgain:
4904         /* assume no frame returned, set zero length */
4905         framesize = 0;
4906         addr_field = 0xff;
4907
4908         /*
4909          * current_rx_buf points to the 1st buffer of the next available
4910          * receive frame. To find the last buffer of the frame look for
4911          * a non-zero status field in the buffer entries. (The status
4912          * field is set by the 16C32 after completing a receive frame.
4913          */
4914         StartIndex = EndIndex = info->current_rx_buf;
4915
4916         for ( ;; ) {
4917                 desc = &info->rx_buf_list[EndIndex];
4918                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4919
4920                 if (desc->status == 0xff)
4921                         goto Cleanup;   /* current desc still in use, no frames available */
4922
4923                 if (framesize == 0 && info->params.addr_filter != 0xff)
4924                         addr_field = desc_ex->virt_addr[0];
4925
4926                 framesize += desc->length;
4927
4928                 /* Status != 0 means last buffer of frame */
4929                 if (desc->status)
4930                         break;
4931
4932                 EndIndex++;
4933                 if (EndIndex == info->rx_buf_count)
4934                         EndIndex = 0;
4935
4936                 if (EndIndex == info->current_rx_buf) {
4937                         /* all buffers have been 'used' but none mark      */
4938                         /* the end of a frame. Reset buffers and receiver. */
4939                         if ( info->rx_enabled ){
4940                                 spin_lock_irqsave(&info->lock,flags);
4941                                 rx_start(info);
4942                                 spin_unlock_irqrestore(&info->lock,flags);
4943                         }
4944                         goto Cleanup;
4945                 }
4946
4947         }
4948
4949         /* check status of receive frame */
4950
4951         /* frame status is byte stored after frame data
4952          *
4953          * 7 EOM (end of msg), 1 = last buffer of frame
4954          * 6 Short Frame, 1 = short frame
4955          * 5 Abort, 1 = frame aborted
4956          * 4 Residue, 1 = last byte is partial
4957          * 3 Overrun, 1 = overrun occurred during frame reception
4958          * 2 CRC,     1 = CRC error detected
4959          *
4960          */
4961         status = desc->status;
4962
4963         /* ignore CRC bit if not using CRC (bit is undefined) */
4964         /* Note:CRC is not save to data buffer */
4965         if (info->params.crc_type == HDLC_CRC_NONE)
4966                 status &= ~BIT2;
4967
4968         if (framesize == 0 ||
4969                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4970                 /* discard 0 byte frames, this seems to occur sometime
4971                  * when remote is idling flags.
4972                  */
4973                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4974                 goto CheckAgain;
4975         }
4976
4977         if (framesize < 2)
4978                 status |= BIT6;
4979
4980         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4981                 /* received frame has errors,
4982                  * update counts and mark frame size as 0
4983                  */
4984                 if (status & BIT6)
4985                         info->icount.rxshort++;
4986                 else if (status & BIT5)
4987                         info->icount.rxabort++;
4988                 else if (status & BIT3)
4989                         info->icount.rxover++;
4990                 else
4991                         info->icount.rxcrc++;
4992
4993                 framesize = 0;
4994 #ifdef CONFIG_HDLC
4995                 {
4996                         struct net_device_stats *stats = hdlc_stats(info->netdev);
4997                         stats->rx_errors++;
4998                         stats->rx_frame_errors++;
4999                 }
5000 #endif
5001         }
5002
5003         if ( debug_level >= DEBUG_LEVEL_BH )
5004                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
5005                         __FILE__,__LINE__,info->device_name,status,framesize);
5006
5007         if ( debug_level >= DEBUG_LEVEL_DATA )
5008                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
5009                         min_t(int, framesize,SCABUFSIZE),0);
5010
5011         if (framesize) {
5012                 if (framesize > info->max_frame_size)
5013                         info->icount.rxlong++;
5014                 else {
5015                         /* copy dma buffer(s) to contiguous intermediate buffer */
5016                         int copy_count = framesize;
5017                         int index = StartIndex;
5018                         unsigned char *ptmp = info->tmp_rx_buf;
5019                         info->tmp_rx_buf_count = framesize;
5020
5021                         info->icount.rxok++;
5022
5023                         while(copy_count) {
5024                                 int partial_count = min(copy_count,SCABUFSIZE);
5025                                 memcpy( ptmp,
5026                                         info->rx_buf_list_ex[index].virt_addr,
5027                                         partial_count );
5028                                 ptmp += partial_count;
5029                                 copy_count -= partial_count;
5030
5031                                 if ( ++index == info->rx_buf_count )
5032                                         index = 0;
5033                         }
5034
5035 #ifdef CONFIG_HDLC
5036                         if (info->netcount)
5037                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5038                         else
5039 #endif
5040                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5041                                                   info->flag_buf, framesize);
5042                 }
5043         }
5044         /* Free the buffers used by this frame. */
5045         rx_free_frame_buffers( info, StartIndex, EndIndex );
5046
5047         ReturnCode = 1;
5048
5049 Cleanup:
5050         if ( info->rx_enabled && info->rx_overflow ) {
5051                 /* Receiver is enabled, but needs to restarted due to
5052                  * rx buffer overflow. If buffers are empty, restart receiver.
5053                  */
5054                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5055                         spin_lock_irqsave(&info->lock,flags);
5056                         rx_start(info);
5057                         spin_unlock_irqrestore(&info->lock,flags);
5058                 }
5059         }
5060
5061         return ReturnCode;
5062 }
5063
5064 /* load the transmit DMA buffer with data
5065  */
5066 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5067 {
5068         unsigned short copy_count;
5069         unsigned int i = 0;
5070         SCADESC *desc;
5071         SCADESC_EX *desc_ex;
5072
5073         if ( debug_level >= DEBUG_LEVEL_DATA )
5074                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5075
5076         /* Copy source buffer to one or more DMA buffers, starting with
5077          * the first transmit dma buffer.
5078          */
5079         for(i=0;;)
5080         {
5081                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5082
5083                 desc = &info->tx_buf_list[i];
5084                 desc_ex = &info->tx_buf_list_ex[i];
5085
5086                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5087
5088                 desc->length = copy_count;
5089                 desc->status = 0;
5090
5091                 buf += copy_count;
5092                 count -= copy_count;
5093
5094                 if (!count)
5095                         break;
5096
5097                 i++;
5098                 if (i >= info->tx_buf_count)
5099                         i = 0;
5100         }
5101
5102         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5103         info->last_tx_buf = ++i;
5104 }
5105
5106 int register_test(SLMP_INFO *info)
5107 {
5108         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5109         static unsigned int count = sizeof(testval)/sizeof(unsigned char);
5110         unsigned int i;
5111         int rc = TRUE;
5112         unsigned long flags;
5113
5114         spin_lock_irqsave(&info->lock,flags);
5115         reset_port(info);
5116
5117         /* assume failure */
5118         info->init_error = DiagStatus_AddressFailure;
5119
5120         /* Write bit patterns to various registers but do it out of */
5121         /* sync, then read back and verify values. */
5122
5123         for (i = 0 ; i < count ; i++) {
5124                 write_reg(info, TMC, testval[i]);
5125                 write_reg(info, IDL, testval[(i+1)%count]);
5126                 write_reg(info, SA0, testval[(i+2)%count]);
5127                 write_reg(info, SA1, testval[(i+3)%count]);
5128
5129                 if ( (read_reg(info, TMC) != testval[i]) ||
5130                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5131                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5132                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5133                 {
5134                         rc = FALSE;
5135                         break;
5136                 }
5137         }
5138
5139         reset_port(info);
5140         spin_unlock_irqrestore(&info->lock,flags);
5141
5142         return rc;
5143 }
5144
5145 int irq_test(SLMP_INFO *info)
5146 {
5147         unsigned long timeout;
5148         unsigned long flags;
5149
5150         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5151
5152         spin_lock_irqsave(&info->lock,flags);
5153         reset_port(info);
5154
5155         /* assume failure */
5156         info->init_error = DiagStatus_IrqFailure;
5157         info->irq_occurred = FALSE;
5158
5159         /* setup timer0 on SCA0 to interrupt */
5160
5161         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5162         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5163
5164         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5165         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5166
5167
5168         /* TMCS, Timer Control/Status Register
5169          *
5170          * 07      CMF, Compare match flag (read only) 1=match
5171          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5172          * 05      Reserved, must be 0
5173          * 04      TME, Timer Enable
5174          * 03..00  Reserved, must be 0
5175          *
5176          * 0101 0000
5177          */
5178         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5179
5180         spin_unlock_irqrestore(&info->lock,flags);
5181
5182         timeout=100;
5183         while( timeout-- && !info->irq_occurred ) {
5184                 msleep_interruptible(10);
5185         }
5186
5187         spin_lock_irqsave(&info->lock,flags);
5188         reset_port(info);
5189         spin_unlock_irqrestore(&info->lock,flags);
5190
5191         return info->irq_occurred;
5192 }
5193
5194 /* initialize individual SCA device (2 ports)
5195  */
5196 static int sca_init(SLMP_INFO *info)
5197 {
5198         /* set wait controller to single mem partition (low), no wait states */
5199         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5200         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5201         write_reg(info, WCRL, 0);       /* wait controller low range */
5202         write_reg(info, WCRM, 0);       /* wait controller mid range */
5203         write_reg(info, WCRH, 0);       /* wait controller high range */
5204
5205         /* DPCR, DMA Priority Control
5206          *
5207          * 07..05  Not used, must be 0
5208          * 04      BRC, bus release condition: 0=all transfers complete
5209          * 03      CCC, channel change condition: 0=every cycle
5210          * 02..00  PR<2..0>, priority 100=round robin
5211          *
5212          * 00000100 = 0x04
5213          */
5214         write_reg(info, DPCR, dma_priority);
5215
5216         /* DMA Master Enable, BIT7: 1=enable all channels */
5217         write_reg(info, DMER, 0x80);
5218
5219         /* enable all interrupt classes */
5220         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5221         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5222         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5223
5224         /* ITCR, interrupt control register
5225          * 07      IPC, interrupt priority, 0=MSCI->DMA
5226          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5227          * 04      VOS, Vector Output, 0=unmodified vector
5228          * 03..00  Reserved, must be 0
5229          */
5230         write_reg(info, ITCR, 0);
5231
5232         return TRUE;
5233 }
5234
5235 /* initialize adapter hardware
5236  */
5237 int init_adapter(SLMP_INFO *info)
5238 {
5239         int i;
5240
5241         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5242         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5243         u32 readval;
5244
5245         info->misc_ctrl_value |= BIT30;
5246         *MiscCtrl = info->misc_ctrl_value;
5247
5248         /*
5249          * Force at least 170ns delay before clearing
5250          * reset bit. Each read from LCR takes at least
5251          * 30ns so 10 times for 300ns to be safe.
5252          */
5253         for(i=0;i<10;i++)
5254                 readval = *MiscCtrl;
5255
5256         info->misc_ctrl_value &= ~BIT30;
5257         *MiscCtrl = info->misc_ctrl_value;
5258
5259         /* init control reg (all DTRs off, all clksel=input) */
5260         info->ctrlreg_value = 0xaa;
5261         write_control_reg(info);
5262
5263         {
5264                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5265                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5266
5267                 switch(read_ahead_count)
5268                 {
5269                 case 16:
5270                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5271                         break;
5272                 case 8:
5273                         lcr1_brdr_value |= BIT5 + BIT4;
5274                         break;
5275                 case 4:
5276                         lcr1_brdr_value |= BIT5 + BIT3;
5277                         break;
5278                 case 0:
5279                         lcr1_brdr_value |= BIT5;
5280                         break;
5281                 }
5282
5283                 *LCR1BRDR = lcr1_brdr_value;
5284                 *MiscCtrl = misc_ctrl_value;
5285         }
5286
5287         sca_init(info->port_array[0]);
5288         sca_init(info->port_array[2]);
5289
5290         return TRUE;
5291 }
5292
5293 /* Loopback an HDLC frame to test the hardware
5294  * interrupt and DMA functions.
5295  */
5296 int loopback_test(SLMP_INFO *info)
5297 {
5298 #define TESTFRAMESIZE 20
5299
5300         unsigned long timeout;
5301         u16 count = TESTFRAMESIZE;
5302         unsigned char buf[TESTFRAMESIZE];
5303         int rc = FALSE;
5304         unsigned long flags;
5305
5306         struct tty_struct *oldtty = info->tty;
5307         u32 speed = info->params.clock_speed;
5308
5309         info->params.clock_speed = 3686400;
5310         info->tty = NULL;
5311
5312         /* assume failure */
5313         info->init_error = DiagStatus_DmaFailure;
5314
5315         /* build and send transmit frame */
5316         for (count = 0; count < TESTFRAMESIZE;++count)
5317                 buf[count] = (unsigned char)count;
5318
5319         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5320
5321         /* program hardware for HDLC and enabled receiver */
5322         spin_lock_irqsave(&info->lock,flags);
5323         hdlc_mode(info);
5324         enable_loopback(info,1);
5325         rx_start(info);
5326         info->tx_count = count;
5327         tx_load_dma_buffer(info,buf,count);
5328         tx_start(info);
5329         spin_unlock_irqrestore(&info->lock,flags);
5330
5331         /* wait for receive complete */
5332         /* Set a timeout for waiting for interrupt. */
5333         for ( timeout = 100; timeout; --timeout ) {
5334                 msleep_interruptible(10);
5335
5336                 if (rx_get_frame(info)) {
5337                         rc = TRUE;
5338                         break;
5339                 }
5340         }
5341
5342         /* verify received frame length and contents */
5343         if (rc == TRUE &&
5344                 ( info->tmp_rx_buf_count != count ||
5345                   memcmp(buf, info->tmp_rx_buf,count))) {
5346                 rc = FALSE;
5347         }
5348
5349         spin_lock_irqsave(&info->lock,flags);
5350         reset_adapter(info);
5351         spin_unlock_irqrestore(&info->lock,flags);
5352
5353         info->params.clock_speed = speed;
5354         info->tty = oldtty;
5355
5356         return rc;
5357 }
5358
5359 /* Perform diagnostics on hardware
5360  */
5361 int adapter_test( SLMP_INFO *info )
5362 {
5363         unsigned long flags;
5364         if ( debug_level >= DEBUG_LEVEL_INFO )
5365                 printk( "%s(%d):Testing device %s\n",
5366                         __FILE__,__LINE__,info->device_name );
5367
5368         spin_lock_irqsave(&info->lock,flags);
5369         init_adapter(info);
5370         spin_unlock_irqrestore(&info->lock,flags);
5371
5372         info->port_array[0]->port_count = 0;
5373
5374         if ( register_test(info->port_array[0]) &&
5375                 register_test(info->port_array[1])) {
5376
5377                 info->port_array[0]->port_count = 2;
5378
5379                 if ( register_test(info->port_array[2]) &&
5380                         register_test(info->port_array[3]) )
5381                         info->port_array[0]->port_count += 2;
5382         }
5383         else {
5384                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5385                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5386                 return -ENODEV;
5387         }
5388
5389         if ( !irq_test(info->port_array[0]) ||
5390                 !irq_test(info->port_array[1]) ||
5391                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5392                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5393                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5394                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5395                 return -ENODEV;
5396         }
5397
5398         if (!loopback_test(info->port_array[0]) ||
5399                 !loopback_test(info->port_array[1]) ||
5400                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5401                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5402                 printk( "%s(%d):DMA test failure for device %s\n",
5403                         __FILE__,__LINE__,info->device_name);
5404                 return -ENODEV;
5405         }
5406
5407         if ( debug_level >= DEBUG_LEVEL_INFO )
5408                 printk( "%s(%d):device %s passed diagnostics\n",
5409                         __FILE__,__LINE__,info->device_name );
5410
5411         info->port_array[0]->init_error = 0;
5412         info->port_array[1]->init_error = 0;
5413         if ( info->port_count > 2 ) {
5414                 info->port_array[2]->init_error = 0;
5415                 info->port_array[3]->init_error = 0;
5416         }
5417
5418         return 0;
5419 }
5420
5421 /* Test the shared memory on a PCI adapter.
5422  */
5423 int memory_test(SLMP_INFO *info)
5424 {
5425         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5426                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5427         unsigned long count = sizeof(testval)/sizeof(unsigned long);
5428         unsigned long i;
5429         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5430         unsigned long * addr = (unsigned long *)info->memory_base;
5431
5432         /* Test data lines with test pattern at one location. */
5433
5434         for ( i = 0 ; i < count ; i++ ) {
5435                 *addr = testval[i];
5436                 if ( *addr != testval[i] )
5437                         return FALSE;
5438         }
5439
5440         /* Test address lines with incrementing pattern over */
5441         /* entire address range. */
5442
5443         for ( i = 0 ; i < limit ; i++ ) {
5444                 *addr = i * 4;
5445                 addr++;
5446         }
5447
5448         addr = (unsigned long *)info->memory_base;
5449
5450         for ( i = 0 ; i < limit ; i++ ) {
5451                 if ( *addr != i * 4 )
5452                         return FALSE;
5453                 addr++;
5454         }
5455
5456         memset( info->memory_base, 0, SCA_MEM_SIZE );
5457         return TRUE;
5458 }
5459
5460 /* Load data into PCI adapter shared memory.
5461  *
5462  * The PCI9050 releases control of the local bus
5463  * after completing the current read or write operation.
5464  *
5465  * While the PCI9050 write FIFO not empty, the
5466  * PCI9050 treats all of the writes as a single transaction
5467  * and does not release the bus. This causes DMA latency problems
5468  * at high speeds when copying large data blocks to the shared memory.
5469  *
5470  * This function breaks a write into multiple transations by
5471  * interleaving a read which flushes the write FIFO and 'completes'
5472  * the write transation. This allows any pending DMA request to gain control
5473  * of the local bus in a timely fasion.
5474  */
5475 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5476 {
5477         /* A load interval of 16 allows for 4 32-bit writes at */
5478         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5479
5480         unsigned short interval = count / sca_pci_load_interval;
5481         unsigned short i;
5482
5483         for ( i = 0 ; i < interval ; i++ )
5484         {
5485                 memcpy(dest, src, sca_pci_load_interval);
5486                 read_status_reg(info);
5487                 dest += sca_pci_load_interval;
5488                 src += sca_pci_load_interval;
5489         }
5490
5491         memcpy(dest, src, count % sca_pci_load_interval);
5492 }
5493
5494 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5495 {
5496         int i;
5497         int linecount;
5498         if (xmit)
5499                 printk("%s tx data:\n",info->device_name);
5500         else
5501                 printk("%s rx data:\n",info->device_name);
5502
5503         while(count) {
5504                 if (count > 16)
5505                         linecount = 16;
5506                 else
5507                         linecount = count;
5508
5509                 for(i=0;i<linecount;i++)
5510                         printk("%02X ",(unsigned char)data[i]);
5511                 for(;i<17;i++)
5512                         printk("   ");
5513                 for(i=0;i<linecount;i++) {
5514                         if (data[i]>=040 && data[i]<=0176)
5515                                 printk("%c",data[i]);
5516                         else
5517                                 printk(".");
5518                 }
5519                 printk("\n");
5520
5521                 data  += linecount;
5522                 count -= linecount;
5523         }
5524 }       /* end of trace_block() */
5525
5526 /* called when HDLC frame times out
5527  * update stats and do tx completion processing
5528  */
5529 void tx_timeout(unsigned long context)
5530 {
5531         SLMP_INFO *info = (SLMP_INFO*)context;
5532         unsigned long flags;
5533
5534         if ( debug_level >= DEBUG_LEVEL_INFO )
5535                 printk( "%s(%d):%s tx_timeout()\n",
5536                         __FILE__,__LINE__,info->device_name);
5537         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5538                 info->icount.txtimeout++;
5539         }
5540         spin_lock_irqsave(&info->lock,flags);
5541         info->tx_active = 0;
5542         info->tx_count = info->tx_put = info->tx_get = 0;
5543
5544         spin_unlock_irqrestore(&info->lock,flags);
5545
5546 #ifdef CONFIG_HDLC
5547         if (info->netcount)
5548                 hdlcdev_tx_done(info);
5549         else
5550 #endif
5551                 bh_transmit(info);
5552 }
5553
5554 /* called to periodically check the DSR/RI modem signal input status
5555  */
5556 void status_timeout(unsigned long context)
5557 {
5558         u16 status = 0;
5559         SLMP_INFO *info = (SLMP_INFO*)context;
5560         unsigned long flags;
5561         unsigned char delta;
5562
5563
5564         spin_lock_irqsave(&info->lock,flags);
5565         get_signals(info);
5566         spin_unlock_irqrestore(&info->lock,flags);
5567
5568         /* check for DSR/RI state change */
5569
5570         delta = info->old_signals ^ info->serial_signals;
5571         info->old_signals = info->serial_signals;
5572
5573         if (delta & SerialSignal_DSR)
5574                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5575
5576         if (delta & SerialSignal_RI)
5577                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5578
5579         if (delta & SerialSignal_DCD)
5580                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5581
5582         if (delta & SerialSignal_CTS)
5583                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5584
5585         if (status)
5586                 isr_io_pin(info,status);
5587
5588         info->status_timer.data = (unsigned long)info;
5589         info->status_timer.function = status_timeout;
5590         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
5591         add_timer(&info->status_timer);
5592 }
5593
5594
5595 /* Register Access Routines -
5596  * All registers are memory mapped
5597  */
5598 #define CALC_REGADDR() \
5599         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5600         if (info->port_num > 1) \
5601                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5602         if ( info->port_num & 1) { \
5603                 if (Addr > 0x7f) \
5604                         RegAddr += 0x40;        /* DMA access */ \
5605                 else if (Addr > 0x1f && Addr < 0x60) \
5606                         RegAddr += 0x20;        /* MSCI access */ \
5607         }
5608
5609
5610 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5611 {
5612         CALC_REGADDR();
5613         return *RegAddr;
5614 }
5615 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5616 {
5617         CALC_REGADDR();
5618         *RegAddr = Value;
5619 }
5620
5621 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5622 {
5623         CALC_REGADDR();
5624         return *((u16 *)RegAddr);
5625 }
5626
5627 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5628 {
5629         CALC_REGADDR();
5630         *((u16 *)RegAddr) = Value;
5631 }
5632
5633 unsigned char read_status_reg(SLMP_INFO * info)
5634 {
5635         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5636         return *RegAddr;
5637 }
5638
5639 void write_control_reg(SLMP_INFO * info)
5640 {
5641         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5642         *RegAddr = info->port_array[0]->ctrlreg_value;
5643 }
5644
5645
5646 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5647                                           const struct pci_device_id *ent)
5648 {
5649         if (pci_enable_device(dev)) {
5650                 printk("error enabling pci device %p\n", dev);
5651                 return -EIO;
5652         }
5653         device_init( ++synclinkmp_adapter_count, dev );
5654         return 0;
5655 }
5656
5657 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5658 {
5659 }