drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76 #include <linux/synclink.h>
  77
  78 #include <asm/system.h>
  79 #include <asm/io.h>
  80 #include <asm/irq.h>
  81 #include <asm/dma.h>
  82 #include <asm/types.h>
  83 #include <asm/uaccess.h>
  84
  85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  86 #define SYNCLINK_GENERIC_HDLC 1
  87 #else
  88 #define SYNCLINK_GENERIC_HDLC 0
  89 #endif
  90
  91 /*
  92  * module identification
  93  */
  94 static char *driver_name     = "SyncLink GT";
  95 static char *driver_version  = "$Revision: 4.50 $";
  96 static char *tty_driver_name = "synclink_gt";
  97 static char *tty_dev_prefix  = "ttySLG";
  98 MODULE_LICENSE("GPL");
  99 #define MGSL_MAGIC 0x5401
 100 #define MAX_DEVICES 32
 101
 102 static struct pci_device_id pci_table[] = {
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {0,}, /* terminate list */
 108 };
 109 MODULE_DEVICE_TABLE(pci, pci_table);
 110
 111 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 112 static void remove_one(struct pci_dev *dev);
 113 static struct pci_driver pci_driver = {
 114         .name           = "synclink_gt",
 115         .id_table       = pci_table,
 116         .probe          = init_one,
 117         .remove         = __devexit_p(remove_one),
 118 };
 119
 120 static bool pci_registered;
 121
 122 /*
 123  * module configuration and status
 124  */
 125 static struct slgt_info *slgt_device_list;
 126 static int slgt_device_count;
 127
 128 static int ttymajor;
 129 static int debug_level;
 130 static int maxframe[MAX_DEVICES];
 131 static int dosyncppp[MAX_DEVICES];
 132
 133 module_param(ttymajor, int, 0);
 134 module_param(debug_level, int, 0);
 135 module_param_array(maxframe, int, NULL, 0);
 136 module_param_array(dosyncppp, int, NULL, 0);
 137
 138 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 139 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 140 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 141 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 142
 143 /*
 144  * tty support and callbacks
 145  */
 146 static struct tty_driver *serial_driver;
 147
 148 static int  open(struct tty_struct *tty, struct file * filp);
 149 static void close(struct tty_struct *tty, struct file * filp);
 150 static void hangup(struct tty_struct *tty);
 151 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 152
 153 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 154 static int put_char(struct tty_struct *tty, unsigned char ch);
 155 static void send_xchar(struct tty_struct *tty, char ch);
 156 static void wait_until_sent(struct tty_struct *tty, int timeout);
 157 static int  write_room(struct tty_struct *tty);
 158 static void flush_chars(struct tty_struct *tty);
 159 static void flush_buffer(struct tty_struct *tty);
 160 static void tx_hold(struct tty_struct *tty);
 161 static void tx_release(struct tty_struct *tty);
 162
 163 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 164 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 165 static int  chars_in_buffer(struct tty_struct *tty);
 166 static void throttle(struct tty_struct * tty);
 167 static void unthrottle(struct tty_struct * tty);
 168 static int set_break(struct tty_struct *tty, int break_state);
 169
 170 /*
 171  * generic HDLC support and callbacks
 172  */
 173 #if SYNCLINK_GENERIC_HDLC
 174 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 175 static void hdlcdev_tx_done(struct slgt_info *info);
 176 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 177 static int  hdlcdev_init(struct slgt_info *info);
 178 static void hdlcdev_exit(struct slgt_info *info);
 179 #endif
 180
 181
 182 /*
 183  * device specific structures, macros and functions
 184  */
 185
 186 #define SLGT_MAX_PORTS 4
 187 #define SLGT_REG_SIZE  256
 188
 189 /*
 190  * conditional wait facility
 191  */
 192 struct cond_wait {
 193         struct cond_wait *next;
 194         wait_queue_head_t q;
 195         wait_queue_t wait;
 196         unsigned int data;
 197 };
 198 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 199 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 200 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 201 static void flush_cond_wait(struct cond_wait **head);
 202
 203 /*
 204  * DMA buffer descriptor and access macros
 205  */
 206 struct slgt_desc
 207 {
 208         __le16 count;
 209         __le16 status;
 210         __le32 pbuf;  /* physical address of data buffer */
 211         __le32 next;  /* physical address of next descriptor */
 212
 213         /* driver book keeping */
 214         char *buf;          /* virtual  address of data buffer */
 215         unsigned int pdesc; /* physical address of this descriptor */
 216         dma_addr_t buf_dma_addr;
 217         unsigned short buf_count;
 218 };
 219
 220 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 221 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 222 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 223 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 224 #define desc_count(a)      (le16_to_cpu((a).count))
 225 #define desc_status(a)     (le16_to_cpu((a).status))
 226 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 227 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 228 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 229 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 230 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 231
 232 struct _input_signal_events {
 233         int ri_up;
 234         int ri_down;
 235         int dsr_up;
 236         int dsr_down;
 237         int dcd_up;
 238         int dcd_down;
 239         int cts_up;
 240         int cts_down;
 241 };
 242
 243 /*
 244  * device instance data structure
 245  */
 246 struct slgt_info {
 247         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 248         struct tty_port port;
 249
 250         struct slgt_info *next_device;  /* device list link */
 251
 252         int magic;
 253
 254         char device_name[25];
 255         struct pci_dev *pdev;
 256
 257         int port_count;  /* count of ports on adapter */
 258         int adapter_num; /* adapter instance number */
 259         int port_num;    /* port instance number */
 260
 261         /* array of pointers to port contexts on this adapter */
 262         struct slgt_info *port_array[SLGT_MAX_PORTS];
 263
 264         int                     line;           /* tty line instance number */
 265
 266         struct mgsl_icount      icount;
 267
 268         int                     timeout;
 269         int                     x_char;         /* xon/xoff character */
 270         unsigned int            read_status_mask;
 271         unsigned int            ignore_status_mask;
 272
 273         wait_queue_head_t       status_event_wait_q;
 274         wait_queue_head_t       event_wait_q;
 275         struct timer_list       tx_timer;
 276         struct timer_list       rx_timer;
 277
 278         unsigned int            gpio_present;
 279         struct cond_wait        *gpio_wait_q;
 280
 281         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 282
 283         struct work_struct task;
 284         u32 pending_bh;
 285         bool bh_requested;
 286         bool bh_running;
 287
 288         int isr_overflow;
 289         bool irq_requested;     /* true if IRQ requested */
 290         bool irq_occurred;      /* for diagnostics use */
 291
 292         /* device configuration */
 293
 294         unsigned int bus_type;
 295         unsigned int irq_level;
 296         unsigned long irq_flags;
 297
 298         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 299         u32 phys_reg_addr;
 300         bool reg_addr_requested;
 301
 302         MGSL_PARAMS params;       /* communications parameters */
 303         u32 idle_mode;
 304         u32 max_frame_size;       /* as set by device config */
 305
 306         unsigned int raw_rx_size;
 307         unsigned int if_mode;
 308
 309         /* device status */
 310
 311         bool rx_enabled;
 312         bool rx_restart;
 313
 314         bool tx_enabled;
 315         bool tx_active;
 316
 317         unsigned char signals;    /* serial signal states */
 318         int init_error;  /* initialization error */
 319
 320         unsigned char *tx_buf;
 321         int tx_count;
 322
 323         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 324         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 325         bool drop_rts_on_tx_done;
 326         struct  _input_signal_events    input_signal_events;
 327
 328         int dcd_chkcount;       /* check counts to prevent */
 329         int cts_chkcount;       /* too many IRQs if a signal */
 330         int dsr_chkcount;       /* is floating */
 331         int ri_chkcount;
 332
 333         char *bufs;             /* virtual address of DMA buffer lists */
 334         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 335
 336         unsigned int rbuf_count;
 337         struct slgt_desc *rbufs;
 338         unsigned int rbuf_current;
 339         unsigned int rbuf_index;
 340
 341         unsigned int tbuf_count;
 342         struct slgt_desc *tbufs;
 343         unsigned int tbuf_current;
 344         unsigned int tbuf_start;
 345
 346         unsigned char *tmp_rbuf;
 347         unsigned int tmp_rbuf_count;
 348
 349         /* SPPP/Cisco HDLC device parts */
 350
 351         int netcount;
 352         int dosyncppp;
 353         spinlock_t netlock;
 354 #if SYNCLINK_GENERIC_HDLC
 355         struct net_device *netdev;
 356 #endif
 357
 358 };
 359
 360 static MGSL_PARAMS default_params = {
 361         .mode            = MGSL_MODE_HDLC,
 362         .loopback        = 0,
 363         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 364         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 365         .clock_speed     = 0,
 366         .addr_filter     = 0xff,
 367         .crc_type        = HDLC_CRC_16_CCITT,
 368         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 369         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 370         .data_rate       = 9600,
 371         .data_bits       = 8,
 372         .stop_bits       = 1,
 373         .parity          = ASYNC_PARITY_NONE
 374 };
 375
 376
 377 #define BH_RECEIVE  1
 378 #define BH_TRANSMIT 2
 379 #define BH_STATUS   4
 380 #define IO_PIN_SHUTDOWN_LIMIT 100
 381
 382 #define DMABUFSIZE 256
 383 #define DESC_LIST_SIZE 4096
 384
 385 #define MASK_PARITY  BIT1
 386 #define MASK_FRAMING BIT0
 387 #define MASK_BREAK   BIT14
 388 #define MASK_OVERRUN BIT4
 389
 390 #define GSR   0x00 /* global status */
 391 #define JCR   0x04 /* JTAG control */
 392 #define IODR  0x08 /* GPIO direction */
 393 #define IOER  0x0c /* GPIO interrupt enable */
 394 #define IOVR  0x10 /* GPIO value */
 395 #define IOSR  0x14 /* GPIO interrupt status */
 396 #define TDR   0x80 /* tx data */
 397 #define RDR   0x80 /* rx data */
 398 #define TCR   0x82 /* tx control */
 399 #define TIR   0x84 /* tx idle */
 400 #define TPR   0x85 /* tx preamble */
 401 #define RCR   0x86 /* rx control */
 402 #define VCR   0x88 /* V.24 control */
 403 #define CCR   0x89 /* clock control */
 404 #define BDR   0x8a /* baud divisor */
 405 #define SCR   0x8c /* serial control */
 406 #define SSR   0x8e /* serial status */
 407 #define RDCSR 0x90 /* rx DMA control/status */
 408 #define TDCSR 0x94 /* tx DMA control/status */
 409 #define RDDAR 0x98 /* rx DMA descriptor address */
 410 #define TDDAR 0x9c /* tx DMA descriptor address */
 411
 412 #define RXIDLE      BIT14
 413 #define RXBREAK     BIT14
 414 #define IRQ_TXDATA  BIT13
 415 #define IRQ_TXIDLE  BIT12
 416 #define IRQ_TXUNDER BIT11 /* HDLC */
 417 #define IRQ_RXDATA  BIT10
 418 #define IRQ_RXIDLE  BIT9  /* HDLC */
 419 #define IRQ_RXBREAK BIT9  /* async */
 420 #define IRQ_RXOVER  BIT8
 421 #define IRQ_DSR     BIT7
 422 #define IRQ_CTS     BIT6
 423 #define IRQ_DCD     BIT5
 424 #define IRQ_RI      BIT4
 425 #define IRQ_ALL     0x3ff0
 426 #define IRQ_MASTER  BIT0
 427
 428 #define slgt_irq_on(info, mask) \
 429         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 430 #define slgt_irq_off(info, mask) \
 431         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 432
 433 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 434 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 435 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 436 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 437 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 438 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 439
 440 static void  msc_set_vcr(struct slgt_info *info);
 441
 442 static int  startup(struct slgt_info *info);
 443 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 444 static void shutdown(struct slgt_info *info);
 445 static void program_hw(struct slgt_info *info);
 446 static void change_params(struct slgt_info *info);
 447
 448 static int  register_test(struct slgt_info *info);
 449 static int  irq_test(struct slgt_info *info);
 450 static int  loopback_test(struct slgt_info *info);
 451 static int  adapter_test(struct slgt_info *info);
 452
 453 static void reset_adapter(struct slgt_info *info);
 454 static void reset_port(struct slgt_info *info);
 455 static void async_mode(struct slgt_info *info);
 456 static void sync_mode(struct slgt_info *info);
 457
 458 static void rx_stop(struct slgt_info *info);
 459 static void rx_start(struct slgt_info *info);
 460 static void reset_rbufs(struct slgt_info *info);
 461 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 462 static void rdma_reset(struct slgt_info *info);
 463 static bool rx_get_frame(struct slgt_info *info);
 464 static bool rx_get_buf(struct slgt_info *info);
 465
 466 static void tx_start(struct slgt_info *info);
 467 static void tx_stop(struct slgt_info *info);
 468 static void tx_set_idle(struct slgt_info *info);
 469 static unsigned int free_tbuf_count(struct slgt_info *info);
 470 static unsigned int tbuf_bytes(struct slgt_info *info);
 471 static void reset_tbufs(struct slgt_info *info);
 472 static void tdma_reset(struct slgt_info *info);
 473 static void tdma_start(struct slgt_info *info);
 474 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 475
 476 static void get_signals(struct slgt_info *info);
 477 static void set_signals(struct slgt_info *info);
 478 static void enable_loopback(struct slgt_info *info);
 479 static void set_rate(struct slgt_info *info, u32 data_rate);
 480
 481 static int  bh_action(struct slgt_info *info);
 482 static void bh_handler(struct work_struct *work);
 483 static void bh_transmit(struct slgt_info *info);
 484 static void isr_serial(struct slgt_info *info);
 485 static void isr_rdma(struct slgt_info *info);
 486 static void isr_txeom(struct slgt_info *info, unsigned short status);
 487 static void isr_tdma(struct slgt_info *info);
 488
 489 static int  alloc_dma_bufs(struct slgt_info *info);
 490 static void free_dma_bufs(struct slgt_info *info);
 491 static int  alloc_desc(struct slgt_info *info);
 492 static void free_desc(struct slgt_info *info);
 493 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 494 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 495
 496 static int  alloc_tmp_rbuf(struct slgt_info *info);
 497 static void free_tmp_rbuf(struct slgt_info *info);
 498
 499 static void tx_timeout(unsigned long context);
 500 static void rx_timeout(unsigned long context);
 501
 502 /*
 503  * ioctl handlers
 504  */
 505 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 506 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 507 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 508 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 509 static int  set_txidle(struct slgt_info *info, int idle_mode);
 510 static int  tx_enable(struct slgt_info *info, int enable);
 511 static int  tx_abort(struct slgt_info *info);
 512 static int  rx_enable(struct slgt_info *info, int enable);
 513 static int  modem_input_wait(struct slgt_info *info,int arg);
 514 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 515 static int  tiocmget(struct tty_struct *tty, struct file *file);
 516 static int  tiocmset(struct tty_struct *tty, struct file *file,
 517                      unsigned int set, unsigned int clear);
 518 static int set_break(struct tty_struct *tty, int break_state);
 519 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 520 static int  set_interface(struct slgt_info *info, int if_mode);
 521 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 523 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 524
 525 /*
 526  * driver functions
 527  */
 528 static void add_device(struct slgt_info *info);
 529 static void device_init(int adapter_num, struct pci_dev *pdev);
 530 static int  claim_resources(struct slgt_info *info);
 531 static void release_resources(struct slgt_info *info);
 532
 533 /*
 534  * DEBUG OUTPUT CODE
 535  */
 536 #ifndef DBGINFO
 537 #define DBGINFO(fmt)
 538 #endif
 539 #ifndef DBGERR
 540 #define DBGERR(fmt)
 541 #endif
 542 #ifndef DBGBH
 543 #define DBGBH(fmt)
 544 #endif
 545 #ifndef DBGISR
 546 #define DBGISR(fmt)
 547 #endif
 548
 549 #ifdef DBGDATA
 550 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 551 {
 552         int i;
 553         int linecount;
 554         printk("%s %s data:\n",info->device_name, label);
 555         while(count) {
 556                 linecount = (count > 16) ? 16 : count;
 557                 for(i=0; i < linecount; i++)
 558                         printk("%02X ",(unsigned char)data[i]);
 559                 for(;i<17;i++)
 560                         printk("   ");
 561                 for(i=0;i<linecount;i++) {
 562                         if (data[i]>=040 && data[i]<=0176)
 563                                 printk("%c",data[i]);
 564                         else
 565                                 printk(".");
 566                 }
 567                 printk("\n");
 568                 data  += linecount;
 569                 count -= linecount;
 570         }
 571 }
 572 #else
 573 #define DBGDATA(info, buf, size, label)
 574 #endif
 575
 576 #ifdef DBGTBUF
 577 static void dump_tbufs(struct slgt_info *info)
 578 {
 579         int i;
 580         printk("tbuf_current=%d\n", info->tbuf_current);
 581         for (i=0 ; i < info->tbuf_count ; i++) {
 582                 printk("%d: count=%04X status=%04X\n",
 583                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 584         }
 585 }
 586 #else
 587 #define DBGTBUF(info)
 588 #endif
 589
 590 #ifdef DBGRBUF
 591 static void dump_rbufs(struct slgt_info *info)
 592 {
 593         int i;
 594         printk("rbuf_current=%d\n", info->rbuf_current);
 595         for (i=0 ; i < info->rbuf_count ; i++) {
 596                 printk("%d: count=%04X status=%04X\n",
 597                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 598         }
 599 }
 600 #else
 601 #define DBGRBUF(info)
 602 #endif
 603
 604 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 605 {
 606 #ifdef SANITY_CHECK
 607         if (!info) {
 608                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 609                 return 1;
 610         }
 611         if (info->magic != MGSL_MAGIC) {
 612                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 613                 return 1;
 614         }
 615 #else
 616         if (!info)
 617                 return 1;
 618 #endif
 619         return 0;
 620 }
 621
 622 /**
 623  * line discipline callback wrappers
 624  *
 625  * The wrappers maintain line discipline references
 626  * while calling into the line discipline.
 627  *
 628  * ldisc_receive_buf  - pass receive data to line discipline
 629  */
 630 static void ldisc_receive_buf(struct tty_struct *tty,
 631                               const __u8 *data, char *flags, int count)
 632 {
 633         struct tty_ldisc *ld;
 634         if (!tty)
 635                 return;
 636         ld = tty_ldisc_ref(tty);
 637         if (ld) {
 638                 if (ld->ops->receive_buf)
 639                         ld->ops->receive_buf(tty, data, flags, count);
 640                 tty_ldisc_deref(ld);
 641         }
 642 }
 643
 644 /* tty callbacks */
 645
 646 static int open(struct tty_struct *tty, struct file *filp)
 647 {
 648         struct slgt_info *info;
 649         int retval, line;
 650         unsigned long flags;
 651
 652         line = tty->index;
 653         if ((line < 0) || (line >= slgt_device_count)) {
 654                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 655                 return -ENODEV;
 656         }
 657
 658         info = slgt_device_list;
 659         while(info && info->line != line)
 660                 info = info->next_device;
 661         if (sanity_check(info, tty->name, "open"))
 662                 return -ENODEV;
 663         if (info->init_error) {
 664                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 665                 return -ENODEV;
 666         }
 667
 668         tty->driver_data = info;
 669         info->port.tty = tty;
 670
 671         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 672
 673         /* If port is closing, signal caller to try again */
 674         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 675                 if (info->port.flags & ASYNC_CLOSING)
 676                         interruptible_sleep_on(&info->port.close_wait);
 677                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 678                         -EAGAIN : -ERESTARTSYS);
 679                 goto cleanup;
 680         }
 681
 682         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 683
 684         spin_lock_irqsave(&info->netlock, flags);
 685         if (info->netcount) {
 686                 retval = -EBUSY;
 687                 spin_unlock_irqrestore(&info->netlock, flags);
 688                 goto cleanup;
 689         }
 690         info->port.count++;
 691         spin_unlock_irqrestore(&info->netlock, flags);
 692
 693         if (info->port.count == 1) {
 694                 /* 1st open on this device, init hardware */
 695                 retval = startup(info);
 696                 if (retval < 0)
 697                         goto cleanup;
 698         }
 699
 700         retval = block_til_ready(tty, filp, info);
 701         if (retval) {
 702                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 703                 goto cleanup;
 704         }
 705
 706         retval = 0;
 707
 708 cleanup:
 709         if (retval) {
 710                 if (tty->count == 1)
 711                         info->port.tty = NULL; /* tty layer will release tty struct */
 712                 if(info->port.count)
 713                         info->port.count--;
 714         }
 715
 716         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 717         return retval;
 718 }
 719
 720 static void close(struct tty_struct *tty, struct file *filp)
 721 {
 722         struct slgt_info *info = tty->driver_data;
 723
 724         if (sanity_check(info, tty->name, "close"))
 725                 return;
 726         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 727
 728         if (!info->port.count)
 729                 return;
 730
 731         if (tty_hung_up_p(filp))
 732                 goto cleanup;
 733
 734         if ((tty->count == 1) && (info->port.count != 1)) {
 735                 /*
 736                  * tty->count is 1 and the tty structure will be freed.
 737                  * info->port.count should be one in this case.
 738                  * if it's not, correct it so that the port is shutdown.
 739                  */
 740                 DBGERR(("%s close: bad refcount; tty->count=1, "
 741                        "info->port.count=%d\n", info->device_name, info->port.count));
 742                 info->port.count = 1;
 743         }
 744
 745         info->port.count--;
 746
 747         /* if at least one open remaining, leave hardware active */
 748         if (info->port.count)
 749                 goto cleanup;
 750
 751         info->port.flags |= ASYNC_CLOSING;
 752
 753         /* set tty->closing to notify line discipline to
 754          * only process XON/XOFF characters. Only the N_TTY
 755          * discipline appears to use this (ppp does not).
 756          */
 757         tty->closing = 1;
 758
 759         /* wait for transmit data to clear all layers */
 760
 761         if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 762                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 763                 tty_wait_until_sent(tty, info->port.closing_wait);
 764         }
 765
 766         if (info->port.flags & ASYNC_INITIALIZED)
 767                 wait_until_sent(tty, info->timeout);
 768         flush_buffer(tty);
 769         tty_ldisc_flush(tty);
 770
 771         shutdown(info);
 772
 773         tty->closing = 0;
 774         info->port.tty = NULL;
 775
 776         if (info->port.blocked_open) {
 777                 if (info->port.close_delay) {
 778                         msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
 779                 }
 780                 wake_up_interruptible(&info->port.open_wait);
 781         }
 782
 783         info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 784
 785         wake_up_interruptible(&info->port.close_wait);
 786
 787 cleanup:
 788         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 789 }
 790
 791 static void hangup(struct tty_struct *tty)
 792 {
 793         struct slgt_info *info = tty->driver_data;
 794
 795         if (sanity_check(info, tty->name, "hangup"))
 796                 return;
 797         DBGINFO(("%s hangup\n", info->device_name));
 798
 799         flush_buffer(tty);
 800         shutdown(info);
 801
 802         info->port.count = 0;
 803         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 804         info->port.tty = NULL;
 805
 806         wake_up_interruptible(&info->port.open_wait);
 807 }
 808
 809 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 810 {
 811         struct slgt_info *info = tty->driver_data;
 812         unsigned long flags;
 813
 814         DBGINFO(("%s set_termios\n", tty->driver->name));
 815
 816         change_params(info);
 817
 818         /* Handle transition to B0 status */
 819         if (old_termios->c_cflag & CBAUD &&
 820             !(tty->termios->c_cflag & CBAUD)) {
 821                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 822                 spin_lock_irqsave(&info->lock,flags);
 823                 set_signals(info);
 824                 spin_unlock_irqrestore(&info->lock,flags);
 825         }
 826
 827         /* Handle transition away from B0 status */
 828         if (!(old_termios->c_cflag & CBAUD) &&
 829             tty->termios->c_cflag & CBAUD) {
 830                 info->signals |= SerialSignal_DTR;
 831                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 832                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 833                         info->signals |= SerialSignal_RTS;
 834                 }
 835                 spin_lock_irqsave(&info->lock,flags);
 836                 set_signals(info);
 837                 spin_unlock_irqrestore(&info->lock,flags);
 838         }
 839
 840         /* Handle turning off CRTSCTS */
 841         if (old_termios->c_cflag & CRTSCTS &&
 842             !(tty->termios->c_cflag & CRTSCTS)) {
 843                 tty->hw_stopped = 0;
 844                 tx_release(tty);
 845         }
 846 }
 847
 848 static int write(struct tty_struct *tty,
 849                  const unsigned char *buf, int count)
 850 {
 851         int ret = 0;
 852         struct slgt_info *info = tty->driver_data;
 853         unsigned long flags;
 854         unsigned int bufs_needed;
 855
 856         if (sanity_check(info, tty->name, "write"))
 857                 goto cleanup;
 858         DBGINFO(("%s write count=%d\n", info->device_name, count));
 859
 860         if (!info->tx_buf)
 861                 goto cleanup;
 862
 863         if (count > info->max_frame_size) {
 864                 ret = -EIO;
 865                 goto cleanup;
 866         }
 867
 868         if (!count)
 869                 goto cleanup;
 870
 871         if (!info->tx_active && info->tx_count) {
 872                 /* send accumulated data from send_char() */
 873                 tx_load(info, info->tx_buf, info->tx_count);
 874                 goto start;
 875         }
 876         bufs_needed = (count/DMABUFSIZE);
 877         if (count % DMABUFSIZE)
 878                 ++bufs_needed;
 879         if (bufs_needed > free_tbuf_count(info))
 880                 goto cleanup;
 881
 882         ret = info->tx_count = count;
 883         tx_load(info, buf, count);
 884         goto start;
 885
 886 start:
 887         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 888                 spin_lock_irqsave(&info->lock,flags);
 889                 if (!info->tx_active)
 890                         tx_start(info);
 891                 else
 892                         tdma_start(info);
 893                 spin_unlock_irqrestore(&info->lock,flags);
 894         }
 895
 896 cleanup:
 897         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 898         return ret;
 899 }
 900
 901 static int put_char(struct tty_struct *tty, unsigned char ch)
 902 {
 903         struct slgt_info *info = tty->driver_data;
 904         unsigned long flags;
 905         int ret = 0;
 906
 907         if (sanity_check(info, tty->name, "put_char"))
 908                 return 0;
 909         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 910         if (!info->tx_buf)
 911                 return 0;
 912         spin_lock_irqsave(&info->lock,flags);
 913         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 914                 info->tx_buf[info->tx_count++] = ch;
 915                 ret = 1;
 916         }
 917         spin_unlock_irqrestore(&info->lock,flags);
 918         return ret;
 919 }
 920
 921 static void send_xchar(struct tty_struct *tty, char ch)
 922 {
 923         struct slgt_info *info = tty->driver_data;
 924         unsigned long flags;
 925
 926         if (sanity_check(info, tty->name, "send_xchar"))
 927                 return;
 928         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 929         info->x_char = ch;
 930         if (ch) {
 931                 spin_lock_irqsave(&info->lock,flags);
 932                 if (!info->tx_enabled)
 933                         tx_start(info);
 934                 spin_unlock_irqrestore(&info->lock,flags);
 935         }
 936 }
 937
 938 static void wait_until_sent(struct tty_struct *tty, int timeout)
 939 {
 940         struct slgt_info *info = tty->driver_data;
 941         unsigned long orig_jiffies, char_time;
 942
 943         if (!info )
 944                 return;
 945         if (sanity_check(info, tty->name, "wait_until_sent"))
 946                 return;
 947         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 948         if (!(info->port.flags & ASYNC_INITIALIZED))
 949                 goto exit;
 950
 951         orig_jiffies = jiffies;
 952
 953         /* Set check interval to 1/5 of estimated time to
 954          * send a character, and make it at least 1. The check
 955          * interval should also be less than the timeout.
 956          * Note: use tight timings here to satisfy the NIST-PCTS.
 957          */
 958
 959         lock_kernel();
 960
 961         if (info->params.data_rate) {
 962                 char_time = info->timeout/(32 * 5);
 963                 if (!char_time)
 964                         char_time++;
 965         } else
 966                 char_time = 1;
 967
 968         if (timeout)
 969                 char_time = min_t(unsigned long, char_time, timeout);
 970
 971         while (info->tx_active) {
 972                 msleep_interruptible(jiffies_to_msecs(char_time));
 973                 if (signal_pending(current))
 974                         break;
 975                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 976                         break;
 977         }
 978         unlock_kernel();
 979
 980 exit:
 981         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 982 }
 983
 984 static int write_room(struct tty_struct *tty)
 985 {
 986         struct slgt_info *info = tty->driver_data;
 987         int ret;
 988
 989         if (sanity_check(info, tty->name, "write_room"))
 990                 return 0;
 991         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 992         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 993         return ret;
 994 }
 995
 996 static void flush_chars(struct tty_struct *tty)
 997 {
 998         struct slgt_info *info = tty->driver_data;
 999         unsigned long flags;
1000
1001         if (sanity_check(info, tty->name, "flush_chars"))
1002                 return;
1003         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1004
1005         if (info->tx_count <= 0 || tty->stopped ||
1006             tty->hw_stopped || !info->tx_buf)
1007                 return;
1008
1009         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1010
1011         spin_lock_irqsave(&info->lock,flags);
1012         if (!info->tx_active && info->tx_count) {
1013                 tx_load(info, info->tx_buf,info->tx_count);
1014                 tx_start(info);
1015         }
1016         spin_unlock_irqrestore(&info->lock,flags);
1017 }
1018
1019 static void flush_buffer(struct tty_struct *tty)
1020 {
1021         struct slgt_info *info = tty->driver_data;
1022         unsigned long flags;
1023
1024         if (sanity_check(info, tty->name, "flush_buffer"))
1025                 return;
1026         DBGINFO(("%s flush_buffer\n", info->device_name));
1027
1028         spin_lock_irqsave(&info->lock,flags);
1029         if (!info->tx_active)
1030                 info->tx_count = 0;
1031         spin_unlock_irqrestore(&info->lock,flags);
1032
1033         tty_wakeup(tty);
1034 }
1035
1036 /*
1037  * throttle (stop) transmitter
1038  */
1039 static void tx_hold(struct tty_struct *tty)
1040 {
1041         struct slgt_info *info = tty->driver_data;
1042         unsigned long flags;
1043
1044         if (sanity_check(info, tty->name, "tx_hold"))
1045                 return;
1046         DBGINFO(("%s tx_hold\n", info->device_name));
1047         spin_lock_irqsave(&info->lock,flags);
1048         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1049                 tx_stop(info);
1050         spin_unlock_irqrestore(&info->lock,flags);
1051 }
1052
1053 /*
1054  * release (start) transmitter
1055  */
1056 static void tx_release(struct tty_struct *tty)
1057 {
1058         struct slgt_info *info = tty->driver_data;
1059         unsigned long flags;
1060
1061         if (sanity_check(info, tty->name, "tx_release"))
1062                 return;
1063         DBGINFO(("%s tx_release\n", info->device_name));
1064         spin_lock_irqsave(&info->lock,flags);
1065         if (!info->tx_active && info->tx_count) {
1066                 tx_load(info, info->tx_buf, info->tx_count);
1067                 tx_start(info);
1068         }
1069         spin_unlock_irqrestore(&info->lock,flags);
1070 }
1071
1072 /*
1073  * Service an IOCTL request
1074  *
1075  * Arguments
1076  *
1077  *      tty     pointer to tty instance data
1078  *      file    pointer to associated file object for device
1079  *      cmd     IOCTL command code
1080  *      arg     command argument/context
1081  *
1082  * Return 0 if success, otherwise error code
1083  */
1084 static int ioctl(struct tty_struct *tty, struct file *file,
1085                  unsigned int cmd, unsigned long arg)
1086 {
1087         struct slgt_info *info = tty->driver_data;
1088         struct mgsl_icount cnow;        /* kernel counter temps */
1089         struct serial_icounter_struct __user *p_cuser;  /* user space */
1090         unsigned long flags;
1091         void __user *argp = (void __user *)arg;
1092         int ret;
1093
1094         if (sanity_check(info, tty->name, "ioctl"))
1095                 return -ENODEV;
1096         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1097
1098         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1099             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1100                 if (tty->flags & (1 << TTY_IO_ERROR))
1101                     return -EIO;
1102         }
1103
1104         lock_kernel();
1105
1106         switch (cmd) {
1107         case MGSL_IOCGPARAMS:
1108                 ret = get_params(info, argp);
1109                 break;
1110         case MGSL_IOCSPARAMS:
1111                 ret = set_params(info, argp);
1112                 break;
1113         case MGSL_IOCGTXIDLE:
1114                 ret = get_txidle(info, argp);
1115                 break;
1116         case MGSL_IOCSTXIDLE:
1117                 ret = set_txidle(info, (int)arg);
1118                 break;
1119         case MGSL_IOCTXENABLE:
1120                 ret = tx_enable(info, (int)arg);
1121                 break;
1122         case MGSL_IOCRXENABLE:
1123                 ret = rx_enable(info, (int)arg);
1124                 break;
1125         case MGSL_IOCTXABORT:
1126                 ret = tx_abort(info);
1127                 break;
1128         case MGSL_IOCGSTATS:
1129                 ret = get_stats(info, argp);
1130                 break;
1131         case MGSL_IOCWAITEVENT:
1132                 ret = wait_mgsl_event(info, argp);
1133                 break;
1134         case TIOCMIWAIT:
1135                 ret = modem_input_wait(info,(int)arg);
1136                 break;
1137         case MGSL_IOCGIF:
1138                 ret = get_interface(info, argp);
1139                 break;
1140         case MGSL_IOCSIF:
1141                 ret = set_interface(info,(int)arg);
1142                 break;
1143         case MGSL_IOCSGPIO:
1144                 ret = set_gpio(info, argp);
1145                 break;
1146         case MGSL_IOCGGPIO:
1147                 ret = get_gpio(info, argp);
1148                 break;
1149         case MGSL_IOCWAITGPIO:
1150                 ret = wait_gpio(info, argp);
1151                 break;
1152         case TIOCGICOUNT:
1153                 spin_lock_irqsave(&info->lock,flags);
1154                 cnow = info->icount;
1155                 spin_unlock_irqrestore(&info->lock,flags);
1156                 p_cuser = argp;
1157                 if (put_user(cnow.cts, &p_cuser->cts) ||
1158                     put_user(cnow.dsr, &p_cuser->dsr) ||
1159                     put_user(cnow.rng, &p_cuser->rng) ||
1160                     put_user(cnow.dcd, &p_cuser->dcd) ||
1161                     put_user(cnow.rx, &p_cuser->rx) ||
1162                     put_user(cnow.tx, &p_cuser->tx) ||
1163                     put_user(cnow.frame, &p_cuser->frame) ||
1164                     put_user(cnow.overrun, &p_cuser->overrun) ||
1165                     put_user(cnow.parity, &p_cuser->parity) ||
1166                     put_user(cnow.brk, &p_cuser->brk) ||
1167                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1168                         ret = -EFAULT;
1169                 ret = 0;
1170                 break;
1171         default:
1172                 ret = -ENOIOCTLCMD;
1173         }
1174         unlock_kernel();
1175         return ret;
1176 }
1177
1178 /*
1179  * support for 32 bit ioctl calls on 64 bit systems
1180  */
1181 #ifdef CONFIG_COMPAT
1182 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1183 {
1184         struct MGSL_PARAMS32 tmp_params;
1185
1186         DBGINFO(("%s get_params32\n", info->device_name));
1187         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1188         tmp_params.loopback        = info->params.loopback;
1189         tmp_params.flags           = info->params.flags;
1190         tmp_params.encoding        = info->params.encoding;
1191         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1192         tmp_params.addr_filter     = info->params.addr_filter;
1193         tmp_params.crc_type        = info->params.crc_type;
1194         tmp_params.preamble_length = info->params.preamble_length;
1195         tmp_params.preamble        = info->params.preamble;
1196         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1197         tmp_params.data_bits       = info->params.data_bits;
1198         tmp_params.stop_bits       = info->params.stop_bits;
1199         tmp_params.parity          = info->params.parity;
1200         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1201                 return -EFAULT;
1202         return 0;
1203 }
1204
1205 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1206 {
1207         struct MGSL_PARAMS32 tmp_params;
1208
1209         DBGINFO(("%s set_params32\n", info->device_name));
1210         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1211                 return -EFAULT;
1212
1213         spin_lock(&info->lock);
1214         info->params.mode            = tmp_params.mode;
1215         info->params.loopback        = tmp_params.loopback;
1216         info->params.flags           = tmp_params.flags;
1217         info->params.encoding        = tmp_params.encoding;
1218         info->params.clock_speed     = tmp_params.clock_speed;
1219         info->params.addr_filter     = tmp_params.addr_filter;
1220         info->params.crc_type        = tmp_params.crc_type;
1221         info->params.preamble_length = tmp_params.preamble_length;
1222         info->params.preamble        = tmp_params.preamble;
1223         info->params.data_rate       = tmp_params.data_rate;
1224         info->params.data_bits       = tmp_params.data_bits;
1225         info->params.stop_bits       = tmp_params.stop_bits;
1226         info->params.parity          = tmp_params.parity;
1227         spin_unlock(&info->lock);
1228
1229         change_params(info);
1230
1231         return 0;
1232 }
1233
1234 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1235                          unsigned int cmd, unsigned long arg)
1236 {
1237         struct slgt_info *info = tty->driver_data;
1238         int rc = -ENOIOCTLCMD;
1239
1240         if (sanity_check(info, tty->name, "compat_ioctl"))
1241                 return -ENODEV;
1242         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1243
1244         switch (cmd) {
1245
1246         case MGSL_IOCSPARAMS32:
1247                 rc = set_params32(info, compat_ptr(arg));
1248                 break;
1249
1250         case MGSL_IOCGPARAMS32:
1251                 rc = get_params32(info, compat_ptr(arg));
1252                 break;
1253
1254         case MGSL_IOCGPARAMS:
1255         case MGSL_IOCSPARAMS:
1256         case MGSL_IOCGTXIDLE:
1257         case MGSL_IOCGSTATS:
1258         case MGSL_IOCWAITEVENT:
1259         case MGSL_IOCGIF:
1260         case MGSL_IOCSGPIO:
1261         case MGSL_IOCGGPIO:
1262         case MGSL_IOCWAITGPIO:
1263         case TIOCGICOUNT:
1264                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1265                 break;
1266
1267         case MGSL_IOCSTXIDLE:
1268         case MGSL_IOCTXENABLE:
1269         case MGSL_IOCRXENABLE:
1270         case MGSL_IOCTXABORT:
1271         case TIOCMIWAIT:
1272         case MGSL_IOCSIF:
1273                 rc = ioctl(tty, file, cmd, arg);
1274                 break;
1275         }
1276
1277         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1278         return rc;
1279 }
1280 #else
1281 #define slgt_compat_ioctl NULL
1282 #endif /* ifdef CONFIG_COMPAT */
1283
1284 /*
1285  * proc fs support
1286  */
1287 static inline int line_info(char *buf, struct slgt_info *info)
1288 {
1289         char stat_buf[30];
1290         int ret;
1291         unsigned long flags;
1292
1293         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1294                       info->device_name, info->phys_reg_addr,
1295                       info->irq_level, info->max_frame_size);
1296
1297         /* output current serial signal states */
1298         spin_lock_irqsave(&info->lock,flags);
1299         get_signals(info);
1300         spin_unlock_irqrestore(&info->lock,flags);
1301
1302         stat_buf[0] = 0;
1303         stat_buf[1] = 0;
1304         if (info->signals & SerialSignal_RTS)
1305                 strcat(stat_buf, "|RTS");
1306         if (info->signals & SerialSignal_CTS)
1307                 strcat(stat_buf, "|CTS");
1308         if (info->signals & SerialSignal_DTR)
1309                 strcat(stat_buf, "|DTR");
1310         if (info->signals & SerialSignal_DSR)
1311                 strcat(stat_buf, "|DSR");
1312         if (info->signals & SerialSignal_DCD)
1313                 strcat(stat_buf, "|CD");
1314         if (info->signals & SerialSignal_RI)
1315                 strcat(stat_buf, "|RI");
1316
1317         if (info->params.mode != MGSL_MODE_ASYNC) {
1318                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1319                                info->icount.txok, info->icount.rxok);
1320                 if (info->icount.txunder)
1321                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1322                 if (info->icount.txabort)
1323                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1324                 if (info->icount.rxshort)
1325                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1326                 if (info->icount.rxlong)
1327                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1328                 if (info->icount.rxover)
1329                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1330                 if (info->icount.rxcrc)
1331                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1332         } else {
1333                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1334                                info->icount.tx, info->icount.rx);
1335                 if (info->icount.frame)
1336                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1337                 if (info->icount.parity)
1338                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1339                 if (info->icount.brk)
1340                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1341                 if (info->icount.overrun)
1342                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1343         }
1344
1345         /* Append serial signal status to end */
1346         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1347
1348         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1349                        info->tx_active,info->bh_requested,info->bh_running,
1350                        info->pending_bh);
1351
1352         return ret;
1353 }
1354
1355 /* Called to print information about devices
1356  */
1357 static int read_proc(char *page, char **start, off_t off, int count,
1358                      int *eof, void *data)
1359 {
1360         int len = 0, l;
1361         off_t   begin = 0;
1362         struct slgt_info *info;
1363
1364         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1365
1366         info = slgt_device_list;
1367         while( info ) {
1368                 l = line_info(page + len, info);
1369                 len += l;
1370                 if (len+begin > off+count)
1371                         goto done;
1372                 if (len+begin < off) {
1373                         begin += len;
1374                         len = 0;
1375                 }
1376                 info = info->next_device;
1377         }
1378
1379         *eof = 1;
1380 done:
1381         if (off >= len+begin)
1382                 return 0;
1383         *start = page + (off-begin);
1384         return ((count < begin+len-off) ? count : begin+len-off);
1385 }
1386
1387 /*
1388  * return count of bytes in transmit buffer
1389  */
1390 static int chars_in_buffer(struct tty_struct *tty)
1391 {
1392         struct slgt_info *info = tty->driver_data;
1393         int count;
1394         if (sanity_check(info, tty->name, "chars_in_buffer"))
1395                 return 0;
1396         count = tbuf_bytes(info);
1397         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1398         return count;
1399 }
1400
1401 /*
1402  * signal remote device to throttle send data (our receive data)
1403  */
1404 static void throttle(struct tty_struct * tty)
1405 {
1406         struct slgt_info *info = tty->driver_data;
1407         unsigned long flags;
1408
1409         if (sanity_check(info, tty->name, "throttle"))
1410                 return;
1411         DBGINFO(("%s throttle\n", info->device_name));
1412         if (I_IXOFF(tty))
1413                 send_xchar(tty, STOP_CHAR(tty));
1414         if (tty->termios->c_cflag & CRTSCTS) {
1415                 spin_lock_irqsave(&info->lock,flags);
1416                 info->signals &= ~SerialSignal_RTS;
1417                 set_signals(info);
1418                 spin_unlock_irqrestore(&info->lock,flags);
1419         }
1420 }
1421
1422 /*
1423  * signal remote device to stop throttling send data (our receive data)
1424  */
1425 static void unthrottle(struct tty_struct * tty)
1426 {
1427         struct slgt_info *info = tty->driver_data;
1428         unsigned long flags;
1429
1430         if (sanity_check(info, tty->name, "unthrottle"))
1431                 return;
1432         DBGINFO(("%s unthrottle\n", info->device_name));
1433         if (I_IXOFF(tty)) {
1434                 if (info->x_char)
1435                         info->x_char = 0;
1436                 else
1437                         send_xchar(tty, START_CHAR(tty));
1438         }
1439         if (tty->termios->c_cflag & CRTSCTS) {
1440                 spin_lock_irqsave(&info->lock,flags);
1441                 info->signals |= SerialSignal_RTS;
1442                 set_signals(info);
1443                 spin_unlock_irqrestore(&info->lock,flags);
1444         }
1445 }
1446
1447 /*
1448  * set or clear transmit break condition
1449  * break_state  -1=set break condition, 0=clear
1450  */
1451 static int set_break(struct tty_struct *tty, int break_state)
1452 {
1453         struct slgt_info *info = tty->driver_data;
1454         unsigned short value;
1455         unsigned long flags;
1456
1457         if (sanity_check(info, tty->name, "set_break"))
1458                 return -EINVAL;
1459         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1460
1461         spin_lock_irqsave(&info->lock,flags);
1462         value = rd_reg16(info, TCR);
1463         if (break_state == -1)
1464                 value |= BIT6;
1465         else
1466                 value &= ~BIT6;
1467         wr_reg16(info, TCR, value);
1468         spin_unlock_irqrestore(&info->lock,flags);
1469         return 0;
1470 }
1471
1472 #if SYNCLINK_GENERIC_HDLC
1473
1474 /**
1475  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1476  * set encoding and frame check sequence (FCS) options
1477  *
1478  * dev       pointer to network device structure
1479  * encoding  serial encoding setting
1480  * parity    FCS setting
1481  *
1482  * returns 0 if success, otherwise error code
1483  */
1484 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1485                           unsigned short parity)
1486 {
1487         struct slgt_info *info = dev_to_port(dev);
1488         unsigned char  new_encoding;
1489         unsigned short new_crctype;
1490
1491         /* return error if TTY interface open */
1492         if (info->port.count)
1493                 return -EBUSY;
1494
1495         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1496
1497         switch (encoding)
1498         {
1499         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1500         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1501         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1502         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1503         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1504         default: return -EINVAL;
1505         }
1506
1507         switch (parity)
1508         {
1509         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1510         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1511         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1512         default: return -EINVAL;
1513         }
1514
1515         info->params.encoding = new_encoding;
1516         info->params.crc_type = new_crctype;
1517
1518         /* if network interface up, reprogram hardware */
1519         if (info->netcount)
1520                 program_hw(info);
1521
1522         return 0;
1523 }
1524
1525 /**
1526  * called by generic HDLC layer to send frame
1527  *
1528  * skb  socket buffer containing HDLC frame
1529  * dev  pointer to network device structure
1530  *
1531  * returns 0 if success, otherwise error code
1532  */
1533 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1534 {
1535         struct slgt_info *info = dev_to_port(dev);
1536         unsigned long flags;
1537
1538         DBGINFO(("%s hdlc_xmit\n", dev->name));
1539
1540         /* stop sending until this frame completes */
1541         netif_stop_queue(dev);
1542
1543         /* copy data to device buffers */
1544         info->tx_count = skb->len;
1545         tx_load(info, skb->data, skb->len);
1546
1547         /* update network statistics */
1548         dev->stats.tx_packets++;
1549         dev->stats.tx_bytes += skb->len;
1550
1551         /* done with socket buffer, so free it */
1552         dev_kfree_skb(skb);
1553
1554         /* save start time for transmit timeout detection */
1555         dev->trans_start = jiffies;
1556
1557         /* start hardware transmitter if necessary */
1558         spin_lock_irqsave(&info->lock,flags);
1559         if (!info->tx_active)
1560                 tx_start(info);
1561         spin_unlock_irqrestore(&info->lock,flags);
1562
1563         return 0;
1564 }
1565
1566 /**
1567  * called by network layer when interface enabled
1568  * claim resources and initialize hardware
1569  *
1570  * dev  pointer to network device structure
1571  *
1572  * returns 0 if success, otherwise error code
1573  */
1574 static int hdlcdev_open(struct net_device *dev)
1575 {
1576         struct slgt_info *info = dev_to_port(dev);
1577         int rc;
1578         unsigned long flags;
1579
1580         if (!try_module_get(THIS_MODULE))
1581                 return -EBUSY;
1582
1583         DBGINFO(("%s hdlcdev_open\n", dev->name));
1584
1585         /* generic HDLC layer open processing */
1586         if ((rc = hdlc_open(dev)))
1587                 return rc;
1588
1589         /* arbitrate between network and tty opens */
1590         spin_lock_irqsave(&info->netlock, flags);
1591         if (info->port.count != 0 || info->netcount != 0) {
1592                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1593                 spin_unlock_irqrestore(&info->netlock, flags);
1594                 return -EBUSY;
1595         }
1596         info->netcount=1;
1597         spin_unlock_irqrestore(&info->netlock, flags);
1598
1599         /* claim resources and init adapter */
1600         if ((rc = startup(info)) != 0) {
1601                 spin_lock_irqsave(&info->netlock, flags);
1602                 info->netcount=0;
1603                 spin_unlock_irqrestore(&info->netlock, flags);
1604                 return rc;
1605         }
1606
1607         /* assert DTR and RTS, apply hardware settings */
1608         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1609         program_hw(info);
1610
1611         /* enable network layer transmit */
1612         dev->trans_start = jiffies;
1613         netif_start_queue(dev);
1614
1615         /* inform generic HDLC layer of current DCD status */
1616         spin_lock_irqsave(&info->lock, flags);
1617         get_signals(info);
1618         spin_unlock_irqrestore(&info->lock, flags);
1619         if (info->signals & SerialSignal_DCD)
1620                 netif_carrier_on(dev);
1621         else
1622                 netif_carrier_off(dev);
1623         return 0;
1624 }
1625
1626 /**
1627  * called by network layer when interface is disabled
1628  * shutdown hardware and release resources
1629  *
1630  * dev  pointer to network device structure
1631  *
1632  * returns 0 if success, otherwise error code
1633  */
1634 static int hdlcdev_close(struct net_device *dev)
1635 {
1636         struct slgt_info *info = dev_to_port(dev);
1637         unsigned long flags;
1638
1639         DBGINFO(("%s hdlcdev_close\n", dev->name));
1640
1641         netif_stop_queue(dev);
1642
1643         /* shutdown adapter and release resources */
1644         shutdown(info);
1645
1646         hdlc_close(dev);
1647
1648         spin_lock_irqsave(&info->netlock, flags);
1649         info->netcount=0;
1650         spin_unlock_irqrestore(&info->netlock, flags);
1651
1652         module_put(THIS_MODULE);
1653         return 0;
1654 }
1655
1656 /**
1657  * called by network layer to process IOCTL call to network device
1658  *
1659  * dev  pointer to network device structure
1660  * ifr  pointer to network interface request structure
1661  * cmd  IOCTL command code
1662  *
1663  * returns 0 if success, otherwise error code
1664  */
1665 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1666 {
1667         const size_t size = sizeof(sync_serial_settings);
1668         sync_serial_settings new_line;
1669         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1670         struct slgt_info *info = dev_to_port(dev);
1671         unsigned int flags;
1672
1673         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1674
1675         /* return error if TTY interface open */
1676         if (info->port.count)
1677                 return -EBUSY;
1678
1679         if (cmd != SIOCWANDEV)
1680                 return hdlc_ioctl(dev, ifr, cmd);
1681
1682         switch(ifr->ifr_settings.type) {
1683         case IF_GET_IFACE: /* return current sync_serial_settings */
1684
1685                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1686                 if (ifr->ifr_settings.size < size) {
1687                         ifr->ifr_settings.size = size; /* data size wanted */
1688                         return -ENOBUFS;
1689                 }
1690
1691                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1692                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1693                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1694                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1695
1696                 switch (flags){
1697                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1698                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1699                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1700                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1701                 default: new_line.clock_type = CLOCK_DEFAULT;
1702                 }
1703
1704                 new_line.clock_rate = info->params.clock_speed;
1705                 new_line.loopback   = info->params.loopback ? 1:0;
1706
1707                 if (copy_to_user(line, &new_line, size))
1708                         return -EFAULT;
1709                 return 0;
1710
1711         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1712
1713                 if(!capable(CAP_NET_ADMIN))
1714                         return -EPERM;
1715                 if (copy_from_user(&new_line, line, size))
1716                         return -EFAULT;
1717
1718                 switch (new_line.clock_type)
1719                 {
1720                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1721                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1722                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1723                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1724                 case CLOCK_DEFAULT:  flags = info->params.flags &
1725                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1726                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1727                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1728                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1729                 default: return -EINVAL;
1730                 }
1731
1732                 if (new_line.loopback != 0 && new_line.loopback != 1)
1733                         return -EINVAL;
1734
1735                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1736                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1737                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1738                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1739                 info->params.flags |= flags;
1740
1741                 info->params.loopback = new_line.loopback;
1742
1743                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1744                         info->params.clock_speed = new_line.clock_rate;
1745                 else
1746                         info->params.clock_speed = 0;
1747
1748                 /* if network interface up, reprogram hardware */
1749                 if (info->netcount)
1750                         program_hw(info);
1751                 return 0;
1752
1753         default:
1754                 return hdlc_ioctl(dev, ifr, cmd);
1755         }
1756 }
1757
1758 /**
1759  * called by network layer when transmit timeout is detected
1760  *
1761  * dev  pointer to network device structure
1762  */
1763 static void hdlcdev_tx_timeout(struct net_device *dev)
1764 {
1765         struct slgt_info *info = dev_to_port(dev);
1766         unsigned long flags;
1767
1768         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1769
1770         dev->stats.tx_errors++;
1771         dev->stats.tx_aborted_errors++;
1772
1773         spin_lock_irqsave(&info->lock,flags);
1774         tx_stop(info);
1775         spin_unlock_irqrestore(&info->lock,flags);
1776
1777         netif_wake_queue(dev);
1778 }
1779
1780 /**
1781  * called by device driver when transmit completes
1782  * reenable network layer transmit if stopped
1783  *
1784  * info  pointer to device instance information
1785  */
1786 static void hdlcdev_tx_done(struct slgt_info *info)
1787 {
1788         if (netif_queue_stopped(info->netdev))
1789                 netif_wake_queue(info->netdev);
1790 }
1791
1792 /**
1793  * called by device driver when frame received
1794  * pass frame to network layer
1795  *
1796  * info  pointer to device instance information
1797  * buf   pointer to buffer contianing frame data
1798  * size  count of data bytes in buf
1799  */
1800 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1801 {
1802         struct sk_buff *skb = dev_alloc_skb(size);
1803         struct net_device *dev = info->netdev;
1804
1805         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1806
1807         if (skb == NULL) {
1808                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1809                 dev->stats.rx_dropped++;
1810                 return;
1811         }
1812
1813         memcpy(skb_put(skb, size), buf, size);
1814
1815         skb->protocol = hdlc_type_trans(skb, dev);
1816
1817         dev->stats.rx_packets++;
1818         dev->stats.rx_bytes += size;
1819
1820         netif_rx(skb);
1821
1822         dev->last_rx = jiffies;
1823 }
1824
1825 /**
1826  * called by device driver when adding device instance
1827  * do generic HDLC initialization
1828  *
1829  * info  pointer to device instance information
1830  *
1831  * returns 0 if success, otherwise error code
1832  */
1833 static int hdlcdev_init(struct slgt_info *info)
1834 {
1835         int rc;
1836         struct net_device *dev;
1837         hdlc_device *hdlc;
1838
1839         /* allocate and initialize network and HDLC layer objects */
1840
1841         if (!(dev = alloc_hdlcdev(info))) {
1842                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1843                 return -ENOMEM;
1844         }
1845
1846         /* for network layer reporting purposes only */
1847         dev->mem_start = info->phys_reg_addr;
1848         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1849         dev->irq       = info->irq_level;
1850
1851         /* network layer callbacks and settings */
1852         dev->do_ioctl       = hdlcdev_ioctl;
1853         dev->open           = hdlcdev_open;
1854         dev->stop           = hdlcdev_close;
1855         dev->tx_timeout     = hdlcdev_tx_timeout;
1856         dev->watchdog_timeo = 10*HZ;
1857         dev->tx_queue_len   = 50;
1858
1859         /* generic HDLC layer callbacks and settings */
1860         hdlc         = dev_to_hdlc(dev);
1861         hdlc->attach = hdlcdev_attach;
1862         hdlc->xmit   = hdlcdev_xmit;
1863
1864         /* register objects with HDLC layer */
1865         if ((rc = register_hdlc_device(dev))) {
1866                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1867                 free_netdev(dev);
1868                 return rc;
1869         }
1870
1871         info->netdev = dev;
1872         return 0;
1873 }
1874
1875 /**
1876  * called by device driver when removing device instance
1877  * do generic HDLC cleanup
1878  *
1879  * info  pointer to device instance information
1880  */
1881 static void hdlcdev_exit(struct slgt_info *info)
1882 {
1883         unregister_hdlc_device(info->netdev);
1884         free_netdev(info->netdev);
1885         info->netdev = NULL;
1886 }
1887
1888 #endif /* ifdef CONFIG_HDLC */
1889
1890 /*
1891  * get async data from rx DMA buffers
1892  */
1893 static void rx_async(struct slgt_info *info)
1894 {
1895         struct tty_struct *tty = info->port.tty;
1896         struct mgsl_icount *icount = &info->icount;
1897         unsigned int start, end;
1898         unsigned char *p;
1899         unsigned char status;
1900         struct slgt_desc *bufs = info->rbufs;
1901         int i, count;
1902         int chars = 0;
1903         int stat;
1904         unsigned char ch;
1905
1906         start = end = info->rbuf_current;
1907
1908         while(desc_complete(bufs[end])) {
1909                 count = desc_count(bufs[end]) - info->rbuf_index;
1910                 p     = bufs[end].buf + info->rbuf_index;
1911
1912                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1913                 DBGDATA(info, p, count, "rx");
1914
1915                 for(i=0 ; i < count; i+=2, p+=2) {
1916                         ch = *p;
1917                         icount->rx++;
1918
1919                         stat = 0;
1920
1921                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1922                                 if (status & BIT1)
1923                                         icount->parity++;
1924                                 else if (status & BIT0)
1925                                         icount->frame++;
1926                                 /* discard char if tty control flags say so */
1927                                 if (status & info->ignore_status_mask)
1928                                         continue;
1929                                 if (status & BIT1)
1930                                         stat = TTY_PARITY;
1931                                 else if (status & BIT0)
1932                                         stat = TTY_FRAME;
1933                         }
1934                         if (tty) {
1935                                 tty_insert_flip_char(tty, ch, stat);
1936                                 chars++;
1937                         }
1938                 }
1939
1940                 if (i < count) {
1941                         /* receive buffer not completed */
1942                         info->rbuf_index += i;
1943                         mod_timer(&info->rx_timer, jiffies + 1);
1944                         break;
1945                 }
1946
1947                 info->rbuf_index = 0;
1948                 free_rbufs(info, end, end);
1949
1950                 if (++end == info->rbuf_count)
1951                         end = 0;
1952
1953                 /* if entire list searched then no frame available */
1954                 if (end == start)
1955                         break;
1956         }
1957
1958         if (tty && chars)
1959                 tty_flip_buffer_push(tty);
1960 }
1961
1962 /*
1963  * return next bottom half action to perform
1964  */
1965 static int bh_action(struct slgt_info *info)
1966 {
1967         unsigned long flags;
1968         int rc;
1969
1970         spin_lock_irqsave(&info->lock,flags);
1971
1972         if (info->pending_bh & BH_RECEIVE) {
1973                 info->pending_bh &= ~BH_RECEIVE;
1974                 rc = BH_RECEIVE;
1975         } else if (info->pending_bh & BH_TRANSMIT) {
1976                 info->pending_bh &= ~BH_TRANSMIT;
1977                 rc = BH_TRANSMIT;
1978         } else if (info->pending_bh & BH_STATUS) {
1979                 info->pending_bh &= ~BH_STATUS;
1980                 rc = BH_STATUS;
1981         } else {
1982                 /* Mark BH routine as complete */
1983                 info->bh_running = false;
1984                 info->bh_requested = false;
1985                 rc = 0;
1986         }
1987
1988         spin_unlock_irqrestore(&info->lock,flags);
1989
1990         return rc;
1991 }
1992
1993 /*
1994  * perform bottom half processing
1995  */
1996 static void bh_handler(struct work_struct *work)
1997 {
1998         struct slgt_info *info = container_of(work, struct slgt_info, task);
1999         int action;
2000
2001         if (!info)
2002                 return;
2003         info->bh_running = true;
2004
2005         while((action = bh_action(info))) {
2006                 switch (action) {
2007                 case BH_RECEIVE:
2008                         DBGBH(("%s bh receive\n", info->device_name));
2009                         switch(info->params.mode) {
2010                         case MGSL_MODE_ASYNC:
2011                                 rx_async(info);
2012                                 break;
2013                         case MGSL_MODE_HDLC:
2014                                 while(rx_get_frame(info));
2015                                 break;
2016                         case MGSL_MODE_RAW:
2017                         case MGSL_MODE_MONOSYNC:
2018                         case MGSL_MODE_BISYNC:
2019                                 while(rx_get_buf(info));
2020                                 break;
2021                         }
2022                         /* restart receiver if rx DMA buffers exhausted */
2023                         if (info->rx_restart)
2024                                 rx_start(info);
2025                         break;
2026                 case BH_TRANSMIT:
2027                         bh_transmit(info);
2028                         break;
2029                 case BH_STATUS:
2030                         DBGBH(("%s bh status\n", info->device_name));
2031                         info->ri_chkcount = 0;
2032                         info->dsr_chkcount = 0;
2033                         info->dcd_chkcount = 0;
2034                         info->cts_chkcount = 0;
2035                         break;
2036                 default:
2037                         DBGBH(("%s unknown action\n", info->device_name));
2038                         break;
2039                 }
2040         }
2041         DBGBH(("%s bh_handler exit\n", info->device_name));
2042 }
2043
2044 static void bh_transmit(struct slgt_info *info)
2045 {
2046         struct tty_struct *tty = info->port.tty;
2047
2048         DBGBH(("%s bh_transmit\n", info->device_name));
2049         if (tty)
2050                 tty_wakeup(tty);
2051 }
2052
2053 static void dsr_change(struct slgt_info *info, unsigned short status)
2054 {
2055         if (status & BIT3) {
2056                 info->signals |= SerialSignal_DSR;
2057                 info->input_signal_events.dsr_up++;
2058         } else {
2059                 info->signals &= ~SerialSignal_DSR;
2060                 info->input_signal_events.dsr_down++;
2061         }
2062         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2063         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2064                 slgt_irq_off(info, IRQ_DSR);
2065                 return;
2066         }
2067         info->icount.dsr++;
2068         wake_up_interruptible(&info->status_event_wait_q);
2069         wake_up_interruptible(&info->event_wait_q);
2070         info->pending_bh |= BH_STATUS;
2071 }
2072
2073 static void cts_change(struct slgt_info *info, unsigned short status)
2074 {
2075         if (status & BIT2) {
2076                 info->signals |= SerialSignal_CTS;
2077                 info->input_signal_events.cts_up++;
2078         } else {
2079                 info->signals &= ~SerialSignal_CTS;
2080                 info->input_signal_events.cts_down++;
2081         }
2082         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2083         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2084                 slgt_irq_off(info, IRQ_CTS);
2085                 return;
2086         }
2087         info->icount.cts++;
2088         wake_up_interruptible(&info->status_event_wait_q);
2089         wake_up_interruptible(&info->event_wait_q);
2090         info->pending_bh |= BH_STATUS;
2091
2092         if (info->port.flags & ASYNC_CTS_FLOW) {
2093                 if (info->port.tty) {
2094                         if (info->port.tty->hw_stopped) {
2095                                 if (info->signals & SerialSignal_CTS) {
2096                                         info->port.tty->hw_stopped = 0;
2097                                         info->pending_bh |= BH_TRANSMIT;
2098                                         return;
2099                                 }
2100                         } else {
2101                                 if (!(info->signals & SerialSignal_CTS))
2102                                         info->port.tty->hw_stopped = 1;
2103                         }
2104                 }
2105         }
2106 }
2107
2108 static void dcd_change(struct slgt_info *info, unsigned short status)
2109 {
2110         if (status & BIT1) {
2111                 info->signals |= SerialSignal_DCD;
2112                 info->input_signal_events.dcd_up++;
2113         } else {
2114                 info->signals &= ~SerialSignal_DCD;
2115                 info->input_signal_events.dcd_down++;
2116         }
2117         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2118         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2119                 slgt_irq_off(info, IRQ_DCD);
2120                 return;
2121         }
2122         info->icount.dcd++;
2123 #if SYNCLINK_GENERIC_HDLC
2124         if (info->netcount) {
2125                 if (info->signals & SerialSignal_DCD)
2126                         netif_carrier_on(info->netdev);
2127                 else
2128                         netif_carrier_off(info->netdev);
2129         }
2130 #endif
2131         wake_up_interruptible(&info->status_event_wait_q);
2132         wake_up_interruptible(&info->event_wait_q);
2133         info->pending_bh |= BH_STATUS;
2134
2135         if (info->port.flags & ASYNC_CHECK_CD) {
2136                 if (info->signals & SerialSignal_DCD)
2137                         wake_up_interruptible(&info->port.open_wait);
2138                 else {
2139                         if (info->port.tty)
2140                                 tty_hangup(info->port.tty);
2141                 }
2142         }
2143 }
2144
2145 static void ri_change(struct slgt_info *info, unsigned short status)
2146 {
2147         if (status & BIT0) {
2148                 info->signals |= SerialSignal_RI;
2149                 info->input_signal_events.ri_up++;
2150         } else {
2151                 info->signals &= ~SerialSignal_RI;
2152                 info->input_signal_events.ri_down++;
2153         }
2154         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2155         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2156                 slgt_irq_off(info, IRQ_RI);
2157                 return;
2158         }
2159         info->icount.rng++;
2160         wake_up_interruptible(&info->status_event_wait_q);
2161         wake_up_interruptible(&info->event_wait_q);
2162         info->pending_bh |= BH_STATUS;
2163 }
2164
2165 static void isr_serial(struct slgt_info *info)
2166 {
2167         unsigned short status = rd_reg16(info, SSR);
2168
2169         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2170
2171         wr_reg16(info, SSR, status); /* clear pending */
2172
2173         info->irq_occurred = true;
2174
2175         if (info->params.mode == MGSL_MODE_ASYNC) {
2176                 if (status & IRQ_TXIDLE) {
2177                         if (info->tx_count)
2178                                 isr_txeom(info, status);
2179                 }
2180                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2181                         info->icount.brk++;
2182                         /* process break detection if tty control allows */
2183                         if (info->port.tty) {
2184                                 if (!(status & info->ignore_status_mask)) {
2185                                         if (info->read_status_mask & MASK_BREAK) {
2186                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2187                                                 if (info->port.flags & ASYNC_SAK)
2188                                                         do_SAK(info->port.tty);
2189                                         }
2190                                 }
2191                         }
2192                 }
2193         } else {
2194                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2195                         isr_txeom(info, status);
2196
2197                 if (status & IRQ_RXIDLE) {
2198                         if (status & RXIDLE)
2199                                 info->icount.rxidle++;
2200                         else
2201                                 info->icount.exithunt++;
2202                         wake_up_interruptible(&info->event_wait_q);
2203                 }
2204
2205                 if (status & IRQ_RXOVER)
2206                         rx_start(info);
2207         }
2208
2209         if (status & IRQ_DSR)
2210                 dsr_change(info, status);
2211         if (status & IRQ_CTS)
2212                 cts_change(info, status);
2213         if (status & IRQ_DCD)
2214                 dcd_change(info, status);
2215         if (status & IRQ_RI)
2216                 ri_change(info, status);
2217 }
2218
2219 static void isr_rdma(struct slgt_info *info)
2220 {
2221         unsigned int status = rd_reg32(info, RDCSR);
2222
2223         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2224
2225         /* RDCSR (rx DMA control/status)
2226          *
2227          * 31..07  reserved
2228          * 06      save status byte to DMA buffer
2229          * 05      error
2230          * 04      eol (end of list)
2231          * 03      eob (end of buffer)
2232          * 02      IRQ enable
2233          * 01      reset
2234          * 00      enable
2235          */
2236         wr_reg32(info, RDCSR, status);  /* clear pending */
2237
2238         if (status & (BIT5 + BIT4)) {
2239                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2240                 info->rx_restart = true;
2241         }
2242         info->pending_bh |= BH_RECEIVE;
2243 }
2244
2245 static void isr_tdma(struct slgt_info *info)
2246 {
2247         unsigned int status = rd_reg32(info, TDCSR);
2248
2249         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2250
2251         /* TDCSR (tx DMA control/status)
2252          *
2253          * 31..06  reserved
2254          * 05      error
2255          * 04      eol (end of list)
2256          * 03      eob (end of buffer)
2257          * 02      IRQ enable
2258          * 01      reset
2259          * 00      enable
2260          */
2261         wr_reg32(info, TDCSR, status);  /* clear pending */
2262
2263         if (status & (BIT5 + BIT4 + BIT3)) {
2264                 // another transmit buffer has completed
2265                 // run bottom half to get more send data from user
2266                 info->pending_bh |= BH_TRANSMIT;
2267         }
2268 }
2269
2270 static void isr_txeom(struct slgt_info *info, unsigned short status)
2271 {
2272         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2273
2274         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2275         tdma_reset(info);
2276         reset_tbufs(info);
2277         if (status & IRQ_TXUNDER) {
2278                 unsigned short val = rd_reg16(info, TCR);
2279                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2280                 wr_reg16(info, TCR, val); /* clear reset bit */
2281         }
2282
2283         if (info->tx_active) {
2284                 if (info->params.mode != MGSL_MODE_ASYNC) {
2285                         if (status & IRQ_TXUNDER)
2286                                 info->icount.txunder++;
2287                         else if (status & IRQ_TXIDLE)
2288                                 info->icount.txok++;
2289                 }
2290
2291                 info->tx_active = false;
2292                 info->tx_count = 0;
2293
2294                 del_timer(&info->tx_timer);
2295
2296                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2297                         info->signals &= ~SerialSignal_RTS;
2298                         info->drop_rts_on_tx_done = false;
2299                         set_signals(info);
2300                 }
2301
2302 #if SYNCLINK_GENERIC_HDLC
2303                 if (info->netcount)
2304                         hdlcdev_tx_done(info);
2305                 else
2306 #endif
2307                 {
2308                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2309                                 tx_stop(info);
2310                                 return;
2311                         }
2312                         info->pending_bh |= BH_TRANSMIT;
2313                 }
2314         }
2315 }
2316
2317 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2318 {
2319         struct cond_wait *w, *prev;
2320
2321         /* wake processes waiting for specific transitions */
2322         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2323                 if (w->data & changed) {
2324                         w->data = state;
2325                         wake_up_interruptible(&w->q);
2326                         if (prev != NULL)
2327                                 prev->next = w->next;
2328                         else
2329                                 info->gpio_wait_q = w->next;
2330                 } else
2331                         prev = w;
2332         }
2333 }
2334
2335 /* interrupt service routine
2336  *
2337  *      irq     interrupt number
2338  *      dev_id  device ID supplied during interrupt registration
2339  */
2340 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2341 {
2342         struct slgt_info *info = dev_id;
2343         unsigned int gsr;
2344         unsigned int i;
2345
2346         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2347
2348         spin_lock(&info->lock);
2349
2350         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2351                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2352                 info->irq_occurred = true;
2353                 for(i=0; i < info->port_count ; i++) {
2354                         if (info->port_array[i] == NULL)
2355                                 continue;
2356                         if (gsr & (BIT8 << i))
2357                                 isr_serial(info->port_array[i]);
2358                         if (gsr & (BIT16 << (i*2)))
2359                                 isr_rdma(info->port_array[i]);
2360                         if (gsr & (BIT17 << (i*2)))
2361                                 isr_tdma(info->port_array[i]);
2362                 }
2363         }
2364
2365         if (info->gpio_present) {
2366                 unsigned int state;
2367                 unsigned int changed;
2368                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2369                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2370                         /* read latched state of GPIO signals */
2371                         state = rd_reg32(info, IOVR);
2372                         /* clear pending GPIO interrupt bits */
2373                         wr_reg32(info, IOSR, changed);
2374                         for (i=0 ; i < info->port_count ; i++) {
2375                                 if (info->port_array[i] != NULL)
2376                                         isr_gpio(info->port_array[i], changed, state);
2377                         }
2378                 }
2379         }
2380
2381         for(i=0; i < info->port_count ; i++) {
2382                 struct slgt_info *port = info->port_array[i];
2383
2384                 if (port && (port->port.count || port->netcount) &&
2385                     port->pending_bh && !port->bh_running &&
2386                     !port->bh_requested) {
2387                         DBGISR(("%s bh queued\n", port->device_name));
2388                         schedule_work(&port->task);
2389                         port->bh_requested = true;
2390                 }
2391         }
2392
2393         spin_unlock(&info->lock);
2394
2395         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2396         return IRQ_HANDLED;
2397 }
2398
2399 static int startup(struct slgt_info *info)
2400 {
2401         DBGINFO(("%s startup\n", info->device_name));
2402
2403         if (info->port.flags & ASYNC_INITIALIZED)
2404                 return 0;
2405
2406         if (!info->tx_buf) {
2407                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2408                 if (!info->tx_buf) {
2409                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2410                         return -ENOMEM;
2411                 }
2412         }
2413
2414         info->pending_bh = 0;
2415
2416         memset(&info->icount, 0, sizeof(info->icount));
2417
2418         /* program hardware for current parameters */
2419         change_params(info);
2420
2421         if (info->port.tty)
2422                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2423
2424         info->port.flags |= ASYNC_INITIALIZED;
2425
2426         return 0;
2427 }
2428
2429 /*
2430  *  called by close() and hangup() to shutdown hardware
2431  */
2432 static void shutdown(struct slgt_info *info)
2433 {
2434         unsigned long flags;
2435
2436         if (!(info->port.flags & ASYNC_INITIALIZED))
2437                 return;
2438
2439         DBGINFO(("%s shutdown\n", info->device_name));
2440
2441         /* clear status wait queue because status changes */
2442         /* can't happen after shutting down the hardware */
2443         wake_up_interruptible(&info->status_event_wait_q);
2444         wake_up_interruptible(&info->event_wait_q);
2445
2446         del_timer_sync(&info->tx_timer);
2447         del_timer_sync(&info->rx_timer);
2448
2449         kfree(info->tx_buf);
2450         info->tx_buf = NULL;
2451
2452         spin_lock_irqsave(&info->lock,flags);
2453
2454         tx_stop(info);
2455         rx_stop(info);
2456
2457         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2458
2459         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2460                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2461                 set_signals(info);
2462         }
2463
2464         flush_cond_wait(&info->gpio_wait_q);
2465
2466         spin_unlock_irqrestore(&info->lock,flags);
2467
2468         if (info->port.tty)
2469                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2470
2471         info->port.flags &= ~ASYNC_INITIALIZED;
2472 }
2473
2474 static void program_hw(struct slgt_info *info)
2475 {
2476         unsigned long flags;
2477
2478         spin_lock_irqsave(&info->lock,flags);
2479
2480         rx_stop(info);
2481         tx_stop(info);
2482
2483         if (info->params.mode != MGSL_MODE_ASYNC ||
2484             info->netcount)
2485                 sync_mode(info);
2486         else
2487                 async_mode(info);
2488
2489         set_signals(info);
2490
2491         info->dcd_chkcount = 0;
2492         info->cts_chkcount = 0;
2493         info->ri_chkcount = 0;
2494         info->dsr_chkcount = 0;
2495
2496         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2497         get_signals(info);
2498
2499         if (info->netcount ||
2500             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2501                 rx_start(info);
2502
2503         spin_unlock_irqrestore(&info->lock,flags);
2504 }
2505
2506 /*
2507  * reconfigure adapter based on new parameters
2508  */
2509 static void change_params(struct slgt_info *info)
2510 {
2511         unsigned cflag;
2512         int bits_per_char;
2513
2514         if (!info->port.tty || !info->port.tty->termios)
2515                 return;
2516         DBGINFO(("%s change_params\n", info->device_name));
2517
2518         cflag = info->port.tty->termios->c_cflag;
2519
2520         /* if B0 rate (hangup) specified then negate DTR and RTS */
2521         /* otherwise assert DTR and RTS */
2522         if (cflag & CBAUD)
2523                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2524         else
2525                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2526
2527         /* byte size and parity */
2528
2529         switch (cflag & CSIZE) {
2530         case CS5: info->params.data_bits = 5; break;
2531         case CS6: info->params.data_bits = 6; break;
2532         case CS7: info->params.data_bits = 7; break;
2533         case CS8: info->params.data_bits = 8; break;
2534         default:  info->params.data_bits = 7; break;
2535         }
2536
2537         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2538
2539         if (cflag & PARENB)
2540                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2541         else
2542                 info->params.parity = ASYNC_PARITY_NONE;
2543
2544         /* calculate number of jiffies to transmit a full
2545          * FIFO (32 bytes) at specified data rate
2546          */
2547         bits_per_char = info->params.data_bits +
2548                         info->params.stop_bits + 1;
2549
2550         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2551
2552         if (info->params.data_rate) {
2553                 info->timeout = (32*HZ*bits_per_char) /
2554                                 info->params.data_rate;
2555         }
2556         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2557
2558         if (cflag & CRTSCTS)
2559                 info->port.flags |= ASYNC_CTS_FLOW;
2560         else
2561                 info->port.flags &= ~ASYNC_CTS_FLOW;
2562
2563         if (cflag & CLOCAL)
2564                 info->port.flags &= ~ASYNC_CHECK_CD;
2565         else
2566                 info->port.flags |= ASYNC_CHECK_CD;
2567
2568         /* process tty input control flags */
2569
2570         info->read_status_mask = IRQ_RXOVER;
2571         if (I_INPCK(info->port.tty))
2572                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2573         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2574                 info->read_status_mask |= MASK_BREAK;
2575         if (I_IGNPAR(info->port.tty))
2576                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2577         if (I_IGNBRK(info->port.tty)) {
2578                 info->ignore_status_mask |= MASK_BREAK;
2579                 /* If ignoring parity and break indicators, ignore
2580                  * overruns too.  (For real raw support).
2581                  */
2582                 if (I_IGNPAR(info->port.tty))
2583                         info->ignore_status_mask |= MASK_OVERRUN;
2584         }
2585
2586         program_hw(info);
2587 }
2588
2589 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2590 {
2591         DBGINFO(("%s get_stats\n",  info->device_name));
2592         if (!user_icount) {
2593                 memset(&info->icount, 0, sizeof(info->icount));
2594         } else {
2595                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2596                         return -EFAULT;
2597         }
2598         return 0;
2599 }
2600
2601 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2602 {
2603         DBGINFO(("%s get_params\n", info->device_name));
2604         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2605                 return -EFAULT;
2606         return 0;
2607 }
2608
2609 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2610 {
2611         unsigned long flags;
2612         MGSL_PARAMS tmp_params;
2613
2614         DBGINFO(("%s set_params\n", info->device_name));
2615         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2616                 return -EFAULT;
2617
2618         spin_lock_irqsave(&info->lock, flags);
2619         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2620         spin_unlock_irqrestore(&info->lock, flags);
2621
2622         change_params(info);
2623
2624         return 0;
2625 }
2626
2627 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2628 {
2629         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2630         if (put_user(info->idle_mode, idle_mode))
2631                 return -EFAULT;
2632         return 0;
2633 }
2634
2635 static int set_txidle(struct slgt_info *info, int idle_mode)
2636 {
2637         unsigned long flags;
2638         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2639         spin_lock_irqsave(&info->lock,flags);
2640         info->idle_mode = idle_mode;
2641         if (info->params.mode != MGSL_MODE_ASYNC)
2642                 tx_set_idle(info);
2643         spin_unlock_irqrestore(&info->lock,flags);
2644         return 0;
2645 }
2646
2647 static int tx_enable(struct slgt_info *info, int enable)
2648 {
2649         unsigned long flags;
2650         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2651         spin_lock_irqsave(&info->lock,flags);
2652         if (enable) {
2653                 if (!info->tx_enabled)
2654                         tx_start(info);
2655         } else {
2656                 if (info->tx_enabled)
2657                         tx_stop(info);
2658         }
2659         spin_unlock_irqrestore(&info->lock,flags);
2660         return 0;
2661 }
2662
2663 /*
2664  * abort transmit HDLC frame
2665  */
2666 static int tx_abort(struct slgt_info *info)
2667 {
2668         unsigned long flags;
2669         DBGINFO(("%s tx_abort\n", info->device_name));
2670         spin_lock_irqsave(&info->lock,flags);
2671         tdma_reset(info);
2672         spin_unlock_irqrestore(&info->lock,flags);
2673         return 0;
2674 }
2675
2676 static int rx_enable(struct slgt_info *info, int enable)
2677 {
2678         unsigned long flags;
2679         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2680         spin_lock_irqsave(&info->lock,flags);
2681         if (enable) {
2682                 if (!info->rx_enabled)
2683                         rx_start(info);
2684                 else if (enable == 2) {
2685                         /* force hunt mode (write 1 to RCR[3]) */
2686                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2687                 }
2688         } else {
2689                 if (info->rx_enabled)
2690                         rx_stop(info);
2691         }
2692         spin_unlock_irqrestore(&info->lock,flags);
2693         return 0;
2694 }
2695
2696 /*
2697  *  wait for specified event to occur
2698  */
2699 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2700 {
2701         unsigned long flags;
2702         int s;
2703         int rc=0;
2704         struct mgsl_icount cprev, cnow;
2705         int events;
2706         int mask;
2707         struct  _input_signal_events oldsigs, newsigs;
2708         DECLARE_WAITQUEUE(wait, current);
2709
2710         if (get_user(mask, mask_ptr))
2711                 return -EFAULT;
2712
2713         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2714
2715         spin_lock_irqsave(&info->lock,flags);
2716
2717         /* return immediately if state matches requested events */
2718         get_signals(info);
2719         s = info->signals;
2720
2721         events = mask &
2722                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2723                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2724                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2725                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2726         if (events) {
2727                 spin_unlock_irqrestore(&info->lock,flags);
2728                 goto exit;
2729         }
2730
2731         /* save current irq counts */
2732         cprev = info->icount;
2733         oldsigs = info->input_signal_events;
2734
2735         /* enable hunt and idle irqs if needed */
2736         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2737                 unsigned short val = rd_reg16(info, SCR);
2738                 if (!(val & IRQ_RXIDLE))
2739                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2740         }
2741
2742         set_current_state(TASK_INTERRUPTIBLE);
2743         add_wait_queue(&info->event_wait_q, &wait);
2744
2745         spin_unlock_irqrestore(&info->lock,flags);
2746
2747         for(;;) {
2748                 schedule();
2749                 if (signal_pending(current)) {
2750                         rc = -ERESTARTSYS;
2751                         break;
2752                 }
2753
2754                 /* get current irq counts */
2755                 spin_lock_irqsave(&info->lock,flags);
2756                 cnow = info->icount;
2757                 newsigs = info->input_signal_events;
2758                 set_current_state(TASK_INTERRUPTIBLE);
2759                 spin_unlock_irqrestore(&info->lock,flags);
2760
2761                 /* if no change, wait aborted for some reason */
2762                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2763                     newsigs.dsr_down == oldsigs.dsr_down &&
2764                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2765                     newsigs.dcd_down == oldsigs.dcd_down &&
2766                     newsigs.cts_up   == oldsigs.cts_up   &&
2767                     newsigs.cts_down == oldsigs.cts_down &&
2768                     newsigs.ri_up    == oldsigs.ri_up    &&
2769                     newsigs.ri_down  == oldsigs.ri_down  &&
2770                     cnow.exithunt    == cprev.exithunt   &&
2771                     cnow.rxidle      == cprev.rxidle) {
2772                         rc = -EIO;
2773                         break;
2774                 }
2775
2776                 events = mask &
2777                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2778                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2779                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2780                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2781                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2782                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2783                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2784                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2785                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2786                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2787                 if (events)
2788                         break;
2789
2790                 cprev = cnow;
2791                 oldsigs = newsigs;
2792         }
2793
2794         remove_wait_queue(&info->event_wait_q, &wait);
2795         set_current_state(TASK_RUNNING);
2796
2797
2798         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2799                 spin_lock_irqsave(&info->lock,flags);
2800                 if (!waitqueue_active(&info->event_wait_q)) {
2801                         /* disable enable exit hunt mode/idle rcvd IRQs */
2802                         wr_reg16(info, SCR,
2803                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2804                 }
2805                 spin_unlock_irqrestore(&info->lock,flags);
2806         }
2807 exit:
2808         if (rc == 0)
2809                 rc = put_user(events, mask_ptr);
2810         return rc;
2811 }
2812
2813 static int get_interface(struct slgt_info *info, int __user *if_mode)
2814 {
2815         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2816         if (put_user(info->if_mode, if_mode))
2817                 return -EFAULT;
2818         return 0;
2819 }
2820
2821 static int set_interface(struct slgt_info *info, int if_mode)
2822 {
2823         unsigned long flags;
2824         unsigned short val;
2825
2826         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2827         spin_lock_irqsave(&info->lock,flags);
2828         info->if_mode = if_mode;
2829
2830         msc_set_vcr(info);
2831
2832         /* TCR (tx control) 07  1=RTS driver control */
2833         val = rd_reg16(info, TCR);
2834         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2835                 val |= BIT7;
2836         else
2837                 val &= ~BIT7;
2838         wr_reg16(info, TCR, val);
2839
2840         spin_unlock_irqrestore(&info->lock,flags);
2841         return 0;
2842 }
2843
2844 /*
2845  * set general purpose IO pin state and direction
2846  *
2847  * user_gpio fields:
2848  * state   each bit indicates a pin state
2849  * smask   set bit indicates pin state to set
2850  * dir     each bit indicates a pin direction (0=input, 1=output)
2851  * dmask   set bit indicates pin direction to set
2852  */
2853 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2854 {
2855         unsigned long flags;
2856         struct gpio_desc gpio;
2857         __u32 data;
2858
2859         if (!info->gpio_present)
2860                 return -EINVAL;
2861         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2862                 return -EFAULT;
2863         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2864                  info->device_name, gpio.state, gpio.smask,
2865                  gpio.dir, gpio.dmask));
2866
2867         spin_lock_irqsave(&info->lock,flags);
2868         if (gpio.dmask) {
2869                 data = rd_reg32(info, IODR);
2870                 data |= gpio.dmask & gpio.dir;
2871                 data &= ~(gpio.dmask & ~gpio.dir);
2872                 wr_reg32(info, IODR, data);
2873         }
2874         if (gpio.smask) {
2875                 data = rd_reg32(info, IOVR);
2876                 data |= gpio.smask & gpio.state;
2877                 data &= ~(gpio.smask & ~gpio.state);
2878                 wr_reg32(info, IOVR, data);
2879         }
2880         spin_unlock_irqrestore(&info->lock,flags);
2881
2882         return 0;
2883 }
2884
2885 /*
2886  * get general purpose IO pin state and direction
2887  */
2888 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2889 {
2890         struct gpio_desc gpio;
2891         if (!info->gpio_present)
2892                 return -EINVAL;
2893         gpio.state = rd_reg32(info, IOVR);
2894         gpio.smask = 0xffffffff;
2895         gpio.dir   = rd_reg32(info, IODR);
2896         gpio.dmask = 0xffffffff;
2897         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2898                 return -EFAULT;
2899         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2900                  info->device_name, gpio.state, gpio.dir));
2901         return 0;
2902 }
2903
2904 /*
2905  * conditional wait facility
2906  */
2907 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2908 {
2909         init_waitqueue_head(&w->q);
2910         init_waitqueue_entry(&w->wait, current);
2911         w->data = data;
2912 }
2913
2914 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2915 {
2916         set_current_state(TASK_INTERRUPTIBLE);
2917         add_wait_queue(&w->q, &w->wait);
2918         w->next = *head;
2919         *head = w;
2920 }
2921
2922 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2923 {
2924         struct cond_wait *w, *prev;
2925         remove_wait_queue(&cw->q, &cw->wait);
2926         set_current_state(TASK_RUNNING);
2927         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2928                 if (w == cw) {
2929                         if (prev != NULL)
2930                                 prev->next = w->next;
2931                         else
2932                                 *head = w->next;
2933                         break;
2934                 }
2935         }
2936 }
2937
2938 static void flush_cond_wait(struct cond_wait **head)
2939 {
2940         while (*head != NULL) {
2941                 wake_up_interruptible(&(*head)->q);
2942                 *head = (*head)->next;
2943         }
2944 }
2945
2946 /*
2947  * wait for general purpose I/O pin(s) to enter specified state
2948  *
2949  * user_gpio fields:
2950  * state - bit indicates target pin state
2951  * smask - set bit indicates watched pin
2952  *
2953  * The wait ends when at least one watched pin enters the specified
2954  * state. When 0 (no error) is returned, user_gpio->state is set to the
2955  * state of all GPIO pins when the wait ends.
2956  *
2957  * Note: Each pin may be a dedicated input, dedicated output, or
2958  * configurable input/output. The number and configuration of pins
2959  * varies with the specific adapter model. Only input pins (dedicated
2960  * or configured) can be monitored with this function.
2961  */
2962 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2963 {
2964         unsigned long flags;
2965         int rc = 0;
2966         struct gpio_desc gpio;
2967         struct cond_wait wait;
2968         u32 state;
2969
2970         if (!info->gpio_present)
2971                 return -EINVAL;
2972         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2973                 return -EFAULT;
2974         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2975                  info->device_name, gpio.state, gpio.smask));
2976         /* ignore output pins identified by set IODR bit */
2977         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2978                 return -EINVAL;
2979         init_cond_wait(&wait, gpio.smask);
2980
2981         spin_lock_irqsave(&info->lock, flags);
2982         /* enable interrupts for watched pins */
2983         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2984         /* get current pin states */
2985         state = rd_reg32(info, IOVR);
2986
2987         if (gpio.smask & ~(state ^ gpio.state)) {
2988                 /* already in target state */
2989                 gpio.state = state;
2990         } else {
2991                 /* wait for target state */
2992                 add_cond_wait(&info->gpio_wait_q, &wait);
2993                 spin_unlock_irqrestore(&info->lock, flags);
2994                 schedule();
2995                 if (signal_pending(current))
2996                         rc = -ERESTARTSYS;
2997                 else
2998                         gpio.state = wait.data;
2999                 spin_lock_irqsave(&info->lock, flags);
3000                 remove_cond_wait(&info->gpio_wait_q, &wait);
3001         }
3002
3003         /* disable all GPIO interrupts if no waiting processes */
3004         if (info->gpio_wait_q == NULL)
3005                 wr_reg32(info, IOER, 0);
3006         spin_unlock_irqrestore(&info->lock,flags);
3007
3008         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3009                 rc = -EFAULT;
3010         return rc;
3011 }
3012
3013 static int modem_input_wait(struct slgt_info *info,int arg)
3014 {
3015         unsigned long flags;
3016         int rc;
3017         struct mgsl_icount cprev, cnow;
3018         DECLARE_WAITQUEUE(wait, current);
3019
3020         /* save current irq counts */
3021         spin_lock_irqsave(&info->lock,flags);
3022         cprev = info->icount;
3023         add_wait_queue(&info->status_event_wait_q, &wait);
3024         set_current_state(TASK_INTERRUPTIBLE);
3025         spin_unlock_irqrestore(&info->lock,flags);
3026
3027         for(;;) {
3028                 schedule();
3029                 if (signal_pending(current)) {
3030                         rc = -ERESTARTSYS;
3031                         break;
3032                 }
3033
3034                 /* get new irq counts */
3035                 spin_lock_irqsave(&info->lock,flags);
3036                 cnow = info->icount;
3037                 set_current_state(TASK_INTERRUPTIBLE);
3038                 spin_unlock_irqrestore(&info->lock,flags);
3039
3040                 /* if no change, wait aborted for some reason */
3041                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3042                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3043                         rc = -EIO;
3044                         break;
3045                 }
3046
3047                 /* check for change in caller specified modem input */
3048                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3049                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3050                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3051                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3052                         rc = 0;
3053                         break;
3054                 }
3055
3056                 cprev = cnow;
3057         }
3058         remove_wait_queue(&info->status_event_wait_q, &wait);
3059         set_current_state(TASK_RUNNING);
3060         return rc;
3061 }
3062
3063 /*
3064  *  return state of serial control and status signals
3065  */
3066 static int tiocmget(struct tty_struct *tty, struct file *file)
3067 {
3068         struct slgt_info *info = tty->driver_data;
3069         unsigned int result;
3070         unsigned long flags;
3071
3072         spin_lock_irqsave(&info->lock,flags);
3073         get_signals(info);
3074         spin_unlock_irqrestore(&info->lock,flags);
3075
3076         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3077                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3078                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3079                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3080                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3081                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3082
3083         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3084         return result;
3085 }
3086
3087 /*
3088  * set modem control signals (DTR/RTS)
3089  *
3090  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3091  *              TIOCMSET = set/clear signal values
3092  *      value   bit mask for command
3093  */
3094 static int tiocmset(struct tty_struct *tty, struct file *file,
3095                     unsigned int set, unsigned int clear)
3096 {
3097         struct slgt_info *info = tty->driver_data;
3098         unsigned long flags;
3099
3100         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3101
3102         if (set & TIOCM_RTS)
3103                 info->signals |= SerialSignal_RTS;
3104         if (set & TIOCM_DTR)
3105                 info->signals |= SerialSignal_DTR;
3106         if (clear & TIOCM_RTS)
3107                 info->signals &= ~SerialSignal_RTS;
3108         if (clear & TIOCM_DTR)
3109                 info->signals &= ~SerialSignal_DTR;
3110
3111         spin_lock_irqsave(&info->lock,flags);
3112         set_signals(info);
3113         spin_unlock_irqrestore(&info->lock,flags);
3114         return 0;
3115 }
3116
3117 /*
3118  *  block current process until the device is ready to open
3119  */
3120 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3121                            struct slgt_info *info)
3122 {
3123         DECLARE_WAITQUEUE(wait, current);
3124         int             retval;
3125         bool            do_clocal = false;
3126         bool            extra_count = false;
3127         unsigned long   flags;
3128
3129         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3130
3131         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3132                 /* nonblock mode is set or port is not enabled */
3133                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3134                 return 0;
3135         }
3136
3137         if (tty->termios->c_cflag & CLOCAL)
3138                 do_clocal = true;
3139
3140         /* Wait for carrier detect and the line to become
3141          * free (i.e., not in use by the callout).  While we are in
3142          * this loop, info->port.count is dropped by one, so that
3143          * close() knows when to free things.  We restore it upon
3144          * exit, either normal or abnormal.
3145          */
3146
3147         retval = 0;
3148         add_wait_queue(&info->port.open_wait, &wait);
3149
3150         spin_lock_irqsave(&info->lock, flags);
3151         if (!tty_hung_up_p(filp)) {
3152                 extra_count = true;
3153                 info->port.count--;
3154         }
3155         spin_unlock_irqrestore(&info->lock, flags);
3156         info->port.blocked_open++;
3157
3158         while (1) {
3159                 if ((tty->termios->c_cflag & CBAUD)) {
3160                         spin_lock_irqsave(&info->lock,flags);
3161                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3162                         set_signals(info);
3163                         spin_unlock_irqrestore(&info->lock,flags);
3164                 }
3165
3166                 set_current_state(TASK_INTERRUPTIBLE);
3167
3168                 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3169                         retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3170                                         -EAGAIN : -ERESTARTSYS;
3171                         break;
3172                 }
3173
3174                 spin_lock_irqsave(&info->lock,flags);
3175                 get_signals(info);
3176                 spin_unlock_irqrestore(&info->lock,flags);
3177
3178                 if (!(info->port.flags & ASYNC_CLOSING) &&
3179                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3180                         break;
3181                 }
3182
3183                 if (signal_pending(current)) {
3184                         retval = -ERESTARTSYS;
3185                         break;
3186                 }
3187
3188                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3189                 schedule();
3190         }
3191
3192         set_current_state(TASK_RUNNING);
3193         remove_wait_queue(&info->port.open_wait, &wait);
3194
3195         if (extra_count)
3196                 info->port.count++;
3197         info->port.blocked_open--;
3198
3199         if (!retval)
3200                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3201
3202         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3203         return retval;
3204 }
3205
3206 static int alloc_tmp_rbuf(struct slgt_info *info)
3207 {
3208         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3209         if (info->tmp_rbuf == NULL)
3210                 return -ENOMEM;
3211         return 0;
3212 }
3213
3214 static void free_tmp_rbuf(struct slgt_info *info)
3215 {
3216         kfree(info->tmp_rbuf);
3217         info->tmp_rbuf = NULL;
3218 }
3219
3220 /*
3221  * allocate DMA descriptor lists.
3222  */
3223 static int alloc_desc(struct slgt_info *info)
3224 {
3225         unsigned int i;
3226         unsigned int pbufs;
3227
3228         /* allocate memory to hold descriptor lists */
3229         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3230         if (info->bufs == NULL)
3231                 return -ENOMEM;
3232
3233         memset(info->bufs, 0, DESC_LIST_SIZE);
3234
3235         info->rbufs = (struct slgt_desc*)info->bufs;
3236         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3237
3238         pbufs = (unsigned int)info->bufs_dma_addr;
3239
3240         /*
3241          * Build circular lists of descriptors
3242          */
3243
3244         for (i=0; i < info->rbuf_count; i++) {
3245                 /* physical address of this descriptor */
3246                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3247
3248                 /* physical address of next descriptor */
3249                 if (i == info->rbuf_count - 1)
3250                         info->rbufs[i].next = cpu_to_le32(pbufs);
3251                 else
3252                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3253                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3254         }
3255
3256         for (i=0; i < info->tbuf_count; i++) {
3257                 /* physical address of this descriptor */
3258                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3259
3260                 /* physical address of next descriptor */
3261                 if (i == info->tbuf_count - 1)
3262                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3263                 else
3264                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3265         }
3266
3267         return 0;
3268 }
3269
3270 static void free_desc(struct slgt_info *info)
3271 {
3272         if (info->bufs != NULL) {
3273                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3274                 info->bufs  = NULL;
3275                 info->rbufs = NULL;
3276                 info->tbufs = NULL;
3277         }
3278 }
3279
3280 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3281 {
3282         int i;
3283         for (i=0; i < count; i++) {
3284                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3285                         return -ENOMEM;
3286                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3287         }
3288         return 0;
3289 }
3290
3291 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3292 {
3293         int i;
3294         for (i=0; i < count; i++) {
3295                 if (bufs[i].buf == NULL)
3296                         continue;
3297                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3298                 bufs[i].buf = NULL;
3299         }
3300 }
3301
3302 static int alloc_dma_bufs(struct slgt_info *info)
3303 {
3304         info->rbuf_count = 32;
3305         info->tbuf_count = 32;
3306
3307         if (alloc_desc(info) < 0 ||
3308             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3309             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3310             alloc_tmp_rbuf(info) < 0) {
3311                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3312                 return -ENOMEM;
3313         }
3314         reset_rbufs(info);
3315         return 0;
3316 }
3317
3318 static void free_dma_bufs(struct slgt_info *info)
3319 {
3320         if (info->bufs) {
3321                 free_bufs(info, info->rbufs, info->rbuf_count);
3322                 free_bufs(info, info->tbufs, info->tbuf_count);
3323                 free_desc(info);
3324         }
3325         free_tmp_rbuf(info);
3326 }
3327
3328 static int claim_resources(struct slgt_info *info)
3329 {
3330         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3331                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3332                         info->device_name, info->phys_reg_addr));
3333                 info->init_error = DiagStatus_AddressConflict;
3334                 goto errout;
3335         }
3336         else
3337                 info->reg_addr_requested = true;
3338
3339         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3340         if (!info->reg_addr) {
3341                 DBGERR(("%s cant map device registers, addr=%08X\n",
3342                         info->device_name, info->phys_reg_addr));
3343                 info->init_error = DiagStatus_CantAssignPciResources;
3344                 goto errout;
3345         }
3346         return 0;
3347
3348 errout:
3349         release_resources(info);
3350         return -ENODEV;
3351 }
3352
3353 static void release_resources(struct slgt_info *info)
3354 {
3355         if (info->irq_requested) {
3356                 free_irq(info->irq_level, info);
3357                 info->irq_requested = false;
3358         }
3359
3360         if (info->reg_addr_requested) {
3361                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3362                 info->reg_addr_requested = false;
3363         }
3364
3365         if (info->reg_addr) {
3366                 iounmap(info->reg_addr);
3367                 info->reg_addr = NULL;
3368         }
3369 }
3370
3371 /* Add the specified device instance data structure to the
3372  * global linked list of devices and increment the device count.
3373  */
3374 static void add_device(struct slgt_info *info)
3375 {
3376         char *devstr;
3377
3378         info->next_device = NULL;
3379         info->line = slgt_device_count;
3380         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3381
3382         if (info->line < MAX_DEVICES) {
3383                 if (maxframe[info->line])
3384                         info->max_frame_size = maxframe[info->line];
3385                 info->dosyncppp = dosyncppp[info->line];
3386         }
3387
3388         slgt_device_count++;
3389
3390         if (!slgt_device_list)
3391                 slgt_device_list = info;
3392         else {
3393                 struct slgt_info *current_dev = slgt_device_list;
3394                 while(current_dev->next_device)
3395                         current_dev = current_dev->next_device;
3396                 current_dev->next_device = info;
3397         }
3398
3399         if (info->max_frame_size < 4096)
3400                 info->max_frame_size = 4096;
3401         else if (info->max_frame_size > 65535)
3402                 info->max_frame_size = 65535;
3403
3404         switch(info->pdev->device) {
3405         case SYNCLINK_GT_DEVICE_ID:
3406                 devstr = "GT";
3407                 break;
3408         case SYNCLINK_GT2_DEVICE_ID:
3409                 devstr = "GT2";
3410                 break;
3411         case SYNCLINK_GT4_DEVICE_ID:
3412                 devstr = "GT4";
3413                 break;
3414         case SYNCLINK_AC_DEVICE_ID:
3415                 devstr = "AC";
3416                 info->params.mode = MGSL_MODE_ASYNC;
3417                 break;
3418         default:
3419                 devstr = "(unknown model)";
3420         }
3421         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3422                 devstr, info->device_name, info->phys_reg_addr,
3423                 info->irq_level, info->max_frame_size);
3424
3425 #if SYNCLINK_GENERIC_HDLC
3426         hdlcdev_init(info);
3427 #endif
3428 }
3429
3430 /*
3431  *  allocate device instance structure, return NULL on failure
3432  */
3433 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3434 {
3435         struct slgt_info *info;
3436
3437         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3438
3439         if (!info) {
3440                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3441                         driver_name, adapter_num, port_num));
3442         } else {
3443                 tty_port_init(&info->port);
3444                 info->magic = MGSL_MAGIC;
3445                 INIT_WORK(&info->task, bh_handler);
3446                 info->max_frame_size = 4096;
3447                 info->raw_rx_size = DMABUFSIZE;
3448                 info->port.close_delay = 5*HZ/10;
3449                 info->port.closing_wait = 30*HZ;
3450                 init_waitqueue_head(&info->status_event_wait_q);
3451                 init_waitqueue_head(&info->event_wait_q);
3452                 spin_lock_init(&info->netlock);
3453                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3454                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3455                 info->adapter_num = adapter_num;
3456                 info->port_num = port_num;
3457
3458                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3459                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3460
3461                 /* Copy configuration info to device instance data */
3462                 info->pdev = pdev;
3463                 info->irq_level = pdev->irq;
3464                 info->phys_reg_addr = pci_resource_start(pdev,0);
3465
3466                 info->bus_type = MGSL_BUS_TYPE_PCI;
3467                 info->irq_flags = IRQF_SHARED;
3468
3469                 info->init_error = -1; /* assume error, set to 0 on successful init */
3470         }
3471
3472         return info;
3473 }
3474
3475 static void device_init(int adapter_num, struct pci_dev *pdev)
3476 {
3477         struct slgt_info *port_array[SLGT_MAX_PORTS];
3478         int i;
3479         int port_count = 1;
3480
3481         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3482                 port_count = 2;
3483         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3484                 port_count = 4;
3485
3486         /* allocate device instances for all ports */
3487         for (i=0; i < port_count; ++i) {
3488                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3489                 if (port_array[i] == NULL) {
3490                         for (--i; i >= 0; --i)
3491                                 kfree(port_array[i]);
3492                         return;
3493                 }
3494         }
3495
3496         /* give copy of port_array to all ports and add to device list  */
3497         for (i=0; i < port_count; ++i) {
3498                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3499                 add_device(port_array[i]);
3500                 port_array[i]->port_count = port_count;
3501                 spin_lock_init(&port_array[i]->lock);
3502         }
3503
3504         /* Allocate and claim adapter resources */
3505         if (!claim_resources(port_array[0])) {
3506
3507                 alloc_dma_bufs(port_array[0]);
3508
3509                 /* copy resource information from first port to others */
3510                 for (i = 1; i < port_count; ++i) {
3511                         port_array[i]->lock      = port_array[0]->lock;
3512                         port_array[i]->irq_level = port_array[0]->irq_level;
3513                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3514                         alloc_dma_bufs(port_array[i]);
3515                 }
3516
3517                 if (request_irq(port_array[0]->irq_level,
3518                                         slgt_interrupt,
3519                                         port_array[0]->irq_flags,
3520                                         port_array[0]->device_name,
3521                                         port_array[0]) < 0) {
3522                         DBGERR(("%s request_irq failed IRQ=%d\n",
3523                                 port_array[0]->device_name,
3524                                 port_array[0]->irq_level));
3525                 } else {
3526                         port_array[0]->irq_requested = true;
3527                         adapter_test(port_array[0]);
3528                         for (i=1 ; i < port_count ; i++) {
3529                                 port_array[i]->init_error = port_array[0]->init_error;
3530                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3531                         }
3532                 }
3533         }
3534
3535         for (i=0; i < port_count; ++i)
3536                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3537 }
3538
3539 static int __devinit init_one(struct pci_dev *dev,
3540                               const struct pci_device_id *ent)
3541 {
3542         if (pci_enable_device(dev)) {
3543                 printk("error enabling pci device %p\n", dev);
3544                 return -EIO;
3545         }
3546         pci_set_master(dev);
3547         device_init(slgt_device_count, dev);
3548         return 0;
3549 }
3550
3551 static void __devexit remove_one(struct pci_dev *dev)
3552 {
3553 }
3554
3555 static const struct tty_operations ops = {
3556         .open = open,
3557         .close = close,
3558         .write = write,
3559         .put_char = put_char,
3560         .flush_chars = flush_chars,
3561         .write_room = write_room,
3562         .chars_in_buffer = chars_in_buffer,
3563         .flush_buffer = flush_buffer,
3564         .ioctl = ioctl,
3565         .compat_ioctl = slgt_compat_ioctl,
3566         .throttle = throttle,
3567         .unthrottle = unthrottle,
3568         .send_xchar = send_xchar,
3569         .break_ctl = set_break,
3570         .wait_until_sent = wait_until_sent,
3571         .read_proc = read_proc,
3572         .set_termios = set_termios,
3573         .stop = tx_hold,
3574         .start = tx_release,
3575         .hangup = hangup,
3576         .tiocmget = tiocmget,
3577         .tiocmset = tiocmset,
3578 };
3579
3580 static void slgt_cleanup(void)
3581 {
3582         int rc;
3583         struct slgt_info *info;
3584         struct slgt_info *tmp;
3585
3586         printk("unload %s %s\n", driver_name, driver_version);
3587
3588         if (serial_driver) {
3589                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3590                         tty_unregister_device(serial_driver, info->line);
3591                 if ((rc = tty_unregister_driver(serial_driver)))
3592                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3593                 put_tty_driver(serial_driver);
3594         }
3595
3596         /* reset devices */
3597         info = slgt_device_list;
3598         while(info) {
3599                 reset_port(info);
3600                 info = info->next_device;
3601         }
3602
3603         /* release devices */
3604         info = slgt_device_list;
3605         while(info) {
3606 #if SYNCLINK_GENERIC_HDLC
3607                 hdlcdev_exit(info);
3608 #endif
3609                 free_dma_bufs(info);
3610                 free_tmp_rbuf(info);
3611                 if (info->port_num == 0)
3612                         release_resources(info);
3613                 tmp = info;
3614                 info = info->next_device;
3615                 kfree(tmp);
3616         }
3617
3618         if (pci_registered)
3619                 pci_unregister_driver(&pci_driver);
3620 }
3621
3622 /*
3623  *  Driver initialization entry point.
3624  */
3625 static int __init slgt_init(void)
3626 {
3627         int rc;
3628
3629         printk("%s %s\n", driver_name, driver_version);
3630
3631         serial_driver = alloc_tty_driver(MAX_DEVICES);
3632         if (!serial_driver) {
3633                 printk("%s can't allocate tty driver\n", driver_name);
3634                 return -ENOMEM;
3635         }
3636
3637         /* Initialize the tty_driver structure */
3638
3639         serial_driver->owner = THIS_MODULE;
3640         serial_driver->driver_name = tty_driver_name;
3641         serial_driver->name = tty_dev_prefix;
3642         serial_driver->major = ttymajor;
3643         serial_driver->minor_start = 64;
3644         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3645         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3646         serial_driver->init_termios = tty_std_termios;
3647         serial_driver->init_termios.c_cflag =
3648                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3649         serial_driver->init_termios.c_ispeed = 9600;
3650         serial_driver->init_termios.c_ospeed = 9600;
3651         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3652         tty_set_operations(serial_driver, &ops);
3653         if ((rc = tty_register_driver(serial_driver)) < 0) {
3654                 DBGERR(("%s can't register serial driver\n", driver_name));
3655                 put_tty_driver(serial_driver);
3656                 serial_driver = NULL;
3657                 goto error;
3658         }
3659
3660         printk("%s %s, tty major#%d\n",
3661                 driver_name, driver_version,
3662                 serial_driver->major);
3663
3664         slgt_device_count = 0;
3665         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3666                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3667                 goto error;
3668         }
3669         pci_registered = true;
3670
3671         if (!slgt_device_list)
3672                 printk("%s no devices found\n",driver_name);
3673
3674         return 0;
3675
3676 error:
3677         slgt_cleanup();
3678         return rc;
3679 }
3680
3681 static void __exit slgt_exit(void)
3682 {
3683         slgt_cleanup();
3684 }
3685
3686 module_init(slgt_init);
3687 module_exit(slgt_exit);
3688
3689 /*
3690  * register access routines
3691  */
3692
3693 #define CALC_REGADDR() \
3694         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3695         if (addr >= 0x80) \
3696                 reg_addr += (info->port_num) * 32;
3697
3698 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3699 {
3700         CALC_REGADDR();
3701         return readb((void __iomem *)reg_addr);
3702 }
3703
3704 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3705 {
3706         CALC_REGADDR();
3707         writeb(value, (void __iomem *)reg_addr);
3708 }
3709
3710 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3711 {
3712         CALC_REGADDR();
3713         return readw((void __iomem *)reg_addr);
3714 }
3715
3716 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3717 {
3718         CALC_REGADDR();
3719         writew(value, (void __iomem *)reg_addr);
3720 }
3721
3722 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3723 {
3724         CALC_REGADDR();
3725         return readl((void __iomem *)reg_addr);
3726 }
3727
3728 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3729 {
3730         CALC_REGADDR();
3731         writel(value, (void __iomem *)reg_addr);
3732 }
3733
3734 static void rdma_reset(struct slgt_info *info)
3735 {
3736         unsigned int i;
3737
3738         /* set reset bit */
3739         wr_reg32(info, RDCSR, BIT1);
3740
3741         /* wait for enable bit cleared */
3742         for(i=0 ; i < 1000 ; i++)
3743                 if (!(rd_reg32(info, RDCSR) & BIT0))
3744                         break;
3745 }
3746
3747 static void tdma_reset(struct slgt_info *info)
3748 {
3749         unsigned int i;
3750
3751         /* set reset bit */
3752         wr_reg32(info, TDCSR, BIT1);
3753
3754         /* wait for enable bit cleared */
3755         for(i=0 ; i < 1000 ; i++)
3756                 if (!(rd_reg32(info, TDCSR) & BIT0))
3757                         break;
3758 }
3759
3760 /*
3761  * enable internal loopback
3762  * TxCLK and RxCLK are generated from BRG
3763  * and TxD is looped back to RxD internally.
3764  */
3765 static void enable_loopback(struct slgt_info *info)
3766 {
3767         /* SCR (serial control) BIT2=looopback enable */
3768         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3769
3770         if (info->params.mode != MGSL_MODE_ASYNC) {
3771                 /* CCR (clock control)
3772                  * 07..05  tx clock source (010 = BRG)
3773                  * 04..02  rx clock source (010 = BRG)
3774                  * 01      auxclk enable   (0 = disable)
3775                  * 00      BRG enable      (1 = enable)
3776                  *
3777                  * 0100 1001
3778                  */
3779                 wr_reg8(info, CCR, 0x49);
3780
3781                 /* set speed if available, otherwise use default */
3782                 if (info->params.clock_speed)
3783                         set_rate(info, info->params.clock_speed);
3784                 else
3785                         set_rate(info, 3686400);
3786         }
3787 }
3788
3789 /*
3790  *  set baud rate generator to specified rate
3791  */
3792 static void set_rate(struct slgt_info *info, u32 rate)
3793 {
3794         unsigned int div;
3795         static unsigned int osc = 14745600;
3796
3797         /* div = osc/rate - 1
3798          *
3799          * Round div up if osc/rate is not integer to
3800          * force to next slowest rate.
3801          */
3802
3803         if (rate) {
3804                 div = osc/rate;
3805                 if (!(osc % rate) && div)
3806                         div--;
3807                 wr_reg16(info, BDR, (unsigned short)div);
3808         }
3809 }
3810
3811 static void rx_stop(struct slgt_info *info)
3812 {
3813         unsigned short val;
3814
3815         /* disable and reset receiver */
3816         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3817         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3818         wr_reg16(info, RCR, val);                  /* clear reset bit */
3819
3820         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3821
3822         /* clear pending rx interrupts */
3823         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3824
3825         rdma_reset(info);
3826
3827         info->rx_enabled = false;
3828         info->rx_restart = false;
3829 }
3830
3831 static void rx_start(struct slgt_info *info)
3832 {
3833         unsigned short val;
3834
3835         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3836
3837         /* clear pending rx overrun IRQ */
3838         wr_reg16(info, SSR, IRQ_RXOVER);
3839
3840         /* reset and disable receiver */
3841         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3842         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3843         wr_reg16(info, RCR, val);                  /* clear reset bit */
3844
3845         rdma_reset(info);
3846         reset_rbufs(info);
3847
3848         /* set 1st descriptor address */
3849         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3850
3851         if (info->params.mode != MGSL_MODE_ASYNC) {
3852                 /* enable rx DMA and DMA interrupt */
3853                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3854         } else {
3855                 /* enable saving of rx status, rx DMA and DMA interrupt */
3856                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3857         }
3858
3859         slgt_irq_on(info, IRQ_RXOVER);
3860
3861         /* enable receiver */
3862         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3863
3864         info->rx_restart = false;
3865         info->rx_enabled = true;
3866 }
3867
3868 static void tx_start(struct slgt_info *info)
3869 {
3870         if (!info->tx_enabled) {
3871                 wr_reg16(info, TCR,
3872                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3873                 info->tx_enabled = true;
3874         }
3875
3876         if (info->tx_count) {
3877                 info->drop_rts_on_tx_done = false;
3878
3879                 if (info->params.mode != MGSL_MODE_ASYNC) {
3880                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3881                                 get_signals(info);
3882                                 if (!(info->signals & SerialSignal_RTS)) {
3883                                         info->signals |= SerialSignal_RTS;
3884                                         set_signals(info);
3885                                         info->drop_rts_on_tx_done = true;
3886                                 }
3887                         }
3888
3889                         slgt_irq_off(info, IRQ_TXDATA);
3890                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3891                         /* clear tx idle and underrun status bits */
3892                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3893                         if (info->params.mode == MGSL_MODE_HDLC)
3894                                 mod_timer(&info->tx_timer, jiffies +
3895                                                 msecs_to_jiffies(5000));
3896                 } else {
3897                         slgt_irq_off(info, IRQ_TXDATA);
3898                         slgt_irq_on(info, IRQ_TXIDLE);
3899                         /* clear tx idle status bit */
3900                         wr_reg16(info, SSR, IRQ_TXIDLE);
3901                 }
3902                 tdma_start(info);
3903                 info->tx_active = true;
3904         }
3905 }
3906
3907 /*
3908  * start transmit DMA if inactive and there are unsent buffers
3909  */
3910 static void tdma_start(struct slgt_info *info)
3911 {
3912         unsigned int i;
3913
3914         if (rd_reg32(info, TDCSR) & BIT0)
3915                 return;
3916
3917         /* transmit DMA inactive, check for unsent buffers */
3918         i = info->tbuf_start;
3919         while (!desc_count(info->tbufs[i])) {
3920                 if (++i == info->tbuf_count)
3921                         i = 0;
3922                 if (i == info->tbuf_current)
3923                         return;
3924         }
3925         info->tbuf_start = i;
3926
3927         /* there are unsent buffers, start transmit DMA */
3928
3929         /* reset needed if previous error condition */
3930         tdma_reset(info);
3931
3932         /* set 1st descriptor address */
3933         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3934         wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3935 }
3936
3937 static void tx_stop(struct slgt_info *info)
3938 {
3939         unsigned short val;
3940
3941         del_timer(&info->tx_timer);
3942
3943         tdma_reset(info);
3944
3945         /* reset and disable transmitter */
3946         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3947         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3948
3949         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3950
3951         /* clear tx idle and underrun status bit */
3952         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3953
3954         reset_tbufs(info);
3955
3956         info->tx_enabled = false;
3957         info->tx_active = false;
3958 }
3959
3960 static void reset_port(struct slgt_info *info)
3961 {
3962         if (!info->reg_addr)
3963                 return;
3964
3965         tx_stop(info);
3966         rx_stop(info);
3967
3968         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3969         set_signals(info);
3970
3971         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3972 }
3973
3974 static void reset_adapter(struct slgt_info *info)
3975 {
3976         int i;
3977         for (i=0; i < info->port_count; ++i) {
3978                 if (info->port_array[i])
3979                         reset_port(info->port_array[i]);
3980         }
3981 }
3982
3983 static void async_mode(struct slgt_info *info)
3984 {
3985         unsigned short val;
3986
3987         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3988         tx_stop(info);
3989         rx_stop(info);
3990
3991         /* TCR (tx control)
3992          *
3993          * 15..13  mode, 010=async
3994          * 12..10  encoding, 000=NRZ
3995          * 09      parity enable
3996          * 08      1=odd parity, 0=even parity
3997          * 07      1=RTS driver control
3998          * 06      1=break enable
3999          * 05..04  character length
4000          *         00=5 bits
4001          *         01=6 bits
4002          *         10=7 bits
4003          *         11=8 bits
4004          * 03      0=1 stop bit, 1=2 stop bits
4005          * 02      reset
4006          * 01      enable
4007          * 00      auto-CTS enable
4008          */
4009         val = 0x4000;
4010
4011         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4012                 val |= BIT7;
4013
4014         if (info->params.parity != ASYNC_PARITY_NONE) {
4015                 val |= BIT9;
4016                 if (info->params.parity == ASYNC_PARITY_ODD)
4017                         val |= BIT8;
4018         }
4019
4020         switch (info->params.data_bits)
4021         {
4022         case 6: val |= BIT4; break;
4023         case 7: val |= BIT5; break;
4024         case 8: val |= BIT5 + BIT4; break;
4025         }
4026
4027         if (info->params.stop_bits != 1)
4028                 val |= BIT3;
4029
4030         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4031                 val |= BIT0;
4032
4033         wr_reg16(info, TCR, val);
4034
4035         /* RCR (rx control)
4036          *
4037          * 15..13  mode, 010=async
4038          * 12..10  encoding, 000=NRZ
4039          * 09      parity enable
4040          * 08      1=odd parity, 0=even parity
4041          * 07..06  reserved, must be 0
4042          * 05..04  character length
4043          *         00=5 bits
4044          *         01=6 bits
4045          *         10=7 bits
4046          *         11=8 bits
4047          * 03      reserved, must be zero
4048          * 02      reset
4049          * 01      enable
4050          * 00      auto-DCD enable
4051          */
4052         val = 0x4000;
4053
4054         if (info->params.parity != ASYNC_PARITY_NONE) {
4055                 val |= BIT9;
4056                 if (info->params.parity == ASYNC_PARITY_ODD)
4057                         val |= BIT8;
4058         }
4059
4060         switch (info->params.data_bits)
4061         {
4062         case 6: val |= BIT4; break;
4063         case 7: val |= BIT5; break;
4064         case 8: val |= BIT5 + BIT4; break;
4065         }
4066
4067         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4068                 val |= BIT0;
4069
4070         wr_reg16(info, RCR, val);
4071
4072         /* CCR (clock control)
4073          *
4074          * 07..05  011 = tx clock source is BRG/16
4075          * 04..02  010 = rx clock source is BRG
4076          * 01      0 = auxclk disabled
4077          * 00      1 = BRG enabled
4078          *
4079          * 0110 1001
4080          */
4081         wr_reg8(info, CCR, 0x69);
4082
4083         msc_set_vcr(info);
4084
4085         /* SCR (serial control)
4086          *
4087          * 15  1=tx req on FIFO half empty
4088          * 14  1=rx req on FIFO half full
4089          * 13  tx data  IRQ enable
4090          * 12  tx idle  IRQ enable
4091          * 11  rx break on IRQ enable
4092          * 10  rx data  IRQ enable
4093          * 09  rx break off IRQ enable
4094          * 08  overrun  IRQ enable
4095          * 07  DSR      IRQ enable
4096          * 06  CTS      IRQ enable
4097          * 05  DCD      IRQ enable
4098          * 04  RI       IRQ enable
4099          * 03  reserved, must be zero
4100          * 02  1=txd->rxd internal loopback enable
4101          * 01  reserved, must be zero
4102          * 00  1=master IRQ enable
4103          */
4104         val = BIT15 + BIT14 + BIT0;
4105         wr_reg16(info, SCR, val);
4106
4107         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4108
4109         set_rate(info, info->params.data_rate * 16);
4110
4111         if (info->params.loopback)
4112                 enable_loopback(info);
4113 }
4114
4115 static void sync_mode(struct slgt_info *info)
4116 {
4117         unsigned short val;
4118
4119         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4120         tx_stop(info);
4121         rx_stop(info);
4122
4123         /* TCR (tx control)
4124          *
4125          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4126          * 12..10  encoding
4127          * 09      CRC enable
4128          * 08      CRC32
4129          * 07      1=RTS driver control
4130          * 06      preamble enable
4131          * 05..04  preamble length
4132          * 03      share open/close flag
4133          * 02      reset
4134          * 01      enable
4135          * 00      auto-CTS enable
4136          */
4137         val = BIT2;
4138
4139         switch(info->params.mode) {
4140         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4141         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4142         case MGSL_MODE_RAW:      val |= BIT13; break;
4143         }
4144         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4145                 val |= BIT7;
4146
4147         switch(info->params.encoding)
4148         {
4149         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4150         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4151         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4152         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4153         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4154         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4155         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4156         }
4157
4158         switch (info->params.crc_type & HDLC_CRC_MASK)
4159         {
4160         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4161         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4162         }
4163
4164         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4165                 val |= BIT6;
4166
4167         switch (info->params.preamble_length)
4168         {
4169         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4170         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4171         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4172         }
4173
4174         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4175                 val |= BIT0;
4176
4177         wr_reg16(info, TCR, val);
4178
4179         /* TPR (transmit preamble) */
4180
4181         switch (info->params.preamble)
4182         {
4183         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4184         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4185         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4186         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4187         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4188         default:                          val = 0x7e; break;
4189         }
4190         wr_reg8(info, TPR, (unsigned char)val);
4191
4192         /* RCR (rx control)
4193          *
4194          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4195          * 12..10  encoding
4196          * 09      CRC enable
4197          * 08      CRC32
4198          * 07..03  reserved, must be 0
4199          * 02      reset
4200          * 01      enable
4201          * 00      auto-DCD enable
4202          */
4203         val = 0;
4204
4205         switch(info->params.mode) {
4206         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4207         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4208         case MGSL_MODE_RAW:      val |= BIT13; break;
4209         }
4210
4211         switch(info->params.encoding)
4212         {
4213         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4214         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4215         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4216         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4217         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4218         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4219         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4220         }
4221
4222         switch (info->params.crc_type & HDLC_CRC_MASK)
4223         {
4224         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4225         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4226         }
4227
4228         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4229                 val |= BIT0;
4230
4231         wr_reg16(info, RCR, val);
4232
4233         /* CCR (clock control)
4234          *
4235          * 07..05  tx clock source
4236          * 04..02  rx clock source
4237          * 01      auxclk enable
4238          * 00      BRG enable
4239          */
4240         val = 0;
4241
4242         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4243         {
4244                 // when RxC source is DPLL, BRG generates 16X DPLL
4245                 // reference clock, so take TxC from BRG/16 to get
4246                 // transmit clock at actual data rate
4247                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4248                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4249                 else
4250                         val |= BIT6;    /* 010, txclk = BRG */
4251         }
4252         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4253                 val |= BIT7;    /* 100, txclk = DPLL Input */
4254         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4255                 val |= BIT5;    /* 001, txclk = RXC Input */
4256
4257         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4258                 val |= BIT3;    /* 010, rxclk = BRG */
4259         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4260                 val |= BIT4;    /* 100, rxclk = DPLL */
4261         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4262                 val |= BIT2;    /* 001, rxclk = TXC Input */
4263
4264         if (info->params.clock_speed)
4265                 val |= BIT1 + BIT0;
4266
4267         wr_reg8(info, CCR, (unsigned char)val);
4268
4269         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4270         {
4271                 // program DPLL mode
4272                 switch(info->params.encoding)
4273                 {
4274                 case HDLC_ENCODING_BIPHASE_MARK:
4275                 case HDLC_ENCODING_BIPHASE_SPACE:
4276                         val = BIT7; break;
4277                 case HDLC_ENCODING_BIPHASE_LEVEL:
4278                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4279                         val = BIT7 + BIT6; break;
4280                 default: val = BIT6;    // NRZ encodings
4281                 }
4282                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4283
4284                 // DPLL requires a 16X reference clock from BRG
4285                 set_rate(info, info->params.clock_speed * 16);
4286         }
4287         else
4288                 set_rate(info, info->params.clock_speed);
4289
4290         tx_set_idle(info);
4291
4292         msc_set_vcr(info);
4293
4294         /* SCR (serial control)
4295          *
4296          * 15  1=tx req on FIFO half empty
4297          * 14  1=rx req on FIFO half full
4298          * 13  tx data  IRQ enable
4299          * 12  tx idle  IRQ enable
4300          * 11  underrun IRQ enable
4301          * 10  rx data  IRQ enable
4302          * 09  rx idle  IRQ enable
4303          * 08  overrun  IRQ enable
4304          * 07  DSR      IRQ enable
4305          * 06  CTS      IRQ enable
4306          * 05  DCD      IRQ enable
4307          * 04  RI       IRQ enable
4308          * 03  reserved, must be zero
4309          * 02  1=txd->rxd internal loopback enable
4310          * 01  reserved, must be zero
4311          * 00  1=master IRQ enable
4312          */
4313         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4314
4315         if (info->params.loopback)
4316                 enable_loopback(info);
4317 }
4318
4319 /*
4320  *  set transmit idle mode
4321  */
4322 static void tx_set_idle(struct slgt_info *info)
4323 {
4324         unsigned char val;
4325         unsigned short tcr;
4326
4327         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4328          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4329          */
4330         tcr = rd_reg16(info, TCR);
4331         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4332                 /* disable preamble, set idle size to 16 bits */
4333                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4334                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4335                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4336         } else if (!(tcr & BIT6)) {
4337                 /* preamble is disabled, set idle size to 8 bits */
4338                 tcr &= ~(BIT5 + BIT4);
4339         }
4340         wr_reg16(info, TCR, tcr);
4341
4342         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4343                 /* LSB of custom tx idle specified in tx idle register */
4344                 val = (unsigned char)(info->idle_mode & 0xff);
4345         } else {
4346                 /* standard 8 bit idle patterns */
4347                 switch(info->idle_mode)
4348                 {
4349                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4350                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4351                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4352                 case HDLC_TXIDLE_ZEROS:
4353                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4354                 default:                         val = 0xff;
4355                 }
4356         }
4357
4358         wr_reg8(info, TIR, val);
4359 }
4360
4361 /*
4362  * get state of V24 status (input) signals
4363  */
4364 static void get_signals(struct slgt_info *info)
4365 {
4366         unsigned short status = rd_reg16(info, SSR);
4367
4368         /* clear all serial signals except DTR and RTS */
4369         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4370
4371         if (status & BIT3)
4372                 info->signals |= SerialSignal_DSR;
4373         if (status & BIT2)
4374                 info->signals |= SerialSignal_CTS;
4375         if (status & BIT1)
4376                 info->signals |= SerialSignal_DCD;
4377         if (status & BIT0)
4378                 info->signals |= SerialSignal_RI;
4379 }
4380
4381 /*
4382  * set V.24 Control Register based on current configuration
4383  */
4384 static void msc_set_vcr(struct slgt_info *info)
4385 {
4386         unsigned char val = 0;
4387
4388         /* VCR (V.24 control)
4389          *
4390          * 07..04  serial IF select
4391          * 03      DTR
4392          * 02      RTS
4393          * 01      LL
4394          * 00      RL
4395          */
4396
4397         switch(info->if_mode & MGSL_INTERFACE_MASK)
4398         {
4399         case MGSL_INTERFACE_RS232:
4400                 val |= BIT5; /* 0010 */
4401                 break;
4402         case MGSL_INTERFACE_V35:
4403                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4404                 break;
4405         case MGSL_INTERFACE_RS422:
4406                 val |= BIT6; /* 0100 */
4407                 break;
4408         }
4409
4410         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4411                 val |= BIT4;
4412         if (info->signals & SerialSignal_DTR)
4413                 val |= BIT3;
4414         if (info->signals & SerialSignal_RTS)
4415                 val |= BIT2;
4416         if (info->if_mode & MGSL_INTERFACE_LL)
4417                 val |= BIT1;
4418         if (info->if_mode & MGSL_INTERFACE_RL)
4419                 val |= BIT0;
4420         wr_reg8(info, VCR, val);
4421 }
4422
4423 /*
4424  * set state of V24 control (output) signals
4425  */
4426 static void set_signals(struct slgt_info *info)
4427 {
4428         unsigned char val = rd_reg8(info, VCR);
4429         if (info->signals & SerialSignal_DTR)
4430                 val |= BIT3;
4431         else
4432                 val &= ~BIT3;
4433         if (info->signals & SerialSignal_RTS)
4434                 val |= BIT2;
4435         else
4436                 val &= ~BIT2;
4437         wr_reg8(info, VCR, val);
4438 }
4439
4440 /*
4441  * free range of receive DMA buffers (i to last)
4442  */
4443 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4444 {
4445         int done = 0;
4446
4447         while(!done) {
4448                 /* reset current buffer for reuse */
4449                 info->rbufs[i].status = 0;
4450                 switch(info->params.mode) {
4451                 case MGSL_MODE_RAW:
4452                 case MGSL_MODE_MONOSYNC:
4453                 case MGSL_MODE_BISYNC:
4454                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4455                         break;
4456                 default:
4457                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4458                 }
4459
4460                 if (i == last)
4461                         done = 1;
4462                 if (++i == info->rbuf_count)
4463                         i = 0;
4464         }
4465         info->rbuf_current = i;
4466 }
4467
4468 /*
4469  * mark all receive DMA buffers as free
4470  */
4471 static void reset_rbufs(struct slgt_info *info)
4472 {
4473         free_rbufs(info, 0, info->rbuf_count - 1);
4474 }
4475
4476 /*
4477  * pass receive HDLC frame to upper layer
4478  *
4479  * return true if frame available, otherwise false
4480  */
4481 static bool rx_get_frame(struct slgt_info *info)
4482 {
4483         unsigned int start, end;
4484         unsigned short status;
4485         unsigned int framesize = 0;
4486         unsigned long flags;
4487         struct tty_struct *tty = info->port.tty;
4488         unsigned char addr_field = 0xff;
4489         unsigned int crc_size = 0;
4490
4491         switch (info->params.crc_type & HDLC_CRC_MASK) {
4492         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4493         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4494         }
4495
4496 check_again:
4497
4498         framesize = 0;
4499         addr_field = 0xff;
4500         start = end = info->rbuf_current;
4501
4502         for (;;) {
4503                 if (!desc_complete(info->rbufs[end]))
4504                         goto cleanup;
4505
4506                 if (framesize == 0 && info->params.addr_filter != 0xff)
4507                         addr_field = info->rbufs[end].buf[0];
4508
4509                 framesize += desc_count(info->rbufs[end]);
4510
4511                 if (desc_eof(info->rbufs[end]))
4512                         break;
4513
4514                 if (++end == info->rbuf_count)
4515                         end = 0;
4516
4517                 if (end == info->rbuf_current) {
4518                         if (info->rx_enabled){
4519                                 spin_lock_irqsave(&info->lock,flags);
4520                                 rx_start(info);
4521                                 spin_unlock_irqrestore(&info->lock,flags);
4522                         }
4523                         goto cleanup;
4524                 }
4525         }
4526
4527         /* status
4528          *
4529          * 15      buffer complete
4530          * 14..06  reserved
4531          * 05..04  residue
4532          * 02      eof (end of frame)
4533          * 01      CRC error
4534          * 00      abort
4535          */
4536         status = desc_status(info->rbufs[end]);
4537
4538         /* ignore CRC bit if not using CRC (bit is undefined) */
4539         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4540                 status &= ~BIT1;
4541
4542         if (framesize == 0 ||
4543                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4544                 free_rbufs(info, start, end);
4545                 goto check_again;
4546         }
4547
4548         if (framesize < (2 + crc_size) || status & BIT0) {
4549                 info->icount.rxshort++;
4550                 framesize = 0;
4551         } else if (status & BIT1) {
4552                 info->icount.rxcrc++;
4553                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4554                         framesize = 0;
4555         }
4556
4557 #if SYNCLINK_GENERIC_HDLC
4558         if (framesize == 0) {
4559                 info->netdev->stats.rx_errors++;
4560                 info->netdev->stats.rx_frame_errors++;
4561         }
4562 #endif
4563
4564         DBGBH(("%s rx frame status=%04X size=%d\n",
4565                 info->device_name, status, framesize));
4566         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4567
4568         if (framesize) {
4569                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4570                         framesize -= crc_size;
4571                         crc_size = 0;
4572                 }
4573
4574                 if (framesize > info->max_frame_size + crc_size)
4575                         info->icount.rxlong++;
4576                 else {
4577                         /* copy dma buffer(s) to contiguous temp buffer */
4578                         int copy_count = framesize;
4579                         int i = start;
4580                         unsigned char *p = info->tmp_rbuf;
4581                         info->tmp_rbuf_count = framesize;
4582
4583                         info->icount.rxok++;
4584
4585                         while(copy_count) {
4586                                 int partial_count = min(copy_count, DMABUFSIZE);
4587                                 memcpy(p, info->rbufs[i].buf, partial_count);
4588                                 p += partial_count;
4589                                 copy_count -= partial_count;
4590                                 if (++i == info->rbuf_count)
4591                                         i = 0;
4592                         }
4593
4594                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4595                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4596                                 framesize++;
4597                         }
4598
4599 #if SYNCLINK_GENERIC_HDLC
4600                         if (info->netcount)
4601                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4602                         else
4603 #endif
4604                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4605                 }
4606         }
4607         free_rbufs(info, start, end);
4608         return true;
4609
4610 cleanup:
4611         return false;
4612 }
4613
4614 /*
4615  * pass receive buffer (RAW synchronous mode) to tty layer
4616  * return true if buffer available, otherwise false
4617  */
4618 static bool rx_get_buf(struct slgt_info *info)
4619 {
4620         unsigned int i = info->rbuf_current;
4621         unsigned int count;
4622
4623         if (!desc_complete(info->rbufs[i]))
4624                 return false;
4625         count = desc_count(info->rbufs[i]);
4626         switch(info->params.mode) {
4627         case MGSL_MODE_MONOSYNC:
4628         case MGSL_MODE_BISYNC:
4629                 /* ignore residue in byte synchronous modes */
4630                 if (desc_residue(info->rbufs[i]))
4631                         count--;
4632                 break;
4633         }
4634         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4635         DBGINFO(("rx_get_buf size=%d\n", count));
4636         if (count)
4637                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4638                                   info->flag_buf, count);
4639         free_rbufs(info, i, i);
4640         return true;
4641 }
4642
4643 static void reset_tbufs(struct slgt_info *info)
4644 {
4645         unsigned int i;
4646         info->tbuf_current = 0;
4647         for (i=0 ; i < info->tbuf_count ; i++) {
4648                 info->tbufs[i].status = 0;
4649                 info->tbufs[i].count  = 0;
4650         }
4651 }
4652
4653 /*
4654  * return number of free transmit DMA buffers
4655  */
4656 static unsigned int free_tbuf_count(struct slgt_info *info)
4657 {
4658         unsigned int count = 0;
4659         unsigned int i = info->tbuf_current;
4660
4661         do
4662         {
4663                 if (desc_count(info->tbufs[i]))
4664                         break; /* buffer in use */
4665                 ++count;
4666                 if (++i == info->tbuf_count)
4667                         i=0;
4668         } while (i != info->tbuf_current);
4669
4670         /* if tx DMA active, last zero count buffer is in use */
4671         if (count && (rd_reg32(info, TDCSR) & BIT0))
4672                 --count;
4673
4674         return count;
4675 }
4676
4677 /*
4678  * return number of bytes in unsent transmit DMA buffers
4679  * and the serial controller tx FIFO
4680  */
4681 static unsigned int tbuf_bytes(struct slgt_info *info)
4682 {
4683         unsigned int total_count = 0;
4684         unsigned int i = info->tbuf_current;
4685         unsigned int reg_value;
4686         unsigned int count;
4687         unsigned int active_buf_count = 0;
4688
4689         /*
4690          * Add descriptor counts for all tx DMA buffers.
4691          * If count is zero (cleared by DMA controller after read),
4692          * the buffer is complete or is actively being read from.
4693          *
4694          * Record buf_count of last buffer with zero count starting
4695          * from current ring position. buf_count is mirror
4696          * copy of count and is not cleared by serial controller.
4697          * If DMA controller is active, that buffer is actively
4698          * being read so add to total.
4699          */
4700         do {
4701                 count = desc_count(info->tbufs[i]);
4702                 if (count)
4703                         total_count += count;
4704                 else if (!total_count)
4705                         active_buf_count = info->tbufs[i].buf_count;
4706                 if (++i == info->tbuf_count)
4707                         i = 0;
4708         } while (i != info->tbuf_current);
4709
4710         /* read tx DMA status register */
4711         reg_value = rd_reg32(info, TDCSR);
4712
4713         /* if tx DMA active, last zero count buffer is in use */
4714         if (reg_value & BIT0)
4715                 total_count += active_buf_count;
4716
4717         /* add tx FIFO count = reg_value[15..8] */
4718         total_count += (reg_value >> 8) & 0xff;
4719
4720         /* if transmitter active add one byte for shift register */
4721         if (info->tx_active)
4722                 total_count++;
4723
4724         return total_count;
4725 }
4726
4727 /*
4728  * load transmit DMA buffer(s) with data
4729  */
4730 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4731 {
4732         unsigned short count;
4733         unsigned int i;
4734         struct slgt_desc *d;
4735
4736         if (size == 0)
4737                 return;
4738
4739         DBGDATA(info, buf, size, "tx");
4740
4741         info->tbuf_start = i = info->tbuf_current;
4742
4743         while (size) {
4744                 d = &info->tbufs[i];
4745                 if (++i == info->tbuf_count)
4746                         i = 0;
4747
4748                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4749                 memcpy(d->buf, buf, count);
4750
4751                 size -= count;
4752                 buf  += count;
4753
4754                 /*
4755                  * set EOF bit for last buffer of HDLC frame or
4756                  * for every buffer in raw mode
4757                  */
4758                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4759                     info->params.mode == MGSL_MODE_RAW)
4760                         set_desc_eof(*d, 1);
4761                 else
4762                         set_desc_eof(*d, 0);
4763
4764                 set_desc_count(*d, count);
4765                 d->buf_count = count;
4766         }
4767
4768         info->tbuf_current = i;
4769 }
4770
4771 static int register_test(struct slgt_info *info)
4772 {
4773         static unsigned short patterns[] =
4774                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4775         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4776         unsigned int i;
4777         int rc = 0;
4778
4779         for (i=0 ; i < count ; i++) {
4780                 wr_reg16(info, TIR, patterns[i]);
4781                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4782                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4783                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4784                         rc = -ENODEV;
4785                         break;
4786                 }
4787         }
4788         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4789         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4790         return rc;
4791 }
4792
4793 static int irq_test(struct slgt_info *info)
4794 {
4795         unsigned long timeout;
4796         unsigned long flags;
4797         struct tty_struct *oldtty = info->port.tty;
4798         u32 speed = info->params.data_rate;
4799
4800         info->params.data_rate = 921600;
4801         info->port.tty = NULL;
4802
4803         spin_lock_irqsave(&info->lock, flags);
4804         async_mode(info);
4805         slgt_irq_on(info, IRQ_TXIDLE);
4806
4807         /* enable transmitter */
4808         wr_reg16(info, TCR,
4809                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4810
4811         /* write one byte and wait for tx idle */
4812         wr_reg16(info, TDR, 0);
4813
4814         /* assume failure */
4815         info->init_error = DiagStatus_IrqFailure;
4816         info->irq_occurred = false;
4817
4818         spin_unlock_irqrestore(&info->lock, flags);
4819
4820         timeout=100;
4821         while(timeout-- && !info->irq_occurred)
4822                 msleep_interruptible(10);
4823
4824         spin_lock_irqsave(&info->lock,flags);
4825         reset_port(info);
4826         spin_unlock_irqrestore(&info->lock,flags);
4827
4828         info->params.data_rate = speed;
4829         info->port.tty = oldtty;
4830
4831         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4832         return info->irq_occurred ? 0 : -ENODEV;
4833 }
4834
4835 static int loopback_test_rx(struct slgt_info *info)
4836 {
4837         unsigned char *src, *dest;
4838         int count;
4839
4840         if (desc_complete(info->rbufs[0])) {
4841                 count = desc_count(info->rbufs[0]);
4842                 src   = info->rbufs[0].buf;
4843                 dest  = info->tmp_rbuf;
4844
4845                 for( ; count ; count-=2, src+=2) {
4846                         /* src=data byte (src+1)=status byte */
4847                         if (!(*(src+1) & (BIT9 + BIT8))) {
4848                                 *dest = *src;
4849                                 dest++;
4850                                 info->tmp_rbuf_count++;
4851                         }
4852                 }
4853                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4854                 return 1;
4855         }
4856         return 0;
4857 }
4858
4859 static int loopback_test(struct slgt_info *info)
4860 {
4861 #define TESTFRAMESIZE 20
4862
4863         unsigned long timeout;
4864         u16 count = TESTFRAMESIZE;
4865         unsigned char buf[TESTFRAMESIZE];
4866         int rc = -ENODEV;
4867         unsigned long flags;
4868
4869         struct tty_struct *oldtty = info->port.tty;
4870         MGSL_PARAMS params;
4871
4872         memcpy(&params, &info->params, sizeof(params));
4873
4874         info->params.mode = MGSL_MODE_ASYNC;
4875         info->params.data_rate = 921600;
4876         info->params.loopback = 1;
4877         info->port.tty = NULL;
4878
4879         /* build and send transmit frame */
4880         for (count = 0; count < TESTFRAMESIZE; ++count)
4881                 buf[count] = (unsigned char)count;
4882
4883         info->tmp_rbuf_count = 0;
4884         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4885
4886         /* program hardware for HDLC and enabled receiver */
4887         spin_lock_irqsave(&info->lock,flags);
4888         async_mode(info);
4889         rx_start(info);
4890         info->tx_count = count;
4891         tx_load(info, buf, count);
4892         tx_start(info);
4893         spin_unlock_irqrestore(&info->lock, flags);
4894
4895         /* wait for receive complete */
4896         for (timeout = 100; timeout; --timeout) {
4897                 msleep_interruptible(10);
4898                 if (loopback_test_rx(info)) {
4899                         rc = 0;
4900                         break;
4901                 }
4902         }
4903
4904         /* verify received frame length and contents */
4905         if (!rc && (info->tmp_rbuf_count != count ||
4906                   memcmp(buf, info->tmp_rbuf, count))) {
4907                 rc = -ENODEV;
4908         }
4909
4910         spin_lock_irqsave(&info->lock,flags);
4911         reset_adapter(info);
4912         spin_unlock_irqrestore(&info->lock,flags);
4913
4914         memcpy(&info->params, &params, sizeof(info->params));
4915         info->port.tty = oldtty;
4916
4917         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4918         return rc;
4919 }
4920
4921 static int adapter_test(struct slgt_info *info)
4922 {
4923         DBGINFO(("testing %s\n", info->device_name));
4924         if (register_test(info) < 0) {
4925                 printk("register test failure %s addr=%08X\n",
4926                         info->device_name, info->phys_reg_addr);
4927         } else if (irq_test(info) < 0) {
4928                 printk("IRQ test failure %s IRQ=%d\n",
4929                         info->device_name, info->irq_level);
4930         } else if (loopback_test(info) < 0) {
4931                 printk("loopback test failure %s\n", info->device_name);
4932         }
4933         return info->init_error;
4934 }
4935
4936 /*
4937  * transmit timeout handler
4938  */
4939 static void tx_timeout(unsigned long context)
4940 {
4941         struct slgt_info *info = (struct slgt_info*)context;
4942         unsigned long flags;
4943
4944         DBGINFO(("%s tx_timeout\n", info->device_name));
4945         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4946                 info->icount.txtimeout++;
4947         }
4948         spin_lock_irqsave(&info->lock,flags);
4949         info->tx_active = false;
4950         info->tx_count = 0;
4951         spin_unlock_irqrestore(&info->lock,flags);
4952
4953 #if SYNCLINK_GENERIC_HDLC
4954         if (info->netcount)
4955                 hdlcdev_tx_done(info);
4956         else
4957 #endif
4958                 bh_transmit(info);
4959 }
4960
4961 /*
4962  * receive buffer polling timer
4963  */
4964 static void rx_timeout(unsigned long context)
4965 {
4966         struct slgt_info *info = (struct slgt_info*)context;
4967         unsigned long flags;
4968
4969         DBGINFO(("%s rx_timeout\n", info->device_name));
4970         spin_lock_irqsave(&info->lock, flags);
4971         info->pending_bh |= BH_RECEIVE;
4972         spin_unlock_irqrestore(&info->lock, flags);
4973         bh_handler(&info->task);
4974 }
4975