drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76 #include <linux/synclink.h>
  77
  78 #include <asm/system.h>
  79 #include <asm/io.h>
  80 #include <asm/irq.h>
  81 #include <asm/dma.h>
  82 #include <asm/types.h>
  83 #include <asm/uaccess.h>
  84
  85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  86 #define SYNCLINK_GENERIC_HDLC 1
  87 #else
  88 #define SYNCLINK_GENERIC_HDLC 0
  89 #endif
  90
  91 /*
  92  * module identification
  93  */
  94 static char *driver_name     = "SyncLink GT";
  95 static char *driver_version  = "$Revision: 4.50 $";
  96 static char *tty_driver_name = "synclink_gt";
  97 static char *tty_dev_prefix  = "ttySLG";
  98 MODULE_LICENSE("GPL");
  99 #define MGSL_MAGIC 0x5401
 100 #define MAX_DEVICES 32
 101
 102 static struct pci_device_id pci_table[] = {
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {0,}, /* terminate list */
 108 };
 109 MODULE_DEVICE_TABLE(pci, pci_table);
 110
 111 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 112 static void remove_one(struct pci_dev *dev);
 113 static struct pci_driver pci_driver = {
 114         .name           = "synclink_gt",
 115         .id_table       = pci_table,
 116         .probe          = init_one,
 117         .remove         = __devexit_p(remove_one),
 118 };
 119
 120 static bool pci_registered;
 121
 122 /*
 123  * module configuration and status
 124  */
 125 static struct slgt_info *slgt_device_list;
 126 static int slgt_device_count;
 127
 128 static int ttymajor;
 129 static int debug_level;
 130 static int maxframe[MAX_DEVICES];
 131 static int dosyncppp[MAX_DEVICES];
 132
 133 module_param(ttymajor, int, 0);
 134 module_param(debug_level, int, 0);
 135 module_param_array(maxframe, int, NULL, 0);
 136 module_param_array(dosyncppp, int, NULL, 0);
 137
 138 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 139 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 140 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 141 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 142
 143 /*
 144  * tty support and callbacks
 145  */
 146 static struct tty_driver *serial_driver;
 147
 148 static int  open(struct tty_struct *tty, struct file * filp);
 149 static void close(struct tty_struct *tty, struct file * filp);
 150 static void hangup(struct tty_struct *tty);
 151 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 152
 153 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 154 static int put_char(struct tty_struct *tty, unsigned char ch);
 155 static void send_xchar(struct tty_struct *tty, char ch);
 156 static void wait_until_sent(struct tty_struct *tty, int timeout);
 157 static int  write_room(struct tty_struct *tty);
 158 static void flush_chars(struct tty_struct *tty);
 159 static void flush_buffer(struct tty_struct *tty);
 160 static void tx_hold(struct tty_struct *tty);
 161 static void tx_release(struct tty_struct *tty);
 162
 163 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 164 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 165 static int  chars_in_buffer(struct tty_struct *tty);
 166 static void throttle(struct tty_struct * tty);
 167 static void unthrottle(struct tty_struct * tty);
 168 static int set_break(struct tty_struct *tty, int break_state);
 169
 170 /*
 171  * generic HDLC support and callbacks
 172  */
 173 #if SYNCLINK_GENERIC_HDLC
 174 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 175 static void hdlcdev_tx_done(struct slgt_info *info);
 176 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 177 static int  hdlcdev_init(struct slgt_info *info);
 178 static void hdlcdev_exit(struct slgt_info *info);
 179 #endif
 180
 181
 182 /*
 183  * device specific structures, macros and functions
 184  */
 185
 186 #define SLGT_MAX_PORTS 4
 187 #define SLGT_REG_SIZE  256
 188
 189 /*
 190  * conditional wait facility
 191  */
 192 struct cond_wait {
 193         struct cond_wait *next;
 194         wait_queue_head_t q;
 195         wait_queue_t wait;
 196         unsigned int data;
 197 };
 198 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 199 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 200 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 201 static void flush_cond_wait(struct cond_wait **head);
 202
 203 /*
 204  * DMA buffer descriptor and access macros
 205  */
 206 struct slgt_desc
 207 {
 208         __le16 count;
 209         __le16 status;
 210         __le32 pbuf;  /* physical address of data buffer */
 211         __le32 next;  /* physical address of next descriptor */
 212
 213         /* driver book keeping */
 214         char *buf;          /* virtual  address of data buffer */
 215         unsigned int pdesc; /* physical address of this descriptor */
 216         dma_addr_t buf_dma_addr;
 217 };
 218
 219 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 220 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 221 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 222 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 223 #define desc_count(a)      (le16_to_cpu((a).count))
 224 #define desc_status(a)     (le16_to_cpu((a).status))
 225 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 226 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 227 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 228 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 229 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 230
 231 struct _input_signal_events {
 232         int ri_up;
 233         int ri_down;
 234         int dsr_up;
 235         int dsr_down;
 236         int dcd_up;
 237         int dcd_down;
 238         int cts_up;
 239         int cts_down;
 240 };
 241
 242 /*
 243  * device instance data structure
 244  */
 245 struct slgt_info {
 246         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 247         struct tty_port port;
 248
 249         struct slgt_info *next_device;  /* device list link */
 250
 251         int magic;
 252
 253         char device_name[25];
 254         struct pci_dev *pdev;
 255
 256         int port_count;  /* count of ports on adapter */
 257         int adapter_num; /* adapter instance number */
 258         int port_num;    /* port instance number */
 259
 260         /* array of pointers to port contexts on this adapter */
 261         struct slgt_info *port_array[SLGT_MAX_PORTS];
 262
 263         int                     line;           /* tty line instance number */
 264
 265         struct mgsl_icount      icount;
 266
 267         int                     timeout;
 268         int                     x_char;         /* xon/xoff character */
 269         unsigned int            read_status_mask;
 270         unsigned int            ignore_status_mask;
 271
 272         wait_queue_head_t       status_event_wait_q;
 273         wait_queue_head_t       event_wait_q;
 274         struct timer_list       tx_timer;
 275         struct timer_list       rx_timer;
 276
 277         unsigned int            gpio_present;
 278         struct cond_wait        *gpio_wait_q;
 279
 280         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 281
 282         struct work_struct task;
 283         u32 pending_bh;
 284         bool bh_requested;
 285         bool bh_running;
 286
 287         int isr_overflow;
 288         bool irq_requested;     /* true if IRQ requested */
 289         bool irq_occurred;      /* for diagnostics use */
 290
 291         /* device configuration */
 292
 293         unsigned int bus_type;
 294         unsigned int irq_level;
 295         unsigned long irq_flags;
 296
 297         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 298         u32 phys_reg_addr;
 299         bool reg_addr_requested;
 300
 301         MGSL_PARAMS params;       /* communications parameters */
 302         u32 idle_mode;
 303         u32 max_frame_size;       /* as set by device config */
 304
 305         unsigned int raw_rx_size;
 306         unsigned int if_mode;
 307
 308         /* device status */
 309
 310         bool rx_enabled;
 311         bool rx_restart;
 312
 313         bool tx_enabled;
 314         bool tx_active;
 315
 316         unsigned char signals;    /* serial signal states */
 317         int init_error;  /* initialization error */
 318
 319         unsigned char *tx_buf;
 320         int tx_count;
 321
 322         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 323         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 324         bool drop_rts_on_tx_done;
 325         struct  _input_signal_events    input_signal_events;
 326
 327         int dcd_chkcount;       /* check counts to prevent */
 328         int cts_chkcount;       /* too many IRQs if a signal */
 329         int dsr_chkcount;       /* is floating */
 330         int ri_chkcount;
 331
 332         char *bufs;             /* virtual address of DMA buffer lists */
 333         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 334
 335         unsigned int rbuf_count;
 336         struct slgt_desc *rbufs;
 337         unsigned int rbuf_current;
 338         unsigned int rbuf_index;
 339
 340         unsigned int tbuf_count;
 341         struct slgt_desc *tbufs;
 342         unsigned int tbuf_current;
 343         unsigned int tbuf_start;
 344
 345         unsigned char *tmp_rbuf;
 346         unsigned int tmp_rbuf_count;
 347
 348         /* SPPP/Cisco HDLC device parts */
 349
 350         int netcount;
 351         int dosyncppp;
 352         spinlock_t netlock;
 353 #if SYNCLINK_GENERIC_HDLC
 354         struct net_device *netdev;
 355 #endif
 356
 357 };
 358
 359 static MGSL_PARAMS default_params = {
 360         .mode            = MGSL_MODE_HDLC,
 361         .loopback        = 0,
 362         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 363         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 364         .clock_speed     = 0,
 365         .addr_filter     = 0xff,
 366         .crc_type        = HDLC_CRC_16_CCITT,
 367         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 368         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 369         .data_rate       = 9600,
 370         .data_bits       = 8,
 371         .stop_bits       = 1,
 372         .parity          = ASYNC_PARITY_NONE
 373 };
 374
 375
 376 #define BH_RECEIVE  1
 377 #define BH_TRANSMIT 2
 378 #define BH_STATUS   4
 379 #define IO_PIN_SHUTDOWN_LIMIT 100
 380
 381 #define DMABUFSIZE 256
 382 #define DESC_LIST_SIZE 4096
 383
 384 #define MASK_PARITY  BIT1
 385 #define MASK_FRAMING BIT0
 386 #define MASK_BREAK   BIT14
 387 #define MASK_OVERRUN BIT4
 388
 389 #define GSR   0x00 /* global status */
 390 #define JCR   0x04 /* JTAG control */
 391 #define IODR  0x08 /* GPIO direction */
 392 #define IOER  0x0c /* GPIO interrupt enable */
 393 #define IOVR  0x10 /* GPIO value */
 394 #define IOSR  0x14 /* GPIO interrupt status */
 395 #define TDR   0x80 /* tx data */
 396 #define RDR   0x80 /* rx data */
 397 #define TCR   0x82 /* tx control */
 398 #define TIR   0x84 /* tx idle */
 399 #define TPR   0x85 /* tx preamble */
 400 #define RCR   0x86 /* rx control */
 401 #define VCR   0x88 /* V.24 control */
 402 #define CCR   0x89 /* clock control */
 403 #define BDR   0x8a /* baud divisor */
 404 #define SCR   0x8c /* serial control */
 405 #define SSR   0x8e /* serial status */
 406 #define RDCSR 0x90 /* rx DMA control/status */
 407 #define TDCSR 0x94 /* tx DMA control/status */
 408 #define RDDAR 0x98 /* rx DMA descriptor address */
 409 #define TDDAR 0x9c /* tx DMA descriptor address */
 410
 411 #define RXIDLE      BIT14
 412 #define RXBREAK     BIT14
 413 #define IRQ_TXDATA  BIT13
 414 #define IRQ_TXIDLE  BIT12
 415 #define IRQ_TXUNDER BIT11 /* HDLC */
 416 #define IRQ_RXDATA  BIT10
 417 #define IRQ_RXIDLE  BIT9  /* HDLC */
 418 #define IRQ_RXBREAK BIT9  /* async */
 419 #define IRQ_RXOVER  BIT8
 420 #define IRQ_DSR     BIT7
 421 #define IRQ_CTS     BIT6
 422 #define IRQ_DCD     BIT5
 423 #define IRQ_RI      BIT4
 424 #define IRQ_ALL     0x3ff0
 425 #define IRQ_MASTER  BIT0
 426
 427 #define slgt_irq_on(info, mask) \
 428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 429 #define slgt_irq_off(info, mask) \
 430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 431
 432 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 437 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 438
 439 static void  msc_set_vcr(struct slgt_info *info);
 440
 441 static int  startup(struct slgt_info *info);
 442 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 443 static void shutdown(struct slgt_info *info);
 444 static void program_hw(struct slgt_info *info);
 445 static void change_params(struct slgt_info *info);
 446
 447 static int  register_test(struct slgt_info *info);
 448 static int  irq_test(struct slgt_info *info);
 449 static int  loopback_test(struct slgt_info *info);
 450 static int  adapter_test(struct slgt_info *info);
 451
 452 static void reset_adapter(struct slgt_info *info);
 453 static void reset_port(struct slgt_info *info);
 454 static void async_mode(struct slgt_info *info);
 455 static void sync_mode(struct slgt_info *info);
 456
 457 static void rx_stop(struct slgt_info *info);
 458 static void rx_start(struct slgt_info *info);
 459 static void reset_rbufs(struct slgt_info *info);
 460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 461 static void rdma_reset(struct slgt_info *info);
 462 static bool rx_get_frame(struct slgt_info *info);
 463 static bool rx_get_buf(struct slgt_info *info);
 464
 465 static void tx_start(struct slgt_info *info);
 466 static void tx_stop(struct slgt_info *info);
 467 static void tx_set_idle(struct slgt_info *info);
 468 static unsigned int free_tbuf_count(struct slgt_info *info);
 469 static void reset_tbufs(struct slgt_info *info);
 470 static void tdma_reset(struct slgt_info *info);
 471 static void tdma_start(struct slgt_info *info);
 472 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 473
 474 static void get_signals(struct slgt_info *info);
 475 static void set_signals(struct slgt_info *info);
 476 static void enable_loopback(struct slgt_info *info);
 477 static void set_rate(struct slgt_info *info, u32 data_rate);
 478
 479 static int  bh_action(struct slgt_info *info);
 480 static void bh_handler(struct work_struct *work);
 481 static void bh_transmit(struct slgt_info *info);
 482 static void isr_serial(struct slgt_info *info);
 483 static void isr_rdma(struct slgt_info *info);
 484 static void isr_txeom(struct slgt_info *info, unsigned short status);
 485 static void isr_tdma(struct slgt_info *info);
 486
 487 static int  alloc_dma_bufs(struct slgt_info *info);
 488 static void free_dma_bufs(struct slgt_info *info);
 489 static int  alloc_desc(struct slgt_info *info);
 490 static void free_desc(struct slgt_info *info);
 491 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 493
 494 static int  alloc_tmp_rbuf(struct slgt_info *info);
 495 static void free_tmp_rbuf(struct slgt_info *info);
 496
 497 static void tx_timeout(unsigned long context);
 498 static void rx_timeout(unsigned long context);
 499
 500 /*
 501  * ioctl handlers
 502  */
 503 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 504 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 506 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 507 static int  set_txidle(struct slgt_info *info, int idle_mode);
 508 static int  tx_enable(struct slgt_info *info, int enable);
 509 static int  tx_abort(struct slgt_info *info);
 510 static int  rx_enable(struct slgt_info *info, int enable);
 511 static int  modem_input_wait(struct slgt_info *info,int arg);
 512 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 513 static int  tiocmget(struct tty_struct *tty, struct file *file);
 514 static int  tiocmset(struct tty_struct *tty, struct file *file,
 515                      unsigned int set, unsigned int clear);
 516 static int set_break(struct tty_struct *tty, int break_state);
 517 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 518 static int  set_interface(struct slgt_info *info, int if_mode);
 519 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522
 523 /*
 524  * driver functions
 525  */
 526 static void add_device(struct slgt_info *info);
 527 static void device_init(int adapter_num, struct pci_dev *pdev);
 528 static int  claim_resources(struct slgt_info *info);
 529 static void release_resources(struct slgt_info *info);
 530
 531 /*
 532  * DEBUG OUTPUT CODE
 533  */
 534 #ifndef DBGINFO
 535 #define DBGINFO(fmt)
 536 #endif
 537 #ifndef DBGERR
 538 #define DBGERR(fmt)
 539 #endif
 540 #ifndef DBGBH
 541 #define DBGBH(fmt)
 542 #endif
 543 #ifndef DBGISR
 544 #define DBGISR(fmt)
 545 #endif
 546
 547 #ifdef DBGDATA
 548 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 549 {
 550         int i;
 551         int linecount;
 552         printk("%s %s data:\n",info->device_name, label);
 553         while(count) {
 554                 linecount = (count > 16) ? 16 : count;
 555                 for(i=0; i < linecount; i++)
 556                         printk("%02X ",(unsigned char)data[i]);
 557                 for(;i<17;i++)
 558                         printk("   ");
 559                 for(i=0;i<linecount;i++) {
 560                         if (data[i]>=040 && data[i]<=0176)
 561                                 printk("%c",data[i]);
 562                         else
 563                                 printk(".");
 564                 }
 565                 printk("\n");
 566                 data  += linecount;
 567                 count -= linecount;
 568         }
 569 }
 570 #else
 571 #define DBGDATA(info, buf, size, label)
 572 #endif
 573
 574 #ifdef DBGTBUF
 575 static void dump_tbufs(struct slgt_info *info)
 576 {
 577         int i;
 578         printk("tbuf_current=%d\n", info->tbuf_current);
 579         for (i=0 ; i < info->tbuf_count ; i++) {
 580                 printk("%d: count=%04X status=%04X\n",
 581                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 582         }
 583 }
 584 #else
 585 #define DBGTBUF(info)
 586 #endif
 587
 588 #ifdef DBGRBUF
 589 static void dump_rbufs(struct slgt_info *info)
 590 {
 591         int i;
 592         printk("rbuf_current=%d\n", info->rbuf_current);
 593         for (i=0 ; i < info->rbuf_count ; i++) {
 594                 printk("%d: count=%04X status=%04X\n",
 595                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 596         }
 597 }
 598 #else
 599 #define DBGRBUF(info)
 600 #endif
 601
 602 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 603 {
 604 #ifdef SANITY_CHECK
 605         if (!info) {
 606                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 607                 return 1;
 608         }
 609         if (info->magic != MGSL_MAGIC) {
 610                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 611                 return 1;
 612         }
 613 #else
 614         if (!info)
 615                 return 1;
 616 #endif
 617         return 0;
 618 }
 619
 620 /**
 621  * line discipline callback wrappers
 622  *
 623  * The wrappers maintain line discipline references
 624  * while calling into the line discipline.
 625  *
 626  * ldisc_receive_buf  - pass receive data to line discipline
 627  */
 628 static void ldisc_receive_buf(struct tty_struct *tty,
 629                               const __u8 *data, char *flags, int count)
 630 {
 631         struct tty_ldisc *ld;
 632         if (!tty)
 633                 return;
 634         ld = tty_ldisc_ref(tty);
 635         if (ld) {
 636                 if (ld->ops->receive_buf)
 637                         ld->ops->receive_buf(tty, data, flags, count);
 638                 tty_ldisc_deref(ld);
 639         }
 640 }
 641
 642 /* tty callbacks */
 643
 644 static int open(struct tty_struct *tty, struct file *filp)
 645 {
 646         struct slgt_info *info;
 647         int retval, line;
 648         unsigned long flags;
 649
 650         line = tty->index;
 651         if ((line < 0) || (line >= slgt_device_count)) {
 652                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 653                 return -ENODEV;
 654         }
 655
 656         info = slgt_device_list;
 657         while(info && info->line != line)
 658                 info = info->next_device;
 659         if (sanity_check(info, tty->name, "open"))
 660                 return -ENODEV;
 661         if (info->init_error) {
 662                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 663                 return -ENODEV;
 664         }
 665
 666         tty->driver_data = info;
 667         info->port.tty = tty;
 668
 669         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 670
 671         /* If port is closing, signal caller to try again */
 672         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 673                 if (info->port.flags & ASYNC_CLOSING)
 674                         interruptible_sleep_on(&info->port.close_wait);
 675                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 676                         -EAGAIN : -ERESTARTSYS);
 677                 goto cleanup;
 678         }
 679
 680         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 681
 682         spin_lock_irqsave(&info->netlock, flags);
 683         if (info->netcount) {
 684                 retval = -EBUSY;
 685                 spin_unlock_irqrestore(&info->netlock, flags);
 686                 goto cleanup;
 687         }
 688         info->port.count++;
 689         spin_unlock_irqrestore(&info->netlock, flags);
 690
 691         if (info->port.count == 1) {
 692                 /* 1st open on this device, init hardware */
 693                 retval = startup(info);
 694                 if (retval < 0)
 695                         goto cleanup;
 696         }
 697
 698         retval = block_til_ready(tty, filp, info);
 699         if (retval) {
 700                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 701                 goto cleanup;
 702         }
 703
 704         retval = 0;
 705
 706 cleanup:
 707         if (retval) {
 708                 if (tty->count == 1)
 709                         info->port.tty = NULL; /* tty layer will release tty struct */
 710                 if(info->port.count)
 711                         info->port.count--;
 712         }
 713
 714         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 715         return retval;
 716 }
 717
 718 static void close(struct tty_struct *tty, struct file *filp)
 719 {
 720         struct slgt_info *info = tty->driver_data;
 721
 722         if (sanity_check(info, tty->name, "close"))
 723                 return;
 724         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 725
 726         if (!info->port.count)
 727                 return;
 728
 729         if (tty_hung_up_p(filp))
 730                 goto cleanup;
 731
 732         if ((tty->count == 1) && (info->port.count != 1)) {
 733                 /*
 734                  * tty->count is 1 and the tty structure will be freed.
 735                  * info->port.count should be one in this case.
 736                  * if it's not, correct it so that the port is shutdown.
 737                  */
 738                 DBGERR(("%s close: bad refcount; tty->count=1, "
 739                        "info->port.count=%d\n", info->device_name, info->port.count));
 740                 info->port.count = 1;
 741         }
 742
 743         info->port.count--;
 744
 745         /* if at least one open remaining, leave hardware active */
 746         if (info->port.count)
 747                 goto cleanup;
 748
 749         info->port.flags |= ASYNC_CLOSING;
 750
 751         /* set tty->closing to notify line discipline to
 752          * only process XON/XOFF characters. Only the N_TTY
 753          * discipline appears to use this (ppp does not).
 754          */
 755         tty->closing = 1;
 756
 757         /* wait for transmit data to clear all layers */
 758
 759         if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 760                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 761                 tty_wait_until_sent(tty, info->port.closing_wait);
 762         }
 763
 764         if (info->port.flags & ASYNC_INITIALIZED)
 765                 wait_until_sent(tty, info->timeout);
 766         flush_buffer(tty);
 767         tty_ldisc_flush(tty);
 768
 769         shutdown(info);
 770
 771         tty->closing = 0;
 772         info->port.tty = NULL;
 773
 774         if (info->port.blocked_open) {
 775                 if (info->port.close_delay) {
 776                         msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
 777                 }
 778                 wake_up_interruptible(&info->port.open_wait);
 779         }
 780
 781         info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 782
 783         wake_up_interruptible(&info->port.close_wait);
 784
 785 cleanup:
 786         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 787 }
 788
 789 static void hangup(struct tty_struct *tty)
 790 {
 791         struct slgt_info *info = tty->driver_data;
 792
 793         if (sanity_check(info, tty->name, "hangup"))
 794                 return;
 795         DBGINFO(("%s hangup\n", info->device_name));
 796
 797         flush_buffer(tty);
 798         shutdown(info);
 799
 800         info->port.count = 0;
 801         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 802         info->port.tty = NULL;
 803
 804         wake_up_interruptible(&info->port.open_wait);
 805 }
 806
 807 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 808 {
 809         struct slgt_info *info = tty->driver_data;
 810         unsigned long flags;
 811
 812         DBGINFO(("%s set_termios\n", tty->driver->name));
 813
 814         change_params(info);
 815
 816         /* Handle transition to B0 status */
 817         if (old_termios->c_cflag & CBAUD &&
 818             !(tty->termios->c_cflag & CBAUD)) {
 819                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 820                 spin_lock_irqsave(&info->lock,flags);
 821                 set_signals(info);
 822                 spin_unlock_irqrestore(&info->lock,flags);
 823         }
 824
 825         /* Handle transition away from B0 status */
 826         if (!(old_termios->c_cflag & CBAUD) &&
 827             tty->termios->c_cflag & CBAUD) {
 828                 info->signals |= SerialSignal_DTR;
 829                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 830                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 831                         info->signals |= SerialSignal_RTS;
 832                 }
 833                 spin_lock_irqsave(&info->lock,flags);
 834                 set_signals(info);
 835                 spin_unlock_irqrestore(&info->lock,flags);
 836         }
 837
 838         /* Handle turning off CRTSCTS */
 839         if (old_termios->c_cflag & CRTSCTS &&
 840             !(tty->termios->c_cflag & CRTSCTS)) {
 841                 tty->hw_stopped = 0;
 842                 tx_release(tty);
 843         }
 844 }
 845
 846 static int write(struct tty_struct *tty,
 847                  const unsigned char *buf, int count)
 848 {
 849         int ret = 0;
 850         struct slgt_info *info = tty->driver_data;
 851         unsigned long flags;
 852         unsigned int bufs_needed;
 853
 854         if (sanity_check(info, tty->name, "write"))
 855                 goto cleanup;
 856         DBGINFO(("%s write count=%d\n", info->device_name, count));
 857
 858         if (!info->tx_buf)
 859                 goto cleanup;
 860
 861         if (count > info->max_frame_size) {
 862                 ret = -EIO;
 863                 goto cleanup;
 864         }
 865
 866         if (!count)
 867                 goto cleanup;
 868
 869         if (!info->tx_active && info->tx_count) {
 870                 /* send accumulated data from send_char() */
 871                 tx_load(info, info->tx_buf, info->tx_count);
 872                 goto start;
 873         }
 874         bufs_needed = (count/DMABUFSIZE);
 875         if (count % DMABUFSIZE)
 876                 ++bufs_needed;
 877         if (bufs_needed > free_tbuf_count(info))
 878                 goto cleanup;
 879
 880         ret = info->tx_count = count;
 881         tx_load(info, buf, count);
 882         goto start;
 883
 884 start:
 885         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 886                 spin_lock_irqsave(&info->lock,flags);
 887                 if (!info->tx_active)
 888                         tx_start(info);
 889                 else
 890                         tdma_start(info);
 891                 spin_unlock_irqrestore(&info->lock,flags);
 892         }
 893
 894 cleanup:
 895         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 896         return ret;
 897 }
 898
 899 static int put_char(struct tty_struct *tty, unsigned char ch)
 900 {
 901         struct slgt_info *info = tty->driver_data;
 902         unsigned long flags;
 903         int ret = 0;
 904
 905         if (sanity_check(info, tty->name, "put_char"))
 906                 return 0;
 907         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 908         if (!info->tx_buf)
 909                 return 0;
 910         spin_lock_irqsave(&info->lock,flags);
 911         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 912                 info->tx_buf[info->tx_count++] = ch;
 913                 ret = 1;
 914         }
 915         spin_unlock_irqrestore(&info->lock,flags);
 916         return ret;
 917 }
 918
 919 static void send_xchar(struct tty_struct *tty, char ch)
 920 {
 921         struct slgt_info *info = tty->driver_data;
 922         unsigned long flags;
 923
 924         if (sanity_check(info, tty->name, "send_xchar"))
 925                 return;
 926         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 927         info->x_char = ch;
 928         if (ch) {
 929                 spin_lock_irqsave(&info->lock,flags);
 930                 if (!info->tx_enabled)
 931                         tx_start(info);
 932                 spin_unlock_irqrestore(&info->lock,flags);
 933         }
 934 }
 935
 936 static void wait_until_sent(struct tty_struct *tty, int timeout)
 937 {
 938         struct slgt_info *info = tty->driver_data;
 939         unsigned long orig_jiffies, char_time;
 940
 941         if (!info )
 942                 return;
 943         if (sanity_check(info, tty->name, "wait_until_sent"))
 944                 return;
 945         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 946         if (!(info->port.flags & ASYNC_INITIALIZED))
 947                 goto exit;
 948
 949         orig_jiffies = jiffies;
 950
 951         /* Set check interval to 1/5 of estimated time to
 952          * send a character, and make it at least 1. The check
 953          * interval should also be less than the timeout.
 954          * Note: use tight timings here to satisfy the NIST-PCTS.
 955          */
 956
 957         lock_kernel();
 958
 959         if (info->params.data_rate) {
 960                 char_time = info->timeout/(32 * 5);
 961                 if (!char_time)
 962                         char_time++;
 963         } else
 964                 char_time = 1;
 965
 966         if (timeout)
 967                 char_time = min_t(unsigned long, char_time, timeout);
 968
 969         while (info->tx_active) {
 970                 msleep_interruptible(jiffies_to_msecs(char_time));
 971                 if (signal_pending(current))
 972                         break;
 973                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 974                         break;
 975         }
 976         unlock_kernel();
 977
 978 exit:
 979         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 980 }
 981
 982 static int write_room(struct tty_struct *tty)
 983 {
 984         struct slgt_info *info = tty->driver_data;
 985         int ret;
 986
 987         if (sanity_check(info, tty->name, "write_room"))
 988                 return 0;
 989         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 990         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 991         return ret;
 992 }
 993
 994 static void flush_chars(struct tty_struct *tty)
 995 {
 996         struct slgt_info *info = tty->driver_data;
 997         unsigned long flags;
 998
 999         if (sanity_check(info, tty->name, "flush_chars"))
1000                 return;
1001         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1002
1003         if (info->tx_count <= 0 || tty->stopped ||
1004             tty->hw_stopped || !info->tx_buf)
1005                 return;
1006
1007         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1008
1009         spin_lock_irqsave(&info->lock,flags);
1010         if (!info->tx_active && info->tx_count) {
1011                 tx_load(info, info->tx_buf,info->tx_count);
1012                 tx_start(info);
1013         }
1014         spin_unlock_irqrestore(&info->lock,flags);
1015 }
1016
1017 static void flush_buffer(struct tty_struct *tty)
1018 {
1019         struct slgt_info *info = tty->driver_data;
1020         unsigned long flags;
1021
1022         if (sanity_check(info, tty->name, "flush_buffer"))
1023                 return;
1024         DBGINFO(("%s flush_buffer\n", info->device_name));
1025
1026         spin_lock_irqsave(&info->lock,flags);
1027         if (!info->tx_active)
1028                 info->tx_count = 0;
1029         spin_unlock_irqrestore(&info->lock,flags);
1030
1031         tty_wakeup(tty);
1032 }
1033
1034 /*
1035  * throttle (stop) transmitter
1036  */
1037 static void tx_hold(struct tty_struct *tty)
1038 {
1039         struct slgt_info *info = tty->driver_data;
1040         unsigned long flags;
1041
1042         if (sanity_check(info, tty->name, "tx_hold"))
1043                 return;
1044         DBGINFO(("%s tx_hold\n", info->device_name));
1045         spin_lock_irqsave(&info->lock,flags);
1046         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1047                 tx_stop(info);
1048         spin_unlock_irqrestore(&info->lock,flags);
1049 }
1050
1051 /*
1052  * release (start) transmitter
1053  */
1054 static void tx_release(struct tty_struct *tty)
1055 {
1056         struct slgt_info *info = tty->driver_data;
1057         unsigned long flags;
1058
1059         if (sanity_check(info, tty->name, "tx_release"))
1060                 return;
1061         DBGINFO(("%s tx_release\n", info->device_name));
1062         spin_lock_irqsave(&info->lock,flags);
1063         if (!info->tx_active && info->tx_count) {
1064                 tx_load(info, info->tx_buf, info->tx_count);
1065                 tx_start(info);
1066         }
1067         spin_unlock_irqrestore(&info->lock,flags);
1068 }
1069
1070 /*
1071  * Service an IOCTL request
1072  *
1073  * Arguments
1074  *
1075  *      tty     pointer to tty instance data
1076  *      file    pointer to associated file object for device
1077  *      cmd     IOCTL command code
1078  *      arg     command argument/context
1079  *
1080  * Return 0 if success, otherwise error code
1081  */
1082 static int ioctl(struct tty_struct *tty, struct file *file,
1083                  unsigned int cmd, unsigned long arg)
1084 {
1085         struct slgt_info *info = tty->driver_data;
1086         struct mgsl_icount cnow;        /* kernel counter temps */
1087         struct serial_icounter_struct __user *p_cuser;  /* user space */
1088         unsigned long flags;
1089         void __user *argp = (void __user *)arg;
1090         int ret;
1091
1092         if (sanity_check(info, tty->name, "ioctl"))
1093                 return -ENODEV;
1094         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1095
1096         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1097             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1098                 if (tty->flags & (1 << TTY_IO_ERROR))
1099                     return -EIO;
1100         }
1101
1102         lock_kernel();
1103
1104         switch (cmd) {
1105         case MGSL_IOCGPARAMS:
1106                 ret = get_params(info, argp);
1107                 break;
1108         case MGSL_IOCSPARAMS:
1109                 ret = set_params(info, argp);
1110                 break;
1111         case MGSL_IOCGTXIDLE:
1112                 ret = get_txidle(info, argp);
1113                 break;
1114         case MGSL_IOCSTXIDLE:
1115                 ret = set_txidle(info, (int)arg);
1116                 break;
1117         case MGSL_IOCTXENABLE:
1118                 ret = tx_enable(info, (int)arg);
1119                 break;
1120         case MGSL_IOCRXENABLE:
1121                 ret = rx_enable(info, (int)arg);
1122                 break;
1123         case MGSL_IOCTXABORT:
1124                 ret = tx_abort(info);
1125                 break;
1126         case MGSL_IOCGSTATS:
1127                 ret = get_stats(info, argp);
1128                 break;
1129         case MGSL_IOCWAITEVENT:
1130                 ret = wait_mgsl_event(info, argp);
1131                 break;
1132         case TIOCMIWAIT:
1133                 ret = modem_input_wait(info,(int)arg);
1134                 break;
1135         case MGSL_IOCGIF:
1136                 ret = get_interface(info, argp);
1137                 break;
1138         case MGSL_IOCSIF:
1139                 ret = set_interface(info,(int)arg);
1140                 break;
1141         case MGSL_IOCSGPIO:
1142                 ret = set_gpio(info, argp);
1143                 break;
1144         case MGSL_IOCGGPIO:
1145                 ret = get_gpio(info, argp);
1146                 break;
1147         case MGSL_IOCWAITGPIO:
1148                 ret = wait_gpio(info, argp);
1149                 break;
1150         case TIOCGICOUNT:
1151                 spin_lock_irqsave(&info->lock,flags);
1152                 cnow = info->icount;
1153                 spin_unlock_irqrestore(&info->lock,flags);
1154                 p_cuser = argp;
1155                 if (put_user(cnow.cts, &p_cuser->cts) ||
1156                     put_user(cnow.dsr, &p_cuser->dsr) ||
1157                     put_user(cnow.rng, &p_cuser->rng) ||
1158                     put_user(cnow.dcd, &p_cuser->dcd) ||
1159                     put_user(cnow.rx, &p_cuser->rx) ||
1160                     put_user(cnow.tx, &p_cuser->tx) ||
1161                     put_user(cnow.frame, &p_cuser->frame) ||
1162                     put_user(cnow.overrun, &p_cuser->overrun) ||
1163                     put_user(cnow.parity, &p_cuser->parity) ||
1164                     put_user(cnow.brk, &p_cuser->brk) ||
1165                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1166                         ret = -EFAULT;
1167                 ret = 0;
1168                 break;
1169         default:
1170                 ret = -ENOIOCTLCMD;
1171         }
1172         unlock_kernel();
1173         return ret;
1174 }
1175
1176 /*
1177  * support for 32 bit ioctl calls on 64 bit systems
1178  */
1179 #ifdef CONFIG_COMPAT
1180 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1181 {
1182         struct MGSL_PARAMS32 tmp_params;
1183
1184         DBGINFO(("%s get_params32\n", info->device_name));
1185         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1186         tmp_params.loopback        = info->params.loopback;
1187         tmp_params.flags           = info->params.flags;
1188         tmp_params.encoding        = info->params.encoding;
1189         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1190         tmp_params.addr_filter     = info->params.addr_filter;
1191         tmp_params.crc_type        = info->params.crc_type;
1192         tmp_params.preamble_length = info->params.preamble_length;
1193         tmp_params.preamble        = info->params.preamble;
1194         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1195         tmp_params.data_bits       = info->params.data_bits;
1196         tmp_params.stop_bits       = info->params.stop_bits;
1197         tmp_params.parity          = info->params.parity;
1198         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1199                 return -EFAULT;
1200         return 0;
1201 }
1202
1203 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1204 {
1205         struct MGSL_PARAMS32 tmp_params;
1206
1207         DBGINFO(("%s set_params32\n", info->device_name));
1208         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1209                 return -EFAULT;
1210
1211         spin_lock(&info->lock);
1212         info->params.mode            = tmp_params.mode;
1213         info->params.loopback        = tmp_params.loopback;
1214         info->params.flags           = tmp_params.flags;
1215         info->params.encoding        = tmp_params.encoding;
1216         info->params.clock_speed     = tmp_params.clock_speed;
1217         info->params.addr_filter     = tmp_params.addr_filter;
1218         info->params.crc_type        = tmp_params.crc_type;
1219         info->params.preamble_length = tmp_params.preamble_length;
1220         info->params.preamble        = tmp_params.preamble;
1221         info->params.data_rate       = tmp_params.data_rate;
1222         info->params.data_bits       = tmp_params.data_bits;
1223         info->params.stop_bits       = tmp_params.stop_bits;
1224         info->params.parity          = tmp_params.parity;
1225         spin_unlock(&info->lock);
1226
1227         change_params(info);
1228
1229         return 0;
1230 }
1231
1232 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1233                          unsigned int cmd, unsigned long arg)
1234 {
1235         struct slgt_info *info = tty->driver_data;
1236         int rc = -ENOIOCTLCMD;
1237
1238         if (sanity_check(info, tty->name, "compat_ioctl"))
1239                 return -ENODEV;
1240         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1241
1242         switch (cmd) {
1243
1244         case MGSL_IOCSPARAMS32:
1245                 rc = set_params32(info, compat_ptr(arg));
1246                 break;
1247
1248         case MGSL_IOCGPARAMS32:
1249                 rc = get_params32(info, compat_ptr(arg));
1250                 break;
1251
1252         case MGSL_IOCGPARAMS:
1253         case MGSL_IOCSPARAMS:
1254         case MGSL_IOCGTXIDLE:
1255         case MGSL_IOCGSTATS:
1256         case MGSL_IOCWAITEVENT:
1257         case MGSL_IOCGIF:
1258         case MGSL_IOCSGPIO:
1259         case MGSL_IOCGGPIO:
1260         case MGSL_IOCWAITGPIO:
1261         case TIOCGICOUNT:
1262                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1263                 break;
1264
1265         case MGSL_IOCSTXIDLE:
1266         case MGSL_IOCTXENABLE:
1267         case MGSL_IOCRXENABLE:
1268         case MGSL_IOCTXABORT:
1269         case TIOCMIWAIT:
1270         case MGSL_IOCSIF:
1271                 rc = ioctl(tty, file, cmd, arg);
1272                 break;
1273         }
1274
1275         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1276         return rc;
1277 }
1278 #else
1279 #define slgt_compat_ioctl NULL
1280 #endif /* ifdef CONFIG_COMPAT */
1281
1282 /*
1283  * proc fs support
1284  */
1285 static inline int line_info(char *buf, struct slgt_info *info)
1286 {
1287         char stat_buf[30];
1288         int ret;
1289         unsigned long flags;
1290
1291         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1292                       info->device_name, info->phys_reg_addr,
1293                       info->irq_level, info->max_frame_size);
1294
1295         /* output current serial signal states */
1296         spin_lock_irqsave(&info->lock,flags);
1297         get_signals(info);
1298         spin_unlock_irqrestore(&info->lock,flags);
1299
1300         stat_buf[0] = 0;
1301         stat_buf[1] = 0;
1302         if (info->signals & SerialSignal_RTS)
1303                 strcat(stat_buf, "|RTS");
1304         if (info->signals & SerialSignal_CTS)
1305                 strcat(stat_buf, "|CTS");
1306         if (info->signals & SerialSignal_DTR)
1307                 strcat(stat_buf, "|DTR");
1308         if (info->signals & SerialSignal_DSR)
1309                 strcat(stat_buf, "|DSR");
1310         if (info->signals & SerialSignal_DCD)
1311                 strcat(stat_buf, "|CD");
1312         if (info->signals & SerialSignal_RI)
1313                 strcat(stat_buf, "|RI");
1314
1315         if (info->params.mode != MGSL_MODE_ASYNC) {
1316                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1317                                info->icount.txok, info->icount.rxok);
1318                 if (info->icount.txunder)
1319                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1320                 if (info->icount.txabort)
1321                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1322                 if (info->icount.rxshort)
1323                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1324                 if (info->icount.rxlong)
1325                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1326                 if (info->icount.rxover)
1327                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1328                 if (info->icount.rxcrc)
1329                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1330         } else {
1331                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1332                                info->icount.tx, info->icount.rx);
1333                 if (info->icount.frame)
1334                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1335                 if (info->icount.parity)
1336                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1337                 if (info->icount.brk)
1338                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1339                 if (info->icount.overrun)
1340                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1341         }
1342
1343         /* Append serial signal status to end */
1344         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1345
1346         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1347                        info->tx_active,info->bh_requested,info->bh_running,
1348                        info->pending_bh);
1349
1350         return ret;
1351 }
1352
1353 /* Called to print information about devices
1354  */
1355 static int read_proc(char *page, char **start, off_t off, int count,
1356                      int *eof, void *data)
1357 {
1358         int len = 0, l;
1359         off_t   begin = 0;
1360         struct slgt_info *info;
1361
1362         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1363
1364         info = slgt_device_list;
1365         while( info ) {
1366                 l = line_info(page + len, info);
1367                 len += l;
1368                 if (len+begin > off+count)
1369                         goto done;
1370                 if (len+begin < off) {
1371                         begin += len;
1372                         len = 0;
1373                 }
1374                 info = info->next_device;
1375         }
1376
1377         *eof = 1;
1378 done:
1379         if (off >= len+begin)
1380                 return 0;
1381         *start = page + (off-begin);
1382         return ((count < begin+len-off) ? count : begin+len-off);
1383 }
1384
1385 /*
1386  * return count of bytes in transmit buffer
1387  */
1388 static int chars_in_buffer(struct tty_struct *tty)
1389 {
1390         struct slgt_info *info = tty->driver_data;
1391         if (sanity_check(info, tty->name, "chars_in_buffer"))
1392                 return 0;
1393         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1394         return info->tx_count;
1395 }
1396
1397 /*
1398  * signal remote device to throttle send data (our receive data)
1399  */
1400 static void throttle(struct tty_struct * tty)
1401 {
1402         struct slgt_info *info = tty->driver_data;
1403         unsigned long flags;
1404
1405         if (sanity_check(info, tty->name, "throttle"))
1406                 return;
1407         DBGINFO(("%s throttle\n", info->device_name));
1408         if (I_IXOFF(tty))
1409                 send_xchar(tty, STOP_CHAR(tty));
1410         if (tty->termios->c_cflag & CRTSCTS) {
1411                 spin_lock_irqsave(&info->lock,flags);
1412                 info->signals &= ~SerialSignal_RTS;
1413                 set_signals(info);
1414                 spin_unlock_irqrestore(&info->lock,flags);
1415         }
1416 }
1417
1418 /*
1419  * signal remote device to stop throttling send data (our receive data)
1420  */
1421 static void unthrottle(struct tty_struct * tty)
1422 {
1423         struct slgt_info *info = tty->driver_data;
1424         unsigned long flags;
1425
1426         if (sanity_check(info, tty->name, "unthrottle"))
1427                 return;
1428         DBGINFO(("%s unthrottle\n", info->device_name));
1429         if (I_IXOFF(tty)) {
1430                 if (info->x_char)
1431                         info->x_char = 0;
1432                 else
1433                         send_xchar(tty, START_CHAR(tty));
1434         }
1435         if (tty->termios->c_cflag & CRTSCTS) {
1436                 spin_lock_irqsave(&info->lock,flags);
1437                 info->signals |= SerialSignal_RTS;
1438                 set_signals(info);
1439                 spin_unlock_irqrestore(&info->lock,flags);
1440         }
1441 }
1442
1443 /*
1444  * set or clear transmit break condition
1445  * break_state  -1=set break condition, 0=clear
1446  */
1447 static int set_break(struct tty_struct *tty, int break_state)
1448 {
1449         struct slgt_info *info = tty->driver_data;
1450         unsigned short value;
1451         unsigned long flags;
1452
1453         if (sanity_check(info, tty->name, "set_break"))
1454                 return -EINVAL;
1455         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1456
1457         spin_lock_irqsave(&info->lock,flags);
1458         value = rd_reg16(info, TCR);
1459         if (break_state == -1)
1460                 value |= BIT6;
1461         else
1462                 value &= ~BIT6;
1463         wr_reg16(info, TCR, value);
1464         spin_unlock_irqrestore(&info->lock,flags);
1465         return 0;
1466 }
1467
1468 #if SYNCLINK_GENERIC_HDLC
1469
1470 /**
1471  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1472  * set encoding and frame check sequence (FCS) options
1473  *
1474  * dev       pointer to network device structure
1475  * encoding  serial encoding setting
1476  * parity    FCS setting
1477  *
1478  * returns 0 if success, otherwise error code
1479  */
1480 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1481                           unsigned short parity)
1482 {
1483         struct slgt_info *info = dev_to_port(dev);
1484         unsigned char  new_encoding;
1485         unsigned short new_crctype;
1486
1487         /* return error if TTY interface open */
1488         if (info->port.count)
1489                 return -EBUSY;
1490
1491         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1492
1493         switch (encoding)
1494         {
1495         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1496         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1497         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1498         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1499         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1500         default: return -EINVAL;
1501         }
1502
1503         switch (parity)
1504         {
1505         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1506         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1507         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1508         default: return -EINVAL;
1509         }
1510
1511         info->params.encoding = new_encoding;
1512         info->params.crc_type = new_crctype;
1513
1514         /* if network interface up, reprogram hardware */
1515         if (info->netcount)
1516                 program_hw(info);
1517
1518         return 0;
1519 }
1520
1521 /**
1522  * called by generic HDLC layer to send frame
1523  *
1524  * skb  socket buffer containing HDLC frame
1525  * dev  pointer to network device structure
1526  *
1527  * returns 0 if success, otherwise error code
1528  */
1529 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1530 {
1531         struct slgt_info *info = dev_to_port(dev);
1532         unsigned long flags;
1533
1534         DBGINFO(("%s hdlc_xmit\n", dev->name));
1535
1536         /* stop sending until this frame completes */
1537         netif_stop_queue(dev);
1538
1539         /* copy data to device buffers */
1540         info->tx_count = skb->len;
1541         tx_load(info, skb->data, skb->len);
1542
1543         /* update network statistics */
1544         dev->stats.tx_packets++;
1545         dev->stats.tx_bytes += skb->len;
1546
1547         /* done with socket buffer, so free it */
1548         dev_kfree_skb(skb);
1549
1550         /* save start time for transmit timeout detection */
1551         dev->trans_start = jiffies;
1552
1553         /* start hardware transmitter if necessary */
1554         spin_lock_irqsave(&info->lock,flags);
1555         if (!info->tx_active)
1556                 tx_start(info);
1557         spin_unlock_irqrestore(&info->lock,flags);
1558
1559         return 0;
1560 }
1561
1562 /**
1563  * called by network layer when interface enabled
1564  * claim resources and initialize hardware
1565  *
1566  * dev  pointer to network device structure
1567  *
1568  * returns 0 if success, otherwise error code
1569  */
1570 static int hdlcdev_open(struct net_device *dev)
1571 {
1572         struct slgt_info *info = dev_to_port(dev);
1573         int rc;
1574         unsigned long flags;
1575
1576         if (!try_module_get(THIS_MODULE))
1577                 return -EBUSY;
1578
1579         DBGINFO(("%s hdlcdev_open\n", dev->name));
1580
1581         /* generic HDLC layer open processing */
1582         if ((rc = hdlc_open(dev)))
1583                 return rc;
1584
1585         /* arbitrate between network and tty opens */
1586         spin_lock_irqsave(&info->netlock, flags);
1587         if (info->port.count != 0 || info->netcount != 0) {
1588                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1589                 spin_unlock_irqrestore(&info->netlock, flags);
1590                 return -EBUSY;
1591         }
1592         info->netcount=1;
1593         spin_unlock_irqrestore(&info->netlock, flags);
1594
1595         /* claim resources and init adapter */
1596         if ((rc = startup(info)) != 0) {
1597                 spin_lock_irqsave(&info->netlock, flags);
1598                 info->netcount=0;
1599                 spin_unlock_irqrestore(&info->netlock, flags);
1600                 return rc;
1601         }
1602
1603         /* assert DTR and RTS, apply hardware settings */
1604         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1605         program_hw(info);
1606
1607         /* enable network layer transmit */
1608         dev->trans_start = jiffies;
1609         netif_start_queue(dev);
1610
1611         /* inform generic HDLC layer of current DCD status */
1612         spin_lock_irqsave(&info->lock, flags);
1613         get_signals(info);
1614         spin_unlock_irqrestore(&info->lock, flags);
1615         if (info->signals & SerialSignal_DCD)
1616                 netif_carrier_on(dev);
1617         else
1618                 netif_carrier_off(dev);
1619         return 0;
1620 }
1621
1622 /**
1623  * called by network layer when interface is disabled
1624  * shutdown hardware and release resources
1625  *
1626  * dev  pointer to network device structure
1627  *
1628  * returns 0 if success, otherwise error code
1629  */
1630 static int hdlcdev_close(struct net_device *dev)
1631 {
1632         struct slgt_info *info = dev_to_port(dev);
1633         unsigned long flags;
1634
1635         DBGINFO(("%s hdlcdev_close\n", dev->name));
1636
1637         netif_stop_queue(dev);
1638
1639         /* shutdown adapter and release resources */
1640         shutdown(info);
1641
1642         hdlc_close(dev);
1643
1644         spin_lock_irqsave(&info->netlock, flags);
1645         info->netcount=0;
1646         spin_unlock_irqrestore(&info->netlock, flags);
1647
1648         module_put(THIS_MODULE);
1649         return 0;
1650 }
1651
1652 /**
1653  * called by network layer to process IOCTL call to network device
1654  *
1655  * dev  pointer to network device structure
1656  * ifr  pointer to network interface request structure
1657  * cmd  IOCTL command code
1658  *
1659  * returns 0 if success, otherwise error code
1660  */
1661 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1662 {
1663         const size_t size = sizeof(sync_serial_settings);
1664         sync_serial_settings new_line;
1665         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1666         struct slgt_info *info = dev_to_port(dev);
1667         unsigned int flags;
1668
1669         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1670
1671         /* return error if TTY interface open */
1672         if (info->port.count)
1673                 return -EBUSY;
1674
1675         if (cmd != SIOCWANDEV)
1676                 return hdlc_ioctl(dev, ifr, cmd);
1677
1678         switch(ifr->ifr_settings.type) {
1679         case IF_GET_IFACE: /* return current sync_serial_settings */
1680
1681                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1682                 if (ifr->ifr_settings.size < size) {
1683                         ifr->ifr_settings.size = size; /* data size wanted */
1684                         return -ENOBUFS;
1685                 }
1686
1687                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1688                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1689                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1690                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1691
1692                 switch (flags){
1693                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1694                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1695                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1696                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1697                 default: new_line.clock_type = CLOCK_DEFAULT;
1698                 }
1699
1700                 new_line.clock_rate = info->params.clock_speed;
1701                 new_line.loopback   = info->params.loopback ? 1:0;
1702
1703                 if (copy_to_user(line, &new_line, size))
1704                         return -EFAULT;
1705                 return 0;
1706
1707         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1708
1709                 if(!capable(CAP_NET_ADMIN))
1710                         return -EPERM;
1711                 if (copy_from_user(&new_line, line, size))
1712                         return -EFAULT;
1713
1714                 switch (new_line.clock_type)
1715                 {
1716                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1717                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1718                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1719                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1720                 case CLOCK_DEFAULT:  flags = info->params.flags &
1721                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1722                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1723                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1724                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1725                 default: return -EINVAL;
1726                 }
1727
1728                 if (new_line.loopback != 0 && new_line.loopback != 1)
1729                         return -EINVAL;
1730
1731                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1732                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1733                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1734                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1735                 info->params.flags |= flags;
1736
1737                 info->params.loopback = new_line.loopback;
1738
1739                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1740                         info->params.clock_speed = new_line.clock_rate;
1741                 else
1742                         info->params.clock_speed = 0;
1743
1744                 /* if network interface up, reprogram hardware */
1745                 if (info->netcount)
1746                         program_hw(info);
1747                 return 0;
1748
1749         default:
1750                 return hdlc_ioctl(dev, ifr, cmd);
1751         }
1752 }
1753
1754 /**
1755  * called by network layer when transmit timeout is detected
1756  *
1757  * dev  pointer to network device structure
1758  */
1759 static void hdlcdev_tx_timeout(struct net_device *dev)
1760 {
1761         struct slgt_info *info = dev_to_port(dev);
1762         unsigned long flags;
1763
1764         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1765
1766         dev->stats.tx_errors++;
1767         dev->stats.tx_aborted_errors++;
1768
1769         spin_lock_irqsave(&info->lock,flags);
1770         tx_stop(info);
1771         spin_unlock_irqrestore(&info->lock,flags);
1772
1773         netif_wake_queue(dev);
1774 }
1775
1776 /**
1777  * called by device driver when transmit completes
1778  * reenable network layer transmit if stopped
1779  *
1780  * info  pointer to device instance information
1781  */
1782 static void hdlcdev_tx_done(struct slgt_info *info)
1783 {
1784         if (netif_queue_stopped(info->netdev))
1785                 netif_wake_queue(info->netdev);
1786 }
1787
1788 /**
1789  * called by device driver when frame received
1790  * pass frame to network layer
1791  *
1792  * info  pointer to device instance information
1793  * buf   pointer to buffer contianing frame data
1794  * size  count of data bytes in buf
1795  */
1796 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1797 {
1798         struct sk_buff *skb = dev_alloc_skb(size);
1799         struct net_device *dev = info->netdev;
1800
1801         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1802
1803         if (skb == NULL) {
1804                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1805                 dev->stats.rx_dropped++;
1806                 return;
1807         }
1808
1809         memcpy(skb_put(skb, size), buf, size);
1810
1811         skb->protocol = hdlc_type_trans(skb, dev);
1812
1813         dev->stats.rx_packets++;
1814         dev->stats.rx_bytes += size;
1815
1816         netif_rx(skb);
1817
1818         dev->last_rx = jiffies;
1819 }
1820
1821 /**
1822  * called by device driver when adding device instance
1823  * do generic HDLC initialization
1824  *
1825  * info  pointer to device instance information
1826  *
1827  * returns 0 if success, otherwise error code
1828  */
1829 static int hdlcdev_init(struct slgt_info *info)
1830 {
1831         int rc;
1832         struct net_device *dev;
1833         hdlc_device *hdlc;
1834
1835         /* allocate and initialize network and HDLC layer objects */
1836
1837         if (!(dev = alloc_hdlcdev(info))) {
1838                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1839                 return -ENOMEM;
1840         }
1841
1842         /* for network layer reporting purposes only */
1843         dev->mem_start = info->phys_reg_addr;
1844         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1845         dev->irq       = info->irq_level;
1846
1847         /* network layer callbacks and settings */
1848         dev->do_ioctl       = hdlcdev_ioctl;
1849         dev->open           = hdlcdev_open;
1850         dev->stop           = hdlcdev_close;
1851         dev->tx_timeout     = hdlcdev_tx_timeout;
1852         dev->watchdog_timeo = 10*HZ;
1853         dev->tx_queue_len   = 50;
1854
1855         /* generic HDLC layer callbacks and settings */
1856         hdlc         = dev_to_hdlc(dev);
1857         hdlc->attach = hdlcdev_attach;
1858         hdlc->xmit   = hdlcdev_xmit;
1859
1860         /* register objects with HDLC layer */
1861         if ((rc = register_hdlc_device(dev))) {
1862                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1863                 free_netdev(dev);
1864                 return rc;
1865         }
1866
1867         info->netdev = dev;
1868         return 0;
1869 }
1870
1871 /**
1872  * called by device driver when removing device instance
1873  * do generic HDLC cleanup
1874  *
1875  * info  pointer to device instance information
1876  */
1877 static void hdlcdev_exit(struct slgt_info *info)
1878 {
1879         unregister_hdlc_device(info->netdev);
1880         free_netdev(info->netdev);
1881         info->netdev = NULL;
1882 }
1883
1884 #endif /* ifdef CONFIG_HDLC */
1885
1886 /*
1887  * get async data from rx DMA buffers
1888  */
1889 static void rx_async(struct slgt_info *info)
1890 {
1891         struct tty_struct *tty = info->port.tty;
1892         struct mgsl_icount *icount = &info->icount;
1893         unsigned int start, end;
1894         unsigned char *p;
1895         unsigned char status;
1896         struct slgt_desc *bufs = info->rbufs;
1897         int i, count;
1898         int chars = 0;
1899         int stat;
1900         unsigned char ch;
1901
1902         start = end = info->rbuf_current;
1903
1904         while(desc_complete(bufs[end])) {
1905                 count = desc_count(bufs[end]) - info->rbuf_index;
1906                 p     = bufs[end].buf + info->rbuf_index;
1907
1908                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1909                 DBGDATA(info, p, count, "rx");
1910
1911                 for(i=0 ; i < count; i+=2, p+=2) {
1912                         ch = *p;
1913                         icount->rx++;
1914
1915                         stat = 0;
1916
1917                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1918                                 if (status & BIT1)
1919                                         icount->parity++;
1920                                 else if (status & BIT0)
1921                                         icount->frame++;
1922                                 /* discard char if tty control flags say so */
1923                                 if (status & info->ignore_status_mask)
1924                                         continue;
1925                                 if (status & BIT1)
1926                                         stat = TTY_PARITY;
1927                                 else if (status & BIT0)
1928                                         stat = TTY_FRAME;
1929                         }
1930                         if (tty) {
1931                                 tty_insert_flip_char(tty, ch, stat);
1932                                 chars++;
1933                         }
1934                 }
1935
1936                 if (i < count) {
1937                         /* receive buffer not completed */
1938                         info->rbuf_index += i;
1939                         mod_timer(&info->rx_timer, jiffies + 1);
1940                         break;
1941                 }
1942
1943                 info->rbuf_index = 0;
1944                 free_rbufs(info, end, end);
1945
1946                 if (++end == info->rbuf_count)
1947                         end = 0;
1948
1949                 /* if entire list searched then no frame available */
1950                 if (end == start)
1951                         break;
1952         }
1953
1954         if (tty && chars)
1955                 tty_flip_buffer_push(tty);
1956 }
1957
1958 /*
1959  * return next bottom half action to perform
1960  */
1961 static int bh_action(struct slgt_info *info)
1962 {
1963         unsigned long flags;
1964         int rc;
1965
1966         spin_lock_irqsave(&info->lock,flags);
1967
1968         if (info->pending_bh & BH_RECEIVE) {
1969                 info->pending_bh &= ~BH_RECEIVE;
1970                 rc = BH_RECEIVE;
1971         } else if (info->pending_bh & BH_TRANSMIT) {
1972                 info->pending_bh &= ~BH_TRANSMIT;
1973                 rc = BH_TRANSMIT;
1974         } else if (info->pending_bh & BH_STATUS) {
1975                 info->pending_bh &= ~BH_STATUS;
1976                 rc = BH_STATUS;
1977         } else {
1978                 /* Mark BH routine as complete */
1979                 info->bh_running = false;
1980                 info->bh_requested = false;
1981                 rc = 0;
1982         }
1983
1984         spin_unlock_irqrestore(&info->lock,flags);
1985
1986         return rc;
1987 }
1988
1989 /*
1990  * perform bottom half processing
1991  */
1992 static void bh_handler(struct work_struct *work)
1993 {
1994         struct slgt_info *info = container_of(work, struct slgt_info, task);
1995         int action;
1996
1997         if (!info)
1998                 return;
1999         info->bh_running = true;
2000
2001         while((action = bh_action(info))) {
2002                 switch (action) {
2003                 case BH_RECEIVE:
2004                         DBGBH(("%s bh receive\n", info->device_name));
2005                         switch(info->params.mode) {
2006                         case MGSL_MODE_ASYNC:
2007                                 rx_async(info);
2008                                 break;
2009                         case MGSL_MODE_HDLC:
2010                                 while(rx_get_frame(info));
2011                                 break;
2012                         case MGSL_MODE_RAW:
2013                         case MGSL_MODE_MONOSYNC:
2014                         case MGSL_MODE_BISYNC:
2015                                 while(rx_get_buf(info));
2016                                 break;
2017                         }
2018                         /* restart receiver if rx DMA buffers exhausted */
2019                         if (info->rx_restart)
2020                                 rx_start(info);
2021                         break;
2022                 case BH_TRANSMIT:
2023                         bh_transmit(info);
2024                         break;
2025                 case BH_STATUS:
2026                         DBGBH(("%s bh status\n", info->device_name));
2027                         info->ri_chkcount = 0;
2028                         info->dsr_chkcount = 0;
2029                         info->dcd_chkcount = 0;
2030                         info->cts_chkcount = 0;
2031                         break;
2032                 default:
2033                         DBGBH(("%s unknown action\n", info->device_name));
2034                         break;
2035                 }
2036         }
2037         DBGBH(("%s bh_handler exit\n", info->device_name));
2038 }
2039
2040 static void bh_transmit(struct slgt_info *info)
2041 {
2042         struct tty_struct *tty = info->port.tty;
2043
2044         DBGBH(("%s bh_transmit\n", info->device_name));
2045         if (tty)
2046                 tty_wakeup(tty);
2047 }
2048
2049 static void dsr_change(struct slgt_info *info, unsigned short status)
2050 {
2051         if (status & BIT3) {
2052                 info->signals |= SerialSignal_DSR;
2053                 info->input_signal_events.dsr_up++;
2054         } else {
2055                 info->signals &= ~SerialSignal_DSR;
2056                 info->input_signal_events.dsr_down++;
2057         }
2058         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2059         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2060                 slgt_irq_off(info, IRQ_DSR);
2061                 return;
2062         }
2063         info->icount.dsr++;
2064         wake_up_interruptible(&info->status_event_wait_q);
2065         wake_up_interruptible(&info->event_wait_q);
2066         info->pending_bh |= BH_STATUS;
2067 }
2068
2069 static void cts_change(struct slgt_info *info, unsigned short status)
2070 {
2071         if (status & BIT2) {
2072                 info->signals |= SerialSignal_CTS;
2073                 info->input_signal_events.cts_up++;
2074         } else {
2075                 info->signals &= ~SerialSignal_CTS;
2076                 info->input_signal_events.cts_down++;
2077         }
2078         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2079         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2080                 slgt_irq_off(info, IRQ_CTS);
2081                 return;
2082         }
2083         info->icount.cts++;
2084         wake_up_interruptible(&info->status_event_wait_q);
2085         wake_up_interruptible(&info->event_wait_q);
2086         info->pending_bh |= BH_STATUS;
2087
2088         if (info->port.flags & ASYNC_CTS_FLOW) {
2089                 if (info->port.tty) {
2090                         if (info->port.tty->hw_stopped) {
2091                                 if (info->signals & SerialSignal_CTS) {
2092                                         info->port.tty->hw_stopped = 0;
2093                                         info->pending_bh |= BH_TRANSMIT;
2094                                         return;
2095                                 }
2096                         } else {
2097                                 if (!(info->signals & SerialSignal_CTS))
2098                                         info->port.tty->hw_stopped = 1;
2099                         }
2100                 }
2101         }
2102 }
2103
2104 static void dcd_change(struct slgt_info *info, unsigned short status)
2105 {
2106         if (status & BIT1) {
2107                 info->signals |= SerialSignal_DCD;
2108                 info->input_signal_events.dcd_up++;
2109         } else {
2110                 info->signals &= ~SerialSignal_DCD;
2111                 info->input_signal_events.dcd_down++;
2112         }
2113         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2114         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2115                 slgt_irq_off(info, IRQ_DCD);
2116                 return;
2117         }
2118         info->icount.dcd++;
2119 #if SYNCLINK_GENERIC_HDLC
2120         if (info->netcount) {
2121                 if (info->signals & SerialSignal_DCD)
2122                         netif_carrier_on(info->netdev);
2123                 else
2124                         netif_carrier_off(info->netdev);
2125         }
2126 #endif
2127         wake_up_interruptible(&info->status_event_wait_q);
2128         wake_up_interruptible(&info->event_wait_q);
2129         info->pending_bh |= BH_STATUS;
2130
2131         if (info->port.flags & ASYNC_CHECK_CD) {
2132                 if (info->signals & SerialSignal_DCD)
2133                         wake_up_interruptible(&info->port.open_wait);
2134                 else {
2135                         if (info->port.tty)
2136                                 tty_hangup(info->port.tty);
2137                 }
2138         }
2139 }
2140
2141 static void ri_change(struct slgt_info *info, unsigned short status)
2142 {
2143         if (status & BIT0) {
2144                 info->signals |= SerialSignal_RI;
2145                 info->input_signal_events.ri_up++;
2146         } else {
2147                 info->signals &= ~SerialSignal_RI;
2148                 info->input_signal_events.ri_down++;
2149         }
2150         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2151         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2152                 slgt_irq_off(info, IRQ_RI);
2153                 return;
2154         }
2155         info->icount.rng++;
2156         wake_up_interruptible(&info->status_event_wait_q);
2157         wake_up_interruptible(&info->event_wait_q);
2158         info->pending_bh |= BH_STATUS;
2159 }
2160
2161 static void isr_serial(struct slgt_info *info)
2162 {
2163         unsigned short status = rd_reg16(info, SSR);
2164
2165         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2166
2167         wr_reg16(info, SSR, status); /* clear pending */
2168
2169         info->irq_occurred = true;
2170
2171         if (info->params.mode == MGSL_MODE_ASYNC) {
2172                 if (status & IRQ_TXIDLE) {
2173                         if (info->tx_count)
2174                                 isr_txeom(info, status);
2175                 }
2176                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2177                         info->icount.brk++;
2178                         /* process break detection if tty control allows */
2179                         if (info->port.tty) {
2180                                 if (!(status & info->ignore_status_mask)) {
2181                                         if (info->read_status_mask & MASK_BREAK) {
2182                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2183                                                 if (info->port.flags & ASYNC_SAK)
2184                                                         do_SAK(info->port.tty);
2185                                         }
2186                                 }
2187                         }
2188                 }
2189         } else {
2190                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2191                         isr_txeom(info, status);
2192
2193                 if (status & IRQ_RXIDLE) {
2194                         if (status & RXIDLE)
2195                                 info->icount.rxidle++;
2196                         else
2197                                 info->icount.exithunt++;
2198                         wake_up_interruptible(&info->event_wait_q);
2199                 }
2200
2201                 if (status & IRQ_RXOVER)
2202                         rx_start(info);
2203         }
2204
2205         if (status & IRQ_DSR)
2206                 dsr_change(info, status);
2207         if (status & IRQ_CTS)
2208                 cts_change(info, status);
2209         if (status & IRQ_DCD)
2210                 dcd_change(info, status);
2211         if (status & IRQ_RI)
2212                 ri_change(info, status);
2213 }
2214
2215 static void isr_rdma(struct slgt_info *info)
2216 {
2217         unsigned int status = rd_reg32(info, RDCSR);
2218
2219         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2220
2221         /* RDCSR (rx DMA control/status)
2222          *
2223          * 31..07  reserved
2224          * 06      save status byte to DMA buffer
2225          * 05      error
2226          * 04      eol (end of list)
2227          * 03      eob (end of buffer)
2228          * 02      IRQ enable
2229          * 01      reset
2230          * 00      enable
2231          */
2232         wr_reg32(info, RDCSR, status);  /* clear pending */
2233
2234         if (status & (BIT5 + BIT4)) {
2235                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2236                 info->rx_restart = true;
2237         }
2238         info->pending_bh |= BH_RECEIVE;
2239 }
2240
2241 static void isr_tdma(struct slgt_info *info)
2242 {
2243         unsigned int status = rd_reg32(info, TDCSR);
2244
2245         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2246
2247         /* TDCSR (tx DMA control/status)
2248          *
2249          * 31..06  reserved
2250          * 05      error
2251          * 04      eol (end of list)
2252          * 03      eob (end of buffer)
2253          * 02      IRQ enable
2254          * 01      reset
2255          * 00      enable
2256          */
2257         wr_reg32(info, TDCSR, status);  /* clear pending */
2258
2259         if (status & (BIT5 + BIT4 + BIT3)) {
2260                 // another transmit buffer has completed
2261                 // run bottom half to get more send data from user
2262                 info->pending_bh |= BH_TRANSMIT;
2263         }
2264 }
2265
2266 static void isr_txeom(struct slgt_info *info, unsigned short status)
2267 {
2268         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2269
2270         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2271         tdma_reset(info);
2272         reset_tbufs(info);
2273         if (status & IRQ_TXUNDER) {
2274                 unsigned short val = rd_reg16(info, TCR);
2275                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2276                 wr_reg16(info, TCR, val); /* clear reset bit */
2277         }
2278
2279         if (info->tx_active) {
2280                 if (info->params.mode != MGSL_MODE_ASYNC) {
2281                         if (status & IRQ_TXUNDER)
2282                                 info->icount.txunder++;
2283                         else if (status & IRQ_TXIDLE)
2284                                 info->icount.txok++;
2285                 }
2286
2287                 info->tx_active = false;
2288                 info->tx_count = 0;
2289
2290                 del_timer(&info->tx_timer);
2291
2292                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2293                         info->signals &= ~SerialSignal_RTS;
2294                         info->drop_rts_on_tx_done = false;
2295                         set_signals(info);
2296                 }
2297
2298 #if SYNCLINK_GENERIC_HDLC
2299                 if (info->netcount)
2300                         hdlcdev_tx_done(info);
2301                 else
2302 #endif
2303                 {
2304                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2305                                 tx_stop(info);
2306                                 return;
2307                         }
2308                         info->pending_bh |= BH_TRANSMIT;
2309                 }
2310         }
2311 }
2312
2313 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2314 {
2315         struct cond_wait *w, *prev;
2316
2317         /* wake processes waiting for specific transitions */
2318         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2319                 if (w->data & changed) {
2320                         w->data = state;
2321                         wake_up_interruptible(&w->q);
2322                         if (prev != NULL)
2323                                 prev->next = w->next;
2324                         else
2325                                 info->gpio_wait_q = w->next;
2326                 } else
2327                         prev = w;
2328         }
2329 }
2330
2331 /* interrupt service routine
2332  *
2333  *      irq     interrupt number
2334  *      dev_id  device ID supplied during interrupt registration
2335  */
2336 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2337 {
2338         struct slgt_info *info = dev_id;
2339         unsigned int gsr;
2340         unsigned int i;
2341
2342         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2343
2344         spin_lock(&info->lock);
2345
2346         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2347                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2348                 info->irq_occurred = true;
2349                 for(i=0; i < info->port_count ; i++) {
2350                         if (info->port_array[i] == NULL)
2351                                 continue;
2352                         if (gsr & (BIT8 << i))
2353                                 isr_serial(info->port_array[i]);
2354                         if (gsr & (BIT16 << (i*2)))
2355                                 isr_rdma(info->port_array[i]);
2356                         if (gsr & (BIT17 << (i*2)))
2357                                 isr_tdma(info->port_array[i]);
2358                 }
2359         }
2360
2361         if (info->gpio_present) {
2362                 unsigned int state;
2363                 unsigned int changed;
2364                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2365                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2366                         /* read latched state of GPIO signals */
2367                         state = rd_reg32(info, IOVR);
2368                         /* clear pending GPIO interrupt bits */
2369                         wr_reg32(info, IOSR, changed);
2370                         for (i=0 ; i < info->port_count ; i++) {
2371                                 if (info->port_array[i] != NULL)
2372                                         isr_gpio(info->port_array[i], changed, state);
2373                         }
2374                 }
2375         }
2376
2377         for(i=0; i < info->port_count ; i++) {
2378                 struct slgt_info *port = info->port_array[i];
2379
2380                 if (port && (port->port.count || port->netcount) &&
2381                     port->pending_bh && !port->bh_running &&
2382                     !port->bh_requested) {
2383                         DBGISR(("%s bh queued\n", port->device_name));
2384                         schedule_work(&port->task);
2385                         port->bh_requested = true;
2386                 }
2387         }
2388
2389         spin_unlock(&info->lock);
2390
2391         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2392         return IRQ_HANDLED;
2393 }
2394
2395 static int startup(struct slgt_info *info)
2396 {
2397         DBGINFO(("%s startup\n", info->device_name));
2398
2399         if (info->port.flags & ASYNC_INITIALIZED)
2400                 return 0;
2401
2402         if (!info->tx_buf) {
2403                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2404                 if (!info->tx_buf) {
2405                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2406                         return -ENOMEM;
2407                 }
2408         }
2409
2410         info->pending_bh = 0;
2411
2412         memset(&info->icount, 0, sizeof(info->icount));
2413
2414         /* program hardware for current parameters */
2415         change_params(info);
2416
2417         if (info->port.tty)
2418                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2419
2420         info->port.flags |= ASYNC_INITIALIZED;
2421
2422         return 0;
2423 }
2424
2425 /*
2426  *  called by close() and hangup() to shutdown hardware
2427  */
2428 static void shutdown(struct slgt_info *info)
2429 {
2430         unsigned long flags;
2431
2432         if (!(info->port.flags & ASYNC_INITIALIZED))
2433                 return;
2434
2435         DBGINFO(("%s shutdown\n", info->device_name));
2436
2437         /* clear status wait queue because status changes */
2438         /* can't happen after shutting down the hardware */
2439         wake_up_interruptible(&info->status_event_wait_q);
2440         wake_up_interruptible(&info->event_wait_q);
2441
2442         del_timer_sync(&info->tx_timer);
2443         del_timer_sync(&info->rx_timer);
2444
2445         kfree(info->tx_buf);
2446         info->tx_buf = NULL;
2447
2448         spin_lock_irqsave(&info->lock,flags);
2449
2450         tx_stop(info);
2451         rx_stop(info);
2452
2453         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2454
2455         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2456                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2457                 set_signals(info);
2458         }
2459
2460         flush_cond_wait(&info->gpio_wait_q);
2461
2462         spin_unlock_irqrestore(&info->lock,flags);
2463
2464         if (info->port.tty)
2465                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2466
2467         info->port.flags &= ~ASYNC_INITIALIZED;
2468 }
2469
2470 static void program_hw(struct slgt_info *info)
2471 {
2472         unsigned long flags;
2473
2474         spin_lock_irqsave(&info->lock,flags);
2475
2476         rx_stop(info);
2477         tx_stop(info);
2478
2479         if (info->params.mode != MGSL_MODE_ASYNC ||
2480             info->netcount)
2481                 sync_mode(info);
2482         else
2483                 async_mode(info);
2484
2485         set_signals(info);
2486
2487         info->dcd_chkcount = 0;
2488         info->cts_chkcount = 0;
2489         info->ri_chkcount = 0;
2490         info->dsr_chkcount = 0;
2491
2492         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2493         get_signals(info);
2494
2495         if (info->netcount ||
2496             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2497                 rx_start(info);
2498
2499         spin_unlock_irqrestore(&info->lock,flags);
2500 }
2501
2502 /*
2503  * reconfigure adapter based on new parameters
2504  */
2505 static void change_params(struct slgt_info *info)
2506 {
2507         unsigned cflag;
2508         int bits_per_char;
2509
2510         if (!info->port.tty || !info->port.tty->termios)
2511                 return;
2512         DBGINFO(("%s change_params\n", info->device_name));
2513
2514         cflag = info->port.tty->termios->c_cflag;
2515
2516         /* if B0 rate (hangup) specified then negate DTR and RTS */
2517         /* otherwise assert DTR and RTS */
2518         if (cflag & CBAUD)
2519                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2520         else
2521                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2522
2523         /* byte size and parity */
2524
2525         switch (cflag & CSIZE) {
2526         case CS5: info->params.data_bits = 5; break;
2527         case CS6: info->params.data_bits = 6; break;
2528         case CS7: info->params.data_bits = 7; break;
2529         case CS8: info->params.data_bits = 8; break;
2530         default:  info->params.data_bits = 7; break;
2531         }
2532
2533         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2534
2535         if (cflag & PARENB)
2536                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2537         else
2538                 info->params.parity = ASYNC_PARITY_NONE;
2539
2540         /* calculate number of jiffies to transmit a full
2541          * FIFO (32 bytes) at specified data rate
2542          */
2543         bits_per_char = info->params.data_bits +
2544                         info->params.stop_bits + 1;
2545
2546         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2547
2548         if (info->params.data_rate) {
2549                 info->timeout = (32*HZ*bits_per_char) /
2550                                 info->params.data_rate;
2551         }
2552         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2553
2554         if (cflag & CRTSCTS)
2555                 info->port.flags |= ASYNC_CTS_FLOW;
2556         else
2557                 info->port.flags &= ~ASYNC_CTS_FLOW;
2558
2559         if (cflag & CLOCAL)
2560                 info->port.flags &= ~ASYNC_CHECK_CD;
2561         else
2562                 info->port.flags |= ASYNC_CHECK_CD;
2563
2564         /* process tty input control flags */
2565
2566         info->read_status_mask = IRQ_RXOVER;
2567         if (I_INPCK(info->port.tty))
2568                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2569         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2570                 info->read_status_mask |= MASK_BREAK;
2571         if (I_IGNPAR(info->port.tty))
2572                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2573         if (I_IGNBRK(info->port.tty)) {
2574                 info->ignore_status_mask |= MASK_BREAK;
2575                 /* If ignoring parity and break indicators, ignore
2576                  * overruns too.  (For real raw support).
2577                  */
2578                 if (I_IGNPAR(info->port.tty))
2579                         info->ignore_status_mask |= MASK_OVERRUN;
2580         }
2581
2582         program_hw(info);
2583 }
2584
2585 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2586 {
2587         DBGINFO(("%s get_stats\n",  info->device_name));
2588         if (!user_icount) {
2589                 memset(&info->icount, 0, sizeof(info->icount));
2590         } else {
2591                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2592                         return -EFAULT;
2593         }
2594         return 0;
2595 }
2596
2597 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2598 {
2599         DBGINFO(("%s get_params\n", info->device_name));
2600         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2601                 return -EFAULT;
2602         return 0;
2603 }
2604
2605 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2606 {
2607         unsigned long flags;
2608         MGSL_PARAMS tmp_params;
2609
2610         DBGINFO(("%s set_params\n", info->device_name));
2611         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2612                 return -EFAULT;
2613
2614         spin_lock_irqsave(&info->lock, flags);
2615         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2616         spin_unlock_irqrestore(&info->lock, flags);
2617
2618         change_params(info);
2619
2620         return 0;
2621 }
2622
2623 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2624 {
2625         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2626         if (put_user(info->idle_mode, idle_mode))
2627                 return -EFAULT;
2628         return 0;
2629 }
2630
2631 static int set_txidle(struct slgt_info *info, int idle_mode)
2632 {
2633         unsigned long flags;
2634         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2635         spin_lock_irqsave(&info->lock,flags);
2636         info->idle_mode = idle_mode;
2637         if (info->params.mode != MGSL_MODE_ASYNC)
2638                 tx_set_idle(info);
2639         spin_unlock_irqrestore(&info->lock,flags);
2640         return 0;
2641 }
2642
2643 static int tx_enable(struct slgt_info *info, int enable)
2644 {
2645         unsigned long flags;
2646         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2647         spin_lock_irqsave(&info->lock,flags);
2648         if (enable) {
2649                 if (!info->tx_enabled)
2650                         tx_start(info);
2651         } else {
2652                 if (info->tx_enabled)
2653                         tx_stop(info);
2654         }
2655         spin_unlock_irqrestore(&info->lock,flags);
2656         return 0;
2657 }
2658
2659 /*
2660  * abort transmit HDLC frame
2661  */
2662 static int tx_abort(struct slgt_info *info)
2663 {
2664         unsigned long flags;
2665         DBGINFO(("%s tx_abort\n", info->device_name));
2666         spin_lock_irqsave(&info->lock,flags);
2667         tdma_reset(info);
2668         spin_unlock_irqrestore(&info->lock,flags);
2669         return 0;
2670 }
2671
2672 static int rx_enable(struct slgt_info *info, int enable)
2673 {
2674         unsigned long flags;
2675         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2676         spin_lock_irqsave(&info->lock,flags);
2677         if (enable) {
2678                 if (!info->rx_enabled)
2679                         rx_start(info);
2680                 else if (enable == 2) {
2681                         /* force hunt mode (write 1 to RCR[3]) */
2682                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2683                 }
2684         } else {
2685                 if (info->rx_enabled)
2686                         rx_stop(info);
2687         }
2688         spin_unlock_irqrestore(&info->lock,flags);
2689         return 0;
2690 }
2691
2692 /*
2693  *  wait for specified event to occur
2694  */
2695 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2696 {
2697         unsigned long flags;
2698         int s;
2699         int rc=0;
2700         struct mgsl_icount cprev, cnow;
2701         int events;
2702         int mask;
2703         struct  _input_signal_events oldsigs, newsigs;
2704         DECLARE_WAITQUEUE(wait, current);
2705
2706         if (get_user(mask, mask_ptr))
2707                 return -EFAULT;
2708
2709         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2710
2711         spin_lock_irqsave(&info->lock,flags);
2712
2713         /* return immediately if state matches requested events */
2714         get_signals(info);
2715         s = info->signals;
2716
2717         events = mask &
2718                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2719                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2720                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2721                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2722         if (events) {
2723                 spin_unlock_irqrestore(&info->lock,flags);
2724                 goto exit;
2725         }
2726
2727         /* save current irq counts */
2728         cprev = info->icount;
2729         oldsigs = info->input_signal_events;
2730
2731         /* enable hunt and idle irqs if needed */
2732         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2733                 unsigned short val = rd_reg16(info, SCR);
2734                 if (!(val & IRQ_RXIDLE))
2735                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2736         }
2737
2738         set_current_state(TASK_INTERRUPTIBLE);
2739         add_wait_queue(&info->event_wait_q, &wait);
2740
2741         spin_unlock_irqrestore(&info->lock,flags);
2742
2743         for(;;) {
2744                 schedule();
2745                 if (signal_pending(current)) {
2746                         rc = -ERESTARTSYS;
2747                         break;
2748                 }
2749
2750                 /* get current irq counts */
2751                 spin_lock_irqsave(&info->lock,flags);
2752                 cnow = info->icount;
2753                 newsigs = info->input_signal_events;
2754                 set_current_state(TASK_INTERRUPTIBLE);
2755                 spin_unlock_irqrestore(&info->lock,flags);
2756
2757                 /* if no change, wait aborted for some reason */
2758                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2759                     newsigs.dsr_down == oldsigs.dsr_down &&
2760                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2761                     newsigs.dcd_down == oldsigs.dcd_down &&
2762                     newsigs.cts_up   == oldsigs.cts_up   &&
2763                     newsigs.cts_down == oldsigs.cts_down &&
2764                     newsigs.ri_up    == oldsigs.ri_up    &&
2765                     newsigs.ri_down  == oldsigs.ri_down  &&
2766                     cnow.exithunt    == cprev.exithunt   &&
2767                     cnow.rxidle      == cprev.rxidle) {
2768                         rc = -EIO;
2769                         break;
2770                 }
2771
2772                 events = mask &
2773                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2774                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2775                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2776                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2777                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2778                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2779                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2780                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2781                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2782                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2783                 if (events)
2784                         break;
2785
2786                 cprev = cnow;
2787                 oldsigs = newsigs;
2788         }
2789
2790         remove_wait_queue(&info->event_wait_q, &wait);
2791         set_current_state(TASK_RUNNING);
2792
2793
2794         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2795                 spin_lock_irqsave(&info->lock,flags);
2796                 if (!waitqueue_active(&info->event_wait_q)) {
2797                         /* disable enable exit hunt mode/idle rcvd IRQs */
2798                         wr_reg16(info, SCR,
2799                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2800                 }
2801                 spin_unlock_irqrestore(&info->lock,flags);
2802         }
2803 exit:
2804         if (rc == 0)
2805                 rc = put_user(events, mask_ptr);
2806         return rc;
2807 }
2808
2809 static int get_interface(struct slgt_info *info, int __user *if_mode)
2810 {
2811         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2812         if (put_user(info->if_mode, if_mode))
2813                 return -EFAULT;
2814         return 0;
2815 }
2816
2817 static int set_interface(struct slgt_info *info, int if_mode)
2818 {
2819         unsigned long flags;
2820         unsigned short val;
2821
2822         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2823         spin_lock_irqsave(&info->lock,flags);
2824         info->if_mode = if_mode;
2825
2826         msc_set_vcr(info);
2827
2828         /* TCR (tx control) 07  1=RTS driver control */
2829         val = rd_reg16(info, TCR);
2830         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2831                 val |= BIT7;
2832         else
2833                 val &= ~BIT7;
2834         wr_reg16(info, TCR, val);
2835
2836         spin_unlock_irqrestore(&info->lock,flags);
2837         return 0;
2838 }
2839
2840 /*
2841  * set general purpose IO pin state and direction
2842  *
2843  * user_gpio fields:
2844  * state   each bit indicates a pin state
2845  * smask   set bit indicates pin state to set
2846  * dir     each bit indicates a pin direction (0=input, 1=output)
2847  * dmask   set bit indicates pin direction to set
2848  */
2849 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2850 {
2851         unsigned long flags;
2852         struct gpio_desc gpio;
2853         __u32 data;
2854
2855         if (!info->gpio_present)
2856                 return -EINVAL;
2857         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2858                 return -EFAULT;
2859         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2860                  info->device_name, gpio.state, gpio.smask,
2861                  gpio.dir, gpio.dmask));
2862
2863         spin_lock_irqsave(&info->lock,flags);
2864         if (gpio.dmask) {
2865                 data = rd_reg32(info, IODR);
2866                 data |= gpio.dmask & gpio.dir;
2867                 data &= ~(gpio.dmask & ~gpio.dir);
2868                 wr_reg32(info, IODR, data);
2869         }
2870         if (gpio.smask) {
2871                 data = rd_reg32(info, IOVR);
2872                 data |= gpio.smask & gpio.state;
2873                 data &= ~(gpio.smask & ~gpio.state);
2874                 wr_reg32(info, IOVR, data);
2875         }
2876         spin_unlock_irqrestore(&info->lock,flags);
2877
2878         return 0;
2879 }
2880
2881 /*
2882  * get general purpose IO pin state and direction
2883  */
2884 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2885 {
2886         struct gpio_desc gpio;
2887         if (!info->gpio_present)
2888                 return -EINVAL;
2889         gpio.state = rd_reg32(info, IOVR);
2890         gpio.smask = 0xffffffff;
2891         gpio.dir   = rd_reg32(info, IODR);
2892         gpio.dmask = 0xffffffff;
2893         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2894                 return -EFAULT;
2895         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2896                  info->device_name, gpio.state, gpio.dir));
2897         return 0;
2898 }
2899
2900 /*
2901  * conditional wait facility
2902  */
2903 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2904 {
2905         init_waitqueue_head(&w->q);
2906         init_waitqueue_entry(&w->wait, current);
2907         w->data = data;
2908 }
2909
2910 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2911 {
2912         set_current_state(TASK_INTERRUPTIBLE);
2913         add_wait_queue(&w->q, &w->wait);
2914         w->next = *head;
2915         *head = w;
2916 }
2917
2918 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2919 {
2920         struct cond_wait *w, *prev;
2921         remove_wait_queue(&cw->q, &cw->wait);
2922         set_current_state(TASK_RUNNING);
2923         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2924                 if (w == cw) {
2925                         if (prev != NULL)
2926                                 prev->next = w->next;
2927                         else
2928                                 *head = w->next;
2929                         break;
2930                 }
2931         }
2932 }
2933
2934 static void flush_cond_wait(struct cond_wait **head)
2935 {
2936         while (*head != NULL) {
2937                 wake_up_interruptible(&(*head)->q);
2938                 *head = (*head)->next;
2939         }
2940 }
2941
2942 /*
2943  * wait for general purpose I/O pin(s) to enter specified state
2944  *
2945  * user_gpio fields:
2946  * state - bit indicates target pin state
2947  * smask - set bit indicates watched pin
2948  *
2949  * The wait ends when at least one watched pin enters the specified
2950  * state. When 0 (no error) is returned, user_gpio->state is set to the
2951  * state of all GPIO pins when the wait ends.
2952  *
2953  * Note: Each pin may be a dedicated input, dedicated output, or
2954  * configurable input/output. The number and configuration of pins
2955  * varies with the specific adapter model. Only input pins (dedicated
2956  * or configured) can be monitored with this function.
2957  */
2958 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2959 {
2960         unsigned long flags;
2961         int rc = 0;
2962         struct gpio_desc gpio;
2963         struct cond_wait wait;
2964         u32 state;
2965
2966         if (!info->gpio_present)
2967                 return -EINVAL;
2968         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2969                 return -EFAULT;
2970         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2971                  info->device_name, gpio.state, gpio.smask));
2972         /* ignore output pins identified by set IODR bit */
2973         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2974                 return -EINVAL;
2975         init_cond_wait(&wait, gpio.smask);
2976
2977         spin_lock_irqsave(&info->lock, flags);
2978         /* enable interrupts for watched pins */
2979         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2980         /* get current pin states */
2981         state = rd_reg32(info, IOVR);
2982
2983         if (gpio.smask & ~(state ^ gpio.state)) {
2984                 /* already in target state */
2985                 gpio.state = state;
2986         } else {
2987                 /* wait for target state */
2988                 add_cond_wait(&info->gpio_wait_q, &wait);
2989                 spin_unlock_irqrestore(&info->lock, flags);
2990                 schedule();
2991                 if (signal_pending(current))
2992                         rc = -ERESTARTSYS;
2993                 else
2994                         gpio.state = wait.data;
2995                 spin_lock_irqsave(&info->lock, flags);
2996                 remove_cond_wait(&info->gpio_wait_q, &wait);
2997         }
2998
2999         /* disable all GPIO interrupts if no waiting processes */
3000         if (info->gpio_wait_q == NULL)
3001                 wr_reg32(info, IOER, 0);
3002         spin_unlock_irqrestore(&info->lock,flags);
3003
3004         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3005                 rc = -EFAULT;
3006         return rc;
3007 }
3008
3009 static int modem_input_wait(struct slgt_info *info,int arg)
3010 {
3011         unsigned long flags;
3012         int rc;
3013         struct mgsl_icount cprev, cnow;
3014         DECLARE_WAITQUEUE(wait, current);
3015
3016         /* save current irq counts */
3017         spin_lock_irqsave(&info->lock,flags);
3018         cprev = info->icount;
3019         add_wait_queue(&info->status_event_wait_q, &wait);
3020         set_current_state(TASK_INTERRUPTIBLE);
3021         spin_unlock_irqrestore(&info->lock,flags);
3022
3023         for(;;) {
3024                 schedule();
3025                 if (signal_pending(current)) {
3026                         rc = -ERESTARTSYS;
3027                         break;
3028                 }
3029
3030                 /* get new irq counts */
3031                 spin_lock_irqsave(&info->lock,flags);
3032                 cnow = info->icount;
3033                 set_current_state(TASK_INTERRUPTIBLE);
3034                 spin_unlock_irqrestore(&info->lock,flags);
3035
3036                 /* if no change, wait aborted for some reason */
3037                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3038                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3039                         rc = -EIO;
3040                         break;
3041                 }
3042
3043                 /* check for change in caller specified modem input */
3044                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3045                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3046                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3047                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3048                         rc = 0;
3049                         break;
3050                 }
3051
3052                 cprev = cnow;
3053         }
3054         remove_wait_queue(&info->status_event_wait_q, &wait);
3055         set_current_state(TASK_RUNNING);
3056         return rc;
3057 }
3058
3059 /*
3060  *  return state of serial control and status signals
3061  */
3062 static int tiocmget(struct tty_struct *tty, struct file *file)
3063 {
3064         struct slgt_info *info = tty->driver_data;
3065         unsigned int result;
3066         unsigned long flags;
3067
3068         spin_lock_irqsave(&info->lock,flags);
3069         get_signals(info);
3070         spin_unlock_irqrestore(&info->lock,flags);
3071
3072         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3073                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3074                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3075                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3076                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3077                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3078
3079         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3080         return result;
3081 }
3082
3083 /*
3084  * set modem control signals (DTR/RTS)
3085  *
3086  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3087  *              TIOCMSET = set/clear signal values
3088  *      value   bit mask for command
3089  */
3090 static int tiocmset(struct tty_struct *tty, struct file *file,
3091                     unsigned int set, unsigned int clear)
3092 {
3093         struct slgt_info *info = tty->driver_data;
3094         unsigned long flags;
3095
3096         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3097
3098         if (set & TIOCM_RTS)
3099                 info->signals |= SerialSignal_RTS;
3100         if (set & TIOCM_DTR)
3101                 info->signals |= SerialSignal_DTR;
3102         if (clear & TIOCM_RTS)
3103                 info->signals &= ~SerialSignal_RTS;
3104         if (clear & TIOCM_DTR)
3105                 info->signals &= ~SerialSignal_DTR;
3106
3107         spin_lock_irqsave(&info->lock,flags);
3108         set_signals(info);
3109         spin_unlock_irqrestore(&info->lock,flags);
3110         return 0;
3111 }
3112
3113 /*
3114  *  block current process until the device is ready to open
3115  */
3116 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3117                            struct slgt_info *info)
3118 {
3119         DECLARE_WAITQUEUE(wait, current);
3120         int             retval;
3121         bool            do_clocal = false;
3122         bool            extra_count = false;
3123         unsigned long   flags;
3124
3125         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3126
3127         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3128                 /* nonblock mode is set or port is not enabled */
3129                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3130                 return 0;
3131         }
3132
3133         if (tty->termios->c_cflag & CLOCAL)
3134                 do_clocal = true;
3135
3136         /* Wait for carrier detect and the line to become
3137          * free (i.e., not in use by the callout).  While we are in
3138          * this loop, info->port.count is dropped by one, so that
3139          * close() knows when to free things.  We restore it upon
3140          * exit, either normal or abnormal.
3141          */
3142
3143         retval = 0;
3144         add_wait_queue(&info->port.open_wait, &wait);
3145
3146         spin_lock_irqsave(&info->lock, flags);
3147         if (!tty_hung_up_p(filp)) {
3148                 extra_count = true;
3149                 info->port.count--;
3150         }
3151         spin_unlock_irqrestore(&info->lock, flags);
3152         info->port.blocked_open++;
3153
3154         while (1) {
3155                 if ((tty->termios->c_cflag & CBAUD)) {
3156                         spin_lock_irqsave(&info->lock,flags);
3157                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3158                         set_signals(info);
3159                         spin_unlock_irqrestore(&info->lock,flags);
3160                 }
3161
3162                 set_current_state(TASK_INTERRUPTIBLE);
3163
3164                 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3165                         retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3166                                         -EAGAIN : -ERESTARTSYS;
3167                         break;
3168                 }
3169
3170                 spin_lock_irqsave(&info->lock,flags);
3171                 get_signals(info);
3172                 spin_unlock_irqrestore(&info->lock,flags);
3173
3174                 if (!(info->port.flags & ASYNC_CLOSING) &&
3175                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3176                         break;
3177                 }
3178
3179                 if (signal_pending(current)) {
3180                         retval = -ERESTARTSYS;
3181                         break;
3182                 }
3183
3184                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3185                 schedule();
3186         }
3187
3188         set_current_state(TASK_RUNNING);
3189         remove_wait_queue(&info->port.open_wait, &wait);
3190
3191         if (extra_count)
3192                 info->port.count++;
3193         info->port.blocked_open--;
3194
3195         if (!retval)
3196                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3197
3198         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3199         return retval;
3200 }
3201
3202 static int alloc_tmp_rbuf(struct slgt_info *info)
3203 {
3204         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3205         if (info->tmp_rbuf == NULL)
3206                 return -ENOMEM;
3207         return 0;
3208 }
3209
3210 static void free_tmp_rbuf(struct slgt_info *info)
3211 {
3212         kfree(info->tmp_rbuf);
3213         info->tmp_rbuf = NULL;
3214 }
3215
3216 /*
3217  * allocate DMA descriptor lists.
3218  */
3219 static int alloc_desc(struct slgt_info *info)
3220 {
3221         unsigned int i;
3222         unsigned int pbufs;
3223
3224         /* allocate memory to hold descriptor lists */
3225         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3226         if (info->bufs == NULL)
3227                 return -ENOMEM;
3228
3229         memset(info->bufs, 0, DESC_LIST_SIZE);
3230
3231         info->rbufs = (struct slgt_desc*)info->bufs;
3232         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3233
3234         pbufs = (unsigned int)info->bufs_dma_addr;
3235
3236         /*
3237          * Build circular lists of descriptors
3238          */
3239
3240         for (i=0; i < info->rbuf_count; i++) {
3241                 /* physical address of this descriptor */
3242                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3243
3244                 /* physical address of next descriptor */
3245                 if (i == info->rbuf_count - 1)
3246                         info->rbufs[i].next = cpu_to_le32(pbufs);
3247                 else
3248                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3249                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3250         }
3251
3252         for (i=0; i < info->tbuf_count; i++) {
3253                 /* physical address of this descriptor */
3254                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3255
3256                 /* physical address of next descriptor */
3257                 if (i == info->tbuf_count - 1)
3258                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3259                 else
3260                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3261         }
3262
3263         return 0;
3264 }
3265
3266 static void free_desc(struct slgt_info *info)
3267 {
3268         if (info->bufs != NULL) {
3269                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3270                 info->bufs  = NULL;
3271                 info->rbufs = NULL;
3272                 info->tbufs = NULL;
3273         }
3274 }
3275
3276 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3277 {
3278         int i;
3279         for (i=0; i < count; i++) {
3280                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3281                         return -ENOMEM;
3282                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3283         }
3284         return 0;
3285 }
3286
3287 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3288 {
3289         int i;
3290         for (i=0; i < count; i++) {
3291                 if (bufs[i].buf == NULL)
3292                         continue;
3293                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3294                 bufs[i].buf = NULL;
3295         }
3296 }
3297
3298 static int alloc_dma_bufs(struct slgt_info *info)
3299 {
3300         info->rbuf_count = 32;
3301         info->tbuf_count = 32;
3302
3303         if (alloc_desc(info) < 0 ||
3304             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3305             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3306             alloc_tmp_rbuf(info) < 0) {
3307                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3308                 return -ENOMEM;
3309         }
3310         reset_rbufs(info);
3311         return 0;
3312 }
3313
3314 static void free_dma_bufs(struct slgt_info *info)
3315 {
3316         if (info->bufs) {
3317                 free_bufs(info, info->rbufs, info->rbuf_count);
3318                 free_bufs(info, info->tbufs, info->tbuf_count);
3319                 free_desc(info);
3320         }
3321         free_tmp_rbuf(info);
3322 }
3323
3324 static int claim_resources(struct slgt_info *info)
3325 {
3326         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3327                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3328                         info->device_name, info->phys_reg_addr));
3329                 info->init_error = DiagStatus_AddressConflict;
3330                 goto errout;
3331         }
3332         else
3333                 info->reg_addr_requested = true;
3334
3335         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3336         if (!info->reg_addr) {
3337                 DBGERR(("%s cant map device registers, addr=%08X\n",
3338                         info->device_name, info->phys_reg_addr));
3339                 info->init_error = DiagStatus_CantAssignPciResources;
3340                 goto errout;
3341         }
3342         return 0;
3343
3344 errout:
3345         release_resources(info);
3346         return -ENODEV;
3347 }
3348
3349 static void release_resources(struct slgt_info *info)
3350 {
3351         if (info->irq_requested) {
3352                 free_irq(info->irq_level, info);
3353                 info->irq_requested = false;
3354         }
3355
3356         if (info->reg_addr_requested) {
3357                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3358                 info->reg_addr_requested = false;
3359         }
3360
3361         if (info->reg_addr) {
3362                 iounmap(info->reg_addr);
3363                 info->reg_addr = NULL;
3364         }
3365 }
3366
3367 /* Add the specified device instance data structure to the
3368  * global linked list of devices and increment the device count.
3369  */
3370 static void add_device(struct slgt_info *info)
3371 {
3372         char *devstr;
3373
3374         info->next_device = NULL;
3375         info->line = slgt_device_count;
3376         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3377
3378         if (info->line < MAX_DEVICES) {
3379                 if (maxframe[info->line])
3380                         info->max_frame_size = maxframe[info->line];
3381                 info->dosyncppp = dosyncppp[info->line];
3382         }
3383
3384         slgt_device_count++;
3385
3386         if (!slgt_device_list)
3387                 slgt_device_list = info;
3388         else {
3389                 struct slgt_info *current_dev = slgt_device_list;
3390                 while(current_dev->next_device)
3391                         current_dev = current_dev->next_device;
3392                 current_dev->next_device = info;
3393         }
3394
3395         if (info->max_frame_size < 4096)
3396                 info->max_frame_size = 4096;
3397         else if (info->max_frame_size > 65535)
3398                 info->max_frame_size = 65535;
3399
3400         switch(info->pdev->device) {
3401         case SYNCLINK_GT_DEVICE_ID:
3402                 devstr = "GT";
3403                 break;
3404         case SYNCLINK_GT2_DEVICE_ID:
3405                 devstr = "GT2";
3406                 break;
3407         case SYNCLINK_GT4_DEVICE_ID:
3408                 devstr = "GT4";
3409                 break;
3410         case SYNCLINK_AC_DEVICE_ID:
3411                 devstr = "AC";
3412                 info->params.mode = MGSL_MODE_ASYNC;
3413                 break;
3414         default:
3415                 devstr = "(unknown model)";
3416         }
3417         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3418                 devstr, info->device_name, info->phys_reg_addr,
3419                 info->irq_level, info->max_frame_size);
3420
3421 #if SYNCLINK_GENERIC_HDLC
3422         hdlcdev_init(info);
3423 #endif
3424 }
3425
3426 /*
3427  *  allocate device instance structure, return NULL on failure
3428  */
3429 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3430 {
3431         struct slgt_info *info;
3432
3433         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3434
3435         if (!info) {
3436                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3437                         driver_name, adapter_num, port_num));
3438         } else {
3439                 tty_port_init(&info->port);
3440                 info->magic = MGSL_MAGIC;
3441                 INIT_WORK(&info->task, bh_handler);
3442                 info->max_frame_size = 4096;
3443                 info->raw_rx_size = DMABUFSIZE;
3444                 info->port.close_delay = 5*HZ/10;
3445                 info->port.closing_wait = 30*HZ;
3446                 init_waitqueue_head(&info->status_event_wait_q);
3447                 init_waitqueue_head(&info->event_wait_q);
3448                 spin_lock_init(&info->netlock);
3449                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3450                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3451                 info->adapter_num = adapter_num;
3452                 info->port_num = port_num;
3453
3454                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3455                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3456
3457                 /* Copy configuration info to device instance data */
3458                 info->pdev = pdev;
3459                 info->irq_level = pdev->irq;
3460                 info->phys_reg_addr = pci_resource_start(pdev,0);
3461
3462                 info->bus_type = MGSL_BUS_TYPE_PCI;
3463                 info->irq_flags = IRQF_SHARED;
3464
3465                 info->init_error = -1; /* assume error, set to 0 on successful init */
3466         }
3467
3468         return info;
3469 }
3470
3471 static void device_init(int adapter_num, struct pci_dev *pdev)
3472 {
3473         struct slgt_info *port_array[SLGT_MAX_PORTS];
3474         int i;
3475         int port_count = 1;
3476
3477         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3478                 port_count = 2;
3479         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3480                 port_count = 4;
3481
3482         /* allocate device instances for all ports */
3483         for (i=0; i < port_count; ++i) {
3484                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3485                 if (port_array[i] == NULL) {
3486                         for (--i; i >= 0; --i)
3487                                 kfree(port_array[i]);
3488                         return;
3489                 }
3490         }
3491
3492         /* give copy of port_array to all ports and add to device list  */
3493         for (i=0; i < port_count; ++i) {
3494                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3495                 add_device(port_array[i]);
3496                 port_array[i]->port_count = port_count;
3497                 spin_lock_init(&port_array[i]->lock);
3498         }
3499
3500         /* Allocate and claim adapter resources */
3501         if (!claim_resources(port_array[0])) {
3502
3503                 alloc_dma_bufs(port_array[0]);
3504
3505                 /* copy resource information from first port to others */
3506                 for (i = 1; i < port_count; ++i) {
3507                         port_array[i]->lock      = port_array[0]->lock;
3508                         port_array[i]->irq_level = port_array[0]->irq_level;
3509                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3510                         alloc_dma_bufs(port_array[i]);
3511                 }
3512
3513                 if (request_irq(port_array[0]->irq_level,
3514                                         slgt_interrupt,
3515                                         port_array[0]->irq_flags,
3516                                         port_array[0]->device_name,
3517                                         port_array[0]) < 0) {
3518                         DBGERR(("%s request_irq failed IRQ=%d\n",
3519                                 port_array[0]->device_name,
3520                                 port_array[0]->irq_level));
3521                 } else {
3522                         port_array[0]->irq_requested = true;
3523                         adapter_test(port_array[0]);
3524                         for (i=1 ; i < port_count ; i++) {
3525                                 port_array[i]->init_error = port_array[0]->init_error;
3526                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3527                         }
3528                 }
3529         }
3530
3531         for (i=0; i < port_count; ++i)
3532                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3533 }
3534
3535 static int __devinit init_one(struct pci_dev *dev,
3536                               const struct pci_device_id *ent)
3537 {
3538         if (pci_enable_device(dev)) {
3539                 printk("error enabling pci device %p\n", dev);
3540                 return -EIO;
3541         }
3542         pci_set_master(dev);
3543         device_init(slgt_device_count, dev);
3544         return 0;
3545 }
3546
3547 static void __devexit remove_one(struct pci_dev *dev)
3548 {
3549 }
3550
3551 static const struct tty_operations ops = {
3552         .open = open,
3553         .close = close,
3554         .write = write,
3555         .put_char = put_char,
3556         .flush_chars = flush_chars,
3557         .write_room = write_room,
3558         .chars_in_buffer = chars_in_buffer,
3559         .flush_buffer = flush_buffer,
3560         .ioctl = ioctl,
3561         .compat_ioctl = slgt_compat_ioctl,
3562         .throttle = throttle,
3563         .unthrottle = unthrottle,
3564         .send_xchar = send_xchar,
3565         .break_ctl = set_break,
3566         .wait_until_sent = wait_until_sent,
3567         .read_proc = read_proc,
3568         .set_termios = set_termios,
3569         .stop = tx_hold,
3570         .start = tx_release,
3571         .hangup = hangup,
3572         .tiocmget = tiocmget,
3573         .tiocmset = tiocmset,
3574 };
3575
3576 static void slgt_cleanup(void)
3577 {
3578         int rc;
3579         struct slgt_info *info;
3580         struct slgt_info *tmp;
3581
3582         printk("unload %s %s\n", driver_name, driver_version);
3583
3584         if (serial_driver) {
3585                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3586                         tty_unregister_device(serial_driver, info->line);
3587                 if ((rc = tty_unregister_driver(serial_driver)))
3588                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3589                 put_tty_driver(serial_driver);
3590         }
3591
3592         /* reset devices */
3593         info = slgt_device_list;
3594         while(info) {
3595                 reset_port(info);
3596                 info = info->next_device;
3597         }
3598
3599         /* release devices */
3600         info = slgt_device_list;
3601         while(info) {
3602 #if SYNCLINK_GENERIC_HDLC
3603                 hdlcdev_exit(info);
3604 #endif
3605                 free_dma_bufs(info);
3606                 free_tmp_rbuf(info);
3607                 if (info->port_num == 0)
3608                         release_resources(info);
3609                 tmp = info;
3610                 info = info->next_device;
3611                 kfree(tmp);
3612         }
3613
3614         if (pci_registered)
3615                 pci_unregister_driver(&pci_driver);
3616 }
3617
3618 /*
3619  *  Driver initialization entry point.
3620  */
3621 static int __init slgt_init(void)
3622 {
3623         int rc;
3624
3625         printk("%s %s\n", driver_name, driver_version);
3626
3627         serial_driver = alloc_tty_driver(MAX_DEVICES);
3628         if (!serial_driver) {
3629                 printk("%s can't allocate tty driver\n", driver_name);
3630                 return -ENOMEM;
3631         }
3632
3633         /* Initialize the tty_driver structure */
3634
3635         serial_driver->owner = THIS_MODULE;
3636         serial_driver->driver_name = tty_driver_name;
3637         serial_driver->name = tty_dev_prefix;
3638         serial_driver->major = ttymajor;
3639         serial_driver->minor_start = 64;
3640         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3641         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3642         serial_driver->init_termios = tty_std_termios;
3643         serial_driver->init_termios.c_cflag =
3644                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3645         serial_driver->init_termios.c_ispeed = 9600;
3646         serial_driver->init_termios.c_ospeed = 9600;
3647         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3648         tty_set_operations(serial_driver, &ops);
3649         if ((rc = tty_register_driver(serial_driver)) < 0) {
3650                 DBGERR(("%s can't register serial driver\n", driver_name));
3651                 put_tty_driver(serial_driver);
3652                 serial_driver = NULL;
3653                 goto error;
3654         }
3655
3656         printk("%s %s, tty major#%d\n",
3657                 driver_name, driver_version,
3658                 serial_driver->major);
3659
3660         slgt_device_count = 0;
3661         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3662                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3663                 goto error;
3664         }
3665         pci_registered = true;
3666
3667         if (!slgt_device_list)
3668                 printk("%s no devices found\n",driver_name);
3669
3670         return 0;
3671
3672 error:
3673         slgt_cleanup();
3674         return rc;
3675 }
3676
3677 static void __exit slgt_exit(void)
3678 {
3679         slgt_cleanup();
3680 }
3681
3682 module_init(slgt_init);
3683 module_exit(slgt_exit);
3684
3685 /*
3686  * register access routines
3687  */
3688
3689 #define CALC_REGADDR() \
3690         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3691         if (addr >= 0x80) \
3692                 reg_addr += (info->port_num) * 32;
3693
3694 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3695 {
3696         CALC_REGADDR();
3697         return readb((void __iomem *)reg_addr);
3698 }
3699
3700 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3701 {
3702         CALC_REGADDR();
3703         writeb(value, (void __iomem *)reg_addr);
3704 }
3705
3706 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3707 {
3708         CALC_REGADDR();
3709         return readw((void __iomem *)reg_addr);
3710 }
3711
3712 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3713 {
3714         CALC_REGADDR();
3715         writew(value, (void __iomem *)reg_addr);
3716 }
3717
3718 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3719 {
3720         CALC_REGADDR();
3721         return readl((void __iomem *)reg_addr);
3722 }
3723
3724 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3725 {
3726         CALC_REGADDR();
3727         writel(value, (void __iomem *)reg_addr);
3728 }
3729
3730 static void rdma_reset(struct slgt_info *info)
3731 {
3732         unsigned int i;
3733
3734         /* set reset bit */
3735         wr_reg32(info, RDCSR, BIT1);
3736
3737         /* wait for enable bit cleared */
3738         for(i=0 ; i < 1000 ; i++)
3739                 if (!(rd_reg32(info, RDCSR) & BIT0))
3740                         break;
3741 }
3742
3743 static void tdma_reset(struct slgt_info *info)
3744 {
3745         unsigned int i;
3746
3747         /* set reset bit */
3748         wr_reg32(info, TDCSR, BIT1);
3749
3750         /* wait for enable bit cleared */
3751         for(i=0 ; i < 1000 ; i++)
3752                 if (!(rd_reg32(info, TDCSR) & BIT0))
3753                         break;
3754 }
3755
3756 /*
3757  * enable internal loopback
3758  * TxCLK and RxCLK are generated from BRG
3759  * and TxD is looped back to RxD internally.
3760  */
3761 static void enable_loopback(struct slgt_info *info)
3762 {
3763         /* SCR (serial control) BIT2=looopback enable */
3764         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3765
3766         if (info->params.mode != MGSL_MODE_ASYNC) {
3767                 /* CCR (clock control)
3768                  * 07..05  tx clock source (010 = BRG)
3769                  * 04..02  rx clock source (010 = BRG)
3770                  * 01      auxclk enable   (0 = disable)
3771                  * 00      BRG enable      (1 = enable)
3772                  *
3773                  * 0100 1001
3774                  */
3775                 wr_reg8(info, CCR, 0x49);
3776
3777                 /* set speed if available, otherwise use default */
3778                 if (info->params.clock_speed)
3779                         set_rate(info, info->params.clock_speed);
3780                 else
3781                         set_rate(info, 3686400);
3782         }
3783 }
3784
3785 /*
3786  *  set baud rate generator to specified rate
3787  */
3788 static void set_rate(struct slgt_info *info, u32 rate)
3789 {
3790         unsigned int div;
3791         static unsigned int osc = 14745600;
3792
3793         /* div = osc/rate - 1
3794          *
3795          * Round div up if osc/rate is not integer to
3796          * force to next slowest rate.
3797          */
3798
3799         if (rate) {
3800                 div = osc/rate;
3801                 if (!(osc % rate) && div)
3802                         div--;
3803                 wr_reg16(info, BDR, (unsigned short)div);
3804         }
3805 }
3806
3807 static void rx_stop(struct slgt_info *info)
3808 {
3809         unsigned short val;
3810
3811         /* disable and reset receiver */
3812         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3813         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3814         wr_reg16(info, RCR, val);                  /* clear reset bit */
3815
3816         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3817
3818         /* clear pending rx interrupts */
3819         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3820
3821         rdma_reset(info);
3822
3823         info->rx_enabled = false;
3824         info->rx_restart = false;
3825 }
3826
3827 static void rx_start(struct slgt_info *info)
3828 {
3829         unsigned short val;
3830
3831         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3832
3833         /* clear pending rx overrun IRQ */
3834         wr_reg16(info, SSR, IRQ_RXOVER);
3835
3836         /* reset and disable receiver */
3837         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3838         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3839         wr_reg16(info, RCR, val);                  /* clear reset bit */
3840
3841         rdma_reset(info);
3842         reset_rbufs(info);
3843
3844         /* set 1st descriptor address */
3845         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3846
3847         if (info->params.mode != MGSL_MODE_ASYNC) {
3848                 /* enable rx DMA and DMA interrupt */
3849                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3850         } else {
3851                 /* enable saving of rx status, rx DMA and DMA interrupt */
3852                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3853         }
3854
3855         slgt_irq_on(info, IRQ_RXOVER);
3856
3857         /* enable receiver */
3858         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3859
3860         info->rx_restart = false;
3861         info->rx_enabled = true;
3862 }
3863
3864 static void tx_start(struct slgt_info *info)
3865 {
3866         if (!info->tx_enabled) {
3867                 wr_reg16(info, TCR,
3868                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3869                 info->tx_enabled = true;
3870         }
3871
3872         if (info->tx_count) {
3873                 info->drop_rts_on_tx_done = false;
3874
3875                 if (info->params.mode != MGSL_MODE_ASYNC) {
3876                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3877                                 get_signals(info);
3878                                 if (!(info->signals & SerialSignal_RTS)) {
3879                                         info->signals |= SerialSignal_RTS;
3880                                         set_signals(info);
3881                                         info->drop_rts_on_tx_done = true;
3882                                 }
3883                         }
3884
3885                         slgt_irq_off(info, IRQ_TXDATA);
3886                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3887                         /* clear tx idle and underrun status bits */
3888                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3889                         if (info->params.mode == MGSL_MODE_HDLC)
3890                                 mod_timer(&info->tx_timer, jiffies +
3891                                                 msecs_to_jiffies(5000));
3892                 } else {
3893                         slgt_irq_off(info, IRQ_TXDATA);
3894                         slgt_irq_on(info, IRQ_TXIDLE);
3895                         /* clear tx idle status bit */
3896                         wr_reg16(info, SSR, IRQ_TXIDLE);
3897                 }
3898                 tdma_start(info);
3899                 info->tx_active = true;
3900         }
3901 }
3902
3903 /*
3904  * start transmit DMA if inactive and there are unsent buffers
3905  */
3906 static void tdma_start(struct slgt_info *info)
3907 {
3908         unsigned int i;
3909
3910         if (rd_reg32(info, TDCSR) & BIT0)
3911                 return;
3912
3913         /* transmit DMA inactive, check for unsent buffers */
3914         i = info->tbuf_start;
3915         while (!desc_count(info->tbufs[i])) {
3916                 if (++i == info->tbuf_count)
3917                         i = 0;
3918                 if (i == info->tbuf_current)
3919                         return;
3920         }
3921         info->tbuf_start = i;
3922
3923         /* there are unsent buffers, start transmit DMA */
3924
3925         /* reset needed if previous error condition */
3926         tdma_reset(info);
3927
3928         /* set 1st descriptor address */
3929         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3930         wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3931 }
3932
3933 static void tx_stop(struct slgt_info *info)
3934 {
3935         unsigned short val;
3936
3937         del_timer(&info->tx_timer);
3938
3939         tdma_reset(info);
3940
3941         /* reset and disable transmitter */
3942         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3943         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3944
3945         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3946
3947         /* clear tx idle and underrun status bit */
3948         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3949
3950         reset_tbufs(info);
3951
3952         info->tx_enabled = false;
3953         info->tx_active = false;
3954 }
3955
3956 static void reset_port(struct slgt_info *info)
3957 {
3958         if (!info->reg_addr)
3959                 return;
3960
3961         tx_stop(info);
3962         rx_stop(info);
3963
3964         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3965         set_signals(info);
3966
3967         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3968 }
3969
3970 static void reset_adapter(struct slgt_info *info)
3971 {
3972         int i;
3973         for (i=0; i < info->port_count; ++i) {
3974                 if (info->port_array[i])
3975                         reset_port(info->port_array[i]);
3976         }
3977 }
3978
3979 static void async_mode(struct slgt_info *info)
3980 {
3981         unsigned short val;
3982
3983         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3984         tx_stop(info);
3985         rx_stop(info);
3986
3987         /* TCR (tx control)
3988          *
3989          * 15..13  mode, 010=async
3990          * 12..10  encoding, 000=NRZ
3991          * 09      parity enable
3992          * 08      1=odd parity, 0=even parity
3993          * 07      1=RTS driver control
3994          * 06      1=break enable
3995          * 05..04  character length
3996          *         00=5 bits
3997          *         01=6 bits
3998          *         10=7 bits
3999          *         11=8 bits
4000          * 03      0=1 stop bit, 1=2 stop bits
4001          * 02      reset
4002          * 01      enable
4003          * 00      auto-CTS enable
4004          */
4005         val = 0x4000;
4006
4007         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4008                 val |= BIT7;
4009
4010         if (info->params.parity != ASYNC_PARITY_NONE) {
4011                 val |= BIT9;
4012                 if (info->params.parity == ASYNC_PARITY_ODD)
4013                         val |= BIT8;
4014         }
4015
4016         switch (info->params.data_bits)
4017         {
4018         case 6: val |= BIT4; break;
4019         case 7: val |= BIT5; break;
4020         case 8: val |= BIT5 + BIT4; break;
4021         }
4022
4023         if (info->params.stop_bits != 1)
4024                 val |= BIT3;
4025
4026         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4027                 val |= BIT0;
4028
4029         wr_reg16(info, TCR, val);
4030
4031         /* RCR (rx control)
4032          *
4033          * 15..13  mode, 010=async
4034          * 12..10  encoding, 000=NRZ
4035          * 09      parity enable
4036          * 08      1=odd parity, 0=even parity
4037          * 07..06  reserved, must be 0
4038          * 05..04  character length
4039          *         00=5 bits
4040          *         01=6 bits
4041          *         10=7 bits
4042          *         11=8 bits
4043          * 03      reserved, must be zero
4044          * 02      reset
4045          * 01      enable
4046          * 00      auto-DCD enable
4047          */
4048         val = 0x4000;
4049
4050         if (info->params.parity != ASYNC_PARITY_NONE) {
4051                 val |= BIT9;
4052                 if (info->params.parity == ASYNC_PARITY_ODD)
4053                         val |= BIT8;
4054         }
4055
4056         switch (info->params.data_bits)
4057         {
4058         case 6: val |= BIT4; break;
4059         case 7: val |= BIT5; break;
4060         case 8: val |= BIT5 + BIT4; break;
4061         }
4062
4063         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4064                 val |= BIT0;
4065
4066         wr_reg16(info, RCR, val);
4067
4068         /* CCR (clock control)
4069          *
4070          * 07..05  011 = tx clock source is BRG/16
4071          * 04..02  010 = rx clock source is BRG
4072          * 01      0 = auxclk disabled
4073          * 00      1 = BRG enabled
4074          *
4075          * 0110 1001
4076          */
4077         wr_reg8(info, CCR, 0x69);
4078
4079         msc_set_vcr(info);
4080
4081         /* SCR (serial control)
4082          *
4083          * 15  1=tx req on FIFO half empty
4084          * 14  1=rx req on FIFO half full
4085          * 13  tx data  IRQ enable
4086          * 12  tx idle  IRQ enable
4087          * 11  rx break on IRQ enable
4088          * 10  rx data  IRQ enable
4089          * 09  rx break off IRQ enable
4090          * 08  overrun  IRQ enable
4091          * 07  DSR      IRQ enable
4092          * 06  CTS      IRQ enable
4093          * 05  DCD      IRQ enable
4094          * 04  RI       IRQ enable
4095          * 03  reserved, must be zero
4096          * 02  1=txd->rxd internal loopback enable
4097          * 01  reserved, must be zero
4098          * 00  1=master IRQ enable
4099          */
4100         val = BIT15 + BIT14 + BIT0;
4101         wr_reg16(info, SCR, val);
4102
4103         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4104
4105         set_rate(info, info->params.data_rate * 16);
4106
4107         if (info->params.loopback)
4108                 enable_loopback(info);
4109 }
4110
4111 static void sync_mode(struct slgt_info *info)
4112 {
4113         unsigned short val;
4114
4115         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4116         tx_stop(info);
4117         rx_stop(info);
4118
4119         /* TCR (tx control)
4120          *
4121          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4122          * 12..10  encoding
4123          * 09      CRC enable
4124          * 08      CRC32
4125          * 07      1=RTS driver control
4126          * 06      preamble enable
4127          * 05..04  preamble length
4128          * 03      share open/close flag
4129          * 02      reset
4130          * 01      enable
4131          * 00      auto-CTS enable
4132          */
4133         val = 0;
4134
4135         switch(info->params.mode) {
4136         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4137         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4138         case MGSL_MODE_RAW:      val |= BIT13; break;
4139         }
4140         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4141                 val |= BIT7;
4142
4143         switch(info->params.encoding)
4144         {
4145         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4146         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4147         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4148         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4149         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4150         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4151         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4152         }
4153
4154         switch (info->params.crc_type & HDLC_CRC_MASK)
4155         {
4156         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4157         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4158         }
4159
4160         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4161                 val |= BIT6;
4162
4163         switch (info->params.preamble_length)
4164         {
4165         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4166         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4167         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4168         }
4169
4170         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4171                 val |= BIT0;
4172
4173         wr_reg16(info, TCR, val);
4174
4175         /* TPR (transmit preamble) */
4176
4177         switch (info->params.preamble)
4178         {
4179         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4180         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4181         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4182         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4183         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4184         default:                          val = 0x7e; break;
4185         }
4186         wr_reg8(info, TPR, (unsigned char)val);
4187
4188         /* RCR (rx control)
4189          *
4190          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4191          * 12..10  encoding
4192          * 09      CRC enable
4193          * 08      CRC32
4194          * 07..03  reserved, must be 0
4195          * 02      reset
4196          * 01      enable
4197          * 00      auto-DCD enable
4198          */
4199         val = 0;
4200
4201         switch(info->params.mode) {
4202         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4203         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4204         case MGSL_MODE_RAW:      val |= BIT13; break;
4205         }
4206
4207         switch(info->params.encoding)
4208         {
4209         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4210         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4211         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4212         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4213         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4214         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4215         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4216         }
4217
4218         switch (info->params.crc_type & HDLC_CRC_MASK)
4219         {
4220         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4221         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4222         }
4223
4224         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4225                 val |= BIT0;
4226
4227         wr_reg16(info, RCR, val);
4228
4229         /* CCR (clock control)
4230          *
4231          * 07..05  tx clock source
4232          * 04..02  rx clock source
4233          * 01      auxclk enable
4234          * 00      BRG enable
4235          */
4236         val = 0;
4237
4238         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4239         {
4240                 // when RxC source is DPLL, BRG generates 16X DPLL
4241                 // reference clock, so take TxC from BRG/16 to get
4242                 // transmit clock at actual data rate
4243                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4244                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4245                 else
4246                         val |= BIT6;    /* 010, txclk = BRG */
4247         }
4248         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4249                 val |= BIT7;    /* 100, txclk = DPLL Input */
4250         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4251                 val |= BIT5;    /* 001, txclk = RXC Input */
4252
4253         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4254                 val |= BIT3;    /* 010, rxclk = BRG */
4255         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4256                 val |= BIT4;    /* 100, rxclk = DPLL */
4257         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4258                 val |= BIT2;    /* 001, rxclk = TXC Input */
4259
4260         if (info->params.clock_speed)
4261                 val |= BIT1 + BIT0;
4262
4263         wr_reg8(info, CCR, (unsigned char)val);
4264
4265         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4266         {
4267                 // program DPLL mode
4268                 switch(info->params.encoding)
4269                 {
4270                 case HDLC_ENCODING_BIPHASE_MARK:
4271                 case HDLC_ENCODING_BIPHASE_SPACE:
4272                         val = BIT7; break;
4273                 case HDLC_ENCODING_BIPHASE_LEVEL:
4274                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4275                         val = BIT7 + BIT6; break;
4276                 default: val = BIT6;    // NRZ encodings
4277                 }
4278                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4279
4280                 // DPLL requires a 16X reference clock from BRG
4281                 set_rate(info, info->params.clock_speed * 16);
4282         }
4283         else
4284                 set_rate(info, info->params.clock_speed);
4285
4286         tx_set_idle(info);
4287
4288         msc_set_vcr(info);
4289
4290         /* SCR (serial control)
4291          *
4292          * 15  1=tx req on FIFO half empty
4293          * 14  1=rx req on FIFO half full
4294          * 13  tx data  IRQ enable
4295          * 12  tx idle  IRQ enable
4296          * 11  underrun IRQ enable
4297          * 10  rx data  IRQ enable
4298          * 09  rx idle  IRQ enable
4299          * 08  overrun  IRQ enable
4300          * 07  DSR      IRQ enable
4301          * 06  CTS      IRQ enable
4302          * 05  DCD      IRQ enable
4303          * 04  RI       IRQ enable
4304          * 03  reserved, must be zero
4305          * 02  1=txd->rxd internal loopback enable
4306          * 01  reserved, must be zero
4307          * 00  1=master IRQ enable
4308          */
4309         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4310
4311         if (info->params.loopback)
4312                 enable_loopback(info);
4313 }
4314
4315 /*
4316  *  set transmit idle mode
4317  */
4318 static void tx_set_idle(struct slgt_info *info)
4319 {
4320         unsigned char val;
4321         unsigned short tcr;
4322
4323         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4324          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4325          */
4326         tcr = rd_reg16(info, TCR);
4327         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4328                 /* disable preamble, set idle size to 16 bits */
4329                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4330                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4331                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4332         } else if (!(tcr & BIT6)) {
4333                 /* preamble is disabled, set idle size to 8 bits */
4334                 tcr &= ~(BIT5 + BIT4);
4335         }
4336         wr_reg16(info, TCR, tcr);
4337
4338         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4339                 /* LSB of custom tx idle specified in tx idle register */
4340                 val = (unsigned char)(info->idle_mode & 0xff);
4341         } else {
4342                 /* standard 8 bit idle patterns */
4343                 switch(info->idle_mode)
4344                 {
4345                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4346                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4347                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4348                 case HDLC_TXIDLE_ZEROS:
4349                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4350                 default:                         val = 0xff;
4351                 }
4352         }
4353
4354         wr_reg8(info, TIR, val);
4355 }
4356
4357 /*
4358  * get state of V24 status (input) signals
4359  */
4360 static void get_signals(struct slgt_info *info)
4361 {
4362         unsigned short status = rd_reg16(info, SSR);
4363
4364         /* clear all serial signals except DTR and RTS */
4365         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4366
4367         if (status & BIT3)
4368                 info->signals |= SerialSignal_DSR;
4369         if (status & BIT2)
4370                 info->signals |= SerialSignal_CTS;
4371         if (status & BIT1)
4372                 info->signals |= SerialSignal_DCD;
4373         if (status & BIT0)
4374                 info->signals |= SerialSignal_RI;
4375 }
4376
4377 /*
4378  * set V.24 Control Register based on current configuration
4379  */
4380 static void msc_set_vcr(struct slgt_info *info)
4381 {
4382         unsigned char val = 0;
4383
4384         /* VCR (V.24 control)
4385          *
4386          * 07..04  serial IF select
4387          * 03      DTR
4388          * 02      RTS
4389          * 01      LL
4390          * 00      RL
4391          */
4392
4393         switch(info->if_mode & MGSL_INTERFACE_MASK)
4394         {
4395         case MGSL_INTERFACE_RS232:
4396                 val |= BIT5; /* 0010 */
4397                 break;
4398         case MGSL_INTERFACE_V35:
4399                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4400                 break;
4401         case MGSL_INTERFACE_RS422:
4402                 val |= BIT6; /* 0100 */
4403                 break;
4404         }
4405
4406         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4407                 val |= BIT4;
4408         if (info->signals & SerialSignal_DTR)
4409                 val |= BIT3;
4410         if (info->signals & SerialSignal_RTS)
4411                 val |= BIT2;
4412         if (info->if_mode & MGSL_INTERFACE_LL)
4413                 val |= BIT1;
4414         if (info->if_mode & MGSL_INTERFACE_RL)
4415                 val |= BIT0;
4416         wr_reg8(info, VCR, val);
4417 }
4418
4419 /*
4420  * set state of V24 control (output) signals
4421  */
4422 static void set_signals(struct slgt_info *info)
4423 {
4424         unsigned char val = rd_reg8(info, VCR);
4425         if (info->signals & SerialSignal_DTR)
4426                 val |= BIT3;
4427         else
4428                 val &= ~BIT3;
4429         if (info->signals & SerialSignal_RTS)
4430                 val |= BIT2;
4431         else
4432                 val &= ~BIT2;
4433         wr_reg8(info, VCR, val);
4434 }
4435
4436 /*
4437  * free range of receive DMA buffers (i to last)
4438  */
4439 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4440 {
4441         int done = 0;
4442
4443         while(!done) {
4444                 /* reset current buffer for reuse */
4445                 info->rbufs[i].status = 0;
4446                 switch(info->params.mode) {
4447                 case MGSL_MODE_RAW:
4448                 case MGSL_MODE_MONOSYNC:
4449                 case MGSL_MODE_BISYNC:
4450                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4451                         break;
4452                 default:
4453                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4454                 }
4455
4456                 if (i == last)
4457                         done = 1;
4458                 if (++i == info->rbuf_count)
4459                         i = 0;
4460         }
4461         info->rbuf_current = i;
4462 }
4463
4464 /*
4465  * mark all receive DMA buffers as free
4466  */
4467 static void reset_rbufs(struct slgt_info *info)
4468 {
4469         free_rbufs(info, 0, info->rbuf_count - 1);
4470 }
4471
4472 /*
4473  * pass receive HDLC frame to upper layer
4474  *
4475  * return true if frame available, otherwise false
4476  */
4477 static bool rx_get_frame(struct slgt_info *info)
4478 {
4479         unsigned int start, end;
4480         unsigned short status;
4481         unsigned int framesize = 0;
4482         unsigned long flags;
4483         struct tty_struct *tty = info->port.tty;
4484         unsigned char addr_field = 0xff;
4485         unsigned int crc_size = 0;
4486
4487         switch (info->params.crc_type & HDLC_CRC_MASK) {
4488         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4489         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4490         }
4491
4492 check_again:
4493
4494         framesize = 0;
4495         addr_field = 0xff;
4496         start = end = info->rbuf_current;
4497
4498         for (;;) {
4499                 if (!desc_complete(info->rbufs[end]))
4500                         goto cleanup;
4501
4502                 if (framesize == 0 && info->params.addr_filter != 0xff)
4503                         addr_field = info->rbufs[end].buf[0];
4504
4505                 framesize += desc_count(info->rbufs[end]);
4506
4507                 if (desc_eof(info->rbufs[end]))
4508                         break;
4509
4510                 if (++end == info->rbuf_count)
4511                         end = 0;
4512
4513                 if (end == info->rbuf_current) {
4514                         if (info->rx_enabled){
4515                                 spin_lock_irqsave(&info->lock,flags);
4516                                 rx_start(info);
4517                                 spin_unlock_irqrestore(&info->lock,flags);
4518                         }
4519                         goto cleanup;
4520                 }
4521         }
4522
4523         /* status
4524          *
4525          * 15      buffer complete
4526          * 14..06  reserved
4527          * 05..04  residue
4528          * 02      eof (end of frame)
4529          * 01      CRC error
4530          * 00      abort
4531          */
4532         status = desc_status(info->rbufs[end]);
4533
4534         /* ignore CRC bit if not using CRC (bit is undefined) */
4535         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4536                 status &= ~BIT1;
4537
4538         if (framesize == 0 ||
4539                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4540                 free_rbufs(info, start, end);
4541                 goto check_again;
4542         }
4543
4544         if (framesize < (2 + crc_size) || status & BIT0) {
4545                 info->icount.rxshort++;
4546                 framesize = 0;
4547         } else if (status & BIT1) {
4548                 info->icount.rxcrc++;
4549                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4550                         framesize = 0;
4551         }
4552
4553 #if SYNCLINK_GENERIC_HDLC
4554         if (framesize == 0) {
4555                 info->netdev->stats.rx_errors++;
4556                 info->netdev->stats.rx_frame_errors++;
4557         }
4558 #endif
4559
4560         DBGBH(("%s rx frame status=%04X size=%d\n",
4561                 info->device_name, status, framesize));
4562         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4563
4564         if (framesize) {
4565                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4566                         framesize -= crc_size;
4567                         crc_size = 0;
4568                 }
4569
4570                 if (framesize > info->max_frame_size + crc_size)
4571                         info->icount.rxlong++;
4572                 else {
4573                         /* copy dma buffer(s) to contiguous temp buffer */
4574                         int copy_count = framesize;
4575                         int i = start;
4576                         unsigned char *p = info->tmp_rbuf;
4577                         info->tmp_rbuf_count = framesize;
4578
4579                         info->icount.rxok++;
4580
4581                         while(copy_count) {
4582                                 int partial_count = min(copy_count, DMABUFSIZE);
4583                                 memcpy(p, info->rbufs[i].buf, partial_count);
4584                                 p += partial_count;
4585                                 copy_count -= partial_count;
4586                                 if (++i == info->rbuf_count)
4587                                         i = 0;
4588                         }
4589
4590                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4591                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4592                                 framesize++;
4593                         }
4594
4595 #if SYNCLINK_GENERIC_HDLC
4596                         if (info->netcount)
4597                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4598                         else
4599 #endif
4600                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4601                 }
4602         }
4603         free_rbufs(info, start, end);
4604         return true;
4605
4606 cleanup:
4607         return false;
4608 }
4609
4610 /*
4611  * pass receive buffer (RAW synchronous mode) to tty layer
4612  * return true if buffer available, otherwise false
4613  */
4614 static bool rx_get_buf(struct slgt_info *info)
4615 {
4616         unsigned int i = info->rbuf_current;
4617         unsigned int count;
4618
4619         if (!desc_complete(info->rbufs[i]))
4620                 return false;
4621         count = desc_count(info->rbufs[i]);
4622         switch(info->params.mode) {
4623         case MGSL_MODE_MONOSYNC:
4624         case MGSL_MODE_BISYNC:
4625                 /* ignore residue in byte synchronous modes */
4626                 if (desc_residue(info->rbufs[i]))
4627                         count--;
4628                 break;
4629         }
4630         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4631         DBGINFO(("rx_get_buf size=%d\n", count));
4632         if (count)
4633                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4634                                   info->flag_buf, count);
4635         free_rbufs(info, i, i);
4636         return true;
4637 }
4638
4639 static void reset_tbufs(struct slgt_info *info)
4640 {
4641         unsigned int i;
4642         info->tbuf_current = 0;
4643         for (i=0 ; i < info->tbuf_count ; i++) {
4644                 info->tbufs[i].status = 0;
4645                 info->tbufs[i].count  = 0;
4646         }
4647 }
4648
4649 /*
4650  * return number of free transmit DMA buffers
4651  */
4652 static unsigned int free_tbuf_count(struct slgt_info *info)
4653 {
4654         unsigned int count = 0;
4655         unsigned int i = info->tbuf_current;
4656
4657         do
4658         {
4659                 if (desc_count(info->tbufs[i]))
4660                         break; /* buffer in use */
4661                 ++count;
4662                 if (++i == info->tbuf_count)
4663                         i=0;
4664         } while (i != info->tbuf_current);
4665
4666         /* if tx DMA active, last zero count buffer is in use */
4667         if (count && (rd_reg32(info, TDCSR) & BIT0))
4668                 --count;
4669
4670         return count;
4671 }
4672
4673 /*
4674  * load transmit DMA buffer(s) with data
4675  */
4676 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4677 {
4678         unsigned short count;
4679         unsigned int i;
4680         struct slgt_desc *d;
4681
4682         if (size == 0)
4683                 return;
4684
4685         DBGDATA(info, buf, size, "tx");
4686
4687         info->tbuf_start = i = info->tbuf_current;
4688
4689         while (size) {
4690                 d = &info->tbufs[i];
4691                 if (++i == info->tbuf_count)
4692                         i = 0;
4693
4694                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4695                 memcpy(d->buf, buf, count);
4696
4697                 size -= count;
4698                 buf  += count;
4699
4700                 /*
4701                  * set EOF bit for last buffer of HDLC frame or
4702                  * for every buffer in raw mode
4703                  */
4704                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4705                     info->params.mode == MGSL_MODE_RAW)
4706                         set_desc_eof(*d, 1);
4707                 else
4708                         set_desc_eof(*d, 0);
4709
4710                 set_desc_count(*d, count);
4711         }
4712
4713         info->tbuf_current = i;
4714 }
4715
4716 static int register_test(struct slgt_info *info)
4717 {
4718         static unsigned short patterns[] =
4719                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4720         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4721         unsigned int i;
4722         int rc = 0;
4723
4724         for (i=0 ; i < count ; i++) {
4725                 wr_reg16(info, TIR, patterns[i]);
4726                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4727                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4728                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4729                         rc = -ENODEV;
4730                         break;
4731                 }
4732         }
4733         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4734         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4735         return rc;
4736 }
4737
4738 static int irq_test(struct slgt_info *info)
4739 {
4740         unsigned long timeout;
4741         unsigned long flags;
4742         struct tty_struct *oldtty = info->port.tty;
4743         u32 speed = info->params.data_rate;
4744
4745         info->params.data_rate = 921600;
4746         info->port.tty = NULL;
4747
4748         spin_lock_irqsave(&info->lock, flags);
4749         async_mode(info);
4750         slgt_irq_on(info, IRQ_TXIDLE);
4751
4752         /* enable transmitter */
4753         wr_reg16(info, TCR,
4754                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4755
4756         /* write one byte and wait for tx idle */
4757         wr_reg16(info, TDR, 0);
4758
4759         /* assume failure */
4760         info->init_error = DiagStatus_IrqFailure;
4761         info->irq_occurred = false;
4762
4763         spin_unlock_irqrestore(&info->lock, flags);
4764
4765         timeout=100;
4766         while(timeout-- && !info->irq_occurred)
4767                 msleep_interruptible(10);
4768
4769         spin_lock_irqsave(&info->lock,flags);
4770         reset_port(info);
4771         spin_unlock_irqrestore(&info->lock,flags);
4772
4773         info->params.data_rate = speed;
4774         info->port.tty = oldtty;
4775
4776         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4777         return info->irq_occurred ? 0 : -ENODEV;
4778 }
4779
4780 static int loopback_test_rx(struct slgt_info *info)
4781 {
4782         unsigned char *src, *dest;
4783         int count;
4784
4785         if (desc_complete(info->rbufs[0])) {
4786                 count = desc_count(info->rbufs[0]);
4787                 src   = info->rbufs[0].buf;
4788                 dest  = info->tmp_rbuf;
4789
4790                 for( ; count ; count-=2, src+=2) {
4791                         /* src=data byte (src+1)=status byte */
4792                         if (!(*(src+1) & (BIT9 + BIT8))) {
4793                                 *dest = *src;
4794                                 dest++;
4795                                 info->tmp_rbuf_count++;
4796                         }
4797                 }
4798                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4799                 return 1;
4800         }
4801         return 0;
4802 }
4803
4804 static int loopback_test(struct slgt_info *info)
4805 {
4806 #define TESTFRAMESIZE 20
4807
4808         unsigned long timeout;
4809         u16 count = TESTFRAMESIZE;
4810         unsigned char buf[TESTFRAMESIZE];
4811         int rc = -ENODEV;
4812         unsigned long flags;
4813
4814         struct tty_struct *oldtty = info->port.tty;
4815         MGSL_PARAMS params;
4816
4817         memcpy(&params, &info->params, sizeof(params));
4818
4819         info->params.mode = MGSL_MODE_ASYNC;
4820         info->params.data_rate = 921600;
4821         info->params.loopback = 1;
4822         info->port.tty = NULL;
4823
4824         /* build and send transmit frame */
4825         for (count = 0; count < TESTFRAMESIZE; ++count)
4826                 buf[count] = (unsigned char)count;
4827
4828         info->tmp_rbuf_count = 0;
4829         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4830
4831         /* program hardware for HDLC and enabled receiver */
4832         spin_lock_irqsave(&info->lock,flags);
4833         async_mode(info);
4834         rx_start(info);
4835         info->tx_count = count;
4836         tx_load(info, buf, count);
4837         tx_start(info);
4838         spin_unlock_irqrestore(&info->lock, flags);
4839
4840         /* wait for receive complete */
4841         for (timeout = 100; timeout; --timeout) {
4842                 msleep_interruptible(10);
4843                 if (loopback_test_rx(info)) {
4844                         rc = 0;
4845                         break;
4846                 }
4847         }
4848
4849         /* verify received frame length and contents */
4850         if (!rc && (info->tmp_rbuf_count != count ||
4851                   memcmp(buf, info->tmp_rbuf, count))) {
4852                 rc = -ENODEV;
4853         }
4854
4855         spin_lock_irqsave(&info->lock,flags);
4856         reset_adapter(info);
4857         spin_unlock_irqrestore(&info->lock,flags);
4858
4859         memcpy(&info->params, &params, sizeof(info->params));
4860         info->port.tty = oldtty;
4861
4862         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4863         return rc;
4864 }
4865
4866 static int adapter_test(struct slgt_info *info)
4867 {
4868         DBGINFO(("testing %s\n", info->device_name));
4869         if (register_test(info) < 0) {
4870                 printk("register test failure %s addr=%08X\n",
4871                         info->device_name, info->phys_reg_addr);
4872         } else if (irq_test(info) < 0) {
4873                 printk("IRQ test failure %s IRQ=%d\n",
4874                         info->device_name, info->irq_level);
4875         } else if (loopback_test(info) < 0) {
4876                 printk("loopback test failure %s\n", info->device_name);
4877         }
4878         return info->init_error;
4879 }
4880
4881 /*
4882  * transmit timeout handler
4883  */
4884 static void tx_timeout(unsigned long context)
4885 {
4886         struct slgt_info *info = (struct slgt_info*)context;
4887         unsigned long flags;
4888
4889         DBGINFO(("%s tx_timeout\n", info->device_name));
4890         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4891                 info->icount.txtimeout++;
4892         }
4893         spin_lock_irqsave(&info->lock,flags);
4894         info->tx_active = false;
4895         info->tx_count = 0;
4896         spin_unlock_irqrestore(&info->lock,flags);
4897
4898 #if SYNCLINK_GENERIC_HDLC
4899         if (info->netcount)
4900                 hdlcdev_tx_done(info);
4901         else
4902 #endif
4903                 bh_transmit(info);
4904 }
4905
4906 /*
4907  * receive buffer polling timer
4908  */
4909 static void rx_timeout(unsigned long context)
4910 {
4911         struct slgt_info *info = (struct slgt_info*)context;
4912         unsigned long flags;
4913
4914         DBGINFO(("%s rx_timeout\n", info->device_name));
4915         spin_lock_irqsave(&info->lock, flags);
4916         info->pending_bh |= BH_RECEIVE;
4917         spin_unlock_irqrestore(&info->lock, flags);
4918         bh_handler(&info->task);
4919 }
4920