drivers/char/drm/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35 #include "r300_reg.h"
  36
  37 #include "radeon_microcode.h"
  38
  39 #define RADEON_FIFO_DEBUG       0
  40
  41 static int radeon_do_cleanup_cp(struct drm_device * dev);
  42
  43 static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  44 {
  45         u32 ret;
  46         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  47         ret = RADEON_READ(R520_MC_IND_DATA);
  48         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  49         return ret;
  50 }
  51
  52 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  53 {
  54         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  55         return RADEON_READ(RS690_MC_DATA);
  56 }
  57
  58 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  59 {
  60
  61         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  62                 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
  63         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  64                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
  65         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  66                 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
  67         else
  68                 return RADEON_READ(RADEON_MC_FB_LOCATION);
  69 }
  70
  71 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
  72 {
  73         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  74                 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
  75         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  76                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
  77         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  78                 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
  79         else
  80                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
  81 }
  82
  83 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
  84 {
  85         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  86                 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
  87         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  88                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
  89         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  90                 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
  91         else
  92                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
  93 }
  94
  95 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
  96 {
  97         drm_radeon_private_t *dev_priv = dev->dev_private;
  98
  99         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 100         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 101 }
 102
 103 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 104 {
 105         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 106         return RADEON_READ(RADEON_PCIE_DATA);
 107 }
 108
 109 static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
 110 {
 111         u32 ret;
 112         RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
 113         ret = RADEON_READ(RADEON_IGPGART_DATA);
 114         RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
 115         return ret;
 116 }
 117
 118 #if RADEON_FIFO_DEBUG
 119 static void radeon_status(drm_radeon_private_t * dev_priv)
 120 {
 121         printk("%s:\n", __func__);
 122         printk("RBBM_STATUS = 0x%08x\n",
 123                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 124         printk("CP_RB_RTPR = 0x%08x\n",
 125                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 126         printk("CP_RB_WTPR = 0x%08x\n",
 127                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 128         printk("AIC_CNTL = 0x%08x\n",
 129                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 130         printk("AIC_STAT = 0x%08x\n",
 131                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 132         printk("AIC_PT_BASE = 0x%08x\n",
 133                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 134         printk("TLB_ADDR = 0x%08x\n",
 135                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 136         printk("TLB_DATA = 0x%08x\n",
 137                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 138 }
 139 #endif
 140
 141 /* ================================================================
 142  * Engine, FIFO control
 143  */
 144
 145 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 146 {
 147         u32 tmp;
 148         int i;
 149
 150         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 151
 152         tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 153         tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 154         RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 155
 156         for (i = 0; i < dev_priv->usec_timeout; i++) {
 157                 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 158                       & RADEON_RB3D_DC_BUSY)) {
 159                         return 0;
 160                 }
 161                 DRM_UDELAY(1);
 162         }
 163
 164 #if RADEON_FIFO_DEBUG
 165         DRM_ERROR("failed!\n");
 166         radeon_status(dev_priv);
 167 #endif
 168         return -EBUSY;
 169 }
 170
 171 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 172 {
 173         int i;
 174
 175         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 176
 177         for (i = 0; i < dev_priv->usec_timeout; i++) {
 178                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 179                              & RADEON_RBBM_FIFOCNT_MASK);
 180                 if (slots >= entries)
 181                         return 0;
 182                 DRM_UDELAY(1);
 183         }
 184
 185 #if RADEON_FIFO_DEBUG
 186         DRM_ERROR("failed!\n");
 187         radeon_status(dev_priv);
 188 #endif
 189         return -EBUSY;
 190 }
 191
 192 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 193 {
 194         int i, ret;
 195
 196         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 197
 198         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 199         if (ret)
 200                 return ret;
 201
 202         for (i = 0; i < dev_priv->usec_timeout; i++) {
 203                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 204                       & RADEON_RBBM_ACTIVE)) {
 205                         radeon_do_pixcache_flush(dev_priv);
 206                         return 0;
 207                 }
 208                 DRM_UDELAY(1);
 209         }
 210
 211 #if RADEON_FIFO_DEBUG
 212         DRM_ERROR("failed!\n");
 213         radeon_status(dev_priv);
 214 #endif
 215         return -EBUSY;
 216 }
 217
 218 /* ================================================================
 219  * CP control, initialization
 220  */
 221
 222 /* Load the microcode for the CP */
 223 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 224 {
 225         int i;
 226         DRM_DEBUG("\n");
 227
 228         radeon_do_wait_for_idle(dev_priv);
 229
 230         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 231         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 232             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 233             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 234             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 235             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 236                 DRM_INFO("Loading R100 Microcode\n");
 237                 for (i = 0; i < 256; i++) {
 238                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 239                                      R100_cp_microcode[i][1]);
 240                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 241                                      R100_cp_microcode[i][0]);
 242                 }
 243         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 244                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 245                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 246                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 247                 DRM_INFO("Loading R200 Microcode\n");
 248                 for (i = 0; i < 256; i++) {
 249                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 250                                      R200_cp_microcode[i][1]);
 251                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 252                                      R200_cp_microcode[i][0]);
 253                 }
 254         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 255                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 256                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 257                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 258                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400)) {
 259                 DRM_INFO("Loading R300 Microcode\n");
 260                 for (i = 0; i < 256; i++) {
 261                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 262                                      R300_cp_microcode[i][1]);
 263                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 264                                      R300_cp_microcode[i][0]);
 265                 }
 266         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 267                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 268                 DRM_INFO("Loading R400 Microcode\n");
 269                 for (i = 0; i < 256; i++) {
 270                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 271                                      R420_cp_microcode[i][1]);
 272                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 273                                      R420_cp_microcode[i][0]);
 274                 }
 275         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 276                 DRM_INFO("Loading RS690 Microcode\n");
 277                 for (i = 0; i < 256; i++) {
 278                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 279                                      RS690_cp_microcode[i][1]);
 280                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 281                                      RS690_cp_microcode[i][0]);
 282                 }
 283         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 284                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 285                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 286                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 287                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 288                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 289                 DRM_INFO("Loading R500 Microcode\n");
 290                 for (i = 0; i < 256; i++) {
 291                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 292                                      R520_cp_microcode[i][1]);
 293                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 294                                      R520_cp_microcode[i][0]);
 295                 }
 296         }
 297 }
 298
 299 /* Flush any pending commands to the CP.  This should only be used just
 300  * prior to a wait for idle, as it informs the engine that the command
 301  * stream is ending.
 302  */
 303 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 304 {
 305         DRM_DEBUG("\n");
 306 #if 0
 307         u32 tmp;
 308
 309         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 310         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 311 #endif
 312 }
 313
 314 /* Wait for the CP to go idle.
 315  */
 316 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 317 {
 318         RING_LOCALS;
 319         DRM_DEBUG("\n");
 320
 321         BEGIN_RING(6);
 322
 323         RADEON_PURGE_CACHE();
 324         RADEON_PURGE_ZCACHE();
 325         RADEON_WAIT_UNTIL_IDLE();
 326
 327         ADVANCE_RING();
 328         COMMIT_RING();
 329
 330         return radeon_do_wait_for_idle(dev_priv);
 331 }
 332
 333 /* Start the Command Processor.
 334  */
 335 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 336 {
 337         RING_LOCALS;
 338         DRM_DEBUG("\n");
 339
 340         radeon_do_wait_for_idle(dev_priv);
 341
 342         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 343
 344         dev_priv->cp_running = 1;
 345
 346         BEGIN_RING(6);
 347
 348         RADEON_PURGE_CACHE();
 349         RADEON_PURGE_ZCACHE();
 350         RADEON_WAIT_UNTIL_IDLE();
 351
 352         ADVANCE_RING();
 353         COMMIT_RING();
 354 }
 355
 356 /* Reset the Command Processor.  This will not flush any pending
 357  * commands, so you must wait for the CP command stream to complete
 358  * before calling this routine.
 359  */
 360 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 361 {
 362         u32 cur_read_ptr;
 363         DRM_DEBUG("\n");
 364
 365         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 366         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 367         SET_RING_HEAD(dev_priv, cur_read_ptr);
 368         dev_priv->ring.tail = cur_read_ptr;
 369 }
 370
 371 /* Stop the Command Processor.  This will not flush any pending
 372  * commands, so you must flush the command stream and wait for the CP
 373  * to go idle before calling this routine.
 374  */
 375 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 376 {
 377         DRM_DEBUG("\n");
 378
 379         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 380
 381         dev_priv->cp_running = 0;
 382 }
 383
 384 /* Reset the engine.  This will stop the CP if it is running.
 385  */
 386 static int radeon_do_engine_reset(struct drm_device * dev)
 387 {
 388         drm_radeon_private_t *dev_priv = dev->dev_private;
 389         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 390         DRM_DEBUG("\n");
 391
 392         radeon_do_pixcache_flush(dev_priv);
 393
 394         if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
 395                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 396                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 397
 398                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 399                                                     RADEON_FORCEON_MCLKA |
 400                                                     RADEON_FORCEON_MCLKB |
 401                                                     RADEON_FORCEON_YCLKA |
 402                                                     RADEON_FORCEON_YCLKB |
 403                                                     RADEON_FORCEON_MC |
 404                                                     RADEON_FORCEON_AIC));
 405
 406                 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 407
 408                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 409                                                       RADEON_SOFT_RESET_CP |
 410                                                       RADEON_SOFT_RESET_HI |
 411                                                       RADEON_SOFT_RESET_SE |
 412                                                       RADEON_SOFT_RESET_RE |
 413                                                       RADEON_SOFT_RESET_PP |
 414                                                       RADEON_SOFT_RESET_E2 |
 415                                                       RADEON_SOFT_RESET_RB));
 416                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
 417                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 418                                                       ~(RADEON_SOFT_RESET_CP |
 419                                                         RADEON_SOFT_RESET_HI |
 420                                                         RADEON_SOFT_RESET_SE |
 421                                                         RADEON_SOFT_RESET_RE |
 422                                                         RADEON_SOFT_RESET_PP |
 423                                                         RADEON_SOFT_RESET_E2 |
 424                                                         RADEON_SOFT_RESET_RB)));
 425                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
 426
 427                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 428                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 429                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 430         }
 431
 432         /* Reset the CP ring */
 433         radeon_do_cp_reset(dev_priv);
 434
 435         /* The CP is no longer running after an engine reset */
 436         dev_priv->cp_running = 0;
 437
 438         /* Reset any pending vertex, indirect buffers */
 439         radeon_freelist_reset(dev);
 440
 441         return 0;
 442 }
 443
 444 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 445                                        drm_radeon_private_t * dev_priv)
 446 {
 447         u32 ring_start, cur_read_ptr;
 448         u32 tmp;
 449
 450         /* Initialize the memory controller. With new memory map, the fb location
 451          * is not changed, it should have been properly initialized already. Part
 452          * of the problem is that the code below is bogus, assuming the GART is
 453          * always appended to the fb which is not necessarily the case
 454          */
 455         if (!dev_priv->new_memmap)
 456                 radeon_write_fb_location(dev_priv,
 457                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 458                              | (dev_priv->fb_location >> 16));
 459
 460 #if __OS_HAS_AGP
 461         if (dev_priv->flags & RADEON_IS_AGP) {
 462                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
 463                 radeon_write_agp_location(dev_priv,
 464                              (((dev_priv->gart_vm_start - 1 +
 465                                 dev_priv->gart_size) & 0xffff0000) |
 466                               (dev_priv->gart_vm_start >> 16)));
 467
 468                 ring_start = (dev_priv->cp_ring->offset
 469                               - dev->agp->base
 470                               + dev_priv->gart_vm_start);
 471         } else
 472 #endif
 473                 ring_start = (dev_priv->cp_ring->offset
 474                               - (unsigned long)dev->sg->virtual
 475                               + dev_priv->gart_vm_start);
 476
 477         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 478
 479         /* Set the write pointer delay */
 480         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 481
 482         /* Initialize the ring buffer's read and write pointers */
 483         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 484         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 485         SET_RING_HEAD(dev_priv, cur_read_ptr);
 486         dev_priv->ring.tail = cur_read_ptr;
 487
 488 #if __OS_HAS_AGP
 489         if (dev_priv->flags & RADEON_IS_AGP) {
 490                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 491                              dev_priv->ring_rptr->offset
 492                              - dev->agp->base + dev_priv->gart_vm_start);
 493         } else
 494 #endif
 495         {
 496                 struct drm_sg_mem *entry = dev->sg;
 497                 unsigned long tmp_ofs, page_ofs;
 498
 499                 tmp_ofs = dev_priv->ring_rptr->offset -
 500                                 (unsigned long)dev->sg->virtual;
 501                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 502
 503                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 504                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 505                           (unsigned long)entry->busaddr[page_ofs],
 506                           entry->handle + tmp_ofs);
 507         }
 508
 509         /* Set ring buffer size */
 510 #ifdef __BIG_ENDIAN
 511         RADEON_WRITE(RADEON_CP_RB_CNTL,
 512                      RADEON_BUF_SWAP_32BIT |
 513                      (dev_priv->ring.fetch_size_l2ow << 18) |
 514                      (dev_priv->ring.rptr_update_l2qw << 8) |
 515                      dev_priv->ring.size_l2qw);
 516 #else
 517         RADEON_WRITE(RADEON_CP_RB_CNTL,
 518                      (dev_priv->ring.fetch_size_l2ow << 18) |
 519                      (dev_priv->ring.rptr_update_l2qw << 8) |
 520                      dev_priv->ring.size_l2qw);
 521 #endif
 522
 523         /* Start with assuming that writeback doesn't work */
 524         dev_priv->writeback_works = 0;
 525
 526         /* Initialize the scratch register pointer.  This will cause
 527          * the scratch register values to be written out to memory
 528          * whenever they are updated.
 529          *
 530          * We simply put this behind the ring read pointer, this works
 531          * with PCI GART as well as (whatever kind of) AGP GART
 532          */
 533         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 534                      + RADEON_SCRATCH_REG_OFFSET);
 535
 536         dev_priv->scratch = ((__volatile__ u32 *)
 537                              dev_priv->ring_rptr->handle +
 538                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 539
 540         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 541
 542         /* Turn on bus mastering */
 543         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 544         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 545
 546         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 547         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
 548
 549         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 550         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
 551                      dev_priv->sarea_priv->last_dispatch);
 552
 553         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 554         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
 555
 556         radeon_do_wait_for_idle(dev_priv);
 557
 558         /* Sync everything up */
 559         RADEON_WRITE(RADEON_ISYNC_CNTL,
 560                      (RADEON_ISYNC_ANY2D_IDLE3D |
 561                       RADEON_ISYNC_ANY3D_IDLE2D |
 562                       RADEON_ISYNC_WAIT_IDLEGUI |
 563                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 564
 565 }
 566
 567 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 568 {
 569         u32 tmp;
 570
 571         /* Writeback doesn't seem to work everywhere, test it here and possibly
 572          * enable it if it appears to work
 573          */
 574         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
 575         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 576
 577         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 578                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
 579                     0xdeadbeef)
 580                         break;
 581                 DRM_UDELAY(1);
 582         }
 583
 584         if (tmp < dev_priv->usec_timeout) {
 585                 dev_priv->writeback_works = 1;
 586                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 587         } else {
 588                 dev_priv->writeback_works = 0;
 589                 DRM_INFO("writeback test failed\n");
 590         }
 591         if (radeon_no_wb == 1) {
 592                 dev_priv->writeback_works = 0;
 593                 DRM_INFO("writeback forced off\n");
 594         }
 595
 596         if (!dev_priv->writeback_works) {
 597                 /* Disable writeback to avoid unnecessary bus master transfer */
 598                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 599                              RADEON_RB_NO_UPDATE);
 600                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 601         }
 602 }
 603
 604 /* Enable or disable IGP GART on the chip */
 605 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 606 {
 607         u32 temp, tmp;
 608
 609         tmp = RADEON_READ(RADEON_AIC_CNTL);
 610         if (on) {
 611                 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
 612                          dev_priv->gart_vm_start,
 613                          (long)dev_priv->gart_info.bus_addr,
 614                          dev_priv->gart_size);
 615
 616                 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
 617                 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
 618                 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
 619                 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
 620                                      dev_priv->gart_info.bus_addr);
 621
 622                 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
 623                 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
 624
 625                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
 626                 dev_priv->gart_size = 32*1024*1024;
 627                 radeon_write_agp_location(dev_priv,
 628                              (((dev_priv->gart_vm_start - 1 +
 629                                dev_priv->gart_size) & 0xffff0000) |
 630                              (dev_priv->gart_vm_start >> 16)));
 631
 632                 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
 633                 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
 634
 635                 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
 636                 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
 637                 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
 638                 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
 639        }
 640 }
 641
 642 /* Enable or disable RS690 GART on the chip */
 643 static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
 644 {
 645         u32 temp;
 646
 647         if (on) {
 648                 DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
 649                           dev_priv->gart_vm_start,
 650                           (long)dev_priv->gart_info.bus_addr,
 651                           dev_priv->gart_size);
 652
 653                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL);
 654                 RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000);
 655
 656                 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
 657                                   RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
 658
 659                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
 660                 RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
 661
 662                 RS690_WRITE_MCIND(RS690_MC_GART_BASE,
 663                                   dev_priv->gart_info.bus_addr);
 664
 665                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
 666                 RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
 667
 668                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
 669                                   (unsigned int)dev_priv->gart_vm_start);
 670
 671                 dev_priv->gart_size = 32*1024*1024;
 672                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 673                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 674
 675                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
 676
 677                 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE);
 678                 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
 679                                   RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
 680
 681                 do {
 682                         temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
 683                         if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
 684                             RS690_MC_GART_CLEAR_DONE)
 685                                 break;
 686                         DRM_UDELAY(1);
 687                 } while (1);
 688
 689                 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
 690                                   RS690_MC_GART_CC_CLEAR);
 691                 do {
 692                         temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
 693                         if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
 694                                    RS690_MC_GART_CLEAR_DONE)
 695                                 break;
 696                         DRM_UDELAY(1);
 697                 } while (1);
 698
 699                 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
 700                                   RS690_MC_GART_CC_NO_CHANGE);
 701         } else {
 702                 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS);
 703         }
 704 }
 705
 706 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 707 {
 708         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 709         if (on) {
 710
 711                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 712                           dev_priv->gart_vm_start,
 713                           (long)dev_priv->gart_info.bus_addr,
 714                           dev_priv->gart_size);
 715                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 716                                   dev_priv->gart_vm_start);
 717                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 718                                   dev_priv->gart_info.bus_addr);
 719                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 720                                   dev_priv->gart_vm_start);
 721                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 722                                   dev_priv->gart_vm_start +
 723                                   dev_priv->gart_size - 1);
 724
 725                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 726
 727                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 728                                   RADEON_PCIE_TX_GART_EN);
 729         } else {
 730                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 731                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 732         }
 733 }
 734
 735 /* Enable or disable PCI GART on the chip */
 736 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 737 {
 738         u32 tmp;
 739
 740         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 741                 radeon_set_rs690gart(dev_priv, on);
 742                 return;
 743         }
 744
 745         if (dev_priv->flags & RADEON_IS_IGPGART) {
 746                 radeon_set_igpgart(dev_priv, on);
 747                 return;
 748         }
 749
 750         if (dev_priv->flags & RADEON_IS_PCIE) {
 751                 radeon_set_pciegart(dev_priv, on);
 752                 return;
 753         }
 754
 755         tmp = RADEON_READ(RADEON_AIC_CNTL);
 756
 757         if (on) {
 758                 RADEON_WRITE(RADEON_AIC_CNTL,
 759                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 760
 761                 /* set PCI GART page-table base address
 762                  */
 763                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 764
 765                 /* set address range for PCI address translate
 766                  */
 767                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 768                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 769                              + dev_priv->gart_size - 1);
 770
 771                 /* Turn off AGP aperture -- is this required for PCI GART?
 772                  */
 773                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 774                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 775         } else {
 776                 RADEON_WRITE(RADEON_AIC_CNTL,
 777                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 778         }
 779 }
 780
 781 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 782 {
 783         drm_radeon_private_t *dev_priv = dev->dev_private;
 784
 785         DRM_DEBUG("\n");
 786
 787         /* if we require new memory map but we don't have it fail */
 788         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 789                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 790                 radeon_do_cleanup_cp(dev);
 791                 return -EINVAL;
 792         }
 793
 794         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
 795                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 796                 dev_priv->flags &= ~RADEON_IS_AGP;
 797         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
 798                    && !init->is_pci) {
 799                 DRM_DEBUG("Restoring AGP flag\n");
 800                 dev_priv->flags |= RADEON_IS_AGP;
 801         }
 802
 803         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
 804                 DRM_ERROR("PCI GART memory not allocated!\n");
 805                 radeon_do_cleanup_cp(dev);
 806                 return -EINVAL;
 807         }
 808
 809         dev_priv->usec_timeout = init->usec_timeout;
 810         if (dev_priv->usec_timeout < 1 ||
 811             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
 812                 DRM_DEBUG("TIMEOUT problem!\n");
 813                 radeon_do_cleanup_cp(dev);
 814                 return -EINVAL;
 815         }
 816
 817         /* Enable vblank on CRTC1 for older X servers
 818          */
 819         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
 820
 821         switch(init->func) {
 822         case RADEON_INIT_R200_CP:
 823                 dev_priv->microcode_version = UCODE_R200;
 824                 break;
 825         case RADEON_INIT_R300_CP:
 826                 dev_priv->microcode_version = UCODE_R300;
 827                 break;
 828         default:
 829                 dev_priv->microcode_version = UCODE_R100;
 830         }
 831
 832         dev_priv->do_boxes = 0;
 833         dev_priv->cp_mode = init->cp_mode;
 834
 835         /* We don't support anything other than bus-mastering ring mode,
 836          * but the ring can be in either AGP or PCI space for the ring
 837          * read pointer.
 838          */
 839         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
 840             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
 841                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
 842                 radeon_do_cleanup_cp(dev);
 843                 return -EINVAL;
 844         }
 845
 846         switch (init->fb_bpp) {
 847         case 16:
 848                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
 849                 break;
 850         case 32:
 851         default:
 852                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 853                 break;
 854         }
 855         dev_priv->front_offset = init->front_offset;
 856         dev_priv->front_pitch = init->front_pitch;
 857         dev_priv->back_offset = init->back_offset;
 858         dev_priv->back_pitch = init->back_pitch;
 859
 860         switch (init->depth_bpp) {
 861         case 16:
 862                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 863                 break;
 864         case 32:
 865         default:
 866                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 867                 break;
 868         }
 869         dev_priv->depth_offset = init->depth_offset;
 870         dev_priv->depth_pitch = init->depth_pitch;
 871
 872         /* Hardware state for depth clears.  Remove this if/when we no
 873          * longer clear the depth buffer with a 3D rectangle.  Hard-code
 874          * all values to prevent unwanted 3D state from slipping through
 875          * and screwing with the clear operation.
 876          */
 877         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
 878                                            (dev_priv->color_fmt << 10) |
 879                                            (dev_priv->microcode_version ==
 880                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
 881
 882         dev_priv->depth_clear.rb3d_zstencilcntl =
 883             (dev_priv->depth_fmt |
 884              RADEON_Z_TEST_ALWAYS |
 885              RADEON_STENCIL_TEST_ALWAYS |
 886              RADEON_STENCIL_S_FAIL_REPLACE |
 887              RADEON_STENCIL_ZPASS_REPLACE |
 888              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
 889
 890         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
 891                                          RADEON_BFACE_SOLID |
 892                                          RADEON_FFACE_SOLID |
 893                                          RADEON_FLAT_SHADE_VTX_LAST |
 894                                          RADEON_DIFFUSE_SHADE_FLAT |
 895                                          RADEON_ALPHA_SHADE_FLAT |
 896                                          RADEON_SPECULAR_SHADE_FLAT |
 897                                          RADEON_FOG_SHADE_FLAT |
 898                                          RADEON_VTX_PIX_CENTER_OGL |
 899                                          RADEON_ROUND_MODE_TRUNC |
 900                                          RADEON_ROUND_PREC_8TH_PIX);
 901
 902
 903         dev_priv->ring_offset = init->ring_offset;
 904         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
 905         dev_priv->buffers_offset = init->buffers_offset;
 906         dev_priv->gart_textures_offset = init->gart_textures_offset;
 907
 908         dev_priv->sarea = drm_getsarea(dev);
 909         if (!dev_priv->sarea) {
 910                 DRM_ERROR("could not find sarea!\n");
 911                 radeon_do_cleanup_cp(dev);
 912                 return -EINVAL;
 913         }
 914
 915         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
 916         if (!dev_priv->cp_ring) {
 917                 DRM_ERROR("could not find cp ring region!\n");
 918                 radeon_do_cleanup_cp(dev);
 919                 return -EINVAL;
 920         }
 921         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
 922         if (!dev_priv->ring_rptr) {
 923                 DRM_ERROR("could not find ring read pointer!\n");
 924                 radeon_do_cleanup_cp(dev);
 925                 return -EINVAL;
 926         }
 927         dev->agp_buffer_token = init->buffers_offset;
 928         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
 929         if (!dev->agp_buffer_map) {
 930                 DRM_ERROR("could not find dma buffer region!\n");
 931                 radeon_do_cleanup_cp(dev);
 932                 return -EINVAL;
 933         }
 934
 935         if (init->gart_textures_offset) {
 936                 dev_priv->gart_textures =
 937                     drm_core_findmap(dev, init->gart_textures_offset);
 938                 if (!dev_priv->gart_textures) {
 939                         DRM_ERROR("could not find GART texture region!\n");
 940                         radeon_do_cleanup_cp(dev);
 941                         return -EINVAL;
 942                 }
 943         }
 944
 945         dev_priv->sarea_priv =
 946             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
 947                                     init->sarea_priv_offset);
 948
 949 #if __OS_HAS_AGP
 950         if (dev_priv->flags & RADEON_IS_AGP) {
 951                 drm_core_ioremap(dev_priv->cp_ring, dev);
 952                 drm_core_ioremap(dev_priv->ring_rptr, dev);
 953                 drm_core_ioremap(dev->agp_buffer_map, dev);
 954                 if (!dev_priv->cp_ring->handle ||
 955                     !dev_priv->ring_rptr->handle ||
 956                     !dev->agp_buffer_map->handle) {
 957                         DRM_ERROR("could not find ioremap agp regions!\n");
 958                         radeon_do_cleanup_cp(dev);
 959                         return -EINVAL;
 960                 }
 961         } else
 962 #endif
 963         {
 964                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
 965                 dev_priv->ring_rptr->handle =
 966                     (void *)dev_priv->ring_rptr->offset;
 967                 dev->agp_buffer_map->handle =
 968                     (void *)dev->agp_buffer_map->offset;
 969
 970                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
 971                           dev_priv->cp_ring->handle);
 972                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
 973                           dev_priv->ring_rptr->handle);
 974                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
 975                           dev->agp_buffer_map->handle);
 976         }
 977
 978         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
 979         dev_priv->fb_size =
 980                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
 981                 - dev_priv->fb_location;
 982
 983         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
 984                                         ((dev_priv->front_offset
 985                                           + dev_priv->fb_location) >> 10));
 986
 987         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
 988                                        ((dev_priv->back_offset
 989                                          + dev_priv->fb_location) >> 10));
 990
 991         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
 992                                         ((dev_priv->depth_offset
 993                                           + dev_priv->fb_location) >> 10));
 994
 995         dev_priv->gart_size = init->gart_size;
 996
 997         /* New let's set the memory map ... */
 998         if (dev_priv->new_memmap) {
 999                 u32 base = 0;
1000
1001                 DRM_INFO("Setting GART location based on new memory map\n");
1002
1003                 /* If using AGP, try to locate the AGP aperture at the same
1004                  * location in the card and on the bus, though we have to
1005                  * align it down.
1006                  */
1007 #if __OS_HAS_AGP
1008                 if (dev_priv->flags & RADEON_IS_AGP) {
1009                         base = dev->agp->base;
1010                         /* Check if valid */
1011                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1012                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1013                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1014                                          dev->agp->base);
1015                                 base = 0;
1016                         }
1017                 }
1018 #endif
1019                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1020                 if (base == 0) {
1021                         base = dev_priv->fb_location + dev_priv->fb_size;
1022                         if (base < dev_priv->fb_location ||
1023                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1024                                 base = dev_priv->fb_location
1025                                         - dev_priv->gart_size;
1026                 }
1027                 dev_priv->gart_vm_start = base & 0xffc00000u;
1028                 if (dev_priv->gart_vm_start != base)
1029                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1030                                  base, dev_priv->gart_vm_start);
1031         } else {
1032                 DRM_INFO("Setting GART location based on old memory map\n");
1033                 dev_priv->gart_vm_start = dev_priv->fb_location +
1034                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1035         }
1036
1037 #if __OS_HAS_AGP
1038         if (dev_priv->flags & RADEON_IS_AGP)
1039                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1040                                                  - dev->agp->base
1041                                                  + dev_priv->gart_vm_start);
1042         else
1043 #endif
1044                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1045                                         - (unsigned long)dev->sg->virtual
1046                                         + dev_priv->gart_vm_start);
1047
1048         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1049         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1050         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1051                   dev_priv->gart_buffers_offset);
1052
1053         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1054         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1055                               + init->ring_size / sizeof(u32));
1056         dev_priv->ring.size = init->ring_size;
1057         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1058
1059         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1060         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1061
1062         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1063         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1064         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1065
1066         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1067
1068 #if __OS_HAS_AGP
1069         if (dev_priv->flags & RADEON_IS_AGP) {
1070                 /* Turn off PCI GART */
1071                 radeon_set_pcigart(dev_priv, 0);
1072         } else
1073 #endif
1074         {
1075                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1076                 /* if we have an offset set from userspace */
1077                 if (dev_priv->pcigart_offset_set) {
1078                         dev_priv->gart_info.bus_addr =
1079                             dev_priv->pcigart_offset + dev_priv->fb_location;
1080                         dev_priv->gart_info.mapping.offset =
1081                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1082                         dev_priv->gart_info.mapping.size =
1083                             dev_priv->gart_info.table_size;
1084
1085                         drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1086                         dev_priv->gart_info.addr =
1087                             dev_priv->gart_info.mapping.handle;
1088
1089                         if (dev_priv->flags & RADEON_IS_PCIE)
1090                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1091                         else
1092                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1093                         dev_priv->gart_info.gart_table_location =
1094                             DRM_ATI_GART_FB;
1095
1096                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1097                                   dev_priv->gart_info.addr,
1098                                   dev_priv->pcigart_offset);
1099                 } else {
1100                         if (dev_priv->flags & RADEON_IS_IGPGART)
1101                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1102                         else
1103                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1104                         dev_priv->gart_info.gart_table_location =
1105                             DRM_ATI_GART_MAIN;
1106                         dev_priv->gart_info.addr = NULL;
1107                         dev_priv->gart_info.bus_addr = 0;
1108                         if (dev_priv->flags & RADEON_IS_PCIE) {
1109                                 DRM_ERROR
1110                                     ("Cannot use PCI Express without GART in FB memory\n");
1111                                 radeon_do_cleanup_cp(dev);
1112                                 return -EINVAL;
1113                         }
1114                 }
1115
1116                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1117                         DRM_ERROR("failed to init PCI GART!\n");
1118                         radeon_do_cleanup_cp(dev);
1119                         return -ENOMEM;
1120                 }
1121
1122                 /* Turn on PCI GART */
1123                 radeon_set_pcigart(dev_priv, 1);
1124         }
1125
1126         radeon_cp_load_microcode(dev_priv);
1127         radeon_cp_init_ring_buffer(dev, dev_priv);
1128
1129         dev_priv->last_buf = 0;
1130
1131         radeon_do_engine_reset(dev);
1132         radeon_test_writeback(dev_priv);
1133
1134         return 0;
1135 }
1136
1137 static int radeon_do_cleanup_cp(struct drm_device * dev)
1138 {
1139         drm_radeon_private_t *dev_priv = dev->dev_private;
1140         DRM_DEBUG("\n");
1141
1142         /* Make sure interrupts are disabled here because the uninstall ioctl
1143          * may not have been called from userspace and after dev_private
1144          * is freed, it's too late.
1145          */
1146         if (dev->irq_enabled)
1147                 drm_irq_uninstall(dev);
1148
1149 #if __OS_HAS_AGP
1150         if (dev_priv->flags & RADEON_IS_AGP) {
1151                 if (dev_priv->cp_ring != NULL) {
1152                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1153                         dev_priv->cp_ring = NULL;
1154                 }
1155                 if (dev_priv->ring_rptr != NULL) {
1156                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1157                         dev_priv->ring_rptr = NULL;
1158                 }
1159                 if (dev->agp_buffer_map != NULL) {
1160                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1161                         dev->agp_buffer_map = NULL;
1162                 }
1163         } else
1164 #endif
1165         {
1166
1167                 if (dev_priv->gart_info.bus_addr) {
1168                         /* Turn off PCI GART */
1169                         radeon_set_pcigart(dev_priv, 0);
1170                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1171                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1172                 }
1173
1174                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1175                 {
1176                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1177                         dev_priv->gart_info.addr = 0;
1178                 }
1179         }
1180         /* only clear to the start of flags */
1181         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1182
1183         return 0;
1184 }
1185
1186 /* This code will reinit the Radeon CP hardware after a resume from disc.
1187  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1188  * here we make sure that all Radeon hardware initialisation is re-done without
1189  * affecting running applications.
1190  *
1191  * Charl P. Botha <http://cpbotha.net>
1192  */
1193 static int radeon_do_resume_cp(struct drm_device * dev)
1194 {
1195         drm_radeon_private_t *dev_priv = dev->dev_private;
1196
1197         if (!dev_priv) {
1198                 DRM_ERROR("Called with no initialization\n");
1199                 return -EINVAL;
1200         }
1201
1202         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1203
1204 #if __OS_HAS_AGP
1205         if (dev_priv->flags & RADEON_IS_AGP) {
1206                 /* Turn off PCI GART */
1207                 radeon_set_pcigart(dev_priv, 0);
1208         } else
1209 #endif
1210         {
1211                 /* Turn on PCI GART */
1212                 radeon_set_pcigart(dev_priv, 1);
1213         }
1214
1215         radeon_cp_load_microcode(dev_priv);
1216         radeon_cp_init_ring_buffer(dev, dev_priv);
1217
1218         radeon_do_engine_reset(dev);
1219
1220         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1221
1222         return 0;
1223 }
1224
1225 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1226 {
1227         drm_radeon_init_t *init = data;
1228
1229         LOCK_TEST_WITH_RETURN(dev, file_priv);
1230
1231         if (init->func == RADEON_INIT_R300_CP)
1232                 r300_init_reg_flags(dev);
1233
1234         switch (init->func) {
1235         case RADEON_INIT_CP:
1236         case RADEON_INIT_R200_CP:
1237         case RADEON_INIT_R300_CP:
1238                 return radeon_do_init_cp(dev, init);
1239         case RADEON_CLEANUP_CP:
1240                 return radeon_do_cleanup_cp(dev);
1241         }
1242
1243         return -EINVAL;
1244 }
1245
1246 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1247 {
1248         drm_radeon_private_t *dev_priv = dev->dev_private;
1249         DRM_DEBUG("\n");
1250
1251         LOCK_TEST_WITH_RETURN(dev, file_priv);
1252
1253         if (dev_priv->cp_running) {
1254                 DRM_DEBUG("while CP running\n");
1255                 return 0;
1256         }
1257         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1258                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1259                           dev_priv->cp_mode);
1260                 return 0;
1261         }
1262
1263         radeon_do_cp_start(dev_priv);
1264
1265         return 0;
1266 }
1267
1268 /* Stop the CP.  The engine must have been idled before calling this
1269  * routine.
1270  */
1271 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1272 {
1273         drm_radeon_private_t *dev_priv = dev->dev_private;
1274         drm_radeon_cp_stop_t *stop = data;
1275         int ret;
1276         DRM_DEBUG("\n");
1277
1278         LOCK_TEST_WITH_RETURN(dev, file_priv);
1279
1280         if (!dev_priv->cp_running)
1281                 return 0;
1282
1283         /* Flush any pending CP commands.  This ensures any outstanding
1284          * commands are exectuted by the engine before we turn it off.
1285          */
1286         if (stop->flush) {
1287                 radeon_do_cp_flush(dev_priv);
1288         }
1289
1290         /* If we fail to make the engine go idle, we return an error
1291          * code so that the DRM ioctl wrapper can try again.
1292          */
1293         if (stop->idle) {
1294                 ret = radeon_do_cp_idle(dev_priv);
1295                 if (ret)
1296                         return ret;
1297         }
1298
1299         /* Finally, we can turn off the CP.  If the engine isn't idle,
1300          * we will get some dropped triangles as they won't be fully
1301          * rendered before the CP is shut down.
1302          */
1303         radeon_do_cp_stop(dev_priv);
1304
1305         /* Reset the engine */
1306         radeon_do_engine_reset(dev);
1307
1308         return 0;
1309 }
1310
1311 void radeon_do_release(struct drm_device * dev)
1312 {
1313         drm_radeon_private_t *dev_priv = dev->dev_private;
1314         int i, ret;
1315
1316         if (dev_priv) {
1317                 if (dev_priv->cp_running) {
1318                         /* Stop the cp */
1319                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1320                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1321 #ifdef __linux__
1322                                 schedule();
1323 #else
1324                                 tsleep(&ret, PZERO, "rdnrel", 1);
1325 #endif
1326                         }
1327                         radeon_do_cp_stop(dev_priv);
1328                         radeon_do_engine_reset(dev);
1329                 }
1330
1331                 /* Disable *all* interrupts */
1332                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1333                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1334
1335                 if (dev_priv->mmio) {   /* remove all surfaces */
1336                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1337                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1338                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1339                                              16 * i, 0);
1340                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1341                                              16 * i, 0);
1342                         }
1343                 }
1344
1345                 /* Free memory heap structures */
1346                 radeon_mem_takedown(&(dev_priv->gart_heap));
1347                 radeon_mem_takedown(&(dev_priv->fb_heap));
1348
1349                 /* deallocate kernel resources */
1350                 radeon_do_cleanup_cp(dev);
1351         }
1352 }
1353
1354 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1355  */
1356 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1357 {
1358         drm_radeon_private_t *dev_priv = dev->dev_private;
1359         DRM_DEBUG("\n");
1360
1361         LOCK_TEST_WITH_RETURN(dev, file_priv);
1362
1363         if (!dev_priv) {
1364                 DRM_DEBUG("called before init done\n");
1365                 return -EINVAL;
1366         }
1367
1368         radeon_do_cp_reset(dev_priv);
1369
1370         /* The CP is no longer running after an engine reset */
1371         dev_priv->cp_running = 0;
1372
1373         return 0;
1374 }
1375
1376 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1377 {
1378         drm_radeon_private_t *dev_priv = dev->dev_private;
1379         DRM_DEBUG("\n");
1380
1381         LOCK_TEST_WITH_RETURN(dev, file_priv);
1382
1383         return radeon_do_cp_idle(dev_priv);
1384 }
1385
1386 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1387  */
1388 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1389 {
1390
1391         return radeon_do_resume_cp(dev);
1392 }
1393
1394 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1395 {
1396         DRM_DEBUG("\n");
1397
1398         LOCK_TEST_WITH_RETURN(dev, file_priv);
1399
1400         return radeon_do_engine_reset(dev);
1401 }
1402
1403 /* ================================================================
1404  * Fullscreen mode
1405  */
1406
1407 /* KW: Deprecated to say the least:
1408  */
1409 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1410 {
1411         return 0;
1412 }
1413
1414 /* ================================================================
1415  * Freelist management
1416  */
1417
1418 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1419  *   bufs until freelist code is used.  Note this hides a problem with
1420  *   the scratch register * (used to keep track of last buffer
1421  *   completed) being written to before * the last buffer has actually
1422  *   completed rendering.
1423  *
1424  * KW:  It's also a good way to find free buffers quickly.
1425  *
1426  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1427  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1428  * we essentially have to do this, else old clients will break.
1429  *
1430  * However, it does leave open a potential deadlock where all the
1431  * buffers are held by other clients, which can't release them because
1432  * they can't get the lock.
1433  */
1434
1435 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1436 {
1437         struct drm_device_dma *dma = dev->dma;
1438         drm_radeon_private_t *dev_priv = dev->dev_private;
1439         drm_radeon_buf_priv_t *buf_priv;
1440         struct drm_buf *buf;
1441         int i, t;
1442         int start;
1443
1444         if (++dev_priv->last_buf >= dma->buf_count)
1445                 dev_priv->last_buf = 0;
1446
1447         start = dev_priv->last_buf;
1448
1449         for (t = 0; t < dev_priv->usec_timeout; t++) {
1450                 u32 done_age = GET_SCRATCH(1);
1451                 DRM_DEBUG("done_age = %d\n", done_age);
1452                 for (i = start; i < dma->buf_count; i++) {
1453                         buf = dma->buflist[i];
1454                         buf_priv = buf->dev_private;
1455                         if (buf->file_priv == NULL || (buf->pending &&
1456                                                        buf_priv->age <=
1457                                                        done_age)) {
1458                                 dev_priv->stats.requested_bufs++;
1459                                 buf->pending = 0;
1460                                 return buf;
1461                         }
1462                         start = 0;
1463                 }
1464
1465                 if (t) {
1466                         DRM_UDELAY(1);
1467                         dev_priv->stats.freelist_loops++;
1468                 }
1469         }
1470
1471         DRM_DEBUG("returning NULL!\n");
1472         return NULL;
1473 }
1474
1475 #if 0
1476 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1477 {
1478         struct drm_device_dma *dma = dev->dma;
1479         drm_radeon_private_t *dev_priv = dev->dev_private;
1480         drm_radeon_buf_priv_t *buf_priv;
1481         struct drm_buf *buf;
1482         int i, t;
1483         int start;
1484         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1485
1486         if (++dev_priv->last_buf >= dma->buf_count)
1487                 dev_priv->last_buf = 0;
1488
1489         start = dev_priv->last_buf;
1490         dev_priv->stats.freelist_loops++;
1491
1492         for (t = 0; t < 2; t++) {
1493                 for (i = start; i < dma->buf_count; i++) {
1494                         buf = dma->buflist[i];
1495                         buf_priv = buf->dev_private;
1496                         if (buf->file_priv == 0 || (buf->pending &&
1497                                                     buf_priv->age <=
1498                                                     done_age)) {
1499                                 dev_priv->stats.requested_bufs++;
1500                                 buf->pending = 0;
1501                                 return buf;
1502                         }
1503                 }
1504                 start = 0;
1505         }
1506
1507         return NULL;
1508 }
1509 #endif
1510
1511 void radeon_freelist_reset(struct drm_device * dev)
1512 {
1513         struct drm_device_dma *dma = dev->dma;
1514         drm_radeon_private_t *dev_priv = dev->dev_private;
1515         int i;
1516
1517         dev_priv->last_buf = 0;
1518         for (i = 0; i < dma->buf_count; i++) {
1519                 struct drm_buf *buf = dma->buflist[i];
1520                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1521                 buf_priv->age = 0;
1522         }
1523 }
1524
1525 /* ================================================================
1526  * CP command submission
1527  */
1528
1529 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1530 {
1531         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1532         int i;
1533         u32 last_head = GET_RING_HEAD(dev_priv);
1534
1535         for (i = 0; i < dev_priv->usec_timeout; i++) {
1536                 u32 head = GET_RING_HEAD(dev_priv);
1537
1538                 ring->space = (head - ring->tail) * sizeof(u32);
1539                 if (ring->space <= 0)
1540                         ring->space += ring->size;
1541                 if (ring->space > n)
1542                         return 0;
1543
1544                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1545
1546                 if (head != last_head)
1547                         i = 0;
1548                 last_head = head;
1549
1550                 DRM_UDELAY(1);
1551         }
1552
1553         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1554 #if RADEON_FIFO_DEBUG
1555         radeon_status(dev_priv);
1556         DRM_ERROR("failed!\n");
1557 #endif
1558         return -EBUSY;
1559 }
1560
1561 static int radeon_cp_get_buffers(struct drm_device *dev,
1562                                  struct drm_file *file_priv,
1563                                  struct drm_dma * d)
1564 {
1565         int i;
1566         struct drm_buf *buf;
1567
1568         for (i = d->granted_count; i < d->request_count; i++) {
1569                 buf = radeon_freelist_get(dev);
1570                 if (!buf)
1571                         return -EBUSY;  /* NOTE: broken client */
1572
1573                 buf->file_priv = file_priv;
1574
1575                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1576                                      sizeof(buf->idx)))
1577                         return -EFAULT;
1578                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1579                                      sizeof(buf->total)))
1580                         return -EFAULT;
1581
1582                 d->granted_count++;
1583         }
1584         return 0;
1585 }
1586
1587 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1588 {
1589         struct drm_device_dma *dma = dev->dma;
1590         int ret = 0;
1591         struct drm_dma *d = data;
1592
1593         LOCK_TEST_WITH_RETURN(dev, file_priv);
1594
1595         /* Please don't send us buffers.
1596          */
1597         if (d->send_count != 0) {
1598                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1599                           DRM_CURRENTPID, d->send_count);
1600                 return -EINVAL;
1601         }
1602
1603         /* We'll send you buffers.
1604          */
1605         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1606                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1607                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1608                 return -EINVAL;
1609         }
1610
1611         d->granted_count = 0;
1612
1613         if (d->request_count) {
1614                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1615         }
1616
1617         return ret;
1618 }
1619
1620 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1621 {
1622         drm_radeon_private_t *dev_priv;
1623         int ret = 0;
1624
1625         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1626         if (dev_priv == NULL)
1627                 return -ENOMEM;
1628
1629         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1630         dev->dev_private = (void *)dev_priv;
1631         dev_priv->flags = flags;
1632
1633         switch (flags & RADEON_FAMILY_MASK) {
1634         case CHIP_R100:
1635         case CHIP_RV200:
1636         case CHIP_R200:
1637         case CHIP_R300:
1638         case CHIP_R350:
1639         case CHIP_R420:
1640         case CHIP_RV410:
1641         case CHIP_RV515:
1642         case CHIP_R520:
1643         case CHIP_RV570:
1644         case CHIP_R580:
1645                 dev_priv->flags |= RADEON_HAS_HIERZ;
1646                 break;
1647         default:
1648                 /* all other chips have no hierarchical z buffer */
1649                 break;
1650         }
1651
1652         if (drm_device_is_agp(dev))
1653                 dev_priv->flags |= RADEON_IS_AGP;
1654         else if (drm_device_is_pcie(dev))
1655                 dev_priv->flags |= RADEON_IS_PCIE;
1656         else
1657                 dev_priv->flags |= RADEON_IS_PCI;
1658
1659         DRM_DEBUG("%s card detected\n",
1660                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1661         return ret;
1662 }
1663
1664 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1665  * have to find them.
1666  */
1667 int radeon_driver_firstopen(struct drm_device *dev)
1668 {
1669         int ret;
1670         drm_local_map_t *map;
1671         drm_radeon_private_t *dev_priv = dev->dev_private;
1672
1673         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1674
1675         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1676                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1677                          _DRM_READ_ONLY, &dev_priv->mmio);
1678         if (ret != 0)
1679                 return ret;
1680
1681         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1682         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1683                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1684                          _DRM_WRITE_COMBINING, &map);
1685         if (ret != 0)
1686                 return ret;
1687
1688         return 0;
1689 }
1690
1691 int radeon_driver_unload(struct drm_device *dev)
1692 {
1693         drm_radeon_private_t *dev_priv = dev->dev_private;
1694
1695         DRM_DEBUG("\n");
1696         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1697
1698         dev->dev_private = NULL;
1699         return 0;
1700 }