drivers/char/drm/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35 #include "r300_reg.h"
  36
  37 #include "radeon_microcode.h"
  38
  39 #define RADEON_FIFO_DEBUG       0
  40
  41 static int radeon_do_cleanup_cp(struct drm_device * dev);
  42
  43 static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  44 {
  45         u32 ret;
  46         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  47         ret = RADEON_READ(R520_MC_IND_DATA);
  48         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  49         return ret;
  50 }
  51
  52 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  53 {
  54         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  55         return RADEON_READ(RS690_MC_DATA);
  56 }
  57
  58 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  59 {
  60
  61         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  62                 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
  63         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  64                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
  65         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  66                 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
  67         else
  68                 return RADEON_READ(RADEON_MC_FB_LOCATION);
  69 }
  70
  71 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
  72 {
  73         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  74                 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
  75         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  76                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
  77         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  78                 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
  79         else
  80                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
  81 }
  82
  83 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
  84 {
  85         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  86                 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
  87         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  88                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
  89         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  90                 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
  91         else
  92                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
  93 }
  94
  95 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
  96 {
  97         drm_radeon_private_t *dev_priv = dev->dev_private;
  98
  99         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 100         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 101 }
 102
 103 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 104 {
 105         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 106         return RADEON_READ(RADEON_PCIE_DATA);
 107 }
 108
 109 static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
 110 {
 111         u32 ret;
 112         RADEON_WRITE(RS400_NB_MC_INDEX, addr & 0x7f);
 113         ret = RADEON_READ(RS400_NB_MC_DATA);
 114         RADEON_WRITE(RS400_NB_MC_INDEX, 0x7f);
 115         return ret;
 116 }
 117
 118 #if RADEON_FIFO_DEBUG
 119 static void radeon_status(drm_radeon_private_t * dev_priv)
 120 {
 121         printk("%s:\n", __func__);
 122         printk("RBBM_STATUS = 0x%08x\n",
 123                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 124         printk("CP_RB_RTPR = 0x%08x\n",
 125                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 126         printk("CP_RB_WTPR = 0x%08x\n",
 127                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 128         printk("AIC_CNTL = 0x%08x\n",
 129                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 130         printk("AIC_STAT = 0x%08x\n",
 131                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 132         printk("AIC_PT_BASE = 0x%08x\n",
 133                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 134         printk("TLB_ADDR = 0x%08x\n",
 135                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 136         printk("TLB_DATA = 0x%08x\n",
 137                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 138 }
 139 #endif
 140
 141 /* ================================================================
 142  * Engine, FIFO control
 143  */
 144
 145 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 146 {
 147         u32 tmp;
 148         int i;
 149
 150         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 151
 152         tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 153         tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 154         RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 155
 156         for (i = 0; i < dev_priv->usec_timeout; i++) {
 157                 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 158                       & RADEON_RB3D_DC_BUSY)) {
 159                         return 0;
 160                 }
 161                 DRM_UDELAY(1);
 162         }
 163
 164 #if RADEON_FIFO_DEBUG
 165         DRM_ERROR("failed!\n");
 166         radeon_status(dev_priv);
 167 #endif
 168         return -EBUSY;
 169 }
 170
 171 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 172 {
 173         int i;
 174
 175         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 176
 177         for (i = 0; i < dev_priv->usec_timeout; i++) {
 178                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 179                              & RADEON_RBBM_FIFOCNT_MASK);
 180                 if (slots >= entries)
 181                         return 0;
 182                 DRM_UDELAY(1);
 183         }
 184
 185 #if RADEON_FIFO_DEBUG
 186         DRM_ERROR("failed!\n");
 187         radeon_status(dev_priv);
 188 #endif
 189         return -EBUSY;
 190 }
 191
 192 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 193 {
 194         int i, ret;
 195
 196         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 197
 198         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 199         if (ret)
 200                 return ret;
 201
 202         for (i = 0; i < dev_priv->usec_timeout; i++) {
 203                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 204                       & RADEON_RBBM_ACTIVE)) {
 205                         radeon_do_pixcache_flush(dev_priv);
 206                         return 0;
 207                 }
 208                 DRM_UDELAY(1);
 209         }
 210
 211 #if RADEON_FIFO_DEBUG
 212         DRM_ERROR("failed!\n");
 213         radeon_status(dev_priv);
 214 #endif
 215         return -EBUSY;
 216 }
 217
 218 /* ================================================================
 219  * CP control, initialization
 220  */
 221
 222 /* Load the microcode for the CP */
 223 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 224 {
 225         int i;
 226         DRM_DEBUG("\n");
 227
 228         radeon_do_wait_for_idle(dev_priv);
 229
 230         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 231         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 232             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 233             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 234             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 235             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 236                 DRM_INFO("Loading R100 Microcode\n");
 237                 for (i = 0; i < 256; i++) {
 238                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 239                                      R100_cp_microcode[i][1]);
 240                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 241                                      R100_cp_microcode[i][0]);
 242                 }
 243         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 244                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 245                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 246                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 247                 DRM_INFO("Loading R200 Microcode\n");
 248                 for (i = 0; i < 256; i++) {
 249                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 250                                      R200_cp_microcode[i][1]);
 251                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 252                                      R200_cp_microcode[i][0]);
 253                 }
 254         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 255                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 256                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 257                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 258                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400)) {
 259                 DRM_INFO("Loading R300 Microcode\n");
 260                 for (i = 0; i < 256; i++) {
 261                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 262                                      R300_cp_microcode[i][1]);
 263                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 264                                      R300_cp_microcode[i][0]);
 265                 }
 266         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 267                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 268                 DRM_INFO("Loading R400 Microcode\n");
 269                 for (i = 0; i < 256; i++) {
 270                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 271                                      R420_cp_microcode[i][1]);
 272                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 273                                      R420_cp_microcode[i][0]);
 274                 }
 275         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 276                 DRM_INFO("Loading RS690 Microcode\n");
 277                 for (i = 0; i < 256; i++) {
 278                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 279                                      RS690_cp_microcode[i][1]);
 280                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 281                                      RS690_cp_microcode[i][0]);
 282                 }
 283         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 284                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 285                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 286                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 287                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 288                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 289                 DRM_INFO("Loading R500 Microcode\n");
 290                 for (i = 0; i < 256; i++) {
 291                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 292                                      R520_cp_microcode[i][1]);
 293                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 294                                      R520_cp_microcode[i][0]);
 295                 }
 296         }
 297 }
 298
 299 /* Flush any pending commands to the CP.  This should only be used just
 300  * prior to a wait for idle, as it informs the engine that the command
 301  * stream is ending.
 302  */
 303 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 304 {
 305         DRM_DEBUG("\n");
 306 #if 0
 307         u32 tmp;
 308
 309         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 310         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 311 #endif
 312 }
 313
 314 /* Wait for the CP to go idle.
 315  */
 316 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 317 {
 318         RING_LOCALS;
 319         DRM_DEBUG("\n");
 320
 321         BEGIN_RING(6);
 322
 323         RADEON_PURGE_CACHE();
 324         RADEON_PURGE_ZCACHE();
 325         RADEON_WAIT_UNTIL_IDLE();
 326
 327         ADVANCE_RING();
 328         COMMIT_RING();
 329
 330         return radeon_do_wait_for_idle(dev_priv);
 331 }
 332
 333 /* Start the Command Processor.
 334  */
 335 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 336 {
 337         RING_LOCALS;
 338         DRM_DEBUG("\n");
 339
 340         radeon_do_wait_for_idle(dev_priv);
 341
 342         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 343
 344         dev_priv->cp_running = 1;
 345
 346         BEGIN_RING(6);
 347
 348         RADEON_PURGE_CACHE();
 349         RADEON_PURGE_ZCACHE();
 350         RADEON_WAIT_UNTIL_IDLE();
 351
 352         ADVANCE_RING();
 353         COMMIT_RING();
 354 }
 355
 356 /* Reset the Command Processor.  This will not flush any pending
 357  * commands, so you must wait for the CP command stream to complete
 358  * before calling this routine.
 359  */
 360 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 361 {
 362         u32 cur_read_ptr;
 363         DRM_DEBUG("\n");
 364
 365         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 366         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 367         SET_RING_HEAD(dev_priv, cur_read_ptr);
 368         dev_priv->ring.tail = cur_read_ptr;
 369 }
 370
 371 /* Stop the Command Processor.  This will not flush any pending
 372  * commands, so you must flush the command stream and wait for the CP
 373  * to go idle before calling this routine.
 374  */
 375 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 376 {
 377         DRM_DEBUG("\n");
 378
 379         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 380
 381         dev_priv->cp_running = 0;
 382 }
 383
 384 /* Reset the engine.  This will stop the CP if it is running.
 385  */
 386 static int radeon_do_engine_reset(struct drm_device * dev)
 387 {
 388         drm_radeon_private_t *dev_priv = dev->dev_private;
 389         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 390         DRM_DEBUG("\n");
 391
 392         radeon_do_pixcache_flush(dev_priv);
 393
 394         if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
 395                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 396                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 397
 398                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 399                                                     RADEON_FORCEON_MCLKA |
 400                                                     RADEON_FORCEON_MCLKB |
 401                                                     RADEON_FORCEON_YCLKA |
 402                                                     RADEON_FORCEON_YCLKB |
 403                                                     RADEON_FORCEON_MC |
 404                                                     RADEON_FORCEON_AIC));
 405
 406                 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 407
 408                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 409                                                       RADEON_SOFT_RESET_CP |
 410                                                       RADEON_SOFT_RESET_HI |
 411                                                       RADEON_SOFT_RESET_SE |
 412                                                       RADEON_SOFT_RESET_RE |
 413                                                       RADEON_SOFT_RESET_PP |
 414                                                       RADEON_SOFT_RESET_E2 |
 415                                                       RADEON_SOFT_RESET_RB));
 416                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
 417                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 418                                                       ~(RADEON_SOFT_RESET_CP |
 419                                                         RADEON_SOFT_RESET_HI |
 420                                                         RADEON_SOFT_RESET_SE |
 421                                                         RADEON_SOFT_RESET_RE |
 422                                                         RADEON_SOFT_RESET_PP |
 423                                                         RADEON_SOFT_RESET_E2 |
 424                                                         RADEON_SOFT_RESET_RB)));
 425                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
 426
 427                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 428                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 429                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 430         }
 431
 432         /* Reset the CP ring */
 433         radeon_do_cp_reset(dev_priv);
 434
 435         /* The CP is no longer running after an engine reset */
 436         dev_priv->cp_running = 0;
 437
 438         /* Reset any pending vertex, indirect buffers */
 439         radeon_freelist_reset(dev);
 440
 441         return 0;
 442 }
 443
 444 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 445                                        drm_radeon_private_t * dev_priv)
 446 {
 447         u32 ring_start, cur_read_ptr;
 448         u32 tmp;
 449
 450         /* Initialize the memory controller. With new memory map, the fb location
 451          * is not changed, it should have been properly initialized already. Part
 452          * of the problem is that the code below is bogus, assuming the GART is
 453          * always appended to the fb which is not necessarily the case
 454          */
 455         if (!dev_priv->new_memmap)
 456                 radeon_write_fb_location(dev_priv,
 457                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 458                              | (dev_priv->fb_location >> 16));
 459
 460 #if __OS_HAS_AGP
 461         if (dev_priv->flags & RADEON_IS_AGP) {
 462                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
 463                 radeon_write_agp_location(dev_priv,
 464                              (((dev_priv->gart_vm_start - 1 +
 465                                 dev_priv->gart_size) & 0xffff0000) |
 466                               (dev_priv->gart_vm_start >> 16)));
 467
 468                 ring_start = (dev_priv->cp_ring->offset
 469                               - dev->agp->base
 470                               + dev_priv->gart_vm_start);
 471         } else
 472 #endif
 473                 ring_start = (dev_priv->cp_ring->offset
 474                               - (unsigned long)dev->sg->virtual
 475                               + dev_priv->gart_vm_start);
 476
 477         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 478
 479         /* Set the write pointer delay */
 480         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 481
 482         /* Initialize the ring buffer's read and write pointers */
 483         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 484         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 485         SET_RING_HEAD(dev_priv, cur_read_ptr);
 486         dev_priv->ring.tail = cur_read_ptr;
 487
 488 #if __OS_HAS_AGP
 489         if (dev_priv->flags & RADEON_IS_AGP) {
 490                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 491                              dev_priv->ring_rptr->offset
 492                              - dev->agp->base + dev_priv->gart_vm_start);
 493         } else
 494 #endif
 495         {
 496                 struct drm_sg_mem *entry = dev->sg;
 497                 unsigned long tmp_ofs, page_ofs;
 498
 499                 tmp_ofs = dev_priv->ring_rptr->offset -
 500                                 (unsigned long)dev->sg->virtual;
 501                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 502
 503                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 504                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 505                           (unsigned long)entry->busaddr[page_ofs],
 506                           entry->handle + tmp_ofs);
 507         }
 508
 509         /* Set ring buffer size */
 510 #ifdef __BIG_ENDIAN
 511         RADEON_WRITE(RADEON_CP_RB_CNTL,
 512                      RADEON_BUF_SWAP_32BIT |
 513                      (dev_priv->ring.fetch_size_l2ow << 18) |
 514                      (dev_priv->ring.rptr_update_l2qw << 8) |
 515                      dev_priv->ring.size_l2qw);
 516 #else
 517         RADEON_WRITE(RADEON_CP_RB_CNTL,
 518                      (dev_priv->ring.fetch_size_l2ow << 18) |
 519                      (dev_priv->ring.rptr_update_l2qw << 8) |
 520                      dev_priv->ring.size_l2qw);
 521 #endif
 522
 523         /* Start with assuming that writeback doesn't work */
 524         dev_priv->writeback_works = 0;
 525
 526         /* Initialize the scratch register pointer.  This will cause
 527          * the scratch register values to be written out to memory
 528          * whenever they are updated.
 529          *
 530          * We simply put this behind the ring read pointer, this works
 531          * with PCI GART as well as (whatever kind of) AGP GART
 532          */
 533         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 534                      + RADEON_SCRATCH_REG_OFFSET);
 535
 536         dev_priv->scratch = ((__volatile__ u32 *)
 537                              dev_priv->ring_rptr->handle +
 538                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 539
 540         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 541
 542         /* Turn on bus mastering */
 543         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 544         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 545
 546         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 547         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
 548
 549         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 550         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
 551                      dev_priv->sarea_priv->last_dispatch);
 552
 553         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 554         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
 555
 556         radeon_do_wait_for_idle(dev_priv);
 557
 558         /* Sync everything up */
 559         RADEON_WRITE(RADEON_ISYNC_CNTL,
 560                      (RADEON_ISYNC_ANY2D_IDLE3D |
 561                       RADEON_ISYNC_ANY3D_IDLE2D |
 562                       RADEON_ISYNC_WAIT_IDLEGUI |
 563                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 564
 565 }
 566
 567 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 568 {
 569         u32 tmp;
 570
 571         /* Writeback doesn't seem to work everywhere, test it here and possibly
 572          * enable it if it appears to work
 573          */
 574         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
 575         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 576
 577         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 578                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
 579                     0xdeadbeef)
 580                         break;
 581                 DRM_UDELAY(1);
 582         }
 583
 584         if (tmp < dev_priv->usec_timeout) {
 585                 dev_priv->writeback_works = 1;
 586                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 587         } else {
 588                 dev_priv->writeback_works = 0;
 589                 DRM_INFO("writeback test failed\n");
 590         }
 591         if (radeon_no_wb == 1) {
 592                 dev_priv->writeback_works = 0;
 593                 DRM_INFO("writeback forced off\n");
 594         }
 595
 596         if (!dev_priv->writeback_works) {
 597                 /* Disable writeback to avoid unnecessary bus master transfer */
 598                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 599                              RADEON_RB_NO_UPDATE);
 600                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 601         }
 602 }
 603
 604 /* Enable or disable IGP GART on the chip */
 605 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 606 {
 607         u32 temp, tmp;
 608
 609         tmp = RADEON_READ(RADEON_AIC_CNTL);
 610         if (on) {
 611                 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
 612                          dev_priv->gart_vm_start,
 613                          (long)dev_priv->gart_info.bus_addr,
 614                          dev_priv->gart_size);
 615
 616                 RADEON_WRITE_IGPGART(RS400_MC_MISC_CNTL, RS400_GART_INDEX_REG_EN);
 617                 RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
 618                                                                     RS400_VA_SIZE_32MB));
 619                 RADEON_WRITE_IGPGART(RS400_GART_FEATURE_ID, (RS400_HANG_EN |
 620                                                              RS400_TLB_ENABLE |
 621                                                              RS400_GTW_LAC_EN |
 622                                                              RS400_1LEVEL_GART));
 623                 RADEON_WRITE_IGPGART(RS400_GART_BASE,
 624                                      dev_priv->gart_info.bus_addr);
 625
 626                 temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_MODE_CNTL);
 627                 RADEON_WRITE_IGPGART(RS400_AGP_MODE_CNTL, temp);
 628
 629                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
 630                 dev_priv->gart_size = 32*1024*1024;
 631                 radeon_write_agp_location(dev_priv,
 632                              (((dev_priv->gart_vm_start - 1 +
 633                                dev_priv->gart_size) & 0xffff0000) |
 634                              (dev_priv->gart_vm_start >> 16)));
 635
 636                 temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE);
 637                 RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, temp);
 638
 639                 RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL);
 640                 RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, RS400_GART_CACHE_INVALIDATE);
 641                 RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL);
 642                 RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, 0);
 643        }
 644 }
 645
 646 /* Enable or disable RS690 GART on the chip */
 647 static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
 648 {
 649         u32 temp;
 650
 651         if (on) {
 652                 DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
 653                           dev_priv->gart_vm_start,
 654                           (long)dev_priv->gart_info.bus_addr,
 655                           dev_priv->gart_size);
 656
 657                 temp = RS690_READ_MCIND(dev_priv, RS400_MC_MISC_CNTL);
 658                 RS690_WRITE_MCIND(RS400_MC_MISC_CNTL, (RS400_GART_INDEX_REG_EN |
 659                                                        RS690_BLOCK_GFX_D3_EN));
 660
 661                 RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
 662                                                                  RS400_VA_SIZE_32MB));
 663
 664                 temp = RS690_READ_MCIND(dev_priv, RS400_GART_FEATURE_ID);
 665                 RS690_WRITE_MCIND(RS400_GART_FEATURE_ID, (RS400_HANG_EN |
 666                                                           RS400_TLB_ENABLE |
 667                                                           RS400_GTW_LAC_EN |
 668                                                           RS400_1LEVEL_GART));
 669
 670                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 671                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 672                 RS690_WRITE_MCIND(RS400_GART_BASE, temp);
 673
 674                 temp = RS690_READ_MCIND(dev_priv, RS400_AGP_MODE_CNTL);
 675                 RS690_WRITE_MCIND(RS400_AGP_MODE_CNTL, ((1 << RS400_REQ_TYPE_SNOOP_SHIFT) |
 676                                                         RS400_REQ_TYPE_SNOOP_DIS));
 677
 678                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
 679                                   (unsigned int)dev_priv->gart_vm_start);
 680
 681                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
 682
 683                 dev_priv->gart_size = 32*1024*1024;
 684                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 685                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 686
 687                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
 688
 689                 temp = RS690_READ_MCIND(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE);
 690                 RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
 691                                                                  RS400_VA_SIZE_32MB));
 692
 693                 do {
 694                         temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL);
 695                         if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
 696                             RS690_MC_GART_CLEAR_DONE)
 697                                 break;
 698                         DRM_UDELAY(1);
 699                 } while (1);
 700
 701                 RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL,
 702                                   RS400_GART_CACHE_INVALIDATE);
 703
 704                 do {
 705                         temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL);
 706                         if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
 707                             RS690_MC_GART_CLEAR_DONE)
 708                                 break;
 709                         DRM_UDELAY(1);
 710                 } while (1);
 711
 712                 RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL, 0);
 713         } else {
 714                 RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, 0);
 715         }
 716 }
 717
 718 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 719 {
 720         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 721         if (on) {
 722
 723                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 724                           dev_priv->gart_vm_start,
 725                           (long)dev_priv->gart_info.bus_addr,
 726                           dev_priv->gart_size);
 727                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 728                                   dev_priv->gart_vm_start);
 729                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 730                                   dev_priv->gart_info.bus_addr);
 731                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 732                                   dev_priv->gart_vm_start);
 733                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 734                                   dev_priv->gart_vm_start +
 735                                   dev_priv->gart_size - 1);
 736
 737                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 738
 739                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 740                                   RADEON_PCIE_TX_GART_EN);
 741         } else {
 742                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 743                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 744         }
 745 }
 746
 747 /* Enable or disable PCI GART on the chip */
 748 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 749 {
 750         u32 tmp;
 751
 752         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 753                 radeon_set_rs690gart(dev_priv, on);
 754                 return;
 755         }
 756
 757         if (dev_priv->flags & RADEON_IS_IGPGART) {
 758                 radeon_set_igpgart(dev_priv, on);
 759                 return;
 760         }
 761
 762         if (dev_priv->flags & RADEON_IS_PCIE) {
 763                 radeon_set_pciegart(dev_priv, on);
 764                 return;
 765         }
 766
 767         tmp = RADEON_READ(RADEON_AIC_CNTL);
 768
 769         if (on) {
 770                 RADEON_WRITE(RADEON_AIC_CNTL,
 771                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 772
 773                 /* set PCI GART page-table base address
 774                  */
 775                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 776
 777                 /* set address range for PCI address translate
 778                  */
 779                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 780                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 781                              + dev_priv->gart_size - 1);
 782
 783                 /* Turn off AGP aperture -- is this required for PCI GART?
 784                  */
 785                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 786                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 787         } else {
 788                 RADEON_WRITE(RADEON_AIC_CNTL,
 789                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 790         }
 791 }
 792
 793 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 794 {
 795         drm_radeon_private_t *dev_priv = dev->dev_private;
 796
 797         DRM_DEBUG("\n");
 798
 799         /* if we require new memory map but we don't have it fail */
 800         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 801                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 802                 radeon_do_cleanup_cp(dev);
 803                 return -EINVAL;
 804         }
 805
 806         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
 807                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 808                 dev_priv->flags &= ~RADEON_IS_AGP;
 809         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
 810                    && !init->is_pci) {
 811                 DRM_DEBUG("Restoring AGP flag\n");
 812                 dev_priv->flags |= RADEON_IS_AGP;
 813         }
 814
 815         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
 816                 DRM_ERROR("PCI GART memory not allocated!\n");
 817                 radeon_do_cleanup_cp(dev);
 818                 return -EINVAL;
 819         }
 820
 821         dev_priv->usec_timeout = init->usec_timeout;
 822         if (dev_priv->usec_timeout < 1 ||
 823             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
 824                 DRM_DEBUG("TIMEOUT problem!\n");
 825                 radeon_do_cleanup_cp(dev);
 826                 return -EINVAL;
 827         }
 828
 829         /* Enable vblank on CRTC1 for older X servers
 830          */
 831         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
 832
 833         switch(init->func) {
 834         case RADEON_INIT_R200_CP:
 835                 dev_priv->microcode_version = UCODE_R200;
 836                 break;
 837         case RADEON_INIT_R300_CP:
 838                 dev_priv->microcode_version = UCODE_R300;
 839                 break;
 840         default:
 841                 dev_priv->microcode_version = UCODE_R100;
 842         }
 843
 844         dev_priv->do_boxes = 0;
 845         dev_priv->cp_mode = init->cp_mode;
 846
 847         /* We don't support anything other than bus-mastering ring mode,
 848          * but the ring can be in either AGP or PCI space for the ring
 849          * read pointer.
 850          */
 851         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
 852             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
 853                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
 854                 radeon_do_cleanup_cp(dev);
 855                 return -EINVAL;
 856         }
 857
 858         switch (init->fb_bpp) {
 859         case 16:
 860                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
 861                 break;
 862         case 32:
 863         default:
 864                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 865                 break;
 866         }
 867         dev_priv->front_offset = init->front_offset;
 868         dev_priv->front_pitch = init->front_pitch;
 869         dev_priv->back_offset = init->back_offset;
 870         dev_priv->back_pitch = init->back_pitch;
 871
 872         switch (init->depth_bpp) {
 873         case 16:
 874                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 875                 break;
 876         case 32:
 877         default:
 878                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 879                 break;
 880         }
 881         dev_priv->depth_offset = init->depth_offset;
 882         dev_priv->depth_pitch = init->depth_pitch;
 883
 884         /* Hardware state for depth clears.  Remove this if/when we no
 885          * longer clear the depth buffer with a 3D rectangle.  Hard-code
 886          * all values to prevent unwanted 3D state from slipping through
 887          * and screwing with the clear operation.
 888          */
 889         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
 890                                            (dev_priv->color_fmt << 10) |
 891                                            (dev_priv->microcode_version ==
 892                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
 893
 894         dev_priv->depth_clear.rb3d_zstencilcntl =
 895             (dev_priv->depth_fmt |
 896              RADEON_Z_TEST_ALWAYS |
 897              RADEON_STENCIL_TEST_ALWAYS |
 898              RADEON_STENCIL_S_FAIL_REPLACE |
 899              RADEON_STENCIL_ZPASS_REPLACE |
 900              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
 901
 902         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
 903                                          RADEON_BFACE_SOLID |
 904                                          RADEON_FFACE_SOLID |
 905                                          RADEON_FLAT_SHADE_VTX_LAST |
 906                                          RADEON_DIFFUSE_SHADE_FLAT |
 907                                          RADEON_ALPHA_SHADE_FLAT |
 908                                          RADEON_SPECULAR_SHADE_FLAT |
 909                                          RADEON_FOG_SHADE_FLAT |
 910                                          RADEON_VTX_PIX_CENTER_OGL |
 911                                          RADEON_ROUND_MODE_TRUNC |
 912                                          RADEON_ROUND_PREC_8TH_PIX);
 913
 914
 915         dev_priv->ring_offset = init->ring_offset;
 916         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
 917         dev_priv->buffers_offset = init->buffers_offset;
 918         dev_priv->gart_textures_offset = init->gart_textures_offset;
 919
 920         dev_priv->sarea = drm_getsarea(dev);
 921         if (!dev_priv->sarea) {
 922                 DRM_ERROR("could not find sarea!\n");
 923                 radeon_do_cleanup_cp(dev);
 924                 return -EINVAL;
 925         }
 926
 927         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
 928         if (!dev_priv->cp_ring) {
 929                 DRM_ERROR("could not find cp ring region!\n");
 930                 radeon_do_cleanup_cp(dev);
 931                 return -EINVAL;
 932         }
 933         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
 934         if (!dev_priv->ring_rptr) {
 935                 DRM_ERROR("could not find ring read pointer!\n");
 936                 radeon_do_cleanup_cp(dev);
 937                 return -EINVAL;
 938         }
 939         dev->agp_buffer_token = init->buffers_offset;
 940         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
 941         if (!dev->agp_buffer_map) {
 942                 DRM_ERROR("could not find dma buffer region!\n");
 943                 radeon_do_cleanup_cp(dev);
 944                 return -EINVAL;
 945         }
 946
 947         if (init->gart_textures_offset) {
 948                 dev_priv->gart_textures =
 949                     drm_core_findmap(dev, init->gart_textures_offset);
 950                 if (!dev_priv->gart_textures) {
 951                         DRM_ERROR("could not find GART texture region!\n");
 952                         radeon_do_cleanup_cp(dev);
 953                         return -EINVAL;
 954                 }
 955         }
 956
 957         dev_priv->sarea_priv =
 958             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
 959                                     init->sarea_priv_offset);
 960
 961 #if __OS_HAS_AGP
 962         if (dev_priv->flags & RADEON_IS_AGP) {
 963                 drm_core_ioremap(dev_priv->cp_ring, dev);
 964                 drm_core_ioremap(dev_priv->ring_rptr, dev);
 965                 drm_core_ioremap(dev->agp_buffer_map, dev);
 966                 if (!dev_priv->cp_ring->handle ||
 967                     !dev_priv->ring_rptr->handle ||
 968                     !dev->agp_buffer_map->handle) {
 969                         DRM_ERROR("could not find ioremap agp regions!\n");
 970                         radeon_do_cleanup_cp(dev);
 971                         return -EINVAL;
 972                 }
 973         } else
 974 #endif
 975         {
 976                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
 977                 dev_priv->ring_rptr->handle =
 978                     (void *)dev_priv->ring_rptr->offset;
 979                 dev->agp_buffer_map->handle =
 980                     (void *)dev->agp_buffer_map->offset;
 981
 982                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
 983                           dev_priv->cp_ring->handle);
 984                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
 985                           dev_priv->ring_rptr->handle);
 986                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
 987                           dev->agp_buffer_map->handle);
 988         }
 989
 990         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
 991         dev_priv->fb_size =
 992                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
 993                 - dev_priv->fb_location;
 994
 995         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
 996                                         ((dev_priv->front_offset
 997                                           + dev_priv->fb_location) >> 10));
 998
 999         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1000                                        ((dev_priv->back_offset
1001                                          + dev_priv->fb_location) >> 10));
1002
1003         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1004                                         ((dev_priv->depth_offset
1005                                           + dev_priv->fb_location) >> 10));
1006
1007         dev_priv->gart_size = init->gart_size;
1008
1009         /* New let's set the memory map ... */
1010         if (dev_priv->new_memmap) {
1011                 u32 base = 0;
1012
1013                 DRM_INFO("Setting GART location based on new memory map\n");
1014
1015                 /* If using AGP, try to locate the AGP aperture at the same
1016                  * location in the card and on the bus, though we have to
1017                  * align it down.
1018                  */
1019 #if __OS_HAS_AGP
1020                 if (dev_priv->flags & RADEON_IS_AGP) {
1021                         base = dev->agp->base;
1022                         /* Check if valid */
1023                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1024                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1025                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1026                                          dev->agp->base);
1027                                 base = 0;
1028                         }
1029                 }
1030 #endif
1031                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1032                 if (base == 0) {
1033                         base = dev_priv->fb_location + dev_priv->fb_size;
1034                         if (base < dev_priv->fb_location ||
1035                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1036                                 base = dev_priv->fb_location
1037                                         - dev_priv->gart_size;
1038                 }
1039                 dev_priv->gart_vm_start = base & 0xffc00000u;
1040                 if (dev_priv->gart_vm_start != base)
1041                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1042                                  base, dev_priv->gart_vm_start);
1043         } else {
1044                 DRM_INFO("Setting GART location based on old memory map\n");
1045                 dev_priv->gart_vm_start = dev_priv->fb_location +
1046                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1047         }
1048
1049 #if __OS_HAS_AGP
1050         if (dev_priv->flags & RADEON_IS_AGP)
1051                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1052                                                  - dev->agp->base
1053                                                  + dev_priv->gart_vm_start);
1054         else
1055 #endif
1056                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1057                                         - (unsigned long)dev->sg->virtual
1058                                         + dev_priv->gart_vm_start);
1059
1060         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1061         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1062         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1063                   dev_priv->gart_buffers_offset);
1064
1065         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1066         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1067                               + init->ring_size / sizeof(u32));
1068         dev_priv->ring.size = init->ring_size;
1069         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1070
1071         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1072         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1073
1074         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1075         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1076         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1077
1078         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1079
1080 #if __OS_HAS_AGP
1081         if (dev_priv->flags & RADEON_IS_AGP) {
1082                 /* Turn off PCI GART */
1083                 radeon_set_pcigart(dev_priv, 0);
1084         } else
1085 #endif
1086         {
1087                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1088                 /* if we have an offset set from userspace */
1089                 if (dev_priv->pcigart_offset_set) {
1090                         dev_priv->gart_info.bus_addr =
1091                             dev_priv->pcigart_offset + dev_priv->fb_location;
1092                         dev_priv->gart_info.mapping.offset =
1093                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1094                         dev_priv->gart_info.mapping.size =
1095                             dev_priv->gart_info.table_size;
1096
1097                         drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1098                         dev_priv->gart_info.addr =
1099                             dev_priv->gart_info.mapping.handle;
1100
1101                         if (dev_priv->flags & RADEON_IS_PCIE)
1102                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1103                         else
1104                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1105                         dev_priv->gart_info.gart_table_location =
1106                             DRM_ATI_GART_FB;
1107
1108                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1109                                   dev_priv->gart_info.addr,
1110                                   dev_priv->pcigart_offset);
1111                 } else {
1112                         if (dev_priv->flags & RADEON_IS_IGPGART)
1113                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1114                         else
1115                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1116                         dev_priv->gart_info.gart_table_location =
1117                             DRM_ATI_GART_MAIN;
1118                         dev_priv->gart_info.addr = NULL;
1119                         dev_priv->gart_info.bus_addr = 0;
1120                         if (dev_priv->flags & RADEON_IS_PCIE) {
1121                                 DRM_ERROR
1122                                     ("Cannot use PCI Express without GART in FB memory\n");
1123                                 radeon_do_cleanup_cp(dev);
1124                                 return -EINVAL;
1125                         }
1126                 }
1127
1128                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1129                         DRM_ERROR("failed to init PCI GART!\n");
1130                         radeon_do_cleanup_cp(dev);
1131                         return -ENOMEM;
1132                 }
1133
1134                 /* Turn on PCI GART */
1135                 radeon_set_pcigart(dev_priv, 1);
1136         }
1137
1138         radeon_cp_load_microcode(dev_priv);
1139         radeon_cp_init_ring_buffer(dev, dev_priv);
1140
1141         dev_priv->last_buf = 0;
1142
1143         radeon_do_engine_reset(dev);
1144         radeon_test_writeback(dev_priv);
1145
1146         return 0;
1147 }
1148
1149 static int radeon_do_cleanup_cp(struct drm_device * dev)
1150 {
1151         drm_radeon_private_t *dev_priv = dev->dev_private;
1152         DRM_DEBUG("\n");
1153
1154         /* Make sure interrupts are disabled here because the uninstall ioctl
1155          * may not have been called from userspace and after dev_private
1156          * is freed, it's too late.
1157          */
1158         if (dev->irq_enabled)
1159                 drm_irq_uninstall(dev);
1160
1161 #if __OS_HAS_AGP
1162         if (dev_priv->flags & RADEON_IS_AGP) {
1163                 if (dev_priv->cp_ring != NULL) {
1164                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1165                         dev_priv->cp_ring = NULL;
1166                 }
1167                 if (dev_priv->ring_rptr != NULL) {
1168                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1169                         dev_priv->ring_rptr = NULL;
1170                 }
1171                 if (dev->agp_buffer_map != NULL) {
1172                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1173                         dev->agp_buffer_map = NULL;
1174                 }
1175         } else
1176 #endif
1177         {
1178
1179                 if (dev_priv->gart_info.bus_addr) {
1180                         /* Turn off PCI GART */
1181                         radeon_set_pcigart(dev_priv, 0);
1182                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1183                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1184                 }
1185
1186                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1187                 {
1188                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1189                         dev_priv->gart_info.addr = 0;
1190                 }
1191         }
1192         /* only clear to the start of flags */
1193         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1194
1195         return 0;
1196 }
1197
1198 /* This code will reinit the Radeon CP hardware after a resume from disc.
1199  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1200  * here we make sure that all Radeon hardware initialisation is re-done without
1201  * affecting running applications.
1202  *
1203  * Charl P. Botha <http://cpbotha.net>
1204  */
1205 static int radeon_do_resume_cp(struct drm_device * dev)
1206 {
1207         drm_radeon_private_t *dev_priv = dev->dev_private;
1208
1209         if (!dev_priv) {
1210                 DRM_ERROR("Called with no initialization\n");
1211                 return -EINVAL;
1212         }
1213
1214         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1215
1216 #if __OS_HAS_AGP
1217         if (dev_priv->flags & RADEON_IS_AGP) {
1218                 /* Turn off PCI GART */
1219                 radeon_set_pcigart(dev_priv, 0);
1220         } else
1221 #endif
1222         {
1223                 /* Turn on PCI GART */
1224                 radeon_set_pcigart(dev_priv, 1);
1225         }
1226
1227         radeon_cp_load_microcode(dev_priv);
1228         radeon_cp_init_ring_buffer(dev, dev_priv);
1229
1230         radeon_do_engine_reset(dev);
1231
1232         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1233
1234         return 0;
1235 }
1236
1237 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1238 {
1239         drm_radeon_init_t *init = data;
1240
1241         LOCK_TEST_WITH_RETURN(dev, file_priv);
1242
1243         if (init->func == RADEON_INIT_R300_CP)
1244                 r300_init_reg_flags(dev);
1245
1246         switch (init->func) {
1247         case RADEON_INIT_CP:
1248         case RADEON_INIT_R200_CP:
1249         case RADEON_INIT_R300_CP:
1250                 return radeon_do_init_cp(dev, init);
1251         case RADEON_CLEANUP_CP:
1252                 return radeon_do_cleanup_cp(dev);
1253         }
1254
1255         return -EINVAL;
1256 }
1257
1258 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1259 {
1260         drm_radeon_private_t *dev_priv = dev->dev_private;
1261         DRM_DEBUG("\n");
1262
1263         LOCK_TEST_WITH_RETURN(dev, file_priv);
1264
1265         if (dev_priv->cp_running) {
1266                 DRM_DEBUG("while CP running\n");
1267                 return 0;
1268         }
1269         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1270                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1271                           dev_priv->cp_mode);
1272                 return 0;
1273         }
1274
1275         radeon_do_cp_start(dev_priv);
1276
1277         return 0;
1278 }
1279
1280 /* Stop the CP.  The engine must have been idled before calling this
1281  * routine.
1282  */
1283 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1284 {
1285         drm_radeon_private_t *dev_priv = dev->dev_private;
1286         drm_radeon_cp_stop_t *stop = data;
1287         int ret;
1288         DRM_DEBUG("\n");
1289
1290         LOCK_TEST_WITH_RETURN(dev, file_priv);
1291
1292         if (!dev_priv->cp_running)
1293                 return 0;
1294
1295         /* Flush any pending CP commands.  This ensures any outstanding
1296          * commands are exectuted by the engine before we turn it off.
1297          */
1298         if (stop->flush) {
1299                 radeon_do_cp_flush(dev_priv);
1300         }
1301
1302         /* If we fail to make the engine go idle, we return an error
1303          * code so that the DRM ioctl wrapper can try again.
1304          */
1305         if (stop->idle) {
1306                 ret = radeon_do_cp_idle(dev_priv);
1307                 if (ret)
1308                         return ret;
1309         }
1310
1311         /* Finally, we can turn off the CP.  If the engine isn't idle,
1312          * we will get some dropped triangles as they won't be fully
1313          * rendered before the CP is shut down.
1314          */
1315         radeon_do_cp_stop(dev_priv);
1316
1317         /* Reset the engine */
1318         radeon_do_engine_reset(dev);
1319
1320         return 0;
1321 }
1322
1323 void radeon_do_release(struct drm_device * dev)
1324 {
1325         drm_radeon_private_t *dev_priv = dev->dev_private;
1326         int i, ret;
1327
1328         if (dev_priv) {
1329                 if (dev_priv->cp_running) {
1330                         /* Stop the cp */
1331                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1332                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1333 #ifdef __linux__
1334                                 schedule();
1335 #else
1336                                 tsleep(&ret, PZERO, "rdnrel", 1);
1337 #endif
1338                         }
1339                         radeon_do_cp_stop(dev_priv);
1340                         radeon_do_engine_reset(dev);
1341                 }
1342
1343                 /* Disable *all* interrupts */
1344                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1345                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1346
1347                 if (dev_priv->mmio) {   /* remove all surfaces */
1348                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1349                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1350                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1351                                              16 * i, 0);
1352                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1353                                              16 * i, 0);
1354                         }
1355                 }
1356
1357                 /* Free memory heap structures */
1358                 radeon_mem_takedown(&(dev_priv->gart_heap));
1359                 radeon_mem_takedown(&(dev_priv->fb_heap));
1360
1361                 /* deallocate kernel resources */
1362                 radeon_do_cleanup_cp(dev);
1363         }
1364 }
1365
1366 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1367  */
1368 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1369 {
1370         drm_radeon_private_t *dev_priv = dev->dev_private;
1371         DRM_DEBUG("\n");
1372
1373         LOCK_TEST_WITH_RETURN(dev, file_priv);
1374
1375         if (!dev_priv) {
1376                 DRM_DEBUG("called before init done\n");
1377                 return -EINVAL;
1378         }
1379
1380         radeon_do_cp_reset(dev_priv);
1381
1382         /* The CP is no longer running after an engine reset */
1383         dev_priv->cp_running = 0;
1384
1385         return 0;
1386 }
1387
1388 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1389 {
1390         drm_radeon_private_t *dev_priv = dev->dev_private;
1391         DRM_DEBUG("\n");
1392
1393         LOCK_TEST_WITH_RETURN(dev, file_priv);
1394
1395         return radeon_do_cp_idle(dev_priv);
1396 }
1397
1398 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1399  */
1400 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1401 {
1402
1403         return radeon_do_resume_cp(dev);
1404 }
1405
1406 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1407 {
1408         DRM_DEBUG("\n");
1409
1410         LOCK_TEST_WITH_RETURN(dev, file_priv);
1411
1412         return radeon_do_engine_reset(dev);
1413 }
1414
1415 /* ================================================================
1416  * Fullscreen mode
1417  */
1418
1419 /* KW: Deprecated to say the least:
1420  */
1421 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1422 {
1423         return 0;
1424 }
1425
1426 /* ================================================================
1427  * Freelist management
1428  */
1429
1430 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1431  *   bufs until freelist code is used.  Note this hides a problem with
1432  *   the scratch register * (used to keep track of last buffer
1433  *   completed) being written to before * the last buffer has actually
1434  *   completed rendering.
1435  *
1436  * KW:  It's also a good way to find free buffers quickly.
1437  *
1438  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1439  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1440  * we essentially have to do this, else old clients will break.
1441  *
1442  * However, it does leave open a potential deadlock where all the
1443  * buffers are held by other clients, which can't release them because
1444  * they can't get the lock.
1445  */
1446
1447 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1448 {
1449         struct drm_device_dma *dma = dev->dma;
1450         drm_radeon_private_t *dev_priv = dev->dev_private;
1451         drm_radeon_buf_priv_t *buf_priv;
1452         struct drm_buf *buf;
1453         int i, t;
1454         int start;
1455
1456         if (++dev_priv->last_buf >= dma->buf_count)
1457                 dev_priv->last_buf = 0;
1458
1459         start = dev_priv->last_buf;
1460
1461         for (t = 0; t < dev_priv->usec_timeout; t++) {
1462                 u32 done_age = GET_SCRATCH(1);
1463                 DRM_DEBUG("done_age = %d\n", done_age);
1464                 for (i = start; i < dma->buf_count; i++) {
1465                         buf = dma->buflist[i];
1466                         buf_priv = buf->dev_private;
1467                         if (buf->file_priv == NULL || (buf->pending &&
1468                                                        buf_priv->age <=
1469                                                        done_age)) {
1470                                 dev_priv->stats.requested_bufs++;
1471                                 buf->pending = 0;
1472                                 return buf;
1473                         }
1474                         start = 0;
1475                 }
1476
1477                 if (t) {
1478                         DRM_UDELAY(1);
1479                         dev_priv->stats.freelist_loops++;
1480                 }
1481         }
1482
1483         DRM_DEBUG("returning NULL!\n");
1484         return NULL;
1485 }
1486
1487 #if 0
1488 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1489 {
1490         struct drm_device_dma *dma = dev->dma;
1491         drm_radeon_private_t *dev_priv = dev->dev_private;
1492         drm_radeon_buf_priv_t *buf_priv;
1493         struct drm_buf *buf;
1494         int i, t;
1495         int start;
1496         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1497
1498         if (++dev_priv->last_buf >= dma->buf_count)
1499                 dev_priv->last_buf = 0;
1500
1501         start = dev_priv->last_buf;
1502         dev_priv->stats.freelist_loops++;
1503
1504         for (t = 0; t < 2; t++) {
1505                 for (i = start; i < dma->buf_count; i++) {
1506                         buf = dma->buflist[i];
1507                         buf_priv = buf->dev_private;
1508                         if (buf->file_priv == 0 || (buf->pending &&
1509                                                     buf_priv->age <=
1510                                                     done_age)) {
1511                                 dev_priv->stats.requested_bufs++;
1512                                 buf->pending = 0;
1513                                 return buf;
1514                         }
1515                 }
1516                 start = 0;
1517         }
1518
1519         return NULL;
1520 }
1521 #endif
1522
1523 void radeon_freelist_reset(struct drm_device * dev)
1524 {
1525         struct drm_device_dma *dma = dev->dma;
1526         drm_radeon_private_t *dev_priv = dev->dev_private;
1527         int i;
1528
1529         dev_priv->last_buf = 0;
1530         for (i = 0; i < dma->buf_count; i++) {
1531                 struct drm_buf *buf = dma->buflist[i];
1532                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1533                 buf_priv->age = 0;
1534         }
1535 }
1536
1537 /* ================================================================
1538  * CP command submission
1539  */
1540
1541 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1542 {
1543         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1544         int i;
1545         u32 last_head = GET_RING_HEAD(dev_priv);
1546
1547         for (i = 0; i < dev_priv->usec_timeout; i++) {
1548                 u32 head = GET_RING_HEAD(dev_priv);
1549
1550                 ring->space = (head - ring->tail) * sizeof(u32);
1551                 if (ring->space <= 0)
1552                         ring->space += ring->size;
1553                 if (ring->space > n)
1554                         return 0;
1555
1556                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1557
1558                 if (head != last_head)
1559                         i = 0;
1560                 last_head = head;
1561
1562                 DRM_UDELAY(1);
1563         }
1564
1565         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1566 #if RADEON_FIFO_DEBUG
1567         radeon_status(dev_priv);
1568         DRM_ERROR("failed!\n");
1569 #endif
1570         return -EBUSY;
1571 }
1572
1573 static int radeon_cp_get_buffers(struct drm_device *dev,
1574                                  struct drm_file *file_priv,
1575                                  struct drm_dma * d)
1576 {
1577         int i;
1578         struct drm_buf *buf;
1579
1580         for (i = d->granted_count; i < d->request_count; i++) {
1581                 buf = radeon_freelist_get(dev);
1582                 if (!buf)
1583                         return -EBUSY;  /* NOTE: broken client */
1584
1585                 buf->file_priv = file_priv;
1586
1587                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1588                                      sizeof(buf->idx)))
1589                         return -EFAULT;
1590                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1591                                      sizeof(buf->total)))
1592                         return -EFAULT;
1593
1594                 d->granted_count++;
1595         }
1596         return 0;
1597 }
1598
1599 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1600 {
1601         struct drm_device_dma *dma = dev->dma;
1602         int ret = 0;
1603         struct drm_dma *d = data;
1604
1605         LOCK_TEST_WITH_RETURN(dev, file_priv);
1606
1607         /* Please don't send us buffers.
1608          */
1609         if (d->send_count != 0) {
1610                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1611                           DRM_CURRENTPID, d->send_count);
1612                 return -EINVAL;
1613         }
1614
1615         /* We'll send you buffers.
1616          */
1617         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1618                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1619                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1620                 return -EINVAL;
1621         }
1622
1623         d->granted_count = 0;
1624
1625         if (d->request_count) {
1626                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1627         }
1628
1629         return ret;
1630 }
1631
1632 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1633 {
1634         drm_radeon_private_t *dev_priv;
1635         int ret = 0;
1636
1637         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1638         if (dev_priv == NULL)
1639                 return -ENOMEM;
1640
1641         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1642         dev->dev_private = (void *)dev_priv;
1643         dev_priv->flags = flags;
1644
1645         switch (flags & RADEON_FAMILY_MASK) {
1646         case CHIP_R100:
1647         case CHIP_RV200:
1648         case CHIP_R200:
1649         case CHIP_R300:
1650         case CHIP_R350:
1651         case CHIP_R420:
1652         case CHIP_RV410:
1653         case CHIP_RV515:
1654         case CHIP_R520:
1655         case CHIP_RV570:
1656         case CHIP_R580:
1657                 dev_priv->flags |= RADEON_HAS_HIERZ;
1658                 break;
1659         default:
1660                 /* all other chips have no hierarchical z buffer */
1661                 break;
1662         }
1663
1664         if (drm_device_is_agp(dev))
1665                 dev_priv->flags |= RADEON_IS_AGP;
1666         else if (drm_device_is_pcie(dev))
1667                 dev_priv->flags |= RADEON_IS_PCIE;
1668         else
1669                 dev_priv->flags |= RADEON_IS_PCI;
1670
1671         DRM_DEBUG("%s card detected\n",
1672                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1673         return ret;
1674 }
1675
1676 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1677  * have to find them.
1678  */
1679 int radeon_driver_firstopen(struct drm_device *dev)
1680 {
1681         int ret;
1682         drm_local_map_t *map;
1683         drm_radeon_private_t *dev_priv = dev->dev_private;
1684
1685         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1686
1687         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1688                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1689                          _DRM_READ_ONLY, &dev_priv->mmio);
1690         if (ret != 0)
1691                 return ret;
1692
1693         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1694         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1695                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1696                          _DRM_WRITE_COMBINING, &map);
1697         if (ret != 0)
1698                 return ret;
1699
1700         return 0;
1701 }
1702
1703 int radeon_driver_unload(struct drm_device *dev)
1704 {
1705         drm_radeon_private_t *dev_priv = dev->dev_private;
1706
1707         DRM_DEBUG("\n");
1708         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1709
1710         dev->dev_private = NULL;
1711         return 0;
1712 }