drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  14 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  17 #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
  18 #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
  19 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  20 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  21 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  22 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  23 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  24 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  25 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  26 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  27 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  28 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  29 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  30 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  31 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  32 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  33 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  34 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  35 #define PCI_DEVICE_ID_INTEL_IGD_HB          0x2A40
  36 #define PCI_DEVICE_ID_INTEL_IGD_IG          0x2A42
  37
  38 /* cover 915 and 945 variants */
  39 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
  40                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
  41                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
  42                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
  43                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
  44                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
  45
  46 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  47                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
  48                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  49                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  50                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  51                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB || \
  52                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
  53
  54 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  55                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  56                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
  57
  58 extern int agp_memory_reserved;
  59
  60
  61 /* Intel 815 register */
  62 #define INTEL_815_APCONT        0x51
  63 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
  64
  65 /* Intel i820 registers */
  66 #define INTEL_I820_RDCR         0x51
  67 #define INTEL_I820_ERRSTS       0xc8
  68
  69 /* Intel i840 registers */
  70 #define INTEL_I840_MCHCFG       0x50
  71 #define INTEL_I840_ERRSTS       0xc8
  72
  73 /* Intel i850 registers */
  74 #define INTEL_I850_MCHCFG       0x50
  75 #define INTEL_I850_ERRSTS       0xc8
  76
  77 /* intel 915G registers */
  78 #define I915_GMADDR     0x18
  79 #define I915_MMADDR     0x10
  80 #define I915_PTEADDR    0x1C
  81 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
  82 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
  83 #define G33_GMCH_GMS_STOLEN_128M       (0x8 << 4)
  84 #define G33_GMCH_GMS_STOLEN_256M       (0x9 << 4)
  85 #define I915_IFPADDR    0x60
  86
  87 /* Intel 965G registers */
  88 #define I965_MSAC 0x62
  89 #define I965_IFPADDR    0x70
  90
  91 /* Intel 7505 registers */
  92 #define INTEL_I7505_APSIZE      0x74
  93 #define INTEL_I7505_NCAPID      0x60
  94 #define INTEL_I7505_NISTAT      0x6c
  95 #define INTEL_I7505_ATTBASE     0x78
  96 #define INTEL_I7505_ERRSTS      0x42
  97 #define INTEL_I7505_AGPCTRL     0x70
  98 #define INTEL_I7505_MCHCFG      0x50
  99
 100 static const struct aper_size_info_fixed intel_i810_sizes[] =
 101 {
 102         {64, 16384, 4},
 103         /* The 32M mode still requires a 64k gatt */
 104         {32, 8192, 4}
 105 };
 106
 107 #define AGP_DCACHE_MEMORY       1
 108 #define AGP_PHYS_MEMORY         2
 109 #define INTEL_AGP_CACHED_MEMORY 3
 110
 111 static struct gatt_mask intel_i810_masks[] =
 112 {
 113         {.mask = I810_PTE_VALID, .type = 0},
 114         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 115         {.mask = I810_PTE_VALID, .type = 0},
 116         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 117          .type = INTEL_AGP_CACHED_MEMORY}
 118 };
 119
 120 static struct _intel_private {
 121         struct pci_dev *pcidev; /* device one */
 122         u8 __iomem *registers;
 123         u32 __iomem *gtt;               /* I915G */
 124         int num_dcache_entries;
 125         /* gtt_entries is the number of gtt entries that are already mapped
 126          * to stolen memory.  Stolen memory is larger than the memory mapped
 127          * through gtt_entries, as it includes some reserved space for the BIOS
 128          * popup and for the GTT.
 129          */
 130         int gtt_entries;                        /* i830+ */
 131         union {
 132                 void __iomem *i9xx_flush_page;
 133                 void *i8xx_flush_page;
 134         };
 135         struct page *i8xx_page;
 136         struct resource ifp_resource;
 137         int resource_valid;
 138 } intel_private;
 139
 140 static int intel_i810_fetch_size(void)
 141 {
 142         u32 smram_miscc;
 143         struct aper_size_info_fixed *values;
 144
 145         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 146         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 147
 148         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 149                 printk(KERN_WARNING PFX "i810 is disabled\n");
 150                 return 0;
 151         }
 152         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 153                 agp_bridge->previous_size =
 154                         agp_bridge->current_size = (void *) (values + 1);
 155                 agp_bridge->aperture_size_idx = 1;
 156                 return values[1].size;
 157         } else {
 158                 agp_bridge->previous_size =
 159                         agp_bridge->current_size = (void *) (values);
 160                 agp_bridge->aperture_size_idx = 0;
 161                 return values[0].size;
 162         }
 163
 164         return 0;
 165 }
 166
 167 static int intel_i810_configure(void)
 168 {
 169         struct aper_size_info_fixed *current_size;
 170         u32 temp;
 171         int i;
 172
 173         current_size = A_SIZE_FIX(agp_bridge->current_size);
 174
 175         if (!intel_private.registers) {
 176                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 177                 temp &= 0xfff80000;
 178
 179                 intel_private.registers = ioremap(temp, 128 * 4096);
 180                 if (!intel_private.registers) {
 181                         printk(KERN_ERR PFX "Unable to remap memory.\n");
 182                         return -ENOMEM;
 183                 }
 184         }
 185
 186         if ((readl(intel_private.registers+I810_DRAM_CTL)
 187                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 188                 /* This will need to be dynamically assigned */
 189                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
 190                 intel_private.num_dcache_entries = 1024;
 191         }
 192         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 193         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 194         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 195         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 196
 197         if (agp_bridge->driver->needs_scratch_page) {
 198                 for (i = 0; i < current_size->num_entries; i++) {
 199                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 200                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI posting. */
 201                 }
 202         }
 203         global_cache_flush();
 204         return 0;
 205 }
 206
 207 static void intel_i810_cleanup(void)
 208 {
 209         writel(0, intel_private.registers+I810_PGETBL_CTL);
 210         readl(intel_private.registers); /* PCI Posting. */
 211         iounmap(intel_private.registers);
 212 }
 213
 214 static void intel_i810_tlbflush(struct agp_memory *mem)
 215 {
 216         return;
 217 }
 218
 219 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 220 {
 221         return;
 222 }
 223
 224 /* Exists to support ARGB cursors */
 225 static void *i8xx_alloc_pages(void)
 226 {
 227         struct page *page;
 228
 229         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 230         if (page == NULL)
 231                 return NULL;
 232
 233         if (set_pages_uc(page, 4) < 0) {
 234                 set_pages_wb(page, 4);
 235                 __free_pages(page, 2);
 236                 return NULL;
 237         }
 238         get_page(page);
 239         atomic_inc(&agp_bridge->current_memory_agp);
 240         return page_address(page);
 241 }
 242
 243 static void i8xx_destroy_pages(void *addr)
 244 {
 245         struct page *page;
 246
 247         if (addr == NULL)
 248                 return;
 249
 250         page = virt_to_page(addr);
 251         set_pages_wb(page, 4);
 252         put_page(page);
 253         __free_pages(page, 2);
 254         atomic_dec(&agp_bridge->current_memory_agp);
 255 }
 256
 257 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 258                                         int type)
 259 {
 260         if (type < AGP_USER_TYPES)
 261                 return type;
 262         else if (type == AGP_USER_CACHED_MEMORY)
 263                 return INTEL_AGP_CACHED_MEMORY;
 264         else
 265                 return 0;
 266 }
 267
 268 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 269                                 int type)
 270 {
 271         int i, j, num_entries;
 272         void *temp;
 273         int ret = -EINVAL;
 274         int mask_type;
 275
 276         if (mem->page_count == 0)
 277                 goto out;
 278
 279         temp = agp_bridge->current_size;
 280         num_entries = A_SIZE_FIX(temp)->num_entries;
 281
 282         if ((pg_start + mem->page_count) > num_entries)
 283                 goto out_err;
 284
 285
 286         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 287                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 288                         ret = -EBUSY;
 289                         goto out_err;
 290                 }
 291         }
 292
 293         if (type != mem->type)
 294                 goto out_err;
 295
 296         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 297
 298         switch (mask_type) {
 299         case AGP_DCACHE_MEMORY:
 300                 if (!mem->is_flushed)
 301                         global_cache_flush();
 302                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 303                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 304                                intel_private.registers+I810_PTE_BASE+(i*4));
 305                 }
 306                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 307                 break;
 308         case AGP_PHYS_MEMORY:
 309         case AGP_NORMAL_MEMORY:
 310                 if (!mem->is_flushed)
 311                         global_cache_flush();
 312                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 313                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 314                                                                mem->memory[i],
 315                                                                mask_type),
 316                                intel_private.registers+I810_PTE_BASE+(j*4));
 317                 }
 318                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 319                 break;
 320         default:
 321                 goto out_err;
 322         }
 323
 324         agp_bridge->driver->tlb_flush(mem);
 325 out:
 326         ret = 0;
 327 out_err:
 328         mem->is_flushed = 1;
 329         return ret;
 330 }
 331
 332 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 333                                 int type)
 334 {
 335         int i;
 336
 337         if (mem->page_count == 0)
 338                 return 0;
 339
 340         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 341                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 342         }
 343         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 344
 345         agp_bridge->driver->tlb_flush(mem);
 346         return 0;
 347 }
 348
 349 /*
 350  * The i810/i830 requires a physical address to program its mouse
 351  * pointer into hardware.
 352  * However the Xserver still writes to it through the agp aperture.
 353  */
 354 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 355 {
 356         struct agp_memory *new;
 357         void *addr;
 358
 359         switch (pg_count) {
 360         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
 361                 break;
 362         case 4:
 363                 /* kludge to get 4 physical pages for ARGB cursor */
 364                 addr = i8xx_alloc_pages();
 365                 break;
 366         default:
 367                 return NULL;
 368         }
 369
 370         if (addr == NULL)
 371                 return NULL;
 372
 373         new = agp_create_memory(pg_count);
 374         if (new == NULL)
 375                 return NULL;
 376
 377         new->memory[0] = virt_to_gart(addr);
 378         if (pg_count == 4) {
 379                 /* kludge to get 4 physical pages for ARGB cursor */
 380                 new->memory[1] = new->memory[0] + PAGE_SIZE;
 381                 new->memory[2] = new->memory[1] + PAGE_SIZE;
 382                 new->memory[3] = new->memory[2] + PAGE_SIZE;
 383         }
 384         new->page_count = pg_count;
 385         new->num_scratch_pages = pg_count;
 386         new->type = AGP_PHYS_MEMORY;
 387         new->physical = new->memory[0];
 388         return new;
 389 }
 390
 391 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 392 {
 393         struct agp_memory *new;
 394
 395         if (type == AGP_DCACHE_MEMORY) {
 396                 if (pg_count != intel_private.num_dcache_entries)
 397                         return NULL;
 398
 399                 new = agp_create_memory(1);
 400                 if (new == NULL)
 401                         return NULL;
 402
 403                 new->type = AGP_DCACHE_MEMORY;
 404                 new->page_count = pg_count;
 405                 new->num_scratch_pages = 0;
 406                 agp_free_page_array(new);
 407                 return new;
 408         }
 409         if (type == AGP_PHYS_MEMORY)
 410                 return alloc_agpphysmem_i8xx(pg_count, type);
 411         return NULL;
 412 }
 413
 414 static void intel_i810_free_by_type(struct agp_memory *curr)
 415 {
 416         agp_free_key(curr->key);
 417         if (curr->type == AGP_PHYS_MEMORY) {
 418                 if (curr->page_count == 4)
 419                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
 420                 else {
 421                         agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
 422                                                              AGP_PAGE_DESTROY_UNMAP);
 423                         agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
 424                                                              AGP_PAGE_DESTROY_FREE);
 425                 }
 426                 agp_free_page_array(curr);
 427         }
 428         kfree(curr);
 429 }
 430
 431 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 432         unsigned long addr, int type)
 433 {
 434         /* Type checking must be done elsewhere */
 435         return addr | bridge->driver->masks[type].mask;
 436 }
 437
 438 static struct aper_size_info_fixed intel_i830_sizes[] =
 439 {
 440         {128, 32768, 5},
 441         /* The 64M mode still requires a 128k gatt */
 442         {64, 16384, 5},
 443         {256, 65536, 6},
 444         {512, 131072, 7},
 445 };
 446
 447 static void intel_i830_init_gtt_entries(void)
 448 {
 449         u16 gmch_ctrl;
 450         int gtt_entries;
 451         u8 rdct;
 452         int local = 0;
 453         static const int ddt[4] = { 0, 16, 32, 64 };
 454         int size; /* reserved space (in kb) at the top of stolen memory */
 455
 456         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 457
 458         if (IS_I965) {
 459                 u32 pgetbl_ctl;
 460                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 461
 462                 /* The 965 has a field telling us the size of the GTT,
 463                  * which may be larger than what is necessary to map the
 464                  * aperture.
 465                  */
 466                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 467                 case I965_PGETBL_SIZE_128KB:
 468                         size = 128;
 469                         break;
 470                 case I965_PGETBL_SIZE_256KB:
 471                         size = 256;
 472                         break;
 473                 case I965_PGETBL_SIZE_512KB:
 474                         size = 512;
 475                         break;
 476                 case I965_PGETBL_SIZE_1MB:
 477                         size = 1024;
 478                         break;
 479                 case I965_PGETBL_SIZE_2MB:
 480                         size = 2048;
 481                         break;
 482                 case I965_PGETBL_SIZE_1_5MB:
 483                         size = 1024 + 512;
 484                         break;
 485                 default:
 486                         printk(KERN_INFO PFX "Unknown page table size, "
 487                                "assuming 512KB\n");
 488                         size = 512;
 489                 }
 490                 size += 4; /* add in BIOS popup space */
 491         } else if (IS_G33) {
 492         /* G33's GTT size defined in gmch_ctrl */
 493                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 494                 case G33_PGETBL_SIZE_1M:
 495                         size = 1024;
 496                         break;
 497                 case G33_PGETBL_SIZE_2M:
 498                         size = 2048;
 499                         break;
 500                 default:
 501                         printk(KERN_INFO PFX "Unknown page table size 0x%x, "
 502                                 "assuming 512KB\n",
 503                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 504                         size = 512;
 505                 }
 506                 size += 4;
 507         } else {
 508                 /* On previous hardware, the GTT size was just what was
 509                  * required to map the aperture.
 510                  */
 511                 size = agp_bridge->driver->fetch_size() + 4;
 512         }
 513
 514         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 515             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 516                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 517                 case I830_GMCH_GMS_STOLEN_512:
 518                         gtt_entries = KB(512) - KB(size);
 519                         break;
 520                 case I830_GMCH_GMS_STOLEN_1024:
 521                         gtt_entries = MB(1) - KB(size);
 522                         break;
 523                 case I830_GMCH_GMS_STOLEN_8192:
 524                         gtt_entries = MB(8) - KB(size);
 525                         break;
 526                 case I830_GMCH_GMS_LOCAL:
 527                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 528                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 529                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 530                         local = 1;
 531                         break;
 532                 default:
 533                         gtt_entries = 0;
 534                         break;
 535                 }
 536         } else {
 537                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 538                 case I855_GMCH_GMS_STOLEN_1M:
 539                         gtt_entries = MB(1) - KB(size);
 540                         break;
 541                 case I855_GMCH_GMS_STOLEN_4M:
 542                         gtt_entries = MB(4) - KB(size);
 543                         break;
 544                 case I855_GMCH_GMS_STOLEN_8M:
 545                         gtt_entries = MB(8) - KB(size);
 546                         break;
 547                 case I855_GMCH_GMS_STOLEN_16M:
 548                         gtt_entries = MB(16) - KB(size);
 549                         break;
 550                 case I855_GMCH_GMS_STOLEN_32M:
 551                         gtt_entries = MB(32) - KB(size);
 552                         break;
 553                 case I915_GMCH_GMS_STOLEN_48M:
 554                         /* Check it's really I915G */
 555                         if (IS_I915 || IS_I965 || IS_G33)
 556                                 gtt_entries = MB(48) - KB(size);
 557                         else
 558                                 gtt_entries = 0;
 559                         break;
 560                 case I915_GMCH_GMS_STOLEN_64M:
 561                         /* Check it's really I915G */
 562                         if (IS_I915 || IS_I965 || IS_G33)
 563                                 gtt_entries = MB(64) - KB(size);
 564                         else
 565                                 gtt_entries = 0;
 566                         break;
 567                 case G33_GMCH_GMS_STOLEN_128M:
 568                         if (IS_G33)
 569                                 gtt_entries = MB(128) - KB(size);
 570                         else
 571                                 gtt_entries = 0;
 572                         break;
 573                 case G33_GMCH_GMS_STOLEN_256M:
 574                         if (IS_G33)
 575                                 gtt_entries = MB(256) - KB(size);
 576                         else
 577                                 gtt_entries = 0;
 578                         break;
 579                 default:
 580                         gtt_entries = 0;
 581                         break;
 582                 }
 583         }
 584         if (gtt_entries > 0)
 585                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
 586                        gtt_entries / KB(1), local ? "local" : "stolen");
 587         else
 588                 printk(KERN_INFO PFX
 589                        "No pre-allocated video memory detected.\n");
 590         gtt_entries /= KB(4);
 591
 592         intel_private.gtt_entries = gtt_entries;
 593 }
 594
 595 static void intel_i830_fini_flush(void)
 596 {
 597         kunmap(intel_private.i8xx_page);
 598         intel_private.i8xx_flush_page = NULL;
 599         unmap_page_from_agp(intel_private.i8xx_page);
 600         flush_agp_mappings();
 601
 602         __free_page(intel_private.i8xx_page);
 603         intel_private.i8xx_page = NULL;
 604 }
 605
 606 static void intel_i830_setup_flush(void)
 607 {
 608         /* return if we've already set the flush mechanism up */
 609         if (intel_private.i8xx_page)
 610                 return;
 611
 612         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 613         if (!intel_private.i8xx_page)
 614                 return;
 615
 616         /* make page uncached */
 617         map_page_into_agp(intel_private.i8xx_page);
 618         flush_agp_mappings();
 619
 620         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 621         if (!intel_private.i8xx_flush_page)
 622                 intel_i830_fini_flush();
 623 }
 624
 625 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 626 {
 627         unsigned int *pg = intel_private.i8xx_flush_page;
 628         int i;
 629
 630         for (i = 0; i < 256; i += 2)
 631                 *(pg + i) = i;
 632
 633         wmb();
 634 }
 635
 636 /* The intel i830 automatically initializes the agp aperture during POST.
 637  * Use the memory already set aside for in the GTT.
 638  */
 639 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 640 {
 641         int page_order;
 642         struct aper_size_info_fixed *size;
 643         int num_entries;
 644         u32 temp;
 645
 646         size = agp_bridge->current_size;
 647         page_order = size->page_order;
 648         num_entries = size->num_entries;
 649         agp_bridge->gatt_table_real = NULL;
 650
 651         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 652         temp &= 0xfff80000;
 653
 654         intel_private.registers = ioremap(temp, 128 * 4096);
 655         if (!intel_private.registers)
 656                 return -ENOMEM;
 657
 658         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 659         global_cache_flush();   /* FIXME: ?? */
 660
 661         /* we have to call this as early as possible after the MMIO base address is known */
 662         intel_i830_init_gtt_entries();
 663
 664         agp_bridge->gatt_table = NULL;
 665
 666         agp_bridge->gatt_bus_addr = temp;
 667
 668         return 0;
 669 }
 670
 671 /* Return the gatt table to a sane state. Use the top of stolen
 672  * memory for the GTT.
 673  */
 674 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 675 {
 676         return 0;
 677 }
 678
 679 static int intel_i830_fetch_size(void)
 680 {
 681         u16 gmch_ctrl;
 682         struct aper_size_info_fixed *values;
 683
 684         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 685
 686         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 687             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 688                 /* 855GM/852GM/865G has 128MB aperture size */
 689                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 690                 agp_bridge->aperture_size_idx = 0;
 691                 return values[0].size;
 692         }
 693
 694         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 695
 696         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 697                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 698                 agp_bridge->aperture_size_idx = 0;
 699                 return values[0].size;
 700         } else {
 701                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 702                 agp_bridge->aperture_size_idx = 1;
 703                 return values[1].size;
 704         }
 705
 706         return 0;
 707 }
 708
 709 static int intel_i830_configure(void)
 710 {
 711         struct aper_size_info_fixed *current_size;
 712         u32 temp;
 713         u16 gmch_ctrl;
 714         int i;
 715
 716         current_size = A_SIZE_FIX(agp_bridge->current_size);
 717
 718         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 719         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 720
 721         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 722         gmch_ctrl |= I830_GMCH_ENABLED;
 723         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
 724
 725         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 726         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 727
 728         if (agp_bridge->driver->needs_scratch_page) {
 729                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 730                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 731                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI Posting. */
 732                 }
 733         }
 734
 735         global_cache_flush();
 736
 737         intel_i830_setup_flush();
 738         return 0;
 739 }
 740
 741 static void intel_i830_cleanup(void)
 742 {
 743         iounmap(intel_private.registers);
 744 }
 745
 746 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 747                                      int type)
 748 {
 749         int i, j, num_entries;
 750         void *temp;
 751         int ret = -EINVAL;
 752         int mask_type;
 753
 754         if (mem->page_count == 0)
 755                 goto out;
 756
 757         temp = agp_bridge->current_size;
 758         num_entries = A_SIZE_FIX(temp)->num_entries;
 759
 760         if (pg_start < intel_private.gtt_entries) {
 761                 printk(KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 762                                 pg_start, intel_private.gtt_entries);
 763
 764                 printk(KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 765                 goto out_err;
 766         }
 767
 768         if ((pg_start + mem->page_count) > num_entries)
 769                 goto out_err;
 770
 771         /* The i830 can't check the GTT for entries since its read only,
 772          * depend on the caller to make the correct offset decisions.
 773          */
 774
 775         if (type != mem->type)
 776                 goto out_err;
 777
 778         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 779
 780         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 781             mask_type != INTEL_AGP_CACHED_MEMORY)
 782                 goto out_err;
 783
 784         if (!mem->is_flushed)
 785                 global_cache_flush();
 786
 787         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 788                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 789                                                        mem->memory[i], mask_type),
 790                        intel_private.registers+I810_PTE_BASE+(j*4));
 791         }
 792         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 793         agp_bridge->driver->tlb_flush(mem);
 794
 795 out:
 796         ret = 0;
 797 out_err:
 798         mem->is_flushed = 1;
 799         return ret;
 800 }
 801
 802 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
 803                                      int type)
 804 {
 805         int i;
 806
 807         if (mem->page_count == 0)
 808                 return 0;
 809
 810         if (pg_start < intel_private.gtt_entries) {
 811                 printk(KERN_INFO PFX "Trying to disable local/stolen memory\n");
 812                 return -EINVAL;
 813         }
 814
 815         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 816                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 817         }
 818         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 819
 820         agp_bridge->driver->tlb_flush(mem);
 821         return 0;
 822 }
 823
 824 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
 825 {
 826         if (type == AGP_PHYS_MEMORY)
 827                 return alloc_agpphysmem_i8xx(pg_count, type);
 828         /* always return NULL for other allocation types for now */
 829         return NULL;
 830 }
 831
 832 static int intel_alloc_chipset_flush_resource(void)
 833 {
 834         int ret;
 835         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
 836                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
 837                                      pcibios_align_resource, agp_bridge->dev);
 838
 839         return ret;
 840 }
 841
 842 static void intel_i915_setup_chipset_flush(void)
 843 {
 844         int ret;
 845         u32 temp;
 846
 847         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
 848         if (!(temp & 0x1)) {
 849                 intel_alloc_chipset_flush_resource();
 850                 intel_private.resource_valid = 1;
 851                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 852         } else {
 853                 temp &= ~1;
 854
 855                 intel_private.resource_valid = 1;
 856                 intel_private.ifp_resource.start = temp;
 857                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
 858                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 859                 /* some BIOSes reserve this area in a pnp some don't */
 860                 if (ret)
 861                         intel_private.resource_valid = 0;
 862         }
 863 }
 864
 865 static void intel_i965_g33_setup_chipset_flush(void)
 866 {
 867         u32 temp_hi, temp_lo;
 868         int ret;
 869
 870         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
 871         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
 872
 873         if (!(temp_lo & 0x1)) {
 874
 875                 intel_alloc_chipset_flush_resource();
 876
 877                 intel_private.resource_valid = 1;
 878                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
 879                         upper_32_bits(intel_private.ifp_resource.start));
 880                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 881         } else {
 882                 u64 l64;
 883
 884                 temp_lo &= ~0x1;
 885                 l64 = ((u64)temp_hi << 32) | temp_lo;
 886
 887                 intel_private.resource_valid = 1;
 888                 intel_private.ifp_resource.start = l64;
 889                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
 890                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 891                 /* some BIOSes reserve this area in a pnp some don't */
 892                 if (ret)
 893                         intel_private.resource_valid = 0;
 894         }
 895 }
 896
 897 static void intel_i9xx_setup_flush(void)
 898 {
 899         /* return if already configured */
 900         if (intel_private.ifp_resource.start)
 901                 return;
 902
 903         /* setup a resource for this object */
 904         intel_private.ifp_resource.name = "Intel Flush Page";
 905         intel_private.ifp_resource.flags = IORESOURCE_MEM;
 906
 907         /* Setup chipset flush for 915 */
 908         if (IS_I965 || IS_G33) {
 909                 intel_i965_g33_setup_chipset_flush();
 910         } else {
 911                 intel_i915_setup_chipset_flush();
 912         }
 913
 914         if (intel_private.ifp_resource.start) {
 915                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
 916                 if (!intel_private.i9xx_flush_page)
 917                         printk(KERN_INFO "unable to ioremap flush  page - no chipset flushing");
 918         }
 919 }
 920
 921 static int intel_i915_configure(void)
 922 {
 923         struct aper_size_info_fixed *current_size;
 924         u32 temp;
 925         u16 gmch_ctrl;
 926         int i;
 927
 928         current_size = A_SIZE_FIX(agp_bridge->current_size);
 929
 930         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
 931
 932         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 933
 934         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 935         gmch_ctrl |= I830_GMCH_ENABLED;
 936         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
 937
 938         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 939         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 940
 941         if (agp_bridge->driver->needs_scratch_page) {
 942                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 943                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
 944                         readl(intel_private.gtt+i);     /* PCI Posting. */
 945                 }
 946         }
 947
 948         global_cache_flush();
 949
 950         intel_i9xx_setup_flush();
 951
 952         return 0;
 953 }
 954
 955 static void intel_i915_cleanup(void)
 956 {
 957         if (intel_private.i9xx_flush_page)
 958                 iounmap(intel_private.i9xx_flush_page);
 959         if (intel_private.resource_valid)
 960                 release_resource(&intel_private.ifp_resource);
 961         intel_private.ifp_resource.start = 0;
 962         intel_private.resource_valid = 0;
 963         iounmap(intel_private.gtt);
 964         iounmap(intel_private.registers);
 965 }
 966
 967 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
 968 {
 969         if (intel_private.i9xx_flush_page)
 970                 writel(1, intel_private.i9xx_flush_page);
 971 }
 972
 973 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
 974                                      int type)
 975 {
 976         int i, j, num_entries;
 977         void *temp;
 978         int ret = -EINVAL;
 979         int mask_type;
 980
 981         if (mem->page_count == 0)
 982                 goto out;
 983
 984         temp = agp_bridge->current_size;
 985         num_entries = A_SIZE_FIX(temp)->num_entries;
 986
 987         if (pg_start < intel_private.gtt_entries) {
 988                 printk(KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 989                                 pg_start, intel_private.gtt_entries);
 990
 991                 printk(KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 992                 goto out_err;
 993         }
 994
 995         if ((pg_start + mem->page_count) > num_entries)
 996                 goto out_err;
 997
 998         /* The i915 can't check the GTT for entries since its read only,
 999          * depend on the caller to make the correct offset decisions.
1000          */
1001
1002         if (type != mem->type)
1003                 goto out_err;
1004
1005         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1006
1007         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1008             mask_type != INTEL_AGP_CACHED_MEMORY)
1009                 goto out_err;
1010
1011         if (!mem->is_flushed)
1012                 global_cache_flush();
1013
1014         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1015                 writel(agp_bridge->driver->mask_memory(agp_bridge,
1016                         mem->memory[i], mask_type), intel_private.gtt+j);
1017         }
1018
1019         readl(intel_private.gtt+j-1);
1020         agp_bridge->driver->tlb_flush(mem);
1021
1022  out:
1023         ret = 0;
1024  out_err:
1025         mem->is_flushed = 1;
1026         return ret;
1027 }
1028
1029 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1030                                      int type)
1031 {
1032         int i;
1033
1034         if (mem->page_count == 0)
1035                 return 0;
1036
1037         if (pg_start < intel_private.gtt_entries) {
1038                 printk(KERN_INFO PFX "Trying to disable local/stolen memory\n");
1039                 return -EINVAL;
1040         }
1041
1042         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1043                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1044
1045         readl(intel_private.gtt+i-1);
1046
1047         agp_bridge->driver->tlb_flush(mem);
1048         return 0;
1049 }
1050
1051 /* Return the aperture size by just checking the resource length.  The effect
1052  * described in the spec of the MSAC registers is just changing of the
1053  * resource size.
1054  */
1055 static int intel_i9xx_fetch_size(void)
1056 {
1057         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1058         int aper_size; /* size in megabytes */
1059         int i;
1060
1061         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1062
1063         for (i = 0; i < num_sizes; i++) {
1064                 if (aper_size == intel_i830_sizes[i].size) {
1065                         agp_bridge->current_size = intel_i830_sizes + i;
1066                         agp_bridge->previous_size = agp_bridge->current_size;
1067                         return aper_size;
1068                 }
1069         }
1070
1071         return 0;
1072 }
1073
1074 /* The intel i915 automatically initializes the agp aperture during POST.
1075  * Use the memory already set aside for in the GTT.
1076  */
1077 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1078 {
1079         int page_order;
1080         struct aper_size_info_fixed *size;
1081         int num_entries;
1082         u32 temp, temp2;
1083         int gtt_map_size = 256 * 1024;
1084
1085         size = agp_bridge->current_size;
1086         page_order = size->page_order;
1087         num_entries = size->num_entries;
1088         agp_bridge->gatt_table_real = NULL;
1089
1090         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1091         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1092
1093         if (IS_G33)
1094             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1095         intel_private.gtt = ioremap(temp2, gtt_map_size);
1096         if (!intel_private.gtt)
1097                 return -ENOMEM;
1098
1099         temp &= 0xfff80000;
1100
1101         intel_private.registers = ioremap(temp, 128 * 4096);
1102         if (!intel_private.registers) {
1103                 iounmap(intel_private.gtt);
1104                 return -ENOMEM;
1105         }
1106
1107         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1108         global_cache_flush();   /* FIXME: ? */
1109
1110         /* we have to call this as early as possible after the MMIO base address is known */
1111         intel_i830_init_gtt_entries();
1112
1113         agp_bridge->gatt_table = NULL;
1114
1115         agp_bridge->gatt_bus_addr = temp;
1116
1117         return 0;
1118 }
1119
1120 /*
1121  * The i965 supports 36-bit physical addresses, but to keep
1122  * the format of the GTT the same, the bits that don't fit
1123  * in a 32-bit word are shifted down to bits 4..7.
1124  *
1125  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1126  * is always zero on 32-bit architectures, so no need to make
1127  * this conditional.
1128  */
1129 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1130         unsigned long addr, int type)
1131 {
1132         /* Shift high bits down */
1133         addr |= (addr >> 28) & 0xf0;
1134
1135         /* Type checking must be done elsewhere */
1136         return addr | bridge->driver->masks[type].mask;
1137 }
1138
1139 /* The intel i965 automatically initializes the agp aperture during POST.
1140  * Use the memory already set aside for in the GTT.
1141  */
1142 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1143 {
1144        int page_order;
1145        struct aper_size_info_fixed *size;
1146        int num_entries;
1147        u32 temp;
1148        int gtt_offset, gtt_size;
1149
1150        size = agp_bridge->current_size;
1151        page_order = size->page_order;
1152        num_entries = size->num_entries;
1153        agp_bridge->gatt_table_real = NULL;
1154
1155        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1156
1157        temp &= 0xfff00000;
1158
1159        if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
1160                gtt_offset = gtt_size = MB(2);
1161        else
1162                gtt_offset = gtt_size = KB(512);
1163
1164        intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1165
1166        if (!intel_private.gtt)
1167                return -ENOMEM;
1168
1169        intel_private.registers = ioremap(temp, 128 * 4096);
1170        if (!intel_private.registers) {
1171                 iounmap(intel_private.gtt);
1172                 return -ENOMEM;
1173         }
1174
1175        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1176        global_cache_flush();   /* FIXME: ? */
1177
1178        /* we have to call this as early as possible after the MMIO base address is known */
1179        intel_i830_init_gtt_entries();
1180
1181        agp_bridge->gatt_table = NULL;
1182
1183        agp_bridge->gatt_bus_addr = temp;
1184
1185        return 0;
1186 }
1187
1188
1189 static int intel_fetch_size(void)
1190 {
1191         int i;
1192         u16 temp;
1193         struct aper_size_info_16 *values;
1194
1195         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1196         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1197
1198         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1199                 if (temp == values[i].size_value) {
1200                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1201                         agp_bridge->aperture_size_idx = i;
1202                         return values[i].size;
1203                 }
1204         }
1205
1206         return 0;
1207 }
1208
1209 static int __intel_8xx_fetch_size(u8 temp)
1210 {
1211         int i;
1212         struct aper_size_info_8 *values;
1213
1214         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1215
1216         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1217                 if (temp == values[i].size_value) {
1218                         agp_bridge->previous_size =
1219                                 agp_bridge->current_size = (void *) (values + i);
1220                         agp_bridge->aperture_size_idx = i;
1221                         return values[i].size;
1222                 }
1223         }
1224         return 0;
1225 }
1226
1227 static int intel_8xx_fetch_size(void)
1228 {
1229         u8 temp;
1230
1231         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1232         return __intel_8xx_fetch_size(temp);
1233 }
1234
1235 static int intel_815_fetch_size(void)
1236 {
1237         u8 temp;
1238
1239         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1240          * one non-reserved bit, so mask the others out ... */
1241         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1242         temp &= (1 << 3);
1243
1244         return __intel_8xx_fetch_size(temp);
1245 }
1246
1247 static void intel_tlbflush(struct agp_memory *mem)
1248 {
1249         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1250         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1251 }
1252
1253
1254 static void intel_8xx_tlbflush(struct agp_memory *mem)
1255 {
1256         u32 temp;
1257         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1258         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1259         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1260         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1261 }
1262
1263
1264 static void intel_cleanup(void)
1265 {
1266         u16 temp;
1267         struct aper_size_info_16 *previous_size;
1268
1269         previous_size = A_SIZE_16(agp_bridge->previous_size);
1270         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1271         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1272         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1273 }
1274
1275
1276 static void intel_8xx_cleanup(void)
1277 {
1278         u16 temp;
1279         struct aper_size_info_8 *previous_size;
1280
1281         previous_size = A_SIZE_8(agp_bridge->previous_size);
1282         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1283         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1284         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1285 }
1286
1287
1288 static int intel_configure(void)
1289 {
1290         u32 temp;
1291         u16 temp2;
1292         struct aper_size_info_16 *current_size;
1293
1294         current_size = A_SIZE_16(agp_bridge->current_size);
1295
1296         /* aperture size */
1297         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1298
1299         /* address to map to */
1300         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1301         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1302
1303         /* attbase - aperture base */
1304         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1305
1306         /* agpctrl */
1307         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1308
1309         /* paccfg/nbxcfg */
1310         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1311         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1312                         (temp2 & ~(1 << 10)) | (1 << 9));
1313         /* clear any possible error conditions */
1314         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1315         return 0;
1316 }
1317
1318 static int intel_815_configure(void)
1319 {
1320         u32 temp, addr;
1321         u8 temp2;
1322         struct aper_size_info_8 *current_size;
1323
1324         /* attbase - aperture base */
1325         /* the Intel 815 chipset spec. says that bits 29-31 in the
1326         * ATTBASE register are reserved -> try not to write them */
1327         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1328                 printk(KERN_EMERG PFX "gatt bus addr too high");
1329                 return -EINVAL;
1330         }
1331
1332         current_size = A_SIZE_8(agp_bridge->current_size);
1333
1334         /* aperture size */
1335         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1336                         current_size->size_value);
1337
1338         /* address to map to */
1339         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1340         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1341
1342         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1343         addr &= INTEL_815_ATTBASE_MASK;
1344         addr |= agp_bridge->gatt_bus_addr;
1345         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1346
1347         /* agpctrl */
1348         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1349
1350         /* apcont */
1351         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1352         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1353
1354         /* clear any possible error conditions */
1355         /* Oddness : this chipset seems to have no ERRSTS register ! */
1356         return 0;
1357 }
1358
1359 static void intel_820_tlbflush(struct agp_memory *mem)
1360 {
1361         return;
1362 }
1363
1364 static void intel_820_cleanup(void)
1365 {
1366         u8 temp;
1367         struct aper_size_info_8 *previous_size;
1368
1369         previous_size = A_SIZE_8(agp_bridge->previous_size);
1370         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1371         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1372                         temp & ~(1 << 1));
1373         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1374                         previous_size->size_value);
1375 }
1376
1377
1378 static int intel_820_configure(void)
1379 {
1380         u32 temp;
1381         u8 temp2;
1382         struct aper_size_info_8 *current_size;
1383
1384         current_size = A_SIZE_8(agp_bridge->current_size);
1385
1386         /* aperture size */
1387         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1388
1389         /* address to map to */
1390         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1391         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1392
1393         /* attbase - aperture base */
1394         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1395
1396         /* agpctrl */
1397         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1398
1399         /* global enable aperture access */
1400         /* This flag is not accessed through MCHCFG register as in */
1401         /* i850 chipset. */
1402         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1403         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1404         /* clear any possible AGP-related error conditions */
1405         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1406         return 0;
1407 }
1408
1409 static int intel_840_configure(void)
1410 {
1411         u32 temp;
1412         u16 temp2;
1413         struct aper_size_info_8 *current_size;
1414
1415         current_size = A_SIZE_8(agp_bridge->current_size);
1416
1417         /* aperture size */
1418         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1419
1420         /* address to map to */
1421         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1422         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1423
1424         /* attbase - aperture base */
1425         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1426
1427         /* agpctrl */
1428         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1429
1430         /* mcgcfg */
1431         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1432         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1433         /* clear any possible error conditions */
1434         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1435         return 0;
1436 }
1437
1438 static int intel_845_configure(void)
1439 {
1440         u32 temp;
1441         u8 temp2;
1442         struct aper_size_info_8 *current_size;
1443
1444         current_size = A_SIZE_8(agp_bridge->current_size);
1445
1446         /* aperture size */
1447         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1448
1449         if (agp_bridge->apbase_config != 0) {
1450                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1451                                        agp_bridge->apbase_config);
1452         } else {
1453                 /* address to map to */
1454                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1455                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1456                 agp_bridge->apbase_config = temp;
1457         }
1458
1459         /* attbase - aperture base */
1460         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1461
1462         /* agpctrl */
1463         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1464
1465         /* agpm */
1466         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1467         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1468         /* clear any possible error conditions */
1469         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1470
1471         intel_i830_setup_flush();
1472         return 0;
1473 }
1474
1475 static int intel_850_configure(void)
1476 {
1477         u32 temp;
1478         u16 temp2;
1479         struct aper_size_info_8 *current_size;
1480
1481         current_size = A_SIZE_8(agp_bridge->current_size);
1482
1483         /* aperture size */
1484         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1485
1486         /* address to map to */
1487         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1488         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1489
1490         /* attbase - aperture base */
1491         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1492
1493         /* agpctrl */
1494         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1495
1496         /* mcgcfg */
1497         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1498         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1499         /* clear any possible AGP-related error conditions */
1500         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1501         return 0;
1502 }
1503
1504 static int intel_860_configure(void)
1505 {
1506         u32 temp;
1507         u16 temp2;
1508         struct aper_size_info_8 *current_size;
1509
1510         current_size = A_SIZE_8(agp_bridge->current_size);
1511
1512         /* aperture size */
1513         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1514
1515         /* address to map to */
1516         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1517         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1518
1519         /* attbase - aperture base */
1520         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1521
1522         /* agpctrl */
1523         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1524
1525         /* mcgcfg */
1526         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1527         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1528         /* clear any possible AGP-related error conditions */
1529         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1530         return 0;
1531 }
1532
1533 static int intel_830mp_configure(void)
1534 {
1535         u32 temp;
1536         u16 temp2;
1537         struct aper_size_info_8 *current_size;
1538
1539         current_size = A_SIZE_8(agp_bridge->current_size);
1540
1541         /* aperture size */
1542         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1543
1544         /* address to map to */
1545         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1546         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1547
1548         /* attbase - aperture base */
1549         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1550
1551         /* agpctrl */
1552         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1553
1554         /* gmch */
1555         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1556         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1557         /* clear any possible AGP-related error conditions */
1558         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1559         return 0;
1560 }
1561
1562 static int intel_7505_configure(void)
1563 {
1564         u32 temp;
1565         u16 temp2;
1566         struct aper_size_info_8 *current_size;
1567
1568         current_size = A_SIZE_8(agp_bridge->current_size);
1569
1570         /* aperture size */
1571         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1572
1573         /* address to map to */
1574         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1575         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1576
1577         /* attbase - aperture base */
1578         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1579
1580         /* agpctrl */
1581         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1582
1583         /* mchcfg */
1584         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1585         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1586
1587         return 0;
1588 }
1589
1590 /* Setup function */
1591 static const struct gatt_mask intel_generic_masks[] =
1592 {
1593         {.mask = 0x00000017, .type = 0}
1594 };
1595
1596 static const struct aper_size_info_8 intel_815_sizes[2] =
1597 {
1598         {64, 16384, 4, 0},
1599         {32, 8192, 3, 8},
1600 };
1601
1602 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1603 {
1604         {256, 65536, 6, 0},
1605         {128, 32768, 5, 32},
1606         {64, 16384, 4, 48},
1607         {32, 8192, 3, 56},
1608         {16, 4096, 2, 60},
1609         {8, 2048, 1, 62},
1610         {4, 1024, 0, 63}
1611 };
1612
1613 static const struct aper_size_info_16 intel_generic_sizes[7] =
1614 {
1615         {256, 65536, 6, 0},
1616         {128, 32768, 5, 32},
1617         {64, 16384, 4, 48},
1618         {32, 8192, 3, 56},
1619         {16, 4096, 2, 60},
1620         {8, 2048, 1, 62},
1621         {4, 1024, 0, 63}
1622 };
1623
1624 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1625 {
1626         {256, 65536, 6, 0},
1627         {128, 32768, 5, 32},
1628         {64, 16384, 4, 48},
1629         {32, 8192, 3, 56}
1630 };
1631
1632 static const struct agp_bridge_driver intel_generic_driver = {
1633         .owner                  = THIS_MODULE,
1634         .aperture_sizes         = intel_generic_sizes,
1635         .size_type              = U16_APER_SIZE,
1636         .num_aperture_sizes     = 7,
1637         .configure              = intel_configure,
1638         .fetch_size             = intel_fetch_size,
1639         .cleanup                = intel_cleanup,
1640         .tlb_flush              = intel_tlbflush,
1641         .mask_memory            = agp_generic_mask_memory,
1642         .masks                  = intel_generic_masks,
1643         .agp_enable             = agp_generic_enable,
1644         .cache_flush            = global_cache_flush,
1645         .create_gatt_table      = agp_generic_create_gatt_table,
1646         .free_gatt_table        = agp_generic_free_gatt_table,
1647         .insert_memory          = agp_generic_insert_memory,
1648         .remove_memory          = agp_generic_remove_memory,
1649         .alloc_by_type          = agp_generic_alloc_by_type,
1650         .free_by_type           = agp_generic_free_by_type,
1651         .agp_alloc_page         = agp_generic_alloc_page,
1652         .agp_destroy_page       = agp_generic_destroy_page,
1653         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1654 };
1655
1656 static const struct agp_bridge_driver intel_810_driver = {
1657         .owner                  = THIS_MODULE,
1658         .aperture_sizes         = intel_i810_sizes,
1659         .size_type              = FIXED_APER_SIZE,
1660         .num_aperture_sizes     = 2,
1661         .needs_scratch_page     = TRUE,
1662         .configure              = intel_i810_configure,
1663         .fetch_size             = intel_i810_fetch_size,
1664         .cleanup                = intel_i810_cleanup,
1665         .tlb_flush              = intel_i810_tlbflush,
1666         .mask_memory            = intel_i810_mask_memory,
1667         .masks                  = intel_i810_masks,
1668         .agp_enable             = intel_i810_agp_enable,
1669         .cache_flush            = global_cache_flush,
1670         .create_gatt_table      = agp_generic_create_gatt_table,
1671         .free_gatt_table        = agp_generic_free_gatt_table,
1672         .insert_memory          = intel_i810_insert_entries,
1673         .remove_memory          = intel_i810_remove_entries,
1674         .alloc_by_type          = intel_i810_alloc_by_type,
1675         .free_by_type           = intel_i810_free_by_type,
1676         .agp_alloc_page         = agp_generic_alloc_page,
1677         .agp_destroy_page       = agp_generic_destroy_page,
1678         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1679 };
1680
1681 static const struct agp_bridge_driver intel_815_driver = {
1682         .owner                  = THIS_MODULE,
1683         .aperture_sizes         = intel_815_sizes,
1684         .size_type              = U8_APER_SIZE,
1685         .num_aperture_sizes     = 2,
1686         .configure              = intel_815_configure,
1687         .fetch_size             = intel_815_fetch_size,
1688         .cleanup                = intel_8xx_cleanup,
1689         .tlb_flush              = intel_8xx_tlbflush,
1690         .mask_memory            = agp_generic_mask_memory,
1691         .masks                  = intel_generic_masks,
1692         .agp_enable             = agp_generic_enable,
1693         .cache_flush            = global_cache_flush,
1694         .create_gatt_table      = agp_generic_create_gatt_table,
1695         .free_gatt_table        = agp_generic_free_gatt_table,
1696         .insert_memory          = agp_generic_insert_memory,
1697         .remove_memory          = agp_generic_remove_memory,
1698         .alloc_by_type          = agp_generic_alloc_by_type,
1699         .free_by_type           = agp_generic_free_by_type,
1700         .agp_alloc_page         = agp_generic_alloc_page,
1701         .agp_destroy_page       = agp_generic_destroy_page,
1702         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1703 };
1704
1705 static const struct agp_bridge_driver intel_830_driver = {
1706         .owner                  = THIS_MODULE,
1707         .aperture_sizes         = intel_i830_sizes,
1708         .size_type              = FIXED_APER_SIZE,
1709         .num_aperture_sizes     = 4,
1710         .needs_scratch_page     = TRUE,
1711         .configure              = intel_i830_configure,
1712         .fetch_size             = intel_i830_fetch_size,
1713         .cleanup                = intel_i830_cleanup,
1714         .tlb_flush              = intel_i810_tlbflush,
1715         .mask_memory            = intel_i810_mask_memory,
1716         .masks                  = intel_i810_masks,
1717         .agp_enable             = intel_i810_agp_enable,
1718         .cache_flush            = global_cache_flush,
1719         .create_gatt_table      = intel_i830_create_gatt_table,
1720         .free_gatt_table        = intel_i830_free_gatt_table,
1721         .insert_memory          = intel_i830_insert_entries,
1722         .remove_memory          = intel_i830_remove_entries,
1723         .alloc_by_type          = intel_i830_alloc_by_type,
1724         .free_by_type           = intel_i810_free_by_type,
1725         .agp_alloc_page         = agp_generic_alloc_page,
1726         .agp_destroy_page       = agp_generic_destroy_page,
1727         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1728         .chipset_flush          = intel_i830_chipset_flush,
1729 };
1730
1731 static const struct agp_bridge_driver intel_820_driver = {
1732         .owner                  = THIS_MODULE,
1733         .aperture_sizes         = intel_8xx_sizes,
1734         .size_type              = U8_APER_SIZE,
1735         .num_aperture_sizes     = 7,
1736         .configure              = intel_820_configure,
1737         .fetch_size             = intel_8xx_fetch_size,
1738         .cleanup                = intel_820_cleanup,
1739         .tlb_flush              = intel_820_tlbflush,
1740         .mask_memory            = agp_generic_mask_memory,
1741         .masks                  = intel_generic_masks,
1742         .agp_enable             = agp_generic_enable,
1743         .cache_flush            = global_cache_flush,
1744         .create_gatt_table      = agp_generic_create_gatt_table,
1745         .free_gatt_table        = agp_generic_free_gatt_table,
1746         .insert_memory          = agp_generic_insert_memory,
1747         .remove_memory          = agp_generic_remove_memory,
1748         .alloc_by_type          = agp_generic_alloc_by_type,
1749         .free_by_type           = agp_generic_free_by_type,
1750         .agp_alloc_page         = agp_generic_alloc_page,
1751         .agp_destroy_page       = agp_generic_destroy_page,
1752         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1753 };
1754
1755 static const struct agp_bridge_driver intel_830mp_driver = {
1756         .owner                  = THIS_MODULE,
1757         .aperture_sizes         = intel_830mp_sizes,
1758         .size_type              = U8_APER_SIZE,
1759         .num_aperture_sizes     = 4,
1760         .configure              = intel_830mp_configure,
1761         .fetch_size             = intel_8xx_fetch_size,
1762         .cleanup                = intel_8xx_cleanup,
1763         .tlb_flush              = intel_8xx_tlbflush,
1764         .mask_memory            = agp_generic_mask_memory,
1765         .masks                  = intel_generic_masks,
1766         .agp_enable             = agp_generic_enable,
1767         .cache_flush            = global_cache_flush,
1768         .create_gatt_table      = agp_generic_create_gatt_table,
1769         .free_gatt_table        = agp_generic_free_gatt_table,
1770         .insert_memory          = agp_generic_insert_memory,
1771         .remove_memory          = agp_generic_remove_memory,
1772         .alloc_by_type          = agp_generic_alloc_by_type,
1773         .free_by_type           = agp_generic_free_by_type,
1774         .agp_alloc_page         = agp_generic_alloc_page,
1775         .agp_destroy_page       = agp_generic_destroy_page,
1776         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1777 };
1778
1779 static const struct agp_bridge_driver intel_840_driver = {
1780         .owner                  = THIS_MODULE,
1781         .aperture_sizes         = intel_8xx_sizes,
1782         .size_type              = U8_APER_SIZE,
1783         .num_aperture_sizes     = 7,
1784         .configure              = intel_840_configure,
1785         .fetch_size             = intel_8xx_fetch_size,
1786         .cleanup                = intel_8xx_cleanup,
1787         .tlb_flush              = intel_8xx_tlbflush,
1788         .mask_memory            = agp_generic_mask_memory,
1789         .masks                  = intel_generic_masks,
1790         .agp_enable             = agp_generic_enable,
1791         .cache_flush            = global_cache_flush,
1792         .create_gatt_table      = agp_generic_create_gatt_table,
1793         .free_gatt_table        = agp_generic_free_gatt_table,
1794         .insert_memory          = agp_generic_insert_memory,
1795         .remove_memory          = agp_generic_remove_memory,
1796         .alloc_by_type          = agp_generic_alloc_by_type,
1797         .free_by_type           = agp_generic_free_by_type,
1798         .agp_alloc_page         = agp_generic_alloc_page,
1799         .agp_destroy_page       = agp_generic_destroy_page,
1800         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1801 };
1802
1803 static const struct agp_bridge_driver intel_845_driver = {
1804         .owner                  = THIS_MODULE,
1805         .aperture_sizes         = intel_8xx_sizes,
1806         .size_type              = U8_APER_SIZE,
1807         .num_aperture_sizes     = 7,
1808         .configure              = intel_845_configure,
1809         .fetch_size             = intel_8xx_fetch_size,
1810         .cleanup                = intel_8xx_cleanup,
1811         .tlb_flush              = intel_8xx_tlbflush,
1812         .mask_memory            = agp_generic_mask_memory,
1813         .masks                  = intel_generic_masks,
1814         .agp_enable             = agp_generic_enable,
1815         .cache_flush            = global_cache_flush,
1816         .create_gatt_table      = agp_generic_create_gatt_table,
1817         .free_gatt_table        = agp_generic_free_gatt_table,
1818         .insert_memory          = agp_generic_insert_memory,
1819         .remove_memory          = agp_generic_remove_memory,
1820         .alloc_by_type          = agp_generic_alloc_by_type,
1821         .free_by_type           = agp_generic_free_by_type,
1822         .agp_alloc_page         = agp_generic_alloc_page,
1823         .agp_destroy_page       = agp_generic_destroy_page,
1824         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1825         .chipset_flush          = intel_i830_chipset_flush,
1826 };
1827
1828 static const struct agp_bridge_driver intel_850_driver = {
1829         .owner                  = THIS_MODULE,
1830         .aperture_sizes         = intel_8xx_sizes,
1831         .size_type              = U8_APER_SIZE,
1832         .num_aperture_sizes     = 7,
1833         .configure              = intel_850_configure,
1834         .fetch_size             = intel_8xx_fetch_size,
1835         .cleanup                = intel_8xx_cleanup,
1836         .tlb_flush              = intel_8xx_tlbflush,
1837         .mask_memory            = agp_generic_mask_memory,
1838         .masks                  = intel_generic_masks,
1839         .agp_enable             = agp_generic_enable,
1840         .cache_flush            = global_cache_flush,
1841         .create_gatt_table      = agp_generic_create_gatt_table,
1842         .free_gatt_table        = agp_generic_free_gatt_table,
1843         .insert_memory          = agp_generic_insert_memory,
1844         .remove_memory          = agp_generic_remove_memory,
1845         .alloc_by_type          = agp_generic_alloc_by_type,
1846         .free_by_type           = agp_generic_free_by_type,
1847         .agp_alloc_page         = agp_generic_alloc_page,
1848         .agp_destroy_page       = agp_generic_destroy_page,
1849         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1850 };
1851
1852 static const struct agp_bridge_driver intel_860_driver = {
1853         .owner                  = THIS_MODULE,
1854         .aperture_sizes         = intel_8xx_sizes,
1855         .size_type              = U8_APER_SIZE,
1856         .num_aperture_sizes     = 7,
1857         .configure              = intel_860_configure,
1858         .fetch_size             = intel_8xx_fetch_size,
1859         .cleanup                = intel_8xx_cleanup,
1860         .tlb_flush              = intel_8xx_tlbflush,
1861         .mask_memory            = agp_generic_mask_memory,
1862         .masks                  = intel_generic_masks,
1863         .agp_enable             = agp_generic_enable,
1864         .cache_flush            = global_cache_flush,
1865         .create_gatt_table      = agp_generic_create_gatt_table,
1866         .free_gatt_table        = agp_generic_free_gatt_table,
1867         .insert_memory          = agp_generic_insert_memory,
1868         .remove_memory          = agp_generic_remove_memory,
1869         .alloc_by_type          = agp_generic_alloc_by_type,
1870         .free_by_type           = agp_generic_free_by_type,
1871         .agp_alloc_page         = agp_generic_alloc_page,
1872         .agp_destroy_page       = agp_generic_destroy_page,
1873         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1874 };
1875
1876 static const struct agp_bridge_driver intel_915_driver = {
1877         .owner                  = THIS_MODULE,
1878         .aperture_sizes         = intel_i830_sizes,
1879         .size_type              = FIXED_APER_SIZE,
1880         .num_aperture_sizes     = 4,
1881         .needs_scratch_page     = TRUE,
1882         .configure              = intel_i915_configure,
1883         .fetch_size             = intel_i9xx_fetch_size,
1884         .cleanup                = intel_i915_cleanup,
1885         .tlb_flush              = intel_i810_tlbflush,
1886         .mask_memory            = intel_i810_mask_memory,
1887         .masks                  = intel_i810_masks,
1888         .agp_enable             = intel_i810_agp_enable,
1889         .cache_flush            = global_cache_flush,
1890         .create_gatt_table      = intel_i915_create_gatt_table,
1891         .free_gatt_table        = intel_i830_free_gatt_table,
1892         .insert_memory          = intel_i915_insert_entries,
1893         .remove_memory          = intel_i915_remove_entries,
1894         .alloc_by_type          = intel_i830_alloc_by_type,
1895         .free_by_type           = intel_i810_free_by_type,
1896         .agp_alloc_page         = agp_generic_alloc_page,
1897         .agp_destroy_page       = agp_generic_destroy_page,
1898         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1899         .chipset_flush          = intel_i915_chipset_flush,
1900 };
1901
1902 static const struct agp_bridge_driver intel_i965_driver = {
1903        .owner                  = THIS_MODULE,
1904        .aperture_sizes         = intel_i830_sizes,
1905        .size_type              = FIXED_APER_SIZE,
1906        .num_aperture_sizes     = 4,
1907        .needs_scratch_page     = TRUE,
1908        .configure              = intel_i915_configure,
1909        .fetch_size             = intel_i9xx_fetch_size,
1910        .cleanup                = intel_i915_cleanup,
1911        .tlb_flush              = intel_i810_tlbflush,
1912        .mask_memory            = intel_i965_mask_memory,
1913        .masks                  = intel_i810_masks,
1914        .agp_enable             = intel_i810_agp_enable,
1915        .cache_flush            = global_cache_flush,
1916        .create_gatt_table      = intel_i965_create_gatt_table,
1917        .free_gatt_table        = intel_i830_free_gatt_table,
1918        .insert_memory          = intel_i915_insert_entries,
1919        .remove_memory          = intel_i915_remove_entries,
1920        .alloc_by_type          = intel_i830_alloc_by_type,
1921        .free_by_type           = intel_i810_free_by_type,
1922        .agp_alloc_page         = agp_generic_alloc_page,
1923        .agp_destroy_page       = agp_generic_destroy_page,
1924        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1925         .chipset_flush          = intel_i915_chipset_flush,
1926 };
1927
1928 static const struct agp_bridge_driver intel_7505_driver = {
1929         .owner                  = THIS_MODULE,
1930         .aperture_sizes         = intel_8xx_sizes,
1931         .size_type              = U8_APER_SIZE,
1932         .num_aperture_sizes     = 7,
1933         .configure              = intel_7505_configure,
1934         .fetch_size             = intel_8xx_fetch_size,
1935         .cleanup                = intel_8xx_cleanup,
1936         .tlb_flush              = intel_8xx_tlbflush,
1937         .mask_memory            = agp_generic_mask_memory,
1938         .masks                  = intel_generic_masks,
1939         .agp_enable             = agp_generic_enable,
1940         .cache_flush            = global_cache_flush,
1941         .create_gatt_table      = agp_generic_create_gatt_table,
1942         .free_gatt_table        = agp_generic_free_gatt_table,
1943         .insert_memory          = agp_generic_insert_memory,
1944         .remove_memory          = agp_generic_remove_memory,
1945         .alloc_by_type          = agp_generic_alloc_by_type,
1946         .free_by_type           = agp_generic_free_by_type,
1947         .agp_alloc_page         = agp_generic_alloc_page,
1948         .agp_destroy_page       = agp_generic_destroy_page,
1949         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1950 };
1951
1952 static const struct agp_bridge_driver intel_g33_driver = {
1953         .owner                  = THIS_MODULE,
1954         .aperture_sizes         = intel_i830_sizes,
1955         .size_type              = FIXED_APER_SIZE,
1956         .num_aperture_sizes     = 4,
1957         .needs_scratch_page     = TRUE,
1958         .configure              = intel_i915_configure,
1959         .fetch_size             = intel_i9xx_fetch_size,
1960         .cleanup                = intel_i915_cleanup,
1961         .tlb_flush              = intel_i810_tlbflush,
1962         .mask_memory            = intel_i965_mask_memory,
1963         .masks                  = intel_i810_masks,
1964         .agp_enable             = intel_i810_agp_enable,
1965         .cache_flush            = global_cache_flush,
1966         .create_gatt_table      = intel_i915_create_gatt_table,
1967         .free_gatt_table        = intel_i830_free_gatt_table,
1968         .insert_memory          = intel_i915_insert_entries,
1969         .remove_memory          = intel_i915_remove_entries,
1970         .alloc_by_type          = intel_i830_alloc_by_type,
1971         .free_by_type           = intel_i810_free_by_type,
1972         .agp_alloc_page         = agp_generic_alloc_page,
1973         .agp_destroy_page       = agp_generic_destroy_page,
1974         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1975         .chipset_flush          = intel_i915_chipset_flush,
1976 };
1977
1978 static int find_gmch(u16 device)
1979 {
1980         struct pci_dev *gmch_device;
1981
1982         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1983         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1984                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1985                                              device, gmch_device);
1986         }
1987
1988         if (!gmch_device)
1989                 return 0;
1990
1991         intel_private.pcidev = gmch_device;
1992         return 1;
1993 }
1994
1995 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1996  * driver and gmch_driver must be non-null, and find_gmch will determine
1997  * which one should be used if a gmch_chip_id is present.
1998  */
1999 static const struct intel_driver_description {
2000         unsigned int chip_id;
2001         unsigned int gmch_chip_id;
2002         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2003         char *name;
2004         const struct agp_bridge_driver *driver;
2005         const struct agp_bridge_driver *gmch_driver;
2006 } intel_agp_chipsets[] = {
2007         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2008         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2009         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2010         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2011                 NULL, &intel_810_driver },
2012         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2013                 NULL, &intel_810_driver },
2014         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2015                 NULL, &intel_810_driver },
2016         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2017                 &intel_815_driver, &intel_810_driver },
2018         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2019         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2020         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2021                 &intel_830mp_driver, &intel_830_driver },
2022         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2023         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2024         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2025                 &intel_845_driver, &intel_830_driver },
2026         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2027         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2028         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2029                 &intel_845_driver, &intel_830_driver },
2030         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2031         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2032                 &intel_845_driver, &intel_830_driver },
2033         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2034         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2035                 NULL, &intel_915_driver },
2036         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2037                 NULL, &intel_915_driver },
2038         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2039                 NULL, &intel_915_driver },
2040         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2041                 NULL, &intel_915_driver },
2042         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2043                 NULL, &intel_915_driver },
2044         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2045                 NULL, &intel_915_driver },
2046         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2047                 NULL, &intel_i965_driver },
2048         { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2049                 NULL, &intel_i965_driver },
2050         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2051                 NULL, &intel_i965_driver },
2052         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2053                 NULL, &intel_i965_driver },
2054         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2055                 NULL, &intel_i965_driver },
2056         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2057                 NULL, &intel_i965_driver },
2058         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2059         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2060         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2061                 NULL, &intel_g33_driver },
2062         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2063                 NULL, &intel_g33_driver },
2064         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2065                 NULL, &intel_g33_driver },
2066         { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
2067             "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2068         { 0, 0, 0, NULL, NULL, NULL }
2069 };
2070
2071 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2072                                      const struct pci_device_id *ent)
2073 {
2074         struct agp_bridge_data *bridge;
2075         u8 cap_ptr = 0;
2076         struct resource *r;
2077         int i;
2078
2079         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2080
2081         bridge = agp_alloc_bridge();
2082         if (!bridge)
2083                 return -ENOMEM;
2084
2085         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2086                 /* In case that multiple models of gfx chip may
2087                    stand on same host bridge type, this can be
2088                    sure we detect the right IGD. */
2089                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2090                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2091                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2092                                 bridge->driver =
2093                                         intel_agp_chipsets[i].gmch_driver;
2094                                 break;
2095                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2096                                 continue;
2097                         } else {
2098                                 bridge->driver = intel_agp_chipsets[i].driver;
2099                                 break;
2100                         }
2101                 }
2102         }
2103
2104         if (intel_agp_chipsets[i].name == NULL) {
2105                 if (cap_ptr)
2106                         printk(KERN_WARNING PFX "Unsupported Intel chipset"
2107                                "(device id: %04x)\n", pdev->device);
2108                 agp_put_bridge(bridge);
2109                 return -ENODEV;
2110         }
2111
2112         if (bridge->driver == NULL) {
2113                 /* bridge has no AGP and no IGD detected */
2114                 if (cap_ptr)
2115                         printk(KERN_WARNING PFX "Failed to find bridge device "
2116                                 "(chip_id: %04x)\n",
2117                                 intel_agp_chipsets[i].gmch_chip_id);
2118                 agp_put_bridge(bridge);
2119                 return -ENODEV;
2120         }
2121
2122         bridge->dev = pdev;
2123         bridge->capndx = cap_ptr;
2124         bridge->dev_private_data = &intel_private;
2125
2126         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
2127                 intel_agp_chipsets[i].name);
2128
2129         /*
2130         * The following fixes the case where the BIOS has "forgotten" to
2131         * provide an address range for the GART.
2132         * 20030610 - hamish@zot.org
2133         */
2134         r = &pdev->resource[0];
2135         if (!r->start && r->end) {
2136                 if (pci_assign_resource(pdev, 0)) {
2137                         printk(KERN_ERR PFX "could not assign resource 0\n");
2138                         agp_put_bridge(bridge);
2139                         return -ENODEV;
2140                 }
2141         }
2142
2143         /*
2144         * If the device has not been properly setup, the following will catch
2145         * the problem and should stop the system from crashing.
2146         * 20030610 - hamish@zot.org
2147         */
2148         if (pci_enable_device(pdev)) {
2149                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
2150                 agp_put_bridge(bridge);
2151                 return -ENODEV;
2152         }
2153
2154         /* Fill in the mode register */
2155         if (cap_ptr) {
2156                 pci_read_config_dword(pdev,
2157                                 bridge->capndx+PCI_AGP_STATUS,
2158                                 &bridge->mode);
2159         }
2160
2161         pci_set_drvdata(pdev, bridge);
2162         return agp_add_bridge(bridge);
2163 }
2164
2165 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2166 {
2167         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2168
2169         agp_remove_bridge(bridge);
2170
2171         if (intel_private.pcidev)
2172                 pci_dev_put(intel_private.pcidev);
2173
2174         agp_put_bridge(bridge);
2175 }
2176
2177 #ifdef CONFIG_PM
2178 static int agp_intel_resume(struct pci_dev *pdev)
2179 {
2180         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2181
2182         pci_restore_state(pdev);
2183
2184         /* We should restore our graphics device's config space,
2185          * as host bridge (00:00) resumes before graphics device (02:00),
2186          * then our access to its pci space can work right.
2187          */
2188         if (intel_private.pcidev)
2189                 pci_restore_state(intel_private.pcidev);
2190
2191         if (bridge->driver == &intel_generic_driver)
2192                 intel_configure();
2193         else if (bridge->driver == &intel_850_driver)
2194                 intel_850_configure();
2195         else if (bridge->driver == &intel_845_driver)
2196                 intel_845_configure();
2197         else if (bridge->driver == &intel_830mp_driver)
2198                 intel_830mp_configure();
2199         else if (bridge->driver == &intel_915_driver)
2200                 intel_i915_configure();
2201         else if (bridge->driver == &intel_830_driver)
2202                 intel_i830_configure();
2203         else if (bridge->driver == &intel_810_driver)
2204                 intel_i810_configure();
2205         else if (bridge->driver == &intel_i965_driver)
2206                 intel_i915_configure();
2207
2208         return 0;
2209 }
2210 #endif
2211
2212 static struct pci_device_id agp_intel_pci_table[] = {
2213 #define ID(x)                                           \
2214         {                                               \
2215         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2216         .class_mask     = ~0,                           \
2217         .vendor         = PCI_VENDOR_ID_INTEL,          \
2218         .device         = x,                            \
2219         .subvendor      = PCI_ANY_ID,                   \
2220         .subdevice      = PCI_ANY_ID,                   \
2221         }
2222         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2223         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2224         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2225         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2226         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2227         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2228         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2229         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2230         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2231         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2232         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2233         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2234         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2235         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2236         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2237         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2238         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2239         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2240         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2241         ID(PCI_DEVICE_ID_INTEL_7505_0),
2242         ID(PCI_DEVICE_ID_INTEL_7205_0),
2243         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2244         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2245         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2246         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2247         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2248         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2249         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2250         ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2251         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2252         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2253         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2254         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2255         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2256         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2257         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2258         ID(PCI_DEVICE_ID_INTEL_IGD_HB),
2259         { }
2260 };
2261
2262 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2263
2264 static struct pci_driver agp_intel_pci_driver = {
2265         .name           = "agpgart-intel",
2266         .id_table       = agp_intel_pci_table,
2267         .probe          = agp_intel_probe,
2268         .remove         = __devexit_p(agp_intel_remove),
2269 #ifdef CONFIG_PM
2270         .resume         = agp_intel_resume,
2271 #endif
2272 };
2273
2274 static int __init agp_intel_init(void)
2275 {
2276         if (agp_off)
2277                 return -EINVAL;
2278         return pci_register_driver(&agp_intel_pci_driver);
2279 }
2280
2281 static void __exit agp_intel_cleanup(void)
2282 {
2283         pci_unregister_driver(&agp_intel_pci_driver);
2284 }
2285
2286 module_init(agp_intel_init);
2287 module_exit(agp_intel_cleanup);
2288
2289 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2290 MODULE_LICENSE("GPL and additional rights");