drivers/block/cciss.h

   1 #ifndef CCISS_H
   2 #define CCISS_H
   3
   4 #include <linux/genhd.h>
   5
   6 #include "cciss_cmd.h"
   7
   8
   9 #define NWD             16
  10 #define NWD_SHIFT       4
  11 #define MAX_PART        (1 << NWD_SHIFT)
  12
  13 #define IO_OK           0
  14 #define IO_ERROR        1
  15
  16 #define MAJOR_NR COMPAQ_CISS_MAJOR
  17
  18 struct ctlr_info;
  19 typedef struct ctlr_info ctlr_info_t;
  20
  21 struct access_method {
  22         void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
  23         void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
  24         unsigned long (*fifo_full)(ctlr_info_t *h);
  25         unsigned long (*intr_pending)(ctlr_info_t *h);
  26         unsigned long (*command_completed)(ctlr_info_t *h);
  27 };
  28 typedef struct _drive_info_struct
  29 {
  30         __u32   LunID;
  31         int     usage_count;
  32         struct request_queue *queue;
  33         sector_t nr_blocks;
  34         int     block_size;
  35         int     heads;
  36         int     sectors;
  37         int     cylinders;
  38         int     raid_level;
  39 } drive_info_struct;
  40
  41 struct ctlr_info
  42 {
  43         int     ctlr;
  44         char    devname[8];
  45         char    *product_name;
  46         char    firm_ver[4]; // Firmware version
  47         struct pci_dev *pdev;
  48         __u32   board_id;
  49         void __iomem *vaddr;
  50         unsigned long paddr;
  51         unsigned long io_mem_addr;
  52         unsigned long io_mem_length;
  53         CfgTable_struct __iomem *cfgtable;
  54         unsigned int intr;
  55         int     interrupts_enabled;
  56         int     major;
  57         int     max_commands;
  58         int     commands_outstanding;
  59         int     max_outstanding; /* Debug */
  60         int     num_luns;
  61         int     highest_lun;
  62         int     usage_count;  /* number of opens all all minor devices */
  63
  64         // information about each logical volume
  65         drive_info_struct drv[CISS_MAX_LUN];
  66
  67         struct access_method access;
  68
  69         /* queue and queue Info */
  70         CommandList_struct *reqQ;
  71         CommandList_struct  *cmpQ;
  72         unsigned int Qdepth;
  73         unsigned int maxQsinceinit;
  74         unsigned int maxSG;
  75         spinlock_t lock;
  76
  77         //* pointers to command and error info pool */
  78         CommandList_struct      *cmd_pool;
  79         dma_addr_t              cmd_pool_dhandle;
  80         ErrorInfo_struct        *errinfo_pool;
  81         dma_addr_t              errinfo_pool_dhandle;
  82         unsigned long           *cmd_pool_bits;
  83         int                     nr_allocs;
  84         int                     nr_frees;
  85         int                     busy_configuring;
  86         int                     busy_initializing;
  87
  88         /* This element holds the zero based queue number of the last
  89          * queue to be started.  It is used for fairness.
  90         */
  91         int                     next_to_run;
  92
  93         // Disk structures we need to pass back
  94         struct gendisk   *gendisk[NWD];
  95 #ifdef CONFIG_CISS_SCSI_TAPE
  96         void *scsi_ctlr; /* ptr to structure containing scsi related stuff */
  97 #endif
  98 };
  99
 100 /*  Defining the diffent access_menthods */
 101 /*
 102  * Memory mapped FIFO interface (SMART 53xx cards)
 103  */
 104 #define SA5_DOORBELL    0x20
 105 #define SA5_REQUEST_PORT_OFFSET 0x40
 106 #define SA5_REPLY_INTR_MASK_OFFSET      0x34
 107 #define SA5_REPLY_PORT_OFFSET           0x44
 108 #define SA5_INTR_STATUS         0x30
 109 #define SA5_SCRATCHPAD_OFFSET   0xB0
 110
 111 #define SA5_CTCFG_OFFSET        0xB4
 112 #define SA5_CTMEM_OFFSET        0xB8
 113
 114 #define SA5_INTR_OFF            0x08
 115 #define SA5B_INTR_OFF           0x04
 116 #define SA5_INTR_PENDING        0x08
 117 #define SA5B_INTR_PENDING       0x04
 118 #define FIFO_EMPTY              0xffffffff
 119 #define CCISS_FIRMWARE_READY    0xffff0000 /* value in scratchpad register */
 120
 121 #define  CISS_ERROR_BIT         0x02
 122
 123 #define CCISS_INTR_ON   1
 124 #define CCISS_INTR_OFF  0
 125 /*
 126         Send the command to the hardware
 127 */
 128 static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
 129 {
 130 #ifdef CCISS_DEBUG
 131          printk("Sending %x - down to controller\n", c->busaddr );
 132 #endif /* CCISS_DEBUG */
 133          writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
 134          h->commands_outstanding++;
 135          if ( h->commands_outstanding > h->max_outstanding)
 136                 h->max_outstanding = h->commands_outstanding;
 137 }
 138
 139 /*
 140  *  This card is the opposite of the other cards.
 141  *   0 turns interrupts on...
 142  *   0x08 turns them off...
 143  */
 144 static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
 145 {
 146         if (val)
 147         { /* Turn interrupts on */
 148                 h->interrupts_enabled = 1;
 149                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 150         } else /* Turn them off */
 151         {
 152                 h->interrupts_enabled = 0;
 153                 writel( SA5_INTR_OFF,
 154                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 155         }
 156 }
 157 /*
 158  *  This card is the opposite of the other cards.
 159  *   0 turns interrupts on...
 160  *   0x04 turns them off...
 161  */
 162 static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
 163 {
 164         if (val)
 165         { /* Turn interrupts on */
 166                 h->interrupts_enabled = 1;
 167                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 168         } else /* Turn them off */
 169         {
 170                 h->interrupts_enabled = 0;
 171                 writel( SA5B_INTR_OFF,
 172                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 173         }
 174 }
 175 /*
 176  *  Returns true if fifo is full.
 177  *
 178  */
 179 static unsigned long SA5_fifo_full(ctlr_info_t *h)
 180 {
 181         if( h->commands_outstanding >= h->max_commands)
 182                 return(1);
 183         else
 184                 return(0);
 185
 186 }
 187 /*
 188  *   returns value read from hardware.
 189  *     returns FIFO_EMPTY if there is nothing to read
 190  */
 191 static unsigned long SA5_completed(ctlr_info_t *h)
 192 {
 193         unsigned long register_value
 194                 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
 195         if(register_value != FIFO_EMPTY)
 196         {
 197                 h->commands_outstanding--;
 198 #ifdef CCISS_DEBUG
 199                 printk("cciss:  Read %lx back from board\n", register_value);
 200 #endif /* CCISS_DEBUG */
 201         }
 202 #ifdef CCISS_DEBUG
 203         else
 204         {
 205                 printk("cciss:  FIFO Empty read\n");
 206         }
 207 #endif
 208         return ( register_value);
 209
 210 }
 211 /*
 212  *      Returns true if an interrupt is pending..
 213  */
 214 static unsigned long SA5_intr_pending(ctlr_info_t *h)
 215 {
 216         unsigned long register_value  =
 217                 readl(h->vaddr + SA5_INTR_STATUS);
 218 #ifdef CCISS_DEBUG
 219         printk("cciss: intr_pending %lx\n", register_value);
 220 #endif  /* CCISS_DEBUG */
 221         if( register_value &  SA5_INTR_PENDING)
 222                 return  1;
 223         return 0 ;
 224 }
 225
 226 /*
 227  *      Returns true if an interrupt is pending..
 228  */
 229 static unsigned long SA5B_intr_pending(ctlr_info_t *h)
 230 {
 231         unsigned long register_value  =
 232                 readl(h->vaddr + SA5_INTR_STATUS);
 233 #ifdef CCISS_DEBUG
 234         printk("cciss: intr_pending %lx\n", register_value);
 235 #endif  /* CCISS_DEBUG */
 236         if( register_value &  SA5B_INTR_PENDING)
 237                 return  1;
 238         return 0 ;
 239 }
 240
 241
 242 static struct access_method SA5_access = {
 243         SA5_submit_command,
 244         SA5_intr_mask,
 245         SA5_fifo_full,
 246         SA5_intr_pending,
 247         SA5_completed,
 248 };
 249
 250 static struct access_method SA5B_access = {
 251         SA5_submit_command,
 252         SA5B_intr_mask,
 253         SA5_fifo_full,
 254         SA5B_intr_pending,
 255         SA5_completed,
 256 };
 257
 258 struct board_type {
 259         __u32   board_id;
 260         char    *product_name;
 261         struct access_method *access;
 262 };
 263
 264 #define CCISS_LOCK(i)   (&hba[i]->lock)
 265
 266 #endif /* CCISS_H */
 267