2 * libata-sff.c - helper library for PCI IDE BMDMA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/libata.h>
38 #include <linux/highmem.h>
42 const struct ata_port_operations ata_sff_port_ops = {
43 .inherits = &ata_base_port_ops,
45 .qc_prep = ata_sff_qc_prep,
46 .qc_issue = ata_sff_qc_issue,
47 .qc_fill_rtf = ata_sff_qc_fill_rtf,
49 .freeze = ata_sff_freeze,
51 .prereset = ata_sff_prereset,
52 .softreset = ata_sff_softreset,
53 .hardreset = sata_sff_hardreset,
54 .postreset = ata_sff_postreset,
55 .error_handler = ata_sff_error_handler,
56 .post_internal_cmd = ata_sff_post_internal_cmd,
58 .sff_dev_select = ata_sff_dev_select,
59 .sff_check_status = ata_sff_check_status,
60 .sff_tf_load = ata_sff_tf_load,
61 .sff_tf_read = ata_sff_tf_read,
62 .sff_exec_command = ata_sff_exec_command,
63 .sff_data_xfer = ata_sff_data_xfer,
64 .sff_irq_on = ata_sff_irq_on,
65 .sff_irq_clear = ata_sff_irq_clear,
67 .port_start = ata_sff_port_start,
70 const struct ata_port_operations ata_bmdma_port_ops = {
71 .inherits = &ata_sff_port_ops,
73 .mode_filter = ata_bmdma_mode_filter,
75 .bmdma_setup = ata_bmdma_setup,
76 .bmdma_start = ata_bmdma_start,
77 .bmdma_stop = ata_bmdma_stop,
78 .bmdma_status = ata_bmdma_status,
82 * ata_fill_sg - Fill PCI IDE PRD table
83 * @qc: Metadata associated with taskfile to be transferred
85 * Fill PCI IDE PRD (scatter-gather) table with segments
86 * associated with the current disk command.
89 * spin_lock_irqsave(host lock)
92 static void ata_fill_sg(struct ata_queued_cmd *qc)
94 struct ata_port *ap = qc->ap;
95 struct scatterlist *sg;
99 for_each_sg(qc->sg, sg, qc->n_elem, si) {
103 /* determine if physical DMA addr spans 64K boundary.
104 * Note h/w doesn't support 64-bit, so we unconditionally
105 * truncate dma_addr_t to u32.
107 addr = (u32) sg_dma_address(sg);
108 sg_len = sg_dma_len(sg);
111 offset = addr & 0xffff;
113 if ((offset + sg_len) > 0x10000)
114 len = 0x10000 - offset;
116 ap->prd[pi].addr = cpu_to_le32(addr);
117 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
118 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
126 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
130 * ata_fill_sg_dumb - Fill PCI IDE PRD table
131 * @qc: Metadata associated with taskfile to be transferred
133 * Fill PCI IDE PRD (scatter-gather) table with segments
134 * associated with the current disk command. Perform the fill
135 * so that we avoid writing any length 64K records for
136 * controllers that don't follow the spec.
139 * spin_lock_irqsave(host lock)
142 static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
144 struct ata_port *ap = qc->ap;
145 struct scatterlist *sg;
149 for_each_sg(qc->sg, sg, qc->n_elem, si) {
151 u32 sg_len, len, blen;
153 /* determine if physical DMA addr spans 64K boundary.
154 * Note h/w doesn't support 64-bit, so we unconditionally
155 * truncate dma_addr_t to u32.
157 addr = (u32) sg_dma_address(sg);
158 sg_len = sg_dma_len(sg);
161 offset = addr & 0xffff;
163 if ((offset + sg_len) > 0x10000)
164 len = 0x10000 - offset;
167 ap->prd[pi].addr = cpu_to_le32(addr);
169 /* Some PATA chipsets like the CS5530 can't
170 cope with 0x0000 meaning 64K as the spec says */
171 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
173 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
175 ap->prd[pi].flags_len = cpu_to_le32(blen);
176 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
184 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
188 * ata_sff_qc_prep - Prepare taskfile for submission
189 * @qc: Metadata associated with taskfile to be prepared
191 * Prepare ATA taskfile for submission.
194 * spin_lock_irqsave(host lock)
196 void ata_sff_qc_prep(struct ata_queued_cmd *qc)
198 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
205 * ata_sff_dumb_qc_prep - Prepare taskfile for submission
206 * @qc: Metadata associated with taskfile to be prepared
208 * Prepare ATA taskfile for submission.
211 * spin_lock_irqsave(host lock)
213 void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc)
215 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
218 ata_fill_sg_dumb(qc);
222 * ata_sff_check_status - Read device status reg & clear interrupt
223 * @ap: port where the device is
225 * Reads ATA taskfile status register for currently-selected device
226 * and return its value. This also clears pending interrupts
230 * Inherited from caller.
232 u8 ata_sff_check_status(struct ata_port *ap)
234 return ioread8(ap->ioaddr.status_addr);
238 * ata_sff_altstatus - Read device alternate status reg
239 * @ap: port where the device is
241 * Reads ATA taskfile alternate status register for
242 * currently-selected device and return its value.
244 * Note: may NOT be used as the check_altstatus() entry in
245 * ata_port_operations.
248 * Inherited from caller.
250 static u8 ata_sff_altstatus(struct ata_port *ap)
252 if (ap->ops->sff_check_altstatus)
253 return ap->ops->sff_check_altstatus(ap);
255 return ioread8(ap->ioaddr.altstatus_addr);
259 * ata_sff_irq_status - Check if the device is busy
260 * @ap: port where the device is
262 * Determine if the port is currently busy. Uses altstatus
263 * if available in order to avoid clearing shared IRQ status
264 * when finding an IRQ source. Non ctl capable devices don't
265 * share interrupt lines fortunately for us.
268 * Inherited from caller.
270 static u8 ata_sff_irq_status(struct ata_port *ap)
274 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
275 status = ata_sff_altstatus(ap);
276 /* Not us: We are busy */
277 if (status & ATA_BUSY)
280 /* Clear INTRQ latch */
281 status = ap->ops->sff_check_status(ap);
286 * ata_sff_sync - Flush writes
287 * @ap: Port to wait for.
290 * If we have an mmio device with no ctl and no altstatus
291 * method this will fail. No such devices are known to exist.
294 * Inherited from caller.
297 static void ata_sff_sync(struct ata_port *ap)
299 if (ap->ops->sff_check_altstatus)
300 ap->ops->sff_check_altstatus(ap);
301 else if (ap->ioaddr.altstatus_addr)
302 ioread8(ap->ioaddr.altstatus_addr);
306 * ata_sff_pause - Flush writes and wait 400nS
307 * @ap: Port to pause for.
310 * If we have an mmio device with no ctl and no altstatus
311 * method this will fail. No such devices are known to exist.
314 * Inherited from caller.
317 void ata_sff_pause(struct ata_port *ap)
324 * ata_sff_dma_pause - Pause before commencing DMA
325 * @ap: Port to pause for.
327 * Perform I/O fencing and ensure sufficient cycle delays occur
328 * for the HDMA1:0 transition
331 void ata_sff_dma_pause(struct ata_port *ap)
333 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
334 /* An altstatus read will cause the needed delay without
335 messing up the IRQ status */
336 ata_sff_altstatus(ap);
339 /* There are no DMA controllers without ctl. BUG here to ensure
340 we never violate the HDMA1:0 transition timing and risk
346 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
347 * @ap: port containing status register to be polled
348 * @tmout_pat: impatience timeout in msecs
349 * @tmout: overall timeout in msecs
351 * Sleep until ATA Status register bit BSY clears,
352 * or a timeout occurs.
355 * Kernel thread context (may sleep).
358 * 0 on success, -errno otherwise.
360 int ata_sff_busy_sleep(struct ata_port *ap,
361 unsigned long tmout_pat, unsigned long tmout)
363 unsigned long timer_start, timeout;
366 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
367 timer_start = jiffies;
368 timeout = ata_deadline(timer_start, tmout_pat);
369 while (status != 0xff && (status & ATA_BUSY) &&
370 time_before(jiffies, timeout)) {
372 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
375 if (status != 0xff && (status & ATA_BUSY))
376 ata_port_printk(ap, KERN_WARNING,
377 "port is slow to respond, please be patient "
378 "(Status 0x%x)\n", status);
380 timeout = ata_deadline(timer_start, tmout);
381 while (status != 0xff && (status & ATA_BUSY) &&
382 time_before(jiffies, timeout)) {
384 status = ap->ops->sff_check_status(ap);
390 if (status & ATA_BUSY) {
391 ata_port_printk(ap, KERN_ERR, "port failed to respond "
392 "(%lu secs, Status 0x%x)\n",
393 DIV_ROUND_UP(tmout, 1000), status);
400 static int ata_sff_check_ready(struct ata_link *link)
402 u8 status = link->ap->ops->sff_check_status(link->ap);
404 return ata_check_ready(status);
408 * ata_sff_wait_ready - sleep until BSY clears, or timeout
409 * @link: SFF link to wait ready status for
410 * @deadline: deadline jiffies for the operation
412 * Sleep until ATA Status register bit BSY clears, or timeout
416 * Kernel thread context (may sleep).
419 * 0 on success, -errno otherwise.
421 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
423 return ata_wait_ready(link, deadline, ata_sff_check_ready);
427 * ata_sff_dev_select - Select device 0/1 on ATA bus
428 * @ap: ATA channel to manipulate
429 * @device: ATA device (numbered from zero) to select
431 * Use the method defined in the ATA specification to
432 * make either device 0, or device 1, active on the
433 * ATA channel. Works with both PIO and MMIO.
435 * May be used as the dev_select() entry in ata_port_operations.
440 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
445 tmp = ATA_DEVICE_OBS;
447 tmp = ATA_DEVICE_OBS | ATA_DEV1;
449 iowrite8(tmp, ap->ioaddr.device_addr);
450 ata_sff_pause(ap); /* needed; also flushes, for mmio */
454 * ata_dev_select - Select device 0/1 on ATA bus
455 * @ap: ATA channel to manipulate
456 * @device: ATA device (numbered from zero) to select
457 * @wait: non-zero to wait for Status register BSY bit to clear
458 * @can_sleep: non-zero if context allows sleeping
460 * Use the method defined in the ATA specification to
461 * make either device 0, or device 1, active on the
464 * This is a high-level version of ata_sff_dev_select(), which
465 * additionally provides the services of inserting the proper
466 * pauses and status polling, where needed.
471 void ata_dev_select(struct ata_port *ap, unsigned int device,
472 unsigned int wait, unsigned int can_sleep)
474 if (ata_msg_probe(ap))
475 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
476 "device %u, wait %u\n", device, wait);
481 ap->ops->sff_dev_select(ap, device);
484 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
491 * ata_sff_irq_on - Enable interrupts on a port.
492 * @ap: Port on which interrupts are enabled.
494 * Enable interrupts on a legacy IDE device using MMIO or PIO,
495 * wait for idle, clear any pending interrupts.
498 * Inherited from caller.
500 u8 ata_sff_irq_on(struct ata_port *ap)
502 struct ata_ioports *ioaddr = &ap->ioaddr;
505 ap->ctl &= ~ATA_NIEN;
506 ap->last_ctl = ap->ctl;
508 if (ioaddr->ctl_addr)
509 iowrite8(ap->ctl, ioaddr->ctl_addr);
510 tmp = ata_wait_idle(ap);
512 ap->ops->sff_irq_clear(ap);
518 * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt.
519 * @ap: Port associated with this ATA transaction.
521 * Clear interrupt and error flags in DMA status register.
523 * May be used as the irq_clear() entry in ata_port_operations.
526 * spin_lock_irqsave(host lock)
528 void ata_sff_irq_clear(struct ata_port *ap)
530 void __iomem *mmio = ap->ioaddr.bmdma_addr;
535 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
539 * ata_sff_tf_load - send taskfile registers to host controller
540 * @ap: Port to which output is sent
541 * @tf: ATA taskfile register set
543 * Outputs ATA taskfile to standard ATA host controller.
546 * Inherited from caller.
548 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
550 struct ata_ioports *ioaddr = &ap->ioaddr;
551 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
553 if (tf->ctl != ap->last_ctl) {
554 if (ioaddr->ctl_addr)
555 iowrite8(tf->ctl, ioaddr->ctl_addr);
556 ap->last_ctl = tf->ctl;
560 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
561 WARN_ON(!ioaddr->ctl_addr);
562 iowrite8(tf->hob_feature, ioaddr->feature_addr);
563 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
564 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
565 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
566 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
567 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
576 iowrite8(tf->feature, ioaddr->feature_addr);
577 iowrite8(tf->nsect, ioaddr->nsect_addr);
578 iowrite8(tf->lbal, ioaddr->lbal_addr);
579 iowrite8(tf->lbam, ioaddr->lbam_addr);
580 iowrite8(tf->lbah, ioaddr->lbah_addr);
581 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
589 if (tf->flags & ATA_TFLAG_DEVICE) {
590 iowrite8(tf->device, ioaddr->device_addr);
591 VPRINTK("device 0x%X\n", tf->device);
598 * ata_sff_tf_read - input device's ATA taskfile shadow registers
599 * @ap: Port from which input is read
600 * @tf: ATA taskfile register set for storing input
602 * Reads ATA taskfile registers for currently-selected device
603 * into @tf. Assumes the device has a fully SFF compliant task file
604 * layout and behaviour. If you device does not (eg has a different
605 * status method) then you will need to provide a replacement tf_read
608 * Inherited from caller.
610 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
612 struct ata_ioports *ioaddr = &ap->ioaddr;
614 tf->command = ata_sff_check_status(ap);
615 tf->feature = ioread8(ioaddr->error_addr);
616 tf->nsect = ioread8(ioaddr->nsect_addr);
617 tf->lbal = ioread8(ioaddr->lbal_addr);
618 tf->lbam = ioread8(ioaddr->lbam_addr);
619 tf->lbah = ioread8(ioaddr->lbah_addr);
620 tf->device = ioread8(ioaddr->device_addr);
622 if (tf->flags & ATA_TFLAG_LBA48) {
623 if (likely(ioaddr->ctl_addr)) {
624 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
625 tf->hob_feature = ioread8(ioaddr->error_addr);
626 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
627 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
628 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
629 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
630 iowrite8(tf->ctl, ioaddr->ctl_addr);
631 ap->last_ctl = tf->ctl;
638 * ata_sff_exec_command - issue ATA command to host controller
639 * @ap: port to which command is being issued
640 * @tf: ATA taskfile register set
642 * Issues ATA command, with proper synchronization with interrupt
643 * handler / other threads.
646 * spin_lock_irqsave(host lock)
648 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
650 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
652 iowrite8(tf->command, ap->ioaddr.command_addr);
657 * ata_tf_to_host - issue ATA taskfile to host controller
658 * @ap: port to which command is being issued
659 * @tf: ATA taskfile register set
661 * Issues ATA taskfile register set to ATA host controller,
662 * with proper synchronization with interrupt handler and
666 * spin_lock_irqsave(host lock)
668 static inline void ata_tf_to_host(struct ata_port *ap,
669 const struct ata_taskfile *tf)
671 ap->ops->sff_tf_load(ap, tf);
672 ap->ops->sff_exec_command(ap, tf);
676 * ata_sff_data_xfer - Transfer data by PIO
677 * @dev: device to target
679 * @buflen: buffer length
682 * Transfer data from/to the device data register by PIO.
685 * Inherited from caller.
690 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
691 unsigned int buflen, int rw)
693 struct ata_port *ap = dev->link->ap;
694 void __iomem *data_addr = ap->ioaddr.data_addr;
695 unsigned int words = buflen >> 1;
697 /* Transfer multiple of 2 bytes */
699 ioread16_rep(data_addr, buf, words);
701 iowrite16_rep(data_addr, buf, words);
703 /* Transfer trailing 1 byte, if any. */
704 if (unlikely(buflen & 0x01)) {
705 __le16 align_buf[1] = { 0 };
706 unsigned char *trailing_buf = buf + buflen - 1;
709 align_buf[0] = cpu_to_le16(ioread16(data_addr));
710 memcpy(trailing_buf, align_buf, 1);
712 memcpy(align_buf, trailing_buf, 1);
713 iowrite16(le16_to_cpu(align_buf[0]), data_addr);
722 * ata_sff_data_xfer_noirq - Transfer data by PIO
723 * @dev: device to target
725 * @buflen: buffer length
728 * Transfer data from/to the device data register by PIO. Do the
729 * transfer with interrupts disabled.
732 * Inherited from caller.
737 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
738 unsigned int buflen, int rw)
741 unsigned int consumed;
743 local_irq_save(flags);
744 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
745 local_irq_restore(flags);
751 * ata_pio_sector - Transfer a sector of data.
752 * @qc: Command on going
754 * Transfer qc->sect_size bytes of data from/to the ATA device.
757 * Inherited from caller.
759 static void ata_pio_sector(struct ata_queued_cmd *qc)
761 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
762 struct ata_port *ap = qc->ap;
767 if (qc->curbytes == qc->nbytes - qc->sect_size)
768 ap->hsm_task_state = HSM_ST_LAST;
770 page = sg_page(qc->cursg);
771 offset = qc->cursg->offset + qc->cursg_ofs;
773 /* get the current page and offset */
774 page = nth_page(page, (offset >> PAGE_SHIFT));
777 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
779 if (PageHighMem(page)) {
782 /* FIXME: use a bounce buffer */
783 local_irq_save(flags);
784 buf = kmap_atomic(page, KM_IRQ0);
786 /* do the actual data transfer */
787 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
790 kunmap_atomic(buf, KM_IRQ0);
791 local_irq_restore(flags);
793 buf = page_address(page);
794 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
798 qc->curbytes += qc->sect_size;
799 qc->cursg_ofs += qc->sect_size;
801 if (qc->cursg_ofs == qc->cursg->length) {
802 qc->cursg = sg_next(qc->cursg);
808 * ata_pio_sectors - Transfer one or many sectors.
809 * @qc: Command on going
811 * Transfer one or many sectors of data from/to the
812 * ATA device for the DRQ request.
815 * Inherited from caller.
817 static void ata_pio_sectors(struct ata_queued_cmd *qc)
819 if (is_multi_taskfile(&qc->tf)) {
820 /* READ/WRITE MULTIPLE */
823 WARN_ON(qc->dev->multi_count == 0);
825 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
826 qc->dev->multi_count);
832 ata_sff_sync(qc->ap); /* flush */
836 * atapi_send_cdb - Write CDB bytes to hardware
837 * @ap: Port to which ATAPI device is attached.
838 * @qc: Taskfile currently active
840 * When device has indicated its readiness to accept
841 * a CDB, this function is called. Send the CDB.
846 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
849 DPRINTK("send cdb\n");
850 WARN_ON(qc->dev->cdb_len < 12);
852 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
854 /* FIXME: If the CDB is for DMA do we need to do the transition delay
855 or is bmdma_start guaranteed to do it ? */
856 switch (qc->tf.protocol) {
858 ap->hsm_task_state = HSM_ST;
860 case ATAPI_PROT_NODATA:
861 ap->hsm_task_state = HSM_ST_LAST;
864 ap->hsm_task_state = HSM_ST_LAST;
866 ap->ops->bmdma_start(qc);
872 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
873 * @qc: Command on going
874 * @bytes: number of bytes
876 * Transfer Transfer data from/to the ATAPI device.
879 * Inherited from caller.
882 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
884 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
885 struct ata_port *ap = qc->ap;
886 struct ata_device *dev = qc->dev;
887 struct ata_eh_info *ehi = &dev->link->eh_info;
888 struct scatterlist *sg;
891 unsigned int offset, count, consumed;
896 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
897 "buf=%u cur=%u bytes=%u",
898 qc->nbytes, qc->curbytes, bytes);
903 offset = sg->offset + qc->cursg_ofs;
905 /* get the current page and offset */
906 page = nth_page(page, (offset >> PAGE_SHIFT));
909 /* don't overrun current sg */
910 count = min(sg->length - qc->cursg_ofs, bytes);
912 /* don't cross page boundaries */
913 count = min(count, (unsigned int)PAGE_SIZE - offset);
915 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
917 if (PageHighMem(page)) {
920 /* FIXME: use bounce buffer */
921 local_irq_save(flags);
922 buf = kmap_atomic(page, KM_IRQ0);
924 /* do the actual data transfer */
925 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw);
927 kunmap_atomic(buf, KM_IRQ0);
928 local_irq_restore(flags);
930 buf = page_address(page);
931 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw);
934 bytes -= min(bytes, consumed);
935 qc->curbytes += count;
936 qc->cursg_ofs += count;
938 if (qc->cursg_ofs == sg->length) {
939 qc->cursg = sg_next(qc->cursg);
943 /* consumed can be larger than count only for the last transfer */
944 WARN_ON(qc->cursg && count != consumed);
952 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
953 * @qc: Command on going
955 * Transfer Transfer data from/to the ATAPI device.
958 * Inherited from caller.
960 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
962 struct ata_port *ap = qc->ap;
963 struct ata_device *dev = qc->dev;
964 struct ata_eh_info *ehi = &dev->link->eh_info;
965 unsigned int ireason, bc_lo, bc_hi, bytes;
966 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
968 /* Abuse qc->result_tf for temp storage of intermediate TF
969 * here to save some kernel stack usage.
970 * For normal completion, qc->result_tf is not relevant. For
971 * error, qc->result_tf is later overwritten by ata_qc_complete().
972 * So, the correctness of qc->result_tf is not affected.
974 ap->ops->sff_tf_read(ap, &qc->result_tf);
975 ireason = qc->result_tf.nsect;
976 bc_lo = qc->result_tf.lbam;
977 bc_hi = qc->result_tf.lbah;
978 bytes = (bc_hi << 8) | bc_lo;
980 /* shall be cleared to zero, indicating xfer of data */
981 if (unlikely(ireason & (1 << 0)))
984 /* make sure transfer direction matches expected */
985 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
986 if (unlikely(do_write != i_write))
989 if (unlikely(!bytes))
992 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
994 if (unlikely(__atapi_pio_bytes(qc, bytes)))
996 ata_sff_sync(ap); /* flush */
1001 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
1004 qc->err_mask |= AC_ERR_HSM;
1005 ap->hsm_task_state = HSM_ST_ERR;
1009 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
1010 * @ap: the target ata_port
1014 * 1 if ok in workqueue, 0 otherwise.
1016 static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
1018 if (qc->tf.flags & ATA_TFLAG_POLLING)
1021 if (ap->hsm_task_state == HSM_ST_FIRST) {
1022 if (qc->tf.protocol == ATA_PROT_PIO &&
1023 (qc->tf.flags & ATA_TFLAG_WRITE))
1026 if (ata_is_atapi(qc->tf.protocol) &&
1027 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1035 * ata_hsm_qc_complete - finish a qc running on standard HSM
1036 * @qc: Command to complete
1037 * @in_wq: 1 if called from workqueue, 0 otherwise
1039 * Finish @qc which is running on standard HSM.
1042 * If @in_wq is zero, spin_lock_irqsave(host lock).
1043 * Otherwise, none on entry and grabs host lock.
1045 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
1047 struct ata_port *ap = qc->ap;
1048 unsigned long flags;
1050 if (ap->ops->error_handler) {
1052 spin_lock_irqsave(ap->lock, flags);
1054 /* EH might have kicked in while host lock is
1057 qc = ata_qc_from_tag(ap, qc->tag);
1059 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
1060 ap->ops->sff_irq_on(ap);
1061 ata_qc_complete(qc);
1063 ata_port_freeze(ap);
1066 spin_unlock_irqrestore(ap->lock, flags);
1068 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1069 ata_qc_complete(qc);
1071 ata_port_freeze(ap);
1075 spin_lock_irqsave(ap->lock, flags);
1076 ap->ops->sff_irq_on(ap);
1077 ata_qc_complete(qc);
1078 spin_unlock_irqrestore(ap->lock, flags);
1080 ata_qc_complete(qc);
1085 * ata_sff_hsm_move - move the HSM to the next state.
1086 * @ap: the target ata_port
1088 * @status: current device status
1089 * @in_wq: 1 if called from workqueue, 0 otherwise
1092 * 1 when poll next status needed, 0 otherwise.
1094 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1095 u8 status, int in_wq)
1097 struct ata_eh_info *ehi = &ap->link.eh_info;
1098 unsigned long flags = 0;
1101 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1103 /* Make sure ata_sff_qc_issue() does not throw things
1104 * like DMA polling into the workqueue. Notice that
1105 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1107 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
1110 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1111 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1113 switch (ap->hsm_task_state) {
1115 /* Send first data block or PACKET CDB */
1117 /* If polling, we will stay in the work queue after
1118 * sending the data. Otherwise, interrupt handler
1119 * takes over after sending the data.
1121 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1123 /* check device status */
1124 if (unlikely((status & ATA_DRQ) == 0)) {
1125 /* handle BSY=0, DRQ=0 as error */
1126 if (likely(status & (ATA_ERR | ATA_DF)))
1127 /* device stops HSM for abort/error */
1128 qc->err_mask |= AC_ERR_DEV;
1130 /* HSM violation. Let EH handle this */
1131 ata_ehi_push_desc(ehi,
1132 "ST_FIRST: !(DRQ|ERR|DF)");
1133 qc->err_mask |= AC_ERR_HSM;
1136 ap->hsm_task_state = HSM_ST_ERR;
1140 /* Device should not ask for data transfer (DRQ=1)
1141 * when it finds something wrong.
1142 * We ignore DRQ here and stop the HSM by
1143 * changing hsm_task_state to HSM_ST_ERR and
1144 * let the EH abort the command or reset the device.
1146 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1147 /* Some ATAPI tape drives forget to clear the ERR bit
1148 * when doing the next command (mostly request sense).
1149 * We ignore ERR here to workaround and proceed sending
1152 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1153 ata_ehi_push_desc(ehi, "ST_FIRST: "
1154 "DRQ=1 with device error, "
1155 "dev_stat 0x%X", status);
1156 qc->err_mask |= AC_ERR_HSM;
1157 ap->hsm_task_state = HSM_ST_ERR;
1162 /* Send the CDB (atapi) or the first data block (ata pio out).
1163 * During the state transition, interrupt handler shouldn't
1164 * be invoked before the data transfer is complete and
1165 * hsm_task_state is changed. Hence, the following locking.
1168 spin_lock_irqsave(ap->lock, flags);
1170 if (qc->tf.protocol == ATA_PROT_PIO) {
1171 /* PIO data out protocol.
1172 * send first data block.
1175 /* ata_pio_sectors() might change the state
1176 * to HSM_ST_LAST. so, the state is changed here
1177 * before ata_pio_sectors().
1179 ap->hsm_task_state = HSM_ST;
1180 ata_pio_sectors(qc);
1183 atapi_send_cdb(ap, qc);
1186 spin_unlock_irqrestore(ap->lock, flags);
1188 /* if polling, ata_pio_task() handles the rest.
1189 * otherwise, interrupt handler takes over from here.
1194 /* complete command or read/write the data register */
1195 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1196 /* ATAPI PIO protocol */
1197 if ((status & ATA_DRQ) == 0) {
1198 /* No more data to transfer or device error.
1199 * Device error will be tagged in HSM_ST_LAST.
1201 ap->hsm_task_state = HSM_ST_LAST;
1205 /* Device should not ask for data transfer (DRQ=1)
1206 * when it finds something wrong.
1207 * We ignore DRQ here and stop the HSM by
1208 * changing hsm_task_state to HSM_ST_ERR and
1209 * let the EH abort the command or reset the device.
1211 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1212 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1213 "DRQ=1 with device error, "
1214 "dev_stat 0x%X", status);
1215 qc->err_mask |= AC_ERR_HSM;
1216 ap->hsm_task_state = HSM_ST_ERR;
1220 atapi_pio_bytes(qc);
1222 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1223 /* bad ireason reported by device */
1227 /* ATA PIO protocol */
1228 if (unlikely((status & ATA_DRQ) == 0)) {
1229 /* handle BSY=0, DRQ=0 as error */
1230 if (likely(status & (ATA_ERR | ATA_DF))) {
1231 /* device stops HSM for abort/error */
1232 qc->err_mask |= AC_ERR_DEV;
1234 /* If diagnostic failed and this is
1235 * IDENTIFY, it's likely a phantom
1236 * device. Mark hint.
1238 if (qc->dev->horkage &
1239 ATA_HORKAGE_DIAGNOSTIC)
1243 /* HSM violation. Let EH handle this.
1244 * Phantom devices also trigger this
1245 * condition. Mark hint.
1247 ata_ehi_push_desc(ehi, "ST-ATA: "
1248 "DRQ=1 with device error, "
1249 "dev_stat 0x%X", status);
1250 qc->err_mask |= AC_ERR_HSM |
1254 ap->hsm_task_state = HSM_ST_ERR;
1258 /* For PIO reads, some devices may ask for
1259 * data transfer (DRQ=1) alone with ERR=1.
1260 * We respect DRQ here and transfer one
1261 * block of junk data before changing the
1262 * hsm_task_state to HSM_ST_ERR.
1264 * For PIO writes, ERR=1 DRQ=1 doesn't make
1265 * sense since the data block has been
1266 * transferred to the device.
1268 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1269 /* data might be corrputed */
1270 qc->err_mask |= AC_ERR_DEV;
1272 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1273 ata_pio_sectors(qc);
1274 status = ata_wait_idle(ap);
1277 if (status & (ATA_BUSY | ATA_DRQ)) {
1278 ata_ehi_push_desc(ehi, "ST-ATA: "
1279 "BUSY|DRQ persists on ERR|DF, "
1280 "dev_stat 0x%X", status);
1281 qc->err_mask |= AC_ERR_HSM;
1284 /* ata_pio_sectors() might change the
1285 * state to HSM_ST_LAST. so, the state
1286 * is changed after ata_pio_sectors().
1288 ap->hsm_task_state = HSM_ST_ERR;
1292 ata_pio_sectors(qc);
1294 if (ap->hsm_task_state == HSM_ST_LAST &&
1295 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1297 status = ata_wait_idle(ap);
1306 if (unlikely(!ata_ok(status))) {
1307 qc->err_mask |= __ac_err_mask(status);
1308 ap->hsm_task_state = HSM_ST_ERR;
1312 /* no more data to transfer */
1313 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1314 ap->print_id, qc->dev->devno, status);
1316 WARN_ON(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1318 ap->hsm_task_state = HSM_ST_IDLE;
1320 /* complete taskfile transaction */
1321 ata_hsm_qc_complete(qc, in_wq);
1327 ap->hsm_task_state = HSM_ST_IDLE;
1329 /* complete taskfile transaction */
1330 ata_hsm_qc_complete(qc, in_wq);
1342 void ata_pio_task(struct work_struct *work)
1344 struct ata_port *ap =
1345 container_of(work, struct ata_port, port_task.work);
1346 struct ata_queued_cmd *qc = ap->port_task_data;
1351 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
1354 * This is purely heuristic. This is a fast path.
1355 * Sometimes when we enter, BSY will be cleared in
1356 * a chk-status or two. If not, the drive is probably seeking
1357 * or something. Snooze for a couple msecs, then
1358 * chk-status again. If still busy, queue delayed work.
1360 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1361 if (status & ATA_BUSY) {
1363 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1364 if (status & ATA_BUSY) {
1365 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1371 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1373 /* another command or interrupt handler
1374 * may be running at this point.
1381 * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner
1382 * @qc: command to issue to device
1384 * Using various libata functions and hooks, this function
1385 * starts an ATA command. ATA commands are grouped into
1386 * classes called "protocols", and issuing each type of protocol
1387 * is slightly different.
1389 * May be used as the qc_issue() entry in ata_port_operations.
1392 * spin_lock_irqsave(host lock)
1395 * Zero on success, AC_ERR_* mask on failure
1397 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1399 struct ata_port *ap = qc->ap;
1401 /* Use polling pio if the LLD doesn't handle
1402 * interrupt driven pio and atapi CDB interrupt.
1404 if (ap->flags & ATA_FLAG_PIO_POLLING) {
1405 switch (qc->tf.protocol) {
1407 case ATA_PROT_NODATA:
1408 case ATAPI_PROT_PIO:
1409 case ATAPI_PROT_NODATA:
1410 qc->tf.flags |= ATA_TFLAG_POLLING;
1412 case ATAPI_PROT_DMA:
1413 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1414 /* see ata_dma_blacklisted() */
1422 /* select the device */
1423 ata_dev_select(ap, qc->dev->devno, 1, 0);
1425 /* start the command */
1426 switch (qc->tf.protocol) {
1427 case ATA_PROT_NODATA:
1428 if (qc->tf.flags & ATA_TFLAG_POLLING)
1429 ata_qc_set_polling(qc);
1431 ata_tf_to_host(ap, &qc->tf);
1432 ap->hsm_task_state = HSM_ST_LAST;
1434 if (qc->tf.flags & ATA_TFLAG_POLLING)
1435 ata_pio_queue_task(ap, qc, 0);
1440 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1442 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1443 ap->ops->bmdma_setup(qc); /* set up bmdma */
1444 ap->ops->bmdma_start(qc); /* initiate bmdma */
1445 ap->hsm_task_state = HSM_ST_LAST;
1449 if (qc->tf.flags & ATA_TFLAG_POLLING)
1450 ata_qc_set_polling(qc);
1452 ata_tf_to_host(ap, &qc->tf);
1454 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1455 /* PIO data out protocol */
1456 ap->hsm_task_state = HSM_ST_FIRST;
1457 ata_pio_queue_task(ap, qc, 0);
1459 /* always send first data block using
1460 * the ata_pio_task() codepath.
1463 /* PIO data in protocol */
1464 ap->hsm_task_state = HSM_ST;
1466 if (qc->tf.flags & ATA_TFLAG_POLLING)
1467 ata_pio_queue_task(ap, qc, 0);
1469 /* if polling, ata_pio_task() handles the rest.
1470 * otherwise, interrupt handler takes over from here.
1476 case ATAPI_PROT_PIO:
1477 case ATAPI_PROT_NODATA:
1478 if (qc->tf.flags & ATA_TFLAG_POLLING)
1479 ata_qc_set_polling(qc);
1481 ata_tf_to_host(ap, &qc->tf);
1483 ap->hsm_task_state = HSM_ST_FIRST;
1485 /* send cdb by polling if no cdb interrupt */
1486 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1487 (qc->tf.flags & ATA_TFLAG_POLLING))
1488 ata_pio_queue_task(ap, qc, 0);
1491 case ATAPI_PROT_DMA:
1492 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1494 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1495 ap->ops->bmdma_setup(qc); /* set up bmdma */
1496 ap->hsm_task_state = HSM_ST_FIRST;
1498 /* send cdb by polling if no cdb interrupt */
1499 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1500 ata_pio_queue_task(ap, qc, 0);
1505 return AC_ERR_SYSTEM;
1512 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1513 * @qc: qc to fill result TF for
1515 * @qc is finished and result TF needs to be filled. Fill it
1516 * using ->sff_tf_read.
1519 * spin_lock_irqsave(host lock)
1522 * true indicating that result TF is successfully filled.
1524 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1526 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1531 * ata_sff_host_intr - Handle host interrupt for given (port, task)
1532 * @ap: Port on which interrupt arrived (possibly...)
1533 * @qc: Taskfile currently active in engine
1535 * Handle host interrupt for given queued command. Currently,
1536 * only DMA interrupts are handled. All other commands are
1537 * handled via polling with interrupts disabled (nIEN bit).
1540 * spin_lock_irqsave(host lock)
1543 * One if interrupt was handled, zero if not (shared irq).
1545 inline unsigned int ata_sff_host_intr(struct ata_port *ap,
1546 struct ata_queued_cmd *qc)
1548 struct ata_eh_info *ehi = &ap->link.eh_info;
1549 u8 status, host_stat = 0;
1551 VPRINTK("ata%u: protocol %d task_state %d\n",
1552 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1554 /* Check whether we are expecting interrupt in this state */
1555 switch (ap->hsm_task_state) {
1557 /* Some pre-ATAPI-4 devices assert INTRQ
1558 * at this state when ready to receive CDB.
1561 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1562 * The flag was turned on only for atapi devices. No
1563 * need to check ata_is_atapi(qc->tf.protocol) again.
1565 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1569 if (qc->tf.protocol == ATA_PROT_DMA ||
1570 qc->tf.protocol == ATAPI_PROT_DMA) {
1571 /* check status of DMA engine */
1572 host_stat = ap->ops->bmdma_status(ap);
1573 VPRINTK("ata%u: host_stat 0x%X\n",
1574 ap->print_id, host_stat);
1576 /* if it's not our irq... */
1577 if (!(host_stat & ATA_DMA_INTR))
1580 /* before we do anything else, clear DMA-Start bit */
1581 ap->ops->bmdma_stop(qc);
1583 if (unlikely(host_stat & ATA_DMA_ERR)) {
1584 /* error when transfering data to/from memory */
1585 qc->err_mask |= AC_ERR_HOST_BUS;
1586 ap->hsm_task_state = HSM_ST_ERR;
1597 /* check main status, clearing INTRQ if needed */
1598 status = ata_sff_irq_status(ap);
1599 if (status & ATA_BUSY)
1602 /* ack bmdma irq events */
1603 ap->ops->sff_irq_clear(ap);
1605 ata_sff_hsm_move(ap, qc, status, 0);
1607 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1608 qc->tf.protocol == ATAPI_PROT_DMA))
1609 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1611 return 1; /* irq handled */
1614 ap->stats.idle_irq++;
1617 if ((ap->stats.idle_irq % 1000) == 0) {
1618 ap->ops->sff_check_status(ap);
1619 ap->ops->sff_irq_clear(ap);
1620 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1624 return 0; /* irq not handled */
1628 * ata_sff_interrupt - Default ATA host interrupt handler
1629 * @irq: irq line (unused)
1630 * @dev_instance: pointer to our ata_host information structure
1632 * Default interrupt handler for PCI IDE devices. Calls
1633 * ata_sff_host_intr() for each port that is not disabled.
1636 * Obtains host lock during operation.
1639 * IRQ_NONE or IRQ_HANDLED.
1641 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1643 struct ata_host *host = dev_instance;
1645 unsigned int handled = 0;
1646 unsigned long flags;
1648 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1649 spin_lock_irqsave(&host->lock, flags);
1651 for (i = 0; i < host->n_ports; i++) {
1652 struct ata_port *ap;
1654 ap = host->ports[i];
1656 !(ap->flags & ATA_FLAG_DISABLED)) {
1657 struct ata_queued_cmd *qc;
1659 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1660 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1661 (qc->flags & ATA_QCFLAG_ACTIVE))
1662 handled |= ata_sff_host_intr(ap, qc);
1666 spin_unlock_irqrestore(&host->lock, flags);
1668 return IRQ_RETVAL(handled);
1672 * ata_sff_freeze - Freeze SFF controller port
1673 * @ap: port to freeze
1675 * Freeze BMDMA controller port.
1678 * Inherited from caller.
1680 void ata_sff_freeze(struct ata_port *ap)
1682 struct ata_ioports *ioaddr = &ap->ioaddr;
1684 ap->ctl |= ATA_NIEN;
1685 ap->last_ctl = ap->ctl;
1687 if (ioaddr->ctl_addr)
1688 iowrite8(ap->ctl, ioaddr->ctl_addr);
1690 /* Under certain circumstances, some controllers raise IRQ on
1691 * ATA_NIEN manipulation. Also, many controllers fail to mask
1692 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1694 ap->ops->sff_check_status(ap);
1696 ap->ops->sff_irq_clear(ap);
1700 * ata_sff_thaw - Thaw SFF controller port
1703 * Thaw SFF controller port.
1706 * Inherited from caller.
1708 void ata_sff_thaw(struct ata_port *ap)
1710 /* clear & re-enable interrupts */
1711 ap->ops->sff_check_status(ap);
1712 ap->ops->sff_irq_clear(ap);
1713 ap->ops->sff_irq_on(ap);
1717 * ata_sff_prereset - prepare SFF link for reset
1718 * @link: SFF link to be reset
1719 * @deadline: deadline jiffies for the operation
1721 * SFF link @link is about to be reset. Initialize it. It first
1722 * calls ata_std_prereset() and wait for !BSY if the port is
1726 * Kernel thread context (may sleep)
1729 * 0 on success, -errno otherwise.
1731 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1733 struct ata_eh_context *ehc = &link->eh_context;
1736 rc = ata_std_prereset(link, deadline);
1740 /* if we're about to do hardreset, nothing more to do */
1741 if (ehc->i.action & ATA_EH_HARDRESET)
1744 /* wait for !BSY if we don't know that no device is attached */
1745 if (!ata_link_offline(link)) {
1746 rc = ata_sff_wait_ready(link, deadline);
1747 if (rc && rc != -ENODEV) {
1748 ata_link_printk(link, KERN_WARNING, "device not ready "
1749 "(errno=%d), forcing hardreset\n", rc);
1750 ehc->i.action |= ATA_EH_HARDRESET;
1758 * ata_devchk - PATA device presence detection
1759 * @ap: ATA channel to examine
1760 * @device: Device to examine (starting at zero)
1762 * This technique was originally described in
1763 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1764 * later found its way into the ATA/ATAPI spec.
1766 * Write a pattern to the ATA shadow registers,
1767 * and if a device is present, it will respond by
1768 * correctly storing and echoing back the
1769 * ATA shadow register contents.
1774 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1776 struct ata_ioports *ioaddr = &ap->ioaddr;
1779 ap->ops->sff_dev_select(ap, device);
1781 iowrite8(0x55, ioaddr->nsect_addr);
1782 iowrite8(0xaa, ioaddr->lbal_addr);
1784 iowrite8(0xaa, ioaddr->nsect_addr);
1785 iowrite8(0x55, ioaddr->lbal_addr);
1787 iowrite8(0x55, ioaddr->nsect_addr);
1788 iowrite8(0xaa, ioaddr->lbal_addr);
1790 nsect = ioread8(ioaddr->nsect_addr);
1791 lbal = ioread8(ioaddr->lbal_addr);
1793 if ((nsect == 0x55) && (lbal == 0xaa))
1794 return 1; /* we found a device */
1796 return 0; /* nothing found */
1800 * ata_sff_dev_classify - Parse returned ATA device signature
1801 * @dev: ATA device to classify (starting at zero)
1802 * @present: device seems present
1803 * @r_err: Value of error register on completion
1805 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1806 * an ATA/ATAPI-defined set of values is placed in the ATA
1807 * shadow registers, indicating the results of device detection
1810 * Select the ATA device, and read the values from the ATA shadow
1811 * registers. Then parse according to the Error register value,
1812 * and the spec-defined values examined by ata_dev_classify().
1818 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1820 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1823 struct ata_port *ap = dev->link->ap;
1824 struct ata_taskfile tf;
1828 ap->ops->sff_dev_select(ap, dev->devno);
1830 memset(&tf, 0, sizeof(tf));
1832 ap->ops->sff_tf_read(ap, &tf);
1837 /* see if device passed diags: continue and warn later */
1839 /* diagnostic fail : do nothing _YET_ */
1840 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1843 else if ((dev->devno == 0) && (err == 0x81))
1846 return ATA_DEV_NONE;
1848 /* determine if device is ATA or ATAPI */
1849 class = ata_dev_classify(&tf);
1851 if (class == ATA_DEV_UNKNOWN) {
1852 /* If the device failed diagnostic, it's likely to
1853 * have reported incorrect device signature too.
1854 * Assume ATA device if the device seems present but
1855 * device signature is invalid with diagnostic
1858 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1859 class = ATA_DEV_ATA;
1861 class = ATA_DEV_NONE;
1862 } else if ((class == ATA_DEV_ATA) &&
1863 (ap->ops->sff_check_status(ap) == 0))
1864 class = ATA_DEV_NONE;
1870 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1871 * @link: SFF link which is just reset
1872 * @devmask: mask of present devices
1873 * @deadline: deadline jiffies for the operation
1875 * Wait devices attached to SFF @link to become ready after
1876 * reset. It contains preceding 150ms wait to avoid accessing TF
1877 * status register too early.
1880 * Kernel thread context (may sleep).
1883 * 0 on success, -ENODEV if some or all of devices in @devmask
1884 * don't seem to exist. -errno on other errors.
1886 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1887 unsigned long deadline)
1889 struct ata_port *ap = link->ap;
1890 struct ata_ioports *ioaddr = &ap->ioaddr;
1891 unsigned int dev0 = devmask & (1 << 0);
1892 unsigned int dev1 = devmask & (1 << 1);
1895 msleep(ATA_WAIT_AFTER_RESET);
1897 /* always check readiness of the master device */
1898 rc = ata_sff_wait_ready(link, deadline);
1899 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1900 * and TF status is 0xff, bail out on it too.
1905 /* if device 1 was found in ata_devchk, wait for register
1906 * access briefly, then wait for BSY to clear.
1911 ap->ops->sff_dev_select(ap, 1);
1913 /* Wait for register access. Some ATAPI devices fail
1914 * to set nsect/lbal after reset, so don't waste too
1915 * much time on it. We're gonna wait for !BSY anyway.
1917 for (i = 0; i < 2; i++) {
1920 nsect = ioread8(ioaddr->nsect_addr);
1921 lbal = ioread8(ioaddr->lbal_addr);
1922 if ((nsect == 1) && (lbal == 1))
1924 msleep(50); /* give drive a breather */
1927 rc = ata_sff_wait_ready(link, deadline);
1935 /* is all this really necessary? */
1936 ap->ops->sff_dev_select(ap, 0);
1938 ap->ops->sff_dev_select(ap, 1);
1940 ap->ops->sff_dev_select(ap, 0);
1945 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1946 unsigned long deadline)
1948 struct ata_ioports *ioaddr = &ap->ioaddr;
1950 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
1952 /* software reset. causes dev0 to be selected */
1953 iowrite8(ap->ctl, ioaddr->ctl_addr);
1954 udelay(20); /* FIXME: flush */
1955 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1956 udelay(20); /* FIXME: flush */
1957 iowrite8(ap->ctl, ioaddr->ctl_addr);
1959 /* wait the port to become ready */
1960 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
1964 * ata_sff_softreset - reset host port via ATA SRST
1965 * @link: ATA link to reset
1966 * @classes: resulting classes of attached devices
1967 * @deadline: deadline jiffies for the operation
1969 * Reset host port using ATA SRST.
1972 * Kernel thread context (may sleep)
1975 * 0 on success, -errno otherwise.
1977 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
1978 unsigned long deadline)
1980 struct ata_port *ap = link->ap;
1981 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1982 unsigned int devmask = 0;
1988 /* determine if device 0/1 are present */
1989 if (ata_devchk(ap, 0))
1990 devmask |= (1 << 0);
1991 if (slave_possible && ata_devchk(ap, 1))
1992 devmask |= (1 << 1);
1994 /* select device 0 again */
1995 ap->ops->sff_dev_select(ap, 0);
1997 /* issue bus reset */
1998 DPRINTK("about to softreset, devmask=%x\n", devmask);
1999 rc = ata_bus_softreset(ap, devmask, deadline);
2000 /* if link is occupied, -ENODEV too is an error */
2001 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2002 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
2006 /* determine by signature whether we have ATA or ATAPI devices */
2007 classes[0] = ata_sff_dev_classify(&link->device[0],
2008 devmask & (1 << 0), &err);
2009 if (slave_possible && err != 0x81)
2010 classes[1] = ata_sff_dev_classify(&link->device[1],
2011 devmask & (1 << 1), &err);
2013 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2018 * sata_sff_hardreset - reset host port via SATA phy reset
2019 * @link: link to reset
2020 * @class: resulting class of attached device
2021 * @deadline: deadline jiffies for the operation
2023 * SATA phy-reset host port using DET bits of SControl register,
2024 * wait for !BSY and classify the attached device.
2027 * Kernel thread context (may sleep)
2030 * 0 on success, -errno otherwise.
2032 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2033 unsigned long deadline)
2035 struct ata_eh_context *ehc = &link->eh_context;
2036 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2040 rc = sata_link_hardreset(link, timing, deadline, &online,
2041 ata_sff_check_ready);
2043 *class = ata_sff_dev_classify(link->device, 1, NULL);
2045 DPRINTK("EXIT, class=%u\n", *class);
2050 * ata_sff_postreset - SFF postreset callback
2051 * @link: the target SFF ata_link
2052 * @classes: classes of attached devices
2054 * This function is invoked after a successful reset. It first
2055 * calls ata_std_postreset() and performs SFF specific postreset
2059 * Kernel thread context (may sleep)
2061 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2063 struct ata_port *ap = link->ap;
2065 ata_std_postreset(link, classes);
2067 /* is double-select really necessary? */
2068 if (classes[0] != ATA_DEV_NONE)
2069 ap->ops->sff_dev_select(ap, 1);
2070 if (classes[1] != ATA_DEV_NONE)
2071 ap->ops->sff_dev_select(ap, 0);
2073 /* bail out if no device is present */
2074 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2075 DPRINTK("EXIT, no device\n");
2079 /* set up device control */
2080 if (ap->ioaddr.ctl_addr)
2081 iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
2085 * ata_sff_error_handler - Stock error handler for BMDMA controller
2086 * @ap: port to handle error for
2088 * Stock error handler for SFF controller. It can handle both
2089 * PATA and SATA controllers. Many controllers should be able to
2090 * use this EH as-is or with some added handling before and
2094 * Kernel thread context (may sleep)
2096 void ata_sff_error_handler(struct ata_port *ap)
2098 ata_reset_fn_t softreset = ap->ops->softreset;
2099 ata_reset_fn_t hardreset = ap->ops->hardreset;
2100 struct ata_queued_cmd *qc;
2101 unsigned long flags;
2104 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2105 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2108 /* reset PIO HSM and stop DMA engine */
2109 spin_lock_irqsave(ap->lock, flags);
2111 ap->hsm_task_state = HSM_ST_IDLE;
2113 if (ap->ioaddr.bmdma_addr &&
2114 qc && (qc->tf.protocol == ATA_PROT_DMA ||
2115 qc->tf.protocol == ATAPI_PROT_DMA)) {
2118 host_stat = ap->ops->bmdma_status(ap);
2120 /* BMDMA controllers indicate host bus error by
2121 * setting DMA_ERR bit and timing out. As it wasn't
2122 * really a timeout event, adjust error mask and
2123 * cancel frozen state.
2125 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2126 qc->err_mask = AC_ERR_HOST_BUS;
2130 ap->ops->bmdma_stop(qc);
2133 ata_sff_sync(ap); /* FIXME: We don't need this */
2134 ap->ops->sff_check_status(ap);
2135 ap->ops->sff_irq_clear(ap);
2137 spin_unlock_irqrestore(ap->lock, flags);
2140 ata_eh_thaw_port(ap);
2142 /* PIO and DMA engines have been stopped, perform recovery */
2144 /* Ignore ata_sff_softreset if ctl isn't accessible and
2145 * built-in hardresets if SCR access isn't available.
2147 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
2149 if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link))
2152 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2153 ap->ops->postreset);
2157 * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller
2158 * @qc: internal command to clean up
2161 * Kernel thread context (may sleep)
2163 void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc)
2165 struct ata_port *ap = qc->ap;
2166 unsigned long flags;
2168 spin_lock_irqsave(ap->lock, flags);
2170 ap->hsm_task_state = HSM_ST_IDLE;
2172 if (ap->ioaddr.bmdma_addr)
2175 spin_unlock_irqrestore(ap->lock, flags);
2179 * ata_sff_port_start - Set port up for dma.
2180 * @ap: Port to initialize
2182 * Called just after data structures for each port are
2183 * initialized. Allocates space for PRD table if the device
2184 * is DMA capable SFF.
2186 * May be used as the port_start() entry in ata_port_operations.
2189 * Inherited from caller.
2191 int ata_sff_port_start(struct ata_port *ap)
2193 if (ap->ioaddr.bmdma_addr)
2194 return ata_port_start(ap);
2199 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2200 * @ioaddr: IO address structure to be initialized
2202 * Utility function which initializes data_addr, error_addr,
2203 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2204 * device_addr, status_addr, and command_addr to standard offsets
2205 * relative to cmd_addr.
2207 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2209 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2211 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2212 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2213 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2214 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2215 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2216 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2217 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2218 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2219 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2220 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2223 unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
2224 unsigned long xfer_mask)
2226 /* Filter out DMA modes if the device has been configured by
2227 the BIOS as PIO only */
2229 if (adev->link->ap->ioaddr.bmdma_addr == NULL)
2230 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
2235 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2236 * @qc: Info associated with this ATA transaction.
2239 * spin_lock_irqsave(host lock)
2241 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2243 struct ata_port *ap = qc->ap;
2244 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2247 /* load PRD table addr. */
2248 mb(); /* make sure PRD table writes are visible to controller */
2249 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2251 /* specify data direction, triple-check start bit is clear */
2252 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2253 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2255 dmactl |= ATA_DMA_WR;
2256 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2258 /* issue r/w command */
2259 ap->ops->sff_exec_command(ap, &qc->tf);
2263 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2264 * @qc: Info associated with this ATA transaction.
2267 * spin_lock_irqsave(host lock)
2269 void ata_bmdma_start(struct ata_queued_cmd *qc)
2271 struct ata_port *ap = qc->ap;
2274 /* start host DMA transaction */
2275 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2276 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2278 /* Strictly, one may wish to issue an ioread8() here, to
2279 * flush the mmio write. However, control also passes
2280 * to the hardware at this point, and it will interrupt
2281 * us when we are to resume control. So, in effect,
2282 * we don't care when the mmio write flushes.
2283 * Further, a read of the DMA status register _immediately_
2284 * following the write may not be what certain flaky hardware
2285 * is expected, so I think it is best to not add a readb()
2286 * without first all the MMIO ATA cards/mobos.
2287 * Or maybe I'm just being paranoid.
2289 * FIXME: The posting of this write means I/O starts are
2290 * unneccessarily delayed for MMIO
2295 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2296 * @qc: Command we are ending DMA for
2298 * Clears the ATA_DMA_START flag in the dma control register
2300 * May be used as the bmdma_stop() entry in ata_port_operations.
2303 * spin_lock_irqsave(host lock)
2305 void ata_bmdma_stop(struct ata_queued_cmd *qc)
2307 struct ata_port *ap = qc->ap;
2308 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2310 /* clear start/stop bit */
2311 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2312 mmio + ATA_DMA_CMD);
2314 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2315 ata_sff_dma_pause(ap);
2319 * ata_bmdma_status - Read PCI IDE BMDMA status
2320 * @ap: Port associated with this ATA transaction.
2322 * Read and return BMDMA status register.
2324 * May be used as the bmdma_status() entry in ata_port_operations.
2327 * spin_lock_irqsave(host lock)
2329 u8 ata_bmdma_status(struct ata_port *ap)
2331 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2335 * ata_bus_reset - reset host port and associated ATA channel
2336 * @ap: port to reset
2338 * This is typically the first time we actually start issuing
2339 * commands to the ATA channel. We wait for BSY to clear, then
2340 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2341 * result. Determine what devices, if any, are on the channel
2342 * by looking at the device 0/1 error register. Look at the signature
2343 * stored in each device's taskfile registers, to determine if
2344 * the device is ATA or ATAPI.
2347 * PCI/etc. bus probe sem.
2348 * Obtains host lock.
2351 * Sets ATA_FLAG_DISABLED if bus reset fails.
2354 * This function is only for drivers which still use old EH and
2355 * will be removed soon.
2357 void ata_bus_reset(struct ata_port *ap)
2359 struct ata_device *device = ap->link.device;
2360 struct ata_ioports *ioaddr = &ap->ioaddr;
2361 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2363 unsigned int dev0, dev1 = 0, devmask = 0;
2366 DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
2368 /* determine if device 0/1 are present */
2369 if (ap->flags & ATA_FLAG_SATA_RESET)
2372 dev0 = ata_devchk(ap, 0);
2374 dev1 = ata_devchk(ap, 1);
2378 devmask |= (1 << 0);
2380 devmask |= (1 << 1);
2382 /* select device 0 again */
2383 ap->ops->sff_dev_select(ap, 0);
2385 /* issue bus reset */
2386 if (ap->flags & ATA_FLAG_SRST) {
2387 rc = ata_bus_softreset(ap, devmask,
2388 ata_deadline(jiffies, 40000));
2389 if (rc && rc != -ENODEV)
2394 * determine by signature whether we have ATA or ATAPI devices
2396 device[0].class = ata_sff_dev_classify(&device[0], dev0, &err);
2397 if ((slave_possible) && (err != 0x81))
2398 device[1].class = ata_sff_dev_classify(&device[1], dev1, &err);
2400 /* is double-select really necessary? */
2401 if (device[1].class != ATA_DEV_NONE)
2402 ap->ops->sff_dev_select(ap, 1);
2403 if (device[0].class != ATA_DEV_NONE)
2404 ap->ops->sff_dev_select(ap, 0);
2406 /* if no devices were detected, disable this port */
2407 if ((device[0].class == ATA_DEV_NONE) &&
2408 (device[1].class == ATA_DEV_NONE))
2411 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2412 /* set up device control for ATA_FLAG_SATA_RESET */
2413 iowrite8(ap->ctl, ioaddr->ctl_addr);
2420 ata_port_printk(ap, KERN_ERR, "disabling port\n");
2421 ata_port_disable(ap);
2429 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
2432 * Some PCI ATA devices report simplex mode but in fact can be told to
2433 * enter non simplex mode. This implements the necessary logic to
2434 * perform the task on such devices. Calling it on other devices will
2435 * have -undefined- behaviour.
2437 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
2439 unsigned long bmdma = pci_resource_start(pdev, 4);
2445 simplex = inb(bmdma + 0x02);
2446 outb(simplex & 0x60, bmdma + 0x02);
2447 simplex = inb(bmdma + 0x02);
2454 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
2455 * @host: target ATA host
2457 * Acquire PCI BMDMA resources and initialize @host accordingly.
2460 * Inherited from calling layer (may sleep).
2463 * 0 on success, -errno otherwise.
2465 int ata_pci_bmdma_init(struct ata_host *host)
2467 struct device *gdev = host->dev;
2468 struct pci_dev *pdev = to_pci_dev(gdev);
2471 /* No BAR4 allocation: No DMA */
2472 if (pci_resource_start(pdev, 4) == 0)
2475 /* TODO: If we get no DMA mask we should fall back to PIO */
2476 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
2479 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
2483 /* request and iomap DMA region */
2484 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
2486 dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
2489 host->iomap = pcim_iomap_table(pdev);
2491 for (i = 0; i < 2; i++) {
2492 struct ata_port *ap = host->ports[i];
2493 void __iomem *bmdma = host->iomap[4] + 8 * i;
2495 if (ata_port_is_dummy(ap))
2498 ap->ioaddr.bmdma_addr = bmdma;
2499 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
2500 (ioread8(bmdma + 2) & 0x80))
2501 host->flags |= ATA_HOST_SIMPLEX;
2503 ata_port_desc(ap, "bmdma 0x%llx",
2504 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
2510 static int ata_resources_present(struct pci_dev *pdev, int port)
2514 /* Check the PCI resources for this channel are enabled */
2516 for (i = 0; i < 2; i ++) {
2517 if (pci_resource_start(pdev, port + i) == 0 ||
2518 pci_resource_len(pdev, port + i) == 0)
2525 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2526 * @host: target ATA host
2528 * Acquire native PCI ATA resources for @host and initialize the
2529 * first two ports of @host accordingly. Ports marked dummy are
2530 * skipped and allocation failure makes the port dummy.
2532 * Note that native PCI resources are valid even for legacy hosts
2533 * as we fix up pdev resources array early in boot, so this
2534 * function can be used for both native and legacy SFF hosts.
2537 * Inherited from calling layer (may sleep).
2540 * 0 if at least one port is initialized, -ENODEV if no port is
2543 int ata_pci_sff_init_host(struct ata_host *host)
2545 struct device *gdev = host->dev;
2546 struct pci_dev *pdev = to_pci_dev(gdev);
2547 unsigned int mask = 0;
2550 /* request, iomap BARs and init port addresses accordingly */
2551 for (i = 0; i < 2; i++) {
2552 struct ata_port *ap = host->ports[i];
2554 void __iomem * const *iomap;
2556 if (ata_port_is_dummy(ap))
2559 /* Discard disabled ports. Some controllers show
2560 * their unused channels this way. Disabled ports are
2563 if (!ata_resources_present(pdev, i)) {
2564 ap->ops = &ata_dummy_port_ops;
2568 rc = pcim_iomap_regions(pdev, 0x3 << base,
2569 dev_driver_string(gdev));
2571 dev_printk(KERN_WARNING, gdev,
2572 "failed to request/iomap BARs for port %d "
2573 "(errno=%d)\n", i, rc);
2575 pcim_pin_device(pdev);
2576 ap->ops = &ata_dummy_port_ops;
2579 host->iomap = iomap = pcim_iomap_table(pdev);
2581 ap->ioaddr.cmd_addr = iomap[base];
2582 ap->ioaddr.altstatus_addr =
2583 ap->ioaddr.ctl_addr = (void __iomem *)
2584 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2585 ata_sff_std_ports(&ap->ioaddr);
2587 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2588 (unsigned long long)pci_resource_start(pdev, base),
2589 (unsigned long long)pci_resource_start(pdev, base + 1));
2595 dev_printk(KERN_ERR, gdev, "no available native port\n");
2603 * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host
2604 * @pdev: target PCI device
2605 * @ppi: array of port_info, must be enough for two ports
2606 * @r_host: out argument for the initialized ATA host
2608 * Helper to allocate ATA host for @pdev, acquire all native PCI
2609 * resources and initialize it accordingly in one go.
2612 * Inherited from calling layer (may sleep).
2615 * 0 on success, -errno otherwise.
2617 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2618 const struct ata_port_info * const * ppi,
2619 struct ata_host **r_host)
2621 struct ata_host *host;
2624 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2627 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2629 dev_printk(KERN_ERR, &pdev->dev,
2630 "failed to allocate ATA host\n");
2635 rc = ata_pci_sff_init_host(host);
2639 /* init DMA related stuff */
2640 rc = ata_pci_bmdma_init(host);
2644 devres_remove_group(&pdev->dev, NULL);
2649 /* This is necessary because PCI and iomap resources are
2650 * merged and releasing the top group won't release the
2651 * acquired resources if some of those have been acquired
2652 * before entering this function.
2654 pcim_iounmap_regions(pdev, 0xf);
2656 devres_release_group(&pdev->dev, NULL);
2661 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2662 * @host: target SFF ATA host
2663 * @irq_handler: irq_handler used when requesting IRQ(s)
2664 * @sht: scsi_host_template to use when registering the host
2666 * This is the counterpart of ata_host_activate() for SFF ATA
2667 * hosts. This separate helper is necessary because SFF hosts
2668 * use two separate interrupts in legacy mode.
2671 * Inherited from calling layer (may sleep).
2674 * 0 on success, -errno otherwise.
2676 int ata_pci_sff_activate_host(struct ata_host *host,
2677 irq_handler_t irq_handler,
2678 struct scsi_host_template *sht)
2680 struct device *dev = host->dev;
2681 struct pci_dev *pdev = to_pci_dev(dev);
2682 const char *drv_name = dev_driver_string(host->dev);
2683 int legacy_mode = 0, rc;
2685 rc = ata_host_start(host);
2689 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2692 /* TODO: What if one channel is in native mode ... */
2693 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2694 mask = (1 << 2) | (1 << 0);
2695 if ((tmp8 & mask) != mask)
2697 #if defined(CONFIG_NO_ATA_LEGACY)
2698 /* Some platforms with PCI limits cannot address compat
2699 port space. In that case we punt if their firmware has
2700 left a device in compatibility mode */
2702 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
2708 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2711 if (!legacy_mode && pdev->irq) {
2712 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2713 IRQF_SHARED, drv_name, host);
2717 ata_port_desc(host->ports[0], "irq %d", pdev->irq);
2718 ata_port_desc(host->ports[1], "irq %d", pdev->irq);
2719 } else if (legacy_mode) {
2720 if (!ata_port_is_dummy(host->ports[0])) {
2721 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2722 irq_handler, IRQF_SHARED,
2727 ata_port_desc(host->ports[0], "irq %d",
2728 ATA_PRIMARY_IRQ(pdev));
2731 if (!ata_port_is_dummy(host->ports[1])) {
2732 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2733 irq_handler, IRQF_SHARED,
2738 ata_port_desc(host->ports[1], "irq %d",
2739 ATA_SECONDARY_IRQ(pdev));
2743 rc = ata_host_register(host, sht);
2746 devres_remove_group(dev, NULL);
2748 devres_release_group(dev, NULL);
2754 * ata_pci_sff_init_one - Initialize/register PCI IDE host controller
2755 * @pdev: Controller to be initialized
2756 * @ppi: array of port_info, must be enough for two ports
2757 * @sht: scsi_host_template to use when registering the host
2758 * @host_priv: host private_data
2760 * This is a helper function which can be called from a driver's
2761 * xxx_init_one() probe function if the hardware uses traditional
2762 * IDE taskfile registers.
2764 * This function calls pci_enable_device(), reserves its register
2765 * regions, sets the dma mask, enables bus master mode, and calls
2769 * Nobody makes a single channel controller that appears solely as
2770 * the secondary legacy port on PCI.
2773 * Inherited from PCI layer (may sleep).
2776 * Zero on success, negative on errno-based value on error.
2778 int ata_pci_sff_init_one(struct pci_dev *pdev,
2779 const struct ata_port_info * const * ppi,
2780 struct scsi_host_template *sht, void *host_priv)
2782 struct device *dev = &pdev->dev;
2783 const struct ata_port_info *pi = NULL;
2784 struct ata_host *host = NULL;
2789 /* look up the first valid port_info */
2790 for (i = 0; i < 2 && ppi[i]; i++) {
2791 if (ppi[i]->port_ops != &ata_dummy_port_ops) {
2798 dev_printk(KERN_ERR, &pdev->dev,
2799 "no valid port_info specified\n");
2803 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2806 rc = pcim_enable_device(pdev);
2810 /* prepare and activate SFF host */
2811 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2814 host->private_data = host_priv;
2816 pci_set_master(pdev);
2817 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2820 devres_remove_group(&pdev->dev, NULL);
2822 devres_release_group(&pdev->dev, NULL);
2827 #endif /* CONFIG_PCI */
2829 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
2830 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2831 EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
2832 EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
2833 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
2834 EXPORT_SYMBOL_GPL(ata_sff_check_status);
2835 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
2836 EXPORT_SYMBOL_GPL(ata_sff_pause);
2837 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
2838 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
2839 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
2840 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
2841 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
2842 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
2843 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
2844 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
2845 EXPORT_SYMBOL_GPL(ata_sff_irq_clear);
2846 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
2847 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
2848 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
2849 EXPORT_SYMBOL_GPL(ata_sff_host_intr);
2850 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
2851 EXPORT_SYMBOL_GPL(ata_sff_freeze);
2852 EXPORT_SYMBOL_GPL(ata_sff_thaw);
2853 EXPORT_SYMBOL_GPL(ata_sff_prereset);
2854 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
2855 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2856 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2857 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2858 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2859 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2860 EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd);
2861 EXPORT_SYMBOL_GPL(ata_sff_port_start);
2862 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2863 EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
2864 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2865 EXPORT_SYMBOL_GPL(ata_bmdma_start);
2866 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2867 EXPORT_SYMBOL_GPL(ata_bmdma_status);
2868 EXPORT_SYMBOL_GPL(ata_bus_reset);
2870 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
2871 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
2872 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2873 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2874 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2875 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2876 #endif /* CONFIG_PCI */