2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56 static int ahci_enable_alpm(struct ata_port *ap,
58 static void ahci_disable_alpm(struct ata_port *ap);
59 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
60 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
62 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
69 AHCI_MAX_SG = 168, /* hardware max is 64K */
70 AHCI_DMA_BOUNDARY = 0xffffffff,
73 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
75 AHCI_CMD_TBL_CDB = 0x40,
76 AHCI_CMD_TBL_HDR_SZ = 0x80,
77 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
78 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
79 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
81 AHCI_IRQ_ON_SG = (1 << 31),
82 AHCI_CMD_ATAPI = (1 << 5),
83 AHCI_CMD_WRITE = (1 << 6),
84 AHCI_CMD_PREFETCH = (1 << 7),
85 AHCI_CMD_RESET = (1 << 8),
86 AHCI_CMD_CLR_BUSY = (1 << 10),
88 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
89 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
90 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
93 board_ahci_vt8251 = 1,
94 board_ahci_ign_iferr = 2,
101 /* global controller registers */
102 HOST_CAP = 0x00, /* host capabilities */
103 HOST_CTL = 0x04, /* global host control */
104 HOST_IRQ_STAT = 0x08, /* interrupt status */
105 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
106 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
107 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
108 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
111 HOST_RESET = (1 << 0), /* reset controller; self-clear */
112 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
113 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
116 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
117 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
118 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
119 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
120 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
121 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
122 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
123 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
124 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
126 /* registers for each SATA port */
127 PORT_LST_ADDR = 0x00, /* command list DMA addr */
128 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
129 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
130 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
131 PORT_IRQ_STAT = 0x10, /* interrupt status */
132 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
133 PORT_CMD = 0x18, /* port command */
134 PORT_TFDATA = 0x20, /* taskfile data */
135 PORT_SIG = 0x24, /* device TF signature */
136 PORT_CMD_ISSUE = 0x38, /* command issue */
137 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
138 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
139 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
140 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
141 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
143 /* PORT_IRQ_{STAT,MASK} bits */
144 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
145 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
146 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
147 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
148 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
149 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
150 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
151 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
153 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
154 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
155 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
156 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
157 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
158 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
159 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
160 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
161 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
163 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
169 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
171 PORT_IRQ_HBUS_DATA_ERR,
172 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
173 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
174 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
177 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
178 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
179 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
180 PORT_CMD_PMP = (1 << 17), /* PMP attached */
181 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
182 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
183 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
184 PORT_CMD_CLO = (1 << 3), /* Command list override */
185 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
186 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
187 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
189 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
190 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
191 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
192 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
194 /* hpriv->flags bits */
195 AHCI_HFLAG_NO_NCQ = (1 << 0),
196 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
197 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
198 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
199 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
200 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
201 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
202 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
203 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
204 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
208 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
209 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
210 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
213 ICH_MAP = 0x90, /* ICH MAP register */
216 EM_CTL_RST = (1 << 9), /* Reset */
217 EM_CTL_TM = (1 << 8), /* Transmit Message */
218 EM_CTL_ALHD = (1 << 26), /* Activity LED */
221 struct ahci_cmd_hdr {
236 struct ahci_em_priv {
237 enum sw_activity blink_policy;
238 struct timer_list timer;
239 unsigned long saved_activity;
240 unsigned long activity;
241 unsigned long led_state;
244 struct ahci_host_priv {
245 unsigned int flags; /* AHCI_HFLAG_* */
246 u32 cap; /* cap to use */
247 u32 port_map; /* port map to use */
248 u32 saved_cap; /* saved initial cap */
249 u32 saved_port_map; /* saved initial port_map */
250 u32 em_loc; /* enclosure management location */
253 struct ahci_port_priv {
254 struct ata_link *active_link;
255 struct ahci_cmd_hdr *cmd_slot;
256 dma_addr_t cmd_slot_dma;
258 dma_addr_t cmd_tbl_dma;
260 dma_addr_t rx_fis_dma;
261 /* for NCQ spurious interrupt analysis */
262 unsigned int ncq_saw_d2h:1;
263 unsigned int ncq_saw_dmas:1;
264 unsigned int ncq_saw_sdb:1;
265 u32 intr_mask; /* interrupts to enable */
266 struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
270 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
271 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
272 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
273 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
274 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
275 static int ahci_port_start(struct ata_port *ap);
276 static void ahci_port_stop(struct ata_port *ap);
277 static void ahci_qc_prep(struct ata_queued_cmd *qc);
278 static void ahci_freeze(struct ata_port *ap);
279 static void ahci_thaw(struct ata_port *ap);
280 static void ahci_pmp_attach(struct ata_port *ap);
281 static void ahci_pmp_detach(struct ata_port *ap);
282 static int ahci_softreset(struct ata_link *link, unsigned int *class,
283 unsigned long deadline);
284 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
285 unsigned long deadline);
286 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
287 unsigned long deadline);
288 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
289 unsigned long deadline);
290 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
291 unsigned long deadline);
292 static void ahci_postreset(struct ata_link *link, unsigned int *class);
293 static void ahci_error_handler(struct ata_port *ap);
294 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
295 static int ahci_port_resume(struct ata_port *ap);
296 static void ahci_dev_config(struct ata_device *dev);
297 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
298 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
301 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
302 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
303 static int ahci_pci_device_resume(struct pci_dev *pdev);
305 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
306 static ssize_t ahci_activity_store(struct ata_device *dev,
307 enum sw_activity val);
308 static void ahci_init_sw_activity(struct ata_link *link);
310 static struct device_attribute *ahci_shost_attrs[] = {
311 &dev_attr_link_power_management_policy,
312 &dev_attr_em_message_type,
313 &dev_attr_em_message,
317 static struct device_attribute *ahci_sdev_attrs[] = {
318 &dev_attr_sw_activity,
319 &dev_attr_unload_heads,
323 static struct scsi_host_template ahci_sht = {
324 ATA_NCQ_SHT(DRV_NAME),
325 .can_queue = AHCI_MAX_CMDS - 1,
326 .sg_tablesize = AHCI_MAX_SG,
327 .dma_boundary = AHCI_DMA_BOUNDARY,
328 .shost_attrs = ahci_shost_attrs,
329 .sdev_attrs = ahci_sdev_attrs,
332 static struct ata_port_operations ahci_ops = {
333 .inherits = &sata_pmp_port_ops,
335 .qc_defer = sata_pmp_qc_defer_cmd_switch,
336 .qc_prep = ahci_qc_prep,
337 .qc_issue = ahci_qc_issue,
338 .qc_fill_rtf = ahci_qc_fill_rtf,
340 .freeze = ahci_freeze,
342 .softreset = ahci_softreset,
343 .hardreset = ahci_hardreset,
344 .postreset = ahci_postreset,
345 .pmp_softreset = ahci_softreset,
346 .error_handler = ahci_error_handler,
347 .post_internal_cmd = ahci_post_internal_cmd,
348 .dev_config = ahci_dev_config,
350 .scr_read = ahci_scr_read,
351 .scr_write = ahci_scr_write,
352 .pmp_attach = ahci_pmp_attach,
353 .pmp_detach = ahci_pmp_detach,
355 .enable_pm = ahci_enable_alpm,
356 .disable_pm = ahci_disable_alpm,
357 .em_show = ahci_led_show,
358 .em_store = ahci_led_store,
359 .sw_activity_show = ahci_activity_show,
360 .sw_activity_store = ahci_activity_store,
362 .port_suspend = ahci_port_suspend,
363 .port_resume = ahci_port_resume,
365 .port_start = ahci_port_start,
366 .port_stop = ahci_port_stop,
369 static struct ata_port_operations ahci_vt8251_ops = {
370 .inherits = &ahci_ops,
371 .hardreset = ahci_vt8251_hardreset,
374 static struct ata_port_operations ahci_p5wdh_ops = {
375 .inherits = &ahci_ops,
376 .hardreset = ahci_p5wdh_hardreset,
379 static struct ata_port_operations ahci_sb600_ops = {
380 .inherits = &ahci_ops,
381 .softreset = ahci_sb600_softreset,
382 .pmp_softreset = ahci_sb600_softreset,
385 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
387 static const struct ata_port_info ahci_port_info[] = {
390 .flags = AHCI_FLAG_COMMON,
391 .pio_mask = 0x1f, /* pio0-4 */
392 .udma_mask = ATA_UDMA6,
393 .port_ops = &ahci_ops,
395 /* board_ahci_vt8251 */
397 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
398 .flags = AHCI_FLAG_COMMON,
399 .pio_mask = 0x1f, /* pio0-4 */
400 .udma_mask = ATA_UDMA6,
401 .port_ops = &ahci_vt8251_ops,
403 /* board_ahci_ign_iferr */
405 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
406 .flags = AHCI_FLAG_COMMON,
407 .pio_mask = 0x1f, /* pio0-4 */
408 .udma_mask = ATA_UDMA6,
409 .port_ops = &ahci_ops,
411 /* board_ahci_sb600 */
413 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
414 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
416 .flags = AHCI_FLAG_COMMON,
417 .pio_mask = 0x1f, /* pio0-4 */
418 .udma_mask = ATA_UDMA6,
419 .port_ops = &ahci_sb600_ops,
423 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
424 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
425 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
426 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
427 .pio_mask = 0x1f, /* pio0-4 */
428 .udma_mask = ATA_UDMA6,
429 .port_ops = &ahci_ops,
431 /* board_ahci_sb700 */
433 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
434 .flags = AHCI_FLAG_COMMON,
435 .pio_mask = 0x1f, /* pio0-4 */
436 .udma_mask = ATA_UDMA6,
437 .port_ops = &ahci_sb600_ops,
439 /* board_ahci_mcp65 */
441 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
442 .flags = AHCI_FLAG_COMMON,
443 .pio_mask = 0x1f, /* pio0-4 */
444 .udma_mask = ATA_UDMA6,
445 .port_ops = &ahci_ops,
447 /* board_ahci_nopmp */
449 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
450 .flags = AHCI_FLAG_COMMON,
451 .pio_mask = 0x1f, /* pio0-4 */
452 .udma_mask = ATA_UDMA6,
453 .port_ops = &ahci_ops,
457 static const struct pci_device_id ahci_pci_tbl[] = {
459 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
460 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
461 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
462 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
463 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
464 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
465 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
466 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
467 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
468 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
469 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
470 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
471 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
472 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
473 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
474 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
476 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
477 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
478 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
479 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
480 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
481 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
482 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
483 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
484 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
485 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
486 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
487 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
488 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
489 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
490 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
491 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
492 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
493 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
495 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
496 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
497 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
500 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
501 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
502 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
504 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
505 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
506 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
509 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
510 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
513 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
516 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
518 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
519 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
520 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
521 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
522 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
530 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
531 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
532 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
533 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
543 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
544 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
545 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
555 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
556 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
557 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
558 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
566 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
567 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
568 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
569 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
570 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
572 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
574 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
577 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
578 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
579 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
580 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
583 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
584 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
585 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
588 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
589 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
592 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
594 /* Generic, PCI class code for AHCI */
595 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
596 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
598 { } /* terminate list */
602 static struct pci_driver ahci_pci_driver = {
604 .id_table = ahci_pci_tbl,
605 .probe = ahci_init_one,
606 .remove = ata_pci_remove_one,
608 .suspend = ahci_pci_device_suspend,
609 .resume = ahci_pci_device_resume,
613 static int ahci_em_messages = 1;
614 module_param(ahci_em_messages, int, 0444);
615 /* add other LED protocol types when they become supported */
616 MODULE_PARM_DESC(ahci_em_messages,
617 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
619 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
620 static int marvell_enable;
622 static int marvell_enable = 1;
624 module_param(marvell_enable, int, 0644);
625 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
628 static inline int ahci_nr_ports(u32 cap)
630 return (cap & 0x1f) + 1;
633 static inline void __iomem *__ahci_port_base(struct ata_host *host,
634 unsigned int port_no)
636 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
638 return mmio + 0x100 + (port_no * 0x80);
641 static inline void __iomem *ahci_port_base(struct ata_port *ap)
643 return __ahci_port_base(ap->host, ap->port_no);
646 static void ahci_enable_ahci(void __iomem *mmio)
651 /* turn on AHCI_EN */
652 tmp = readl(mmio + HOST_CTL);
653 if (tmp & HOST_AHCI_EN)
656 /* Some controllers need AHCI_EN to be written multiple times.
657 * Try a few times before giving up.
659 for (i = 0; i < 5; i++) {
661 writel(tmp, mmio + HOST_CTL);
662 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
663 if (tmp & HOST_AHCI_EN)
672 * ahci_save_initial_config - Save and fixup initial config values
673 * @pdev: target PCI device
674 * @hpriv: host private area to store config values
676 * Some registers containing configuration info might be setup by
677 * BIOS and might be cleared on reset. This function saves the
678 * initial values of those registers into @hpriv such that they
679 * can be restored after controller reset.
681 * If inconsistent, config values are fixed up by this function.
686 static void ahci_save_initial_config(struct pci_dev *pdev,
687 struct ahci_host_priv *hpriv)
689 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
694 /* make sure AHCI mode is enabled before accessing CAP */
695 ahci_enable_ahci(mmio);
697 /* Values prefixed with saved_ are written back to host after
698 * reset. Values without are used for driver operation.
700 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
701 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
703 /* some chips have errata preventing 64bit use */
704 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
705 dev_printk(KERN_INFO, &pdev->dev,
706 "controller can't do 64bit DMA, forcing 32bit\n");
710 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
711 dev_printk(KERN_INFO, &pdev->dev,
712 "controller can't do NCQ, turning off CAP_NCQ\n");
713 cap &= ~HOST_CAP_NCQ;
716 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
717 dev_printk(KERN_INFO, &pdev->dev,
718 "controller can do NCQ, turning on CAP_NCQ\n");
722 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
723 dev_printk(KERN_INFO, &pdev->dev,
724 "controller can't do PMP, turning off CAP_PMP\n");
725 cap &= ~HOST_CAP_PMP;
728 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
730 dev_printk(KERN_INFO, &pdev->dev,
731 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
737 * Temporary Marvell 6145 hack: PATA port presence
738 * is asserted through the standard AHCI port
739 * presence register, as bit 4 (counting from 0)
741 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
742 if (pdev->device == 0x6121)
746 dev_printk(KERN_ERR, &pdev->dev,
747 "MV_AHCI HACK: port_map %x -> %x\n",
750 dev_printk(KERN_ERR, &pdev->dev,
751 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
756 /* cross check port_map and cap.n_ports */
760 for (i = 0; i < AHCI_MAX_PORTS; i++)
761 if (port_map & (1 << i))
764 /* If PI has more ports than n_ports, whine, clear
765 * port_map and let it be generated from n_ports.
767 if (map_ports > ahci_nr_ports(cap)) {
768 dev_printk(KERN_WARNING, &pdev->dev,
769 "implemented port map (0x%x) contains more "
770 "ports than nr_ports (%u), using nr_ports\n",
771 port_map, ahci_nr_ports(cap));
776 /* fabricate port_map from cap.nr_ports */
778 port_map = (1 << ahci_nr_ports(cap)) - 1;
779 dev_printk(KERN_WARNING, &pdev->dev,
780 "forcing PORTS_IMPL to 0x%x\n", port_map);
782 /* write the fixed up value to the PI register */
783 hpriv->saved_port_map = port_map;
786 /* record values to use during operation */
788 hpriv->port_map = port_map;
792 * ahci_restore_initial_config - Restore initial config
793 * @host: target ATA host
795 * Restore initial config stored by ahci_save_initial_config().
800 static void ahci_restore_initial_config(struct ata_host *host)
802 struct ahci_host_priv *hpriv = host->private_data;
803 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
805 writel(hpriv->saved_cap, mmio + HOST_CAP);
806 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
807 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
810 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
812 static const int offset[] = {
813 [SCR_STATUS] = PORT_SCR_STAT,
814 [SCR_CONTROL] = PORT_SCR_CTL,
815 [SCR_ERROR] = PORT_SCR_ERR,
816 [SCR_ACTIVE] = PORT_SCR_ACT,
817 [SCR_NOTIFICATION] = PORT_SCR_NTF,
819 struct ahci_host_priv *hpriv = ap->host->private_data;
821 if (sc_reg < ARRAY_SIZE(offset) &&
822 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
823 return offset[sc_reg];
827 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
829 void __iomem *port_mmio = ahci_port_base(link->ap);
830 int offset = ahci_scr_offset(link->ap, sc_reg);
833 *val = readl(port_mmio + offset);
839 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
841 void __iomem *port_mmio = ahci_port_base(link->ap);
842 int offset = ahci_scr_offset(link->ap, sc_reg);
845 writel(val, port_mmio + offset);
851 static void ahci_start_engine(struct ata_port *ap)
853 void __iomem *port_mmio = ahci_port_base(ap);
857 tmp = readl(port_mmio + PORT_CMD);
858 tmp |= PORT_CMD_START;
859 writel(tmp, port_mmio + PORT_CMD);
860 readl(port_mmio + PORT_CMD); /* flush */
863 static int ahci_stop_engine(struct ata_port *ap)
865 void __iomem *port_mmio = ahci_port_base(ap);
868 tmp = readl(port_mmio + PORT_CMD);
870 /* check if the HBA is idle */
871 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
874 /* setting HBA to idle */
875 tmp &= ~PORT_CMD_START;
876 writel(tmp, port_mmio + PORT_CMD);
878 /* wait for engine to stop. This could be as long as 500 msec */
879 tmp = ata_wait_register(port_mmio + PORT_CMD,
880 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
881 if (tmp & PORT_CMD_LIST_ON)
887 static void ahci_start_fis_rx(struct ata_port *ap)
889 void __iomem *port_mmio = ahci_port_base(ap);
890 struct ahci_host_priv *hpriv = ap->host->private_data;
891 struct ahci_port_priv *pp = ap->private_data;
894 /* set FIS registers */
895 if (hpriv->cap & HOST_CAP_64)
896 writel((pp->cmd_slot_dma >> 16) >> 16,
897 port_mmio + PORT_LST_ADDR_HI);
898 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
900 if (hpriv->cap & HOST_CAP_64)
901 writel((pp->rx_fis_dma >> 16) >> 16,
902 port_mmio + PORT_FIS_ADDR_HI);
903 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
905 /* enable FIS reception */
906 tmp = readl(port_mmio + PORT_CMD);
907 tmp |= PORT_CMD_FIS_RX;
908 writel(tmp, port_mmio + PORT_CMD);
911 readl(port_mmio + PORT_CMD);
914 static int ahci_stop_fis_rx(struct ata_port *ap)
916 void __iomem *port_mmio = ahci_port_base(ap);
919 /* disable FIS reception */
920 tmp = readl(port_mmio + PORT_CMD);
921 tmp &= ~PORT_CMD_FIS_RX;
922 writel(tmp, port_mmio + PORT_CMD);
924 /* wait for completion, spec says 500ms, give it 1000 */
925 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
926 PORT_CMD_FIS_ON, 10, 1000);
927 if (tmp & PORT_CMD_FIS_ON)
933 static void ahci_power_up(struct ata_port *ap)
935 struct ahci_host_priv *hpriv = ap->host->private_data;
936 void __iomem *port_mmio = ahci_port_base(ap);
939 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
942 if (hpriv->cap & HOST_CAP_SSS) {
943 cmd |= PORT_CMD_SPIN_UP;
944 writel(cmd, port_mmio + PORT_CMD);
948 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
951 static void ahci_disable_alpm(struct ata_port *ap)
953 struct ahci_host_priv *hpriv = ap->host->private_data;
954 void __iomem *port_mmio = ahci_port_base(ap);
956 struct ahci_port_priv *pp = ap->private_data;
958 /* IPM bits should be disabled by libata-core */
959 /* get the existing command bits */
960 cmd = readl(port_mmio + PORT_CMD);
962 /* disable ALPM and ASP */
963 cmd &= ~PORT_CMD_ASP;
964 cmd &= ~PORT_CMD_ALPE;
966 /* force the interface back to active */
967 cmd |= PORT_CMD_ICC_ACTIVE;
969 /* write out new cmd value */
970 writel(cmd, port_mmio + PORT_CMD);
971 cmd = readl(port_mmio + PORT_CMD);
973 /* wait 10ms to be sure we've come out of any low power state */
976 /* clear out any PhyRdy stuff from interrupt status */
977 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
979 /* go ahead and clean out PhyRdy Change from Serror too */
980 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
983 * Clear flag to indicate that we should ignore all PhyRdy
986 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
989 * Enable interrupts on Phy Ready.
991 pp->intr_mask |= PORT_IRQ_PHYRDY;
992 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
995 * don't change the link pm policy - we can be called
996 * just to turn of link pm temporarily
1000 static int ahci_enable_alpm(struct ata_port *ap,
1001 enum link_pm policy)
1003 struct ahci_host_priv *hpriv = ap->host->private_data;
1004 void __iomem *port_mmio = ahci_port_base(ap);
1006 struct ahci_port_priv *pp = ap->private_data;
1009 /* Make sure the host is capable of link power management */
1010 if (!(hpriv->cap & HOST_CAP_ALPM))
1014 case MAX_PERFORMANCE:
1017 * if we came here with NOT_AVAILABLE,
1018 * it just means this is the first time we
1019 * have tried to enable - default to max performance,
1020 * and let the user go to lower power modes on request.
1022 ahci_disable_alpm(ap);
1025 /* configure HBA to enter SLUMBER */
1029 /* configure HBA to enter PARTIAL */
1037 * Disable interrupts on Phy Ready. This keeps us from
1038 * getting woken up due to spurious phy ready interrupts
1039 * TBD - Hot plug should be done via polling now, is
1040 * that even supported?
1042 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1043 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1046 * Set a flag to indicate that we should ignore all PhyRdy
1047 * state changes since these can happen now whenever we
1050 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1052 /* get the existing command bits */
1053 cmd = readl(port_mmio + PORT_CMD);
1056 * Set ASP based on Policy
1061 * Setting this bit will instruct the HBA to aggressively
1062 * enter a lower power link state when it's appropriate and
1063 * based on the value set above for ASP
1065 cmd |= PORT_CMD_ALPE;
1067 /* write out new cmd value */
1068 writel(cmd, port_mmio + PORT_CMD);
1069 cmd = readl(port_mmio + PORT_CMD);
1071 /* IPM bits should be set by libata-core */
1076 static void ahci_power_down(struct ata_port *ap)
1078 struct ahci_host_priv *hpriv = ap->host->private_data;
1079 void __iomem *port_mmio = ahci_port_base(ap);
1082 if (!(hpriv->cap & HOST_CAP_SSS))
1085 /* put device into listen mode, first set PxSCTL.DET to 0 */
1086 scontrol = readl(port_mmio + PORT_SCR_CTL);
1088 writel(scontrol, port_mmio + PORT_SCR_CTL);
1090 /* then set PxCMD.SUD to 0 */
1091 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1092 cmd &= ~PORT_CMD_SPIN_UP;
1093 writel(cmd, port_mmio + PORT_CMD);
1097 static void ahci_start_port(struct ata_port *ap)
1099 struct ahci_port_priv *pp = ap->private_data;
1100 struct ata_link *link;
1101 struct ahci_em_priv *emp;
1103 /* enable FIS reception */
1104 ahci_start_fis_rx(ap);
1107 ahci_start_engine(ap);
1110 if (ap->flags & ATA_FLAG_EM) {
1111 ata_port_for_each_link(link, ap) {
1112 emp = &pp->em_priv[link->pmp];
1113 ahci_transmit_led_message(ap, emp->led_state, 4);
1117 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1118 ata_port_for_each_link(link, ap)
1119 ahci_init_sw_activity(link);
1123 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1128 rc = ahci_stop_engine(ap);
1130 *emsg = "failed to stop engine";
1134 /* disable FIS reception */
1135 rc = ahci_stop_fis_rx(ap);
1137 *emsg = "failed stop FIS RX";
1144 static int ahci_reset_controller(struct ata_host *host)
1146 struct pci_dev *pdev = to_pci_dev(host->dev);
1147 struct ahci_host_priv *hpriv = host->private_data;
1148 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1151 /* we must be in AHCI mode, before using anything
1152 * AHCI-specific, such as HOST_RESET.
1154 ahci_enable_ahci(mmio);
1156 /* global controller reset */
1157 if (!ahci_skip_host_reset) {
1158 tmp = readl(mmio + HOST_CTL);
1159 if ((tmp & HOST_RESET) == 0) {
1160 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1161 readl(mmio + HOST_CTL); /* flush */
1165 * to perform host reset, OS should set HOST_RESET
1166 * and poll until this bit is read to be "0".
1167 * reset must complete within 1 second, or
1168 * the hardware should be considered fried.
1170 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1171 HOST_RESET, 10, 1000);
1173 if (tmp & HOST_RESET) {
1174 dev_printk(KERN_ERR, host->dev,
1175 "controller reset failed (0x%x)\n", tmp);
1179 /* turn on AHCI mode */
1180 ahci_enable_ahci(mmio);
1182 /* Some registers might be cleared on reset. Restore
1185 ahci_restore_initial_config(host);
1187 dev_printk(KERN_INFO, host->dev,
1188 "skipping global host reset\n");
1190 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1194 pci_read_config_word(pdev, 0x92, &tmp16);
1195 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1196 tmp16 |= hpriv->port_map;
1197 pci_write_config_word(pdev, 0x92, tmp16);
1204 static void ahci_sw_activity(struct ata_link *link)
1206 struct ata_port *ap = link->ap;
1207 struct ahci_port_priv *pp = ap->private_data;
1208 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1210 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1214 if (!timer_pending(&emp->timer))
1215 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1218 static void ahci_sw_activity_blink(unsigned long arg)
1220 struct ata_link *link = (struct ata_link *)arg;
1221 struct ata_port *ap = link->ap;
1222 struct ahci_port_priv *pp = ap->private_data;
1223 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1224 unsigned long led_message = emp->led_state;
1225 u32 activity_led_state;
1226 unsigned long flags;
1228 led_message &= 0xffff0000;
1229 led_message |= ap->port_no | (link->pmp << 8);
1231 /* check to see if we've had activity. If so,
1232 * toggle state of LED and reset timer. If not,
1233 * turn LED to desired idle state.
1235 spin_lock_irqsave(ap->lock, flags);
1236 if (emp->saved_activity != emp->activity) {
1237 emp->saved_activity = emp->activity;
1238 /* get the current LED state */
1239 activity_led_state = led_message & 0x00010000;
1241 if (activity_led_state)
1242 activity_led_state = 0;
1244 activity_led_state = 1;
1246 /* clear old state */
1247 led_message &= 0xfff8ffff;
1250 led_message |= (activity_led_state << 16);
1251 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1253 /* switch to idle */
1254 led_message &= 0xfff8ffff;
1255 if (emp->blink_policy == BLINK_OFF)
1256 led_message |= (1 << 16);
1258 spin_unlock_irqrestore(ap->lock, flags);
1259 ahci_transmit_led_message(ap, led_message, 4);
1262 static void ahci_init_sw_activity(struct ata_link *link)
1264 struct ata_port *ap = link->ap;
1265 struct ahci_port_priv *pp = ap->private_data;
1266 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1268 /* init activity stats, setup timer */
1269 emp->saved_activity = emp->activity = 0;
1270 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1272 /* check our blink policy and set flag for link if it's enabled */
1273 if (emp->blink_policy)
1274 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1277 static int ahci_reset_em(struct ata_host *host)
1279 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1282 em_ctl = readl(mmio + HOST_EM_CTL);
1283 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1286 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1290 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1293 struct ahci_host_priv *hpriv = ap->host->private_data;
1294 struct ahci_port_priv *pp = ap->private_data;
1295 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1297 u32 message[] = {0, 0};
1298 unsigned long flags;
1300 struct ahci_em_priv *emp;
1302 /* get the slot number from the message */
1303 pmp = (state & 0x0000ff00) >> 8;
1304 if (pmp < MAX_SLOTS)
1305 emp = &pp->em_priv[pmp];
1309 spin_lock_irqsave(ap->lock, flags);
1312 * if we are still busy transmitting a previous message,
1315 em_ctl = readl(mmio + HOST_EM_CTL);
1316 if (em_ctl & EM_CTL_TM) {
1317 spin_unlock_irqrestore(ap->lock, flags);
1322 * create message header - this is all zero except for
1323 * the message size, which is 4 bytes.
1325 message[0] |= (4 << 8);
1327 /* ignore 0:4 of byte zero, fill in port info yourself */
1328 message[1] = ((state & 0xfffffff0) | ap->port_no);
1330 /* write message to EM_LOC */
1331 writel(message[0], mmio + hpriv->em_loc);
1332 writel(message[1], mmio + hpriv->em_loc+4);
1334 /* save off new led state for port/slot */
1335 emp->led_state = message[1];
1338 * tell hardware to transmit the message
1340 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1342 spin_unlock_irqrestore(ap->lock, flags);
1346 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1348 struct ahci_port_priv *pp = ap->private_data;
1349 struct ata_link *link;
1350 struct ahci_em_priv *emp;
1353 ata_port_for_each_link(link, ap) {
1354 emp = &pp->em_priv[link->pmp];
1355 rc += sprintf(buf, "%lx\n", emp->led_state);
1360 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1365 struct ahci_port_priv *pp = ap->private_data;
1366 struct ahci_em_priv *emp;
1368 state = simple_strtoul(buf, NULL, 0);
1370 /* get the slot number from the message */
1371 pmp = (state & 0x0000ff00) >> 8;
1372 if (pmp < MAX_SLOTS)
1373 emp = &pp->em_priv[pmp];
1377 /* mask off the activity bits if we are in sw_activity
1378 * mode, user should turn off sw_activity before setting
1379 * activity led through em_message
1381 if (emp->blink_policy)
1382 state &= 0xfff8ffff;
1384 return ahci_transmit_led_message(ap, state, size);
1387 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1389 struct ata_link *link = dev->link;
1390 struct ata_port *ap = link->ap;
1391 struct ahci_port_priv *pp = ap->private_data;
1392 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1393 u32 port_led_state = emp->led_state;
1395 /* save the desired Activity LED behavior */
1398 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1400 /* set the LED to OFF */
1401 port_led_state &= 0xfff80000;
1402 port_led_state |= (ap->port_no | (link->pmp << 8));
1403 ahci_transmit_led_message(ap, port_led_state, 4);
1405 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1406 if (val == BLINK_OFF) {
1407 /* set LED to ON for idle */
1408 port_led_state &= 0xfff80000;
1409 port_led_state |= (ap->port_no | (link->pmp << 8));
1410 port_led_state |= 0x00010000; /* check this */
1411 ahci_transmit_led_message(ap, port_led_state, 4);
1414 emp->blink_policy = val;
1418 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1420 struct ata_link *link = dev->link;
1421 struct ata_port *ap = link->ap;
1422 struct ahci_port_priv *pp = ap->private_data;
1423 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1425 /* display the saved value of activity behavior for this
1428 return sprintf(buf, "%d\n", emp->blink_policy);
1431 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1432 int port_no, void __iomem *mmio,
1433 void __iomem *port_mmio)
1435 const char *emsg = NULL;
1439 /* make sure port is not active */
1440 rc = ahci_deinit_port(ap, &emsg);
1442 dev_printk(KERN_WARNING, &pdev->dev,
1443 "%s (%d)\n", emsg, rc);
1446 tmp = readl(port_mmio + PORT_SCR_ERR);
1447 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1448 writel(tmp, port_mmio + PORT_SCR_ERR);
1450 /* clear port IRQ */
1451 tmp = readl(port_mmio + PORT_IRQ_STAT);
1452 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1454 writel(tmp, port_mmio + PORT_IRQ_STAT);
1456 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1459 static void ahci_init_controller(struct ata_host *host)
1461 struct ahci_host_priv *hpriv = host->private_data;
1462 struct pci_dev *pdev = to_pci_dev(host->dev);
1463 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1465 void __iomem *port_mmio;
1469 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1470 if (pdev->device == 0x6121)
1474 port_mmio = __ahci_port_base(host, mv);
1476 writel(0, port_mmio + PORT_IRQ_MASK);
1478 /* clear port IRQ */
1479 tmp = readl(port_mmio + PORT_IRQ_STAT);
1480 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1482 writel(tmp, port_mmio + PORT_IRQ_STAT);
1485 for (i = 0; i < host->n_ports; i++) {
1486 struct ata_port *ap = host->ports[i];
1488 port_mmio = ahci_port_base(ap);
1489 if (ata_port_is_dummy(ap))
1492 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1495 tmp = readl(mmio + HOST_CTL);
1496 VPRINTK("HOST_CTL 0x%x\n", tmp);
1497 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1498 tmp = readl(mmio + HOST_CTL);
1499 VPRINTK("HOST_CTL 0x%x\n", tmp);
1502 static void ahci_dev_config(struct ata_device *dev)
1504 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1506 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1507 dev->max_sectors = 255;
1508 ata_dev_printk(dev, KERN_INFO,
1509 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1513 static unsigned int ahci_dev_classify(struct ata_port *ap)
1515 void __iomem *port_mmio = ahci_port_base(ap);
1516 struct ata_taskfile tf;
1519 tmp = readl(port_mmio + PORT_SIG);
1520 tf.lbah = (tmp >> 24) & 0xff;
1521 tf.lbam = (tmp >> 16) & 0xff;
1522 tf.lbal = (tmp >> 8) & 0xff;
1523 tf.nsect = (tmp) & 0xff;
1525 return ata_dev_classify(&tf);
1528 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1531 dma_addr_t cmd_tbl_dma;
1533 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1535 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1536 pp->cmd_slot[tag].status = 0;
1537 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1538 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1541 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1543 void __iomem *port_mmio = ahci_port_base(ap);
1544 struct ahci_host_priv *hpriv = ap->host->private_data;
1545 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1549 /* do we need to kick the port? */
1550 busy = status & (ATA_BUSY | ATA_DRQ);
1551 if (!busy && !force_restart)
1555 rc = ahci_stop_engine(ap);
1559 /* need to do CLO? */
1565 if (!(hpriv->cap & HOST_CAP_CLO)) {
1571 tmp = readl(port_mmio + PORT_CMD);
1572 tmp |= PORT_CMD_CLO;
1573 writel(tmp, port_mmio + PORT_CMD);
1576 tmp = ata_wait_register(port_mmio + PORT_CMD,
1577 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1578 if (tmp & PORT_CMD_CLO)
1581 /* restart engine */
1583 ahci_start_engine(ap);
1587 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1588 struct ata_taskfile *tf, int is_cmd, u16 flags,
1589 unsigned long timeout_msec)
1591 const u32 cmd_fis_len = 5; /* five dwords */
1592 struct ahci_port_priv *pp = ap->private_data;
1593 void __iomem *port_mmio = ahci_port_base(ap);
1594 u8 *fis = pp->cmd_tbl;
1597 /* prep the command */
1598 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1599 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1602 writel(1, port_mmio + PORT_CMD_ISSUE);
1605 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1608 ahci_kick_engine(ap, 1);
1612 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1617 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1618 int pmp, unsigned long deadline,
1619 int (*check_ready)(struct ata_link *link))
1621 struct ata_port *ap = link->ap;
1622 const char *reason = NULL;
1623 unsigned long now, msecs;
1624 struct ata_taskfile tf;
1629 /* prepare for SRST (AHCI-1.1 10.4.1) */
1630 rc = ahci_kick_engine(ap, 1);
1631 if (rc && rc != -EOPNOTSUPP)
1632 ata_link_printk(link, KERN_WARNING,
1633 "failed to reset engine (errno=%d)\n", rc);
1635 ata_tf_init(link->device, &tf);
1637 /* issue the first D2H Register FIS */
1640 if (time_after(now, deadline))
1641 msecs = jiffies_to_msecs(deadline - now);
1644 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1645 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1647 reason = "1st FIS failed";
1651 /* spec says at least 5us, but be generous and sleep for 1ms */
1654 /* issue the second D2H Register FIS */
1655 tf.ctl &= ~ATA_SRST;
1656 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1658 /* wait for link to become ready */
1659 rc = ata_wait_after_reset(link, deadline, check_ready);
1660 /* link occupied, -ENODEV too is an error */
1662 reason = "device not ready";
1665 *class = ahci_dev_classify(ap);
1667 DPRINTK("EXIT, class=%u\n", *class);
1671 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1675 static int ahci_check_ready(struct ata_link *link)
1677 void __iomem *port_mmio = ahci_port_base(link->ap);
1678 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1680 return ata_check_ready(status);
1683 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1684 unsigned long deadline)
1686 int pmp = sata_srst_pmp(link);
1690 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1693 static int ahci_sb600_check_ready(struct ata_link *link)
1695 void __iomem *port_mmio = ahci_port_base(link->ap);
1696 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1697 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1700 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1701 * which can save timeout delay.
1703 if (irq_status & PORT_IRQ_BAD_PMP)
1706 return ata_check_ready(status);
1709 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1710 unsigned long deadline)
1712 struct ata_port *ap = link->ap;
1713 void __iomem *port_mmio = ahci_port_base(ap);
1714 int pmp = sata_srst_pmp(link);
1720 rc = ahci_do_softreset(link, class, pmp, deadline,
1721 ahci_sb600_check_ready);
1724 * Soft reset fails on some ATI chips with IPMS set when PMP
1725 * is enabled but SATA HDD/ODD is connected to SATA port,
1726 * do soft reset again to port 0.
1729 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1730 if (irq_sts & PORT_IRQ_BAD_PMP) {
1731 ata_link_printk(link, KERN_WARNING,
1732 "failed due to HW bug, retry pmp=0\n");
1733 rc = ahci_do_softreset(link, class, 0, deadline,
1741 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1742 unsigned long deadline)
1744 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1745 struct ata_port *ap = link->ap;
1746 struct ahci_port_priv *pp = ap->private_data;
1747 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1748 struct ata_taskfile tf;
1754 ahci_stop_engine(ap);
1756 /* clear D2H reception area to properly wait for D2H FIS */
1757 ata_tf_init(link->device, &tf);
1759 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1761 rc = sata_link_hardreset(link, timing, deadline, &online,
1764 ahci_start_engine(ap);
1767 *class = ahci_dev_classify(ap);
1769 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1773 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1774 unsigned long deadline)
1776 struct ata_port *ap = link->ap;
1782 ahci_stop_engine(ap);
1784 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1785 deadline, &online, NULL);
1787 ahci_start_engine(ap);
1789 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1791 /* vt8251 doesn't clear BSY on signature FIS reception,
1792 * request follow-up softreset.
1794 return online ? -EAGAIN : rc;
1797 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1798 unsigned long deadline)
1800 struct ata_port *ap = link->ap;
1801 struct ahci_port_priv *pp = ap->private_data;
1802 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1803 struct ata_taskfile tf;
1807 ahci_stop_engine(ap);
1809 /* clear D2H reception area to properly wait for D2H FIS */
1810 ata_tf_init(link->device, &tf);
1812 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1814 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1815 deadline, &online, NULL);
1817 ahci_start_engine(ap);
1819 /* The pseudo configuration device on SIMG4726 attached to
1820 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1821 * hardreset if no device is attached to the first downstream
1822 * port && the pseudo device locks up on SRST w/ PMP==0. To
1823 * work around this, wait for !BSY only briefly. If BSY isn't
1824 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1825 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1827 * Wait for two seconds. Devices attached to downstream port
1828 * which can't process the following IDENTIFY after this will
1829 * have to be reset again. For most cases, this should
1830 * suffice while making probing snappish enough.
1833 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1836 ahci_kick_engine(ap, 0);
1841 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1843 struct ata_port *ap = link->ap;
1844 void __iomem *port_mmio = ahci_port_base(ap);
1847 ata_std_postreset(link, class);
1849 /* Make sure port's ATAPI bit is set appropriately */
1850 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1851 if (*class == ATA_DEV_ATAPI)
1852 new_tmp |= PORT_CMD_ATAPI;
1854 new_tmp &= ~PORT_CMD_ATAPI;
1855 if (new_tmp != tmp) {
1856 writel(new_tmp, port_mmio + PORT_CMD);
1857 readl(port_mmio + PORT_CMD); /* flush */
1861 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1863 struct scatterlist *sg;
1864 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1870 * Next, the S/G list.
1872 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1873 dma_addr_t addr = sg_dma_address(sg);
1874 u32 sg_len = sg_dma_len(sg);
1876 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1877 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1878 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1884 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1886 struct ata_port *ap = qc->ap;
1887 struct ahci_port_priv *pp = ap->private_data;
1888 int is_atapi = ata_is_atapi(qc->tf.protocol);
1891 const u32 cmd_fis_len = 5; /* five dwords */
1892 unsigned int n_elem;
1895 * Fill in command table information. First, the header,
1896 * a SATA Register - Host to Device command FIS.
1898 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1900 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1902 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1903 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1907 if (qc->flags & ATA_QCFLAG_DMAMAP)
1908 n_elem = ahci_fill_sg(qc, cmd_tbl);
1911 * Fill in command slot information.
1913 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1914 if (qc->tf.flags & ATA_TFLAG_WRITE)
1915 opts |= AHCI_CMD_WRITE;
1917 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1919 ahci_fill_cmd_slot(pp, qc->tag, opts);
1922 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1924 struct ahci_host_priv *hpriv = ap->host->private_data;
1925 struct ahci_port_priv *pp = ap->private_data;
1926 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1927 struct ata_link *link = NULL;
1928 struct ata_queued_cmd *active_qc;
1929 struct ata_eh_info *active_ehi;
1932 /* determine active link */
1933 ata_port_for_each_link(link, ap)
1934 if (ata_link_active(link))
1939 active_qc = ata_qc_from_tag(ap, link->active_tag);
1940 active_ehi = &link->eh_info;
1942 /* record irq stat */
1943 ata_ehi_clear_desc(host_ehi);
1944 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1946 /* AHCI needs SError cleared; otherwise, it might lock up */
1947 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1948 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1949 host_ehi->serror |= serror;
1951 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1952 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1953 irq_stat &= ~PORT_IRQ_IF_ERR;
1955 if (irq_stat & PORT_IRQ_TF_ERR) {
1956 /* If qc is active, charge it; otherwise, the active
1957 * link. There's no active qc on NCQ errors. It will
1958 * be determined by EH by reading log page 10h.
1961 active_qc->err_mask |= AC_ERR_DEV;
1963 active_ehi->err_mask |= AC_ERR_DEV;
1965 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1966 host_ehi->serror &= ~SERR_INTERNAL;
1969 if (irq_stat & PORT_IRQ_UNK_FIS) {
1970 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1972 active_ehi->err_mask |= AC_ERR_HSM;
1973 active_ehi->action |= ATA_EH_RESET;
1974 ata_ehi_push_desc(active_ehi,
1975 "unknown FIS %08x %08x %08x %08x" ,
1976 unk[0], unk[1], unk[2], unk[3]);
1979 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1980 active_ehi->err_mask |= AC_ERR_HSM;
1981 active_ehi->action |= ATA_EH_RESET;
1982 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1985 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1986 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1987 host_ehi->action |= ATA_EH_RESET;
1988 ata_ehi_push_desc(host_ehi, "host bus error");
1991 if (irq_stat & PORT_IRQ_IF_ERR) {
1992 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1993 host_ehi->action |= ATA_EH_RESET;
1994 ata_ehi_push_desc(host_ehi, "interface fatal error");
1997 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1998 ata_ehi_hotplugged(host_ehi);
1999 ata_ehi_push_desc(host_ehi, "%s",
2000 irq_stat & PORT_IRQ_CONNECT ?
2001 "connection status changed" : "PHY RDY changed");
2004 /* okay, let's hand over to EH */
2006 if (irq_stat & PORT_IRQ_FREEZE)
2007 ata_port_freeze(ap);
2012 static void ahci_port_intr(struct ata_port *ap)
2014 void __iomem *port_mmio = ahci_port_base(ap);
2015 struct ata_eh_info *ehi = &ap->link.eh_info;
2016 struct ahci_port_priv *pp = ap->private_data;
2017 struct ahci_host_priv *hpriv = ap->host->private_data;
2018 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
2019 u32 status, qc_active;
2022 status = readl(port_mmio + PORT_IRQ_STAT);
2023 writel(status, port_mmio + PORT_IRQ_STAT);
2025 /* ignore BAD_PMP while resetting */
2026 if (unlikely(resetting))
2027 status &= ~PORT_IRQ_BAD_PMP;
2029 /* If we are getting PhyRdy, this is
2030 * just a power state change, we should
2031 * clear out this, plus the PhyRdy/Comm
2032 * Wake bits from Serror
2034 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2035 (status & PORT_IRQ_PHYRDY)) {
2036 status &= ~PORT_IRQ_PHYRDY;
2037 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
2040 if (unlikely(status & PORT_IRQ_ERROR)) {
2041 ahci_error_intr(ap, status);
2045 if (status & PORT_IRQ_SDB_FIS) {
2046 /* If SNotification is available, leave notification
2047 * handling to sata_async_notification(). If not,
2048 * emulate it by snooping SDB FIS RX area.
2050 * Snooping FIS RX area is probably cheaper than
2051 * poking SNotification but some constrollers which
2052 * implement SNotification, ICH9 for example, don't
2053 * store AN SDB FIS into receive area.
2055 if (hpriv->cap & HOST_CAP_SNTF)
2056 sata_async_notification(ap);
2058 /* If the 'N' bit in word 0 of the FIS is set,
2059 * we just received asynchronous notification.
2060 * Tell libata about it.
2062 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2063 u32 f0 = le32_to_cpu(f[0]);
2066 sata_async_notification(ap);
2070 /* pp->active_link is valid iff any command is in flight */
2071 if (ap->qc_active && pp->active_link->sactive)
2072 qc_active = readl(port_mmio + PORT_SCR_ACT);
2074 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2076 rc = ata_qc_complete_multiple(ap, qc_active);
2078 /* while resetting, invalid completions are expected */
2079 if (unlikely(rc < 0 && !resetting)) {
2080 ehi->err_mask |= AC_ERR_HSM;
2081 ehi->action |= ATA_EH_RESET;
2082 ata_port_freeze(ap);
2086 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
2088 struct ata_host *host = dev_instance;
2089 struct ahci_host_priv *hpriv;
2090 unsigned int i, handled = 0;
2092 u32 irq_stat, irq_masked;
2096 hpriv = host->private_data;
2097 mmio = host->iomap[AHCI_PCI_BAR];
2099 /* sigh. 0xffffffff is a valid return from h/w */
2100 irq_stat = readl(mmio + HOST_IRQ_STAT);
2104 irq_masked = irq_stat & hpriv->port_map;
2106 spin_lock(&host->lock);
2108 for (i = 0; i < host->n_ports; i++) {
2109 struct ata_port *ap;
2111 if (!(irq_masked & (1 << i)))
2114 ap = host->ports[i];
2117 VPRINTK("port %u\n", i);
2119 VPRINTK("port %u (no irq)\n", i);
2120 if (ata_ratelimit())
2121 dev_printk(KERN_WARNING, host->dev,
2122 "interrupt on disabled port %u\n", i);
2128 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2129 * it should be cleared after all the port events are cleared;
2130 * otherwise, it will raise a spurious interrupt after each
2131 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2134 * Also, use the unmasked value to clear interrupt as spurious
2135 * pending event on a dummy port might cause screaming IRQ.
2137 writel(irq_stat, mmio + HOST_IRQ_STAT);
2139 spin_unlock(&host->lock);
2143 return IRQ_RETVAL(handled);
2146 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2148 struct ata_port *ap = qc->ap;
2149 void __iomem *port_mmio = ahci_port_base(ap);
2150 struct ahci_port_priv *pp = ap->private_data;
2152 /* Keep track of the currently active link. It will be used
2153 * in completion path to determine whether NCQ phase is in
2156 pp->active_link = qc->dev->link;
2158 if (qc->tf.protocol == ATA_PROT_NCQ)
2159 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2160 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2162 ahci_sw_activity(qc->dev->link);
2167 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2169 struct ahci_port_priv *pp = qc->ap->private_data;
2170 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2172 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2176 static void ahci_freeze(struct ata_port *ap)
2178 void __iomem *port_mmio = ahci_port_base(ap);
2181 writel(0, port_mmio + PORT_IRQ_MASK);
2184 static void ahci_thaw(struct ata_port *ap)
2186 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
2187 void __iomem *port_mmio = ahci_port_base(ap);
2189 struct ahci_port_priv *pp = ap->private_data;
2192 tmp = readl(port_mmio + PORT_IRQ_STAT);
2193 writel(tmp, port_mmio + PORT_IRQ_STAT);
2194 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2196 /* turn IRQ back on */
2197 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2200 static void ahci_error_handler(struct ata_port *ap)
2202 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2203 /* restart engine */
2204 ahci_stop_engine(ap);
2205 ahci_start_engine(ap);
2208 sata_pmp_error_handler(ap);
2211 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2213 struct ata_port *ap = qc->ap;
2215 /* make DMA engine forget about the failed command */
2216 if (qc->flags & ATA_QCFLAG_FAILED)
2217 ahci_kick_engine(ap, 1);
2220 static void ahci_pmp_attach(struct ata_port *ap)
2222 void __iomem *port_mmio = ahci_port_base(ap);
2223 struct ahci_port_priv *pp = ap->private_data;
2226 cmd = readl(port_mmio + PORT_CMD);
2227 cmd |= PORT_CMD_PMP;
2228 writel(cmd, port_mmio + PORT_CMD);
2230 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2231 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2234 static void ahci_pmp_detach(struct ata_port *ap)
2236 void __iomem *port_mmio = ahci_port_base(ap);
2237 struct ahci_port_priv *pp = ap->private_data;
2240 cmd = readl(port_mmio + PORT_CMD);
2241 cmd &= ~PORT_CMD_PMP;
2242 writel(cmd, port_mmio + PORT_CMD);
2244 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2245 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2248 static int ahci_port_resume(struct ata_port *ap)
2251 ahci_start_port(ap);
2253 if (sata_pmp_attached(ap))
2254 ahci_pmp_attach(ap);
2256 ahci_pmp_detach(ap);
2262 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2264 const char *emsg = NULL;
2267 rc = ahci_deinit_port(ap, &emsg);
2269 ahci_power_down(ap);
2271 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2272 ahci_start_port(ap);
2278 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2280 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2281 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2284 if (mesg.event & PM_EVENT_SLEEP) {
2285 /* AHCI spec rev1.1 section 8.3.3:
2286 * Software must disable interrupts prior to requesting a
2287 * transition of the HBA to D3 state.
2289 ctl = readl(mmio + HOST_CTL);
2290 ctl &= ~HOST_IRQ_EN;
2291 writel(ctl, mmio + HOST_CTL);
2292 readl(mmio + HOST_CTL); /* flush */
2295 return ata_pci_device_suspend(pdev, mesg);
2298 static int ahci_pci_device_resume(struct pci_dev *pdev)
2300 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2303 rc = ata_pci_device_do_resume(pdev);
2307 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2308 rc = ahci_reset_controller(host);
2312 ahci_init_controller(host);
2315 ata_host_resume(host);
2321 static int ahci_port_start(struct ata_port *ap)
2323 struct device *dev = ap->host->dev;
2324 struct ahci_port_priv *pp;
2328 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2332 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2336 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2339 * First item in chunk of DMA memory: 32-slot command table,
2340 * 32 bytes each in size
2343 pp->cmd_slot_dma = mem_dma;
2345 mem += AHCI_CMD_SLOT_SZ;
2346 mem_dma += AHCI_CMD_SLOT_SZ;
2349 * Second item: Received-FIS area
2352 pp->rx_fis_dma = mem_dma;
2354 mem += AHCI_RX_FIS_SZ;
2355 mem_dma += AHCI_RX_FIS_SZ;
2358 * Third item: data area for storing a single command
2359 * and its scatter-gather table
2362 pp->cmd_tbl_dma = mem_dma;
2365 * Save off initial list of interrupts to be enabled.
2366 * This could be changed later
2368 pp->intr_mask = DEF_PORT_IRQ;
2370 ap->private_data = pp;
2372 /* engage engines, captain */
2373 return ahci_port_resume(ap);
2376 static void ahci_port_stop(struct ata_port *ap)
2378 const char *emsg = NULL;
2381 /* de-initialize port */
2382 rc = ahci_deinit_port(ap, &emsg);
2384 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2387 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2392 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2393 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2395 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2397 dev_printk(KERN_ERR, &pdev->dev,
2398 "64-bit DMA enable failed\n");
2403 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2405 dev_printk(KERN_ERR, &pdev->dev,
2406 "32-bit DMA enable failed\n");
2409 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2411 dev_printk(KERN_ERR, &pdev->dev,
2412 "32-bit consistent DMA enable failed\n");
2419 static void ahci_print_info(struct ata_host *host)
2421 struct ahci_host_priv *hpriv = host->private_data;
2422 struct pci_dev *pdev = to_pci_dev(host->dev);
2423 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2424 u32 vers, cap, impl, speed;
2425 const char *speed_s;
2429 vers = readl(mmio + HOST_VERSION);
2431 impl = hpriv->port_map;
2433 speed = (cap >> 20) & 0xf;
2436 else if (speed == 2)
2441 pci_read_config_word(pdev, 0x0a, &cc);
2442 if (cc == PCI_CLASS_STORAGE_IDE)
2444 else if (cc == PCI_CLASS_STORAGE_SATA)
2446 else if (cc == PCI_CLASS_STORAGE_RAID)
2451 dev_printk(KERN_INFO, &pdev->dev,
2452 "AHCI %02x%02x.%02x%02x "
2453 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2456 (vers >> 24) & 0xff,
2457 (vers >> 16) & 0xff,
2461 ((cap >> 8) & 0x1f) + 1,
2467 dev_printk(KERN_INFO, &pdev->dev,
2474 cap & (1 << 31) ? "64bit " : "",
2475 cap & (1 << 30) ? "ncq " : "",
2476 cap & (1 << 29) ? "sntf " : "",
2477 cap & (1 << 28) ? "ilck " : "",
2478 cap & (1 << 27) ? "stag " : "",
2479 cap & (1 << 26) ? "pm " : "",
2480 cap & (1 << 25) ? "led " : "",
2482 cap & (1 << 24) ? "clo " : "",
2483 cap & (1 << 19) ? "nz " : "",
2484 cap & (1 << 18) ? "only " : "",
2485 cap & (1 << 17) ? "pmp " : "",
2486 cap & (1 << 15) ? "pio " : "",
2487 cap & (1 << 14) ? "slum " : "",
2488 cap & (1 << 13) ? "part " : "",
2489 cap & (1 << 6) ? "ems ": ""
2493 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2494 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2495 * support PMP and the 4726 either directly exports the device
2496 * attached to the first downstream port or acts as a hardware storage
2497 * controller and emulate a single ATA device (can be RAID 0/1 or some
2498 * other configuration).
2500 * When there's no device attached to the first downstream port of the
2501 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2502 * configure the 4726. However, ATA emulation of the device is very
2503 * lame. It doesn't send signature D2H Reg FIS after the initial
2504 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2506 * The following function works around the problem by always using
2507 * hardreset on the port and not depending on receiving signature FIS
2508 * afterward. If signature FIS isn't received soon, ATA class is
2509 * assumed without follow-up softreset.
2511 static void ahci_p5wdh_workaround(struct ata_host *host)
2513 static struct dmi_system_id sysids[] = {
2515 .ident = "P5W DH Deluxe",
2517 DMI_MATCH(DMI_SYS_VENDOR,
2518 "ASUSTEK COMPUTER INC"),
2519 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2524 struct pci_dev *pdev = to_pci_dev(host->dev);
2526 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2527 dmi_check_system(sysids)) {
2528 struct ata_port *ap = host->ports[1];
2530 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2531 "Deluxe on-board SIMG4726 workaround\n");
2533 ap->ops = &ahci_p5wdh_ops;
2534 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2538 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2540 static int printed_version;
2541 unsigned int board_id = ent->driver_data;
2542 struct ata_port_info pi = ahci_port_info[board_id];
2543 const struct ata_port_info *ppi[] = { &pi, NULL };
2544 struct device *dev = &pdev->dev;
2545 struct ahci_host_priv *hpriv;
2546 struct ata_host *host;
2551 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2553 if (!printed_version++)
2554 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2556 /* The AHCI driver can only drive the SATA ports, the PATA driver
2557 can drive them all so if both drivers are selected make sure
2558 AHCI stays out of the way */
2559 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2562 /* acquire resources */
2563 rc = pcim_enable_device(pdev);
2567 /* AHCI controllers often implement SFF compatible interface.
2568 * Grab all PCI BARs just in case.
2570 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2572 pcim_pin_device(pdev);
2576 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2577 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2580 /* ICH6s share the same PCI ID for both piix and ahci
2581 * modes. Enabling ahci mode while MAP indicates
2582 * combined mode is a bad idea. Yield to ata_piix.
2584 pci_read_config_byte(pdev, ICH_MAP, &map);
2586 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2587 "combined mode, can't enable AHCI mode\n");
2592 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2595 hpriv->flags |= (unsigned long)pi.private_data;
2597 /* MCP65 revision A1 and A2 can't do MSI */
2598 if (board_id == board_ahci_mcp65 &&
2599 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2600 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2602 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2605 /* save initial config */
2606 ahci_save_initial_config(pdev, hpriv);
2609 if (hpriv->cap & HOST_CAP_NCQ)
2610 pi.flags |= ATA_FLAG_NCQ;
2612 if (hpriv->cap & HOST_CAP_PMP)
2613 pi.flags |= ATA_FLAG_PMP;
2615 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2617 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2618 u32 em_loc = readl(mmio + HOST_EM_LOC);
2619 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2621 messages = (em_ctl & 0x000f0000) >> 16;
2623 /* we only support LED message type right now */
2624 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2626 hpriv->em_loc = ((em_loc >> 16) * 4);
2627 pi.flags |= ATA_FLAG_EM;
2628 if (!(em_ctl & EM_CTL_ALHD))
2629 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2633 /* CAP.NP sometimes indicate the index of the last enabled
2634 * port, at other times, that of the last possible port, so
2635 * determining the maximum port number requires looking at
2636 * both CAP.NP and port_map.
2638 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2640 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2643 host->iomap = pcim_iomap_table(pdev);
2644 host->private_data = hpriv;
2646 if (pi.flags & ATA_FLAG_EM)
2647 ahci_reset_em(host);
2649 for (i = 0; i < host->n_ports; i++) {
2650 struct ata_port *ap = host->ports[i];
2652 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2653 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2654 0x100 + ap->port_no * 0x80, "port");
2656 /* set initial link pm policy */
2657 ap->pm_policy = NOT_AVAILABLE;
2659 /* set enclosure management message type */
2660 if (ap->flags & ATA_FLAG_EM)
2661 ap->em_message_type = ahci_em_messages;
2664 /* disabled/not-implemented port */
2665 if (!(hpriv->port_map & (1 << i)))
2666 ap->ops = &ata_dummy_port_ops;
2669 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2670 ahci_p5wdh_workaround(host);
2672 /* initialize adapter */
2673 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2677 rc = ahci_reset_controller(host);
2681 ahci_init_controller(host);
2682 ahci_print_info(host);
2684 pci_set_master(pdev);
2685 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2689 static int __init ahci_init(void)
2691 return pci_register_driver(&ahci_pci_driver);
2694 static void __exit ahci_exit(void)
2696 pci_unregister_driver(&ahci_pci_driver);
2700 MODULE_AUTHOR("Jeff Garzik");
2701 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2702 MODULE_LICENSE("GPL");
2703 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2704 MODULE_VERSION(DRV_VERSION);
2706 module_init(ahci_init);
2707 module_exit(ahci_exit);