arch/x86_64/kernel/pci-calgary.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <asm/iommu.h>
  39 #include <asm/calgary.h>
  40 #include <asm/tce.h>
  41 #include <asm/pci-direct.h>
  42 #include <asm/system.h>
  43 #include <asm/dma.h>
  44 #include <asm/rio.h>
  45
  46 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  47 int use_calgary __read_mostly = 1;
  48 #else
  49 int use_calgary __read_mostly = 0;
  50 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  51
  52 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  53 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  54
  55 /* register offsets inside the host bridge space */
  56 #define CALGARY_CONFIG_REG      0x0108
  57 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  58 #define PHB_PLSSR_OFFSET        0x0120
  59 #define PHB_CONFIG_RW_OFFSET    0x0160
  60 #define PHB_IOBASE_BAR_LOW      0x0170
  61 #define PHB_IOBASE_BAR_HIGH     0x0180
  62 #define PHB_MEM_1_LOW           0x0190
  63 #define PHB_MEM_1_HIGH          0x01A0
  64 #define PHB_IO_ADDR_SIZE        0x01B0
  65 #define PHB_MEM_1_SIZE          0x01C0
  66 #define PHB_MEM_ST_OFFSET       0x01D0
  67 #define PHB_AER_OFFSET          0x0200
  68 #define PHB_CONFIG_0_HIGH       0x0220
  69 #define PHB_CONFIG_0_LOW        0x0230
  70 #define PHB_CONFIG_0_END        0x0240
  71 #define PHB_MEM_2_LOW           0x02B0
  72 #define PHB_MEM_2_HIGH          0x02C0
  73 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  74 #define PHB_MEM_2_SIZE_LOW      0x02E0
  75 #define PHB_DOSHOLE_OFFSET      0x08E0
  76
  77 /* CalIOC2 specific */
  78 #define PHB_SAVIOR_L2           0x0DB0
  79 #define PHB_PAGE_MIG_CTRL       0x0DA8
  80 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  81 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  82
  83 /* PHB_CONFIG_RW */
  84 #define PHB_TCE_ENABLE          0x20000000
  85 #define PHB_SLOT_DISABLE        0x1C000000
  86 #define PHB_DAC_DISABLE         0x01000000
  87 #define PHB_MEM2_ENABLE         0x00400000
  88 #define PHB_MCSR_ENABLE         0x00100000
  89 /* TAR (Table Address Register) */
  90 #define TAR_SW_BITS             0x0000ffffffff800fUL
  91 #define TAR_VALID               0x0000000000000008UL
  92 /* CSR (Channel/DMA Status Register) */
  93 #define CSR_AGENT_MASK          0xffe0ffff
  94 /* CCR (Calgary Configuration Register) */
  95 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  96 /* PMCR/PMDR (Page Migration Control/Debug Registers */
  97 #define PMR_SOFTSTOP            0x80000000
  98 #define PMR_SOFTSTOPFAULT       0x40000000
  99 #define PMR_HARDSTOP            0x20000000
 100
 101 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 102 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 103 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 104 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 105 #define PHBS_PER_CALGARY        4
 106
 107 /* register offsets in Calgary's internal register space */
 108 static const unsigned long tar_offsets[] = {
 109         0x0580 /* TAR0 */,
 110         0x0588 /* TAR1 */,
 111         0x0590 /* TAR2 */,
 112         0x0598 /* TAR3 */
 113 };
 114
 115 static const unsigned long split_queue_offsets[] = {
 116         0x4870 /* SPLIT QUEUE 0 */,
 117         0x5870 /* SPLIT QUEUE 1 */,
 118         0x6870 /* SPLIT QUEUE 2 */,
 119         0x7870 /* SPLIT QUEUE 3 */
 120 };
 121
 122 static const unsigned long phb_offsets[] = {
 123         0x8000 /* PHB0 */,
 124         0x9000 /* PHB1 */,
 125         0xA000 /* PHB2 */,
 126         0xB000 /* PHB3 */
 127 };
 128
 129 /* PHB debug registers */
 130
 131 static const unsigned long phb_debug_offsets[] = {
 132         0x4000  /* PHB 0 DEBUG */,
 133         0x5000  /* PHB 1 DEBUG */,
 134         0x6000  /* PHB 2 DEBUG */,
 135         0x7000  /* PHB 3 DEBUG */
 136 };
 137
 138 /*
 139  * STUFF register for each debug PHB,
 140  * byte 1 = start bus number, byte 2 = end bus number
 141  */
 142
 143 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 144
 145 #define EMERGENCY_PAGES 32 /* = 128KB */
 146
 147 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 148 static int translate_empty_slots __read_mostly = 0;
 149 static int calgary_detected __read_mostly = 0;
 150
 151 static struct rio_table_hdr     *rio_table_hdr __initdata;
 152 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 153 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 154
 155 struct calgary_bus_info {
 156         void *tce_space;
 157         unsigned char translation_disabled;
 158         signed char phbid;
 159         void __iomem *bbar;
 160 };
 161
 162 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 163 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 164 static void calgary_dump_error_regs(struct iommu_table *tbl);
 165 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 166 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 167 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 168
 169 static struct cal_chipset_ops calgary_chip_ops = {
 170         .handle_quirks = calgary_handle_quirks,
 171         .tce_cache_blast = calgary_tce_cache_blast,
 172         .dump_error_regs = calgary_dump_error_regs
 173 };
 174
 175 static struct cal_chipset_ops calioc2_chip_ops = {
 176         .handle_quirks = calioc2_handle_quirks,
 177         .tce_cache_blast = calioc2_tce_cache_blast,
 178         .dump_error_regs = calioc2_dump_error_regs
 179 };
 180
 181 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 182
 183 /* enable this to stress test the chip's TCE cache */
 184 #ifdef CONFIG_IOMMU_DEBUG
 185 int debugging __read_mostly = 1;
 186
 187 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 188         int expected, unsigned long start, unsigned long end)
 189 {
 190         unsigned long idx = start;
 191
 192         BUG_ON(start >= end);
 193
 194         while (idx < end) {
 195                 if (!!test_bit(idx, bitmap) != expected)
 196                         return idx;
 197                 ++idx;
 198         }
 199
 200         /* all bits have the expected value */
 201         return ~0UL;
 202 }
 203 #else /* debugging is disabled */
 204 int debugging __read_mostly = 0;
 205
 206 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 207         int expected, unsigned long start, unsigned long end)
 208 {
 209         return ~0UL;
 210 }
 211
 212 #endif /* CONFIG_IOMMU_DEBUG */
 213
 214 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 215 {
 216         unsigned int npages;
 217
 218         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 219         npages >>= PAGE_SHIFT;
 220
 221         return npages;
 222 }
 223
 224 static inline int translate_phb(struct pci_dev* dev)
 225 {
 226         int disabled = bus_info[dev->bus->number].translation_disabled;
 227         return !disabled;
 228 }
 229
 230 static void iommu_range_reserve(struct iommu_table *tbl,
 231         unsigned long start_addr, unsigned int npages)
 232 {
 233         unsigned long index;
 234         unsigned long end;
 235         unsigned long badbit;
 236         unsigned long flags;
 237
 238         index = start_addr >> PAGE_SHIFT;
 239
 240         /* bail out if we're asked to reserve a region we don't cover */
 241         if (index >= tbl->it_size)
 242                 return;
 243
 244         end = index + npages;
 245         if (end > tbl->it_size) /* don't go off the table */
 246                 end = tbl->it_size;
 247
 248         spin_lock_irqsave(&tbl->it_lock, flags);
 249
 250         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 251         if (badbit != ~0UL) {
 252                 if (printk_ratelimit())
 253                         printk(KERN_ERR "Calgary: entry already allocated at "
 254                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 255                                badbit, tbl, start_addr, npages);
 256         }
 257
 258         set_bit_string(tbl->it_map, index, npages);
 259
 260         spin_unlock_irqrestore(&tbl->it_lock, flags);
 261 }
 262
 263 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 264         unsigned int npages)
 265 {
 266         unsigned long flags;
 267         unsigned long offset;
 268
 269         BUG_ON(npages == 0);
 270
 271         spin_lock_irqsave(&tbl->it_lock, flags);
 272
 273         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 274                                        tbl->it_size, npages);
 275         if (offset == ~0UL) {
 276                 tbl->chip_ops->tce_cache_blast(tbl);
 277                 offset = find_next_zero_string(tbl->it_map, 0,
 278                                                tbl->it_size, npages);
 279                 if (offset == ~0UL) {
 280                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 281                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 282                         if (panic_on_overflow)
 283                                 panic("Calgary: fix the allocator.\n");
 284                         else
 285                                 return bad_dma_address;
 286                 }
 287         }
 288
 289         set_bit_string(tbl->it_map, offset, npages);
 290         tbl->it_hint = offset + npages;
 291         BUG_ON(tbl->it_hint > tbl->it_size);
 292
 293         spin_unlock_irqrestore(&tbl->it_lock, flags);
 294
 295         return offset;
 296 }
 297
 298 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 299         unsigned int npages, int direction)
 300 {
 301         unsigned long entry;
 302         dma_addr_t ret = bad_dma_address;
 303
 304         entry = iommu_range_alloc(tbl, npages);
 305
 306         if (unlikely(entry == bad_dma_address))
 307                 goto error;
 308
 309         /* set the return dma address */
 310         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 311
 312         /* put the TCEs in the HW table */
 313         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 314                   direction);
 315
 316         return ret;
 317
 318 error:
 319         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 320                "iommu %p\n", npages, tbl);
 321         return bad_dma_address;
 322 }
 323
 324 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 325         unsigned int npages)
 326 {
 327         unsigned long entry;
 328         unsigned long badbit;
 329         unsigned long badend;
 330         unsigned long flags;
 331
 332         /* were we called with bad_dma_address? */
 333         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 334         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 335                 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
 336                        "address 0x%Lx\n", dma_addr);
 337                 WARN_ON(1);
 338                 return;
 339         }
 340
 341         entry = dma_addr >> PAGE_SHIFT;
 342
 343         BUG_ON(entry + npages > tbl->it_size);
 344
 345         tce_free(tbl, entry, npages);
 346
 347         spin_lock_irqsave(&tbl->it_lock, flags);
 348
 349         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 350         if (badbit != ~0UL) {
 351                 if (printk_ratelimit())
 352                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 353                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 354                                badbit, tbl, dma_addr, entry, npages);
 355         }
 356
 357         __clear_bit_string(tbl->it_map, entry, npages);
 358
 359         spin_unlock_irqrestore(&tbl->it_lock, flags);
 360 }
 361
 362 static inline struct iommu_table *find_iommu_table(struct device *dev)
 363 {
 364         struct pci_dev *pdev;
 365         struct pci_bus *pbus;
 366         struct iommu_table *tbl;
 367
 368         pdev = to_pci_dev(dev);
 369
 370         /* is the device behind a bridge? */
 371         if (unlikely(pdev->bus->parent))
 372                 pbus = pdev->bus->parent;
 373         else
 374                 pbus = pdev->bus;
 375
 376         tbl = pci_iommu(pbus);
 377
 378         BUG_ON(pdev->bus->parent &&
 379                (tbl->it_busno != pdev->bus->parent->number));
 380
 381         return tbl;
 382 }
 383
 384 static void calgary_unmap_sg(struct device *dev,
 385         struct scatterlist *sglist, int nelems, int direction)
 386 {
 387         struct iommu_table *tbl = find_iommu_table(dev);
 388
 389         if (!translate_phb(to_pci_dev(dev)))
 390                 return;
 391
 392         while (nelems--) {
 393                 unsigned int npages;
 394                 dma_addr_t dma = sglist->dma_address;
 395                 unsigned int dmalen = sglist->dma_length;
 396
 397                 if (dmalen == 0)
 398                         break;
 399
 400                 npages = num_dma_pages(dma, dmalen);
 401                 iommu_free(tbl, dma, npages);
 402                 sglist++;
 403         }
 404 }
 405
 406 static int calgary_nontranslate_map_sg(struct device* dev,
 407         struct scatterlist *sg, int nelems, int direction)
 408 {
 409         int i;
 410
 411         for (i = 0; i < nelems; i++ ) {
 412                 struct scatterlist *s = &sg[i];
 413                 BUG_ON(!s->page);
 414                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 415                 s->dma_length = s->length;
 416         }
 417         return nelems;
 418 }
 419
 420 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 421         int nelems, int direction)
 422 {
 423         struct iommu_table *tbl = find_iommu_table(dev);
 424         unsigned long vaddr;
 425         unsigned int npages;
 426         unsigned long entry;
 427         int i;
 428
 429         if (!translate_phb(to_pci_dev(dev)))
 430                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 431
 432         for (i = 0; i < nelems; i++ ) {
 433                 struct scatterlist *s = &sg[i];
 434                 BUG_ON(!s->page);
 435
 436                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 437                 npages = num_dma_pages(vaddr, s->length);
 438
 439                 entry = iommu_range_alloc(tbl, npages);
 440                 if (entry == bad_dma_address) {
 441                         /* makes sure unmap knows to stop */
 442                         s->dma_length = 0;
 443                         goto error;
 444                 }
 445
 446                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 447
 448                 /* insert into HW table */
 449                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 450                           direction);
 451
 452                 s->dma_length = s->length;
 453         }
 454
 455         return nelems;
 456 error:
 457         calgary_unmap_sg(dev, sg, nelems, direction);
 458         for (i = 0; i < nelems; i++) {
 459                 sg[i].dma_address = bad_dma_address;
 460                 sg[i].dma_length = 0;
 461         }
 462         return 0;
 463 }
 464
 465 static dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 466         size_t size, int direction)
 467 {
 468         dma_addr_t dma_handle = bad_dma_address;
 469         unsigned long uaddr;
 470         unsigned int npages;
 471         struct iommu_table *tbl = find_iommu_table(dev);
 472
 473         uaddr = (unsigned long)vaddr;
 474         npages = num_dma_pages(uaddr, size);
 475
 476         if (translate_phb(to_pci_dev(dev)))
 477                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 478         else
 479                 dma_handle = virt_to_bus(vaddr);
 480
 481         return dma_handle;
 482 }
 483
 484 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 485         size_t size, int direction)
 486 {
 487         struct iommu_table *tbl = find_iommu_table(dev);
 488         unsigned int npages;
 489
 490         if (!translate_phb(to_pci_dev(dev)))
 491                 return;
 492
 493         npages = num_dma_pages(dma_handle, size);
 494         iommu_free(tbl, dma_handle, npages);
 495 }
 496
 497 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 498         dma_addr_t *dma_handle, gfp_t flag)
 499 {
 500         void *ret = NULL;
 501         dma_addr_t mapping;
 502         unsigned int npages, order;
 503         struct iommu_table *tbl = find_iommu_table(dev);
 504
 505         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 506         npages = size >> PAGE_SHIFT;
 507         order = get_order(size);
 508
 509         /* alloc enough pages (and possibly more) */
 510         ret = (void *)__get_free_pages(flag, order);
 511         if (!ret)
 512                 goto error;
 513         memset(ret, 0, size);
 514
 515         if (translate_phb(to_pci_dev(dev))) {
 516                 /* set up tces to cover the allocated range */
 517                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 518                 if (mapping == bad_dma_address)
 519                         goto free;
 520
 521                 *dma_handle = mapping;
 522         } else /* non translated slot */
 523                 *dma_handle = virt_to_bus(ret);
 524
 525         return ret;
 526
 527 free:
 528         free_pages((unsigned long)ret, get_order(size));
 529         ret = NULL;
 530 error:
 531         return ret;
 532 }
 533
 534 static const struct dma_mapping_ops calgary_dma_ops = {
 535         .alloc_coherent = calgary_alloc_coherent,
 536         .map_single = calgary_map_single,
 537         .unmap_single = calgary_unmap_single,
 538         .map_sg = calgary_map_sg,
 539         .unmap_sg = calgary_unmap_sg,
 540 };
 541
 542 static inline void __iomem * busno_to_bbar(unsigned char num)
 543 {
 544         return bus_info[num].bbar;
 545 }
 546
 547 static inline int busno_to_phbid(unsigned char num)
 548 {
 549         return bus_info[num].phbid;
 550 }
 551
 552 static inline unsigned long split_queue_offset(unsigned char num)
 553 {
 554         size_t idx = busno_to_phbid(num);
 555
 556         return split_queue_offsets[idx];
 557 }
 558
 559 static inline unsigned long tar_offset(unsigned char num)
 560 {
 561         size_t idx = busno_to_phbid(num);
 562
 563         return tar_offsets[idx];
 564 }
 565
 566 static inline unsigned long phb_offset(unsigned char num)
 567 {
 568         size_t idx = busno_to_phbid(num);
 569
 570         return phb_offsets[idx];
 571 }
 572
 573 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 574 {
 575         unsigned long target = ((unsigned long)bar) | offset;
 576         return (void __iomem*)target;
 577 }
 578
 579 static inline int is_calioc2(unsigned short device)
 580 {
 581         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 582 }
 583
 584 static inline int is_calgary(unsigned short device)
 585 {
 586         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 587 }
 588
 589 static inline int is_cal_pci_dev(unsigned short device)
 590 {
 591         return (is_calgary(device) || is_calioc2(device));
 592 }
 593
 594 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 595 {
 596         u64 val;
 597         u32 aer;
 598         int i = 0;
 599         void __iomem *bbar = tbl->bbar;
 600         void __iomem *target;
 601
 602         /* disable arbitration on the bus */
 603         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 604         aer = readl(target);
 605         writel(0, target);
 606
 607         /* read plssr to ensure it got there */
 608         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 609         val = readl(target);
 610
 611         /* poll split queues until all DMA activity is done */
 612         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 613         do {
 614                 val = readq(target);
 615                 i++;
 616         } while ((val & 0xff) != 0xff && i < 100);
 617         if (i == 100)
 618                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 619                        "continuing anyway\n");
 620
 621         /* invalidate TCE cache */
 622         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 623         writeq(tbl->tar_val, target);
 624
 625         /* enable arbitration */
 626         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 627         writel(aer, target);
 628         (void)readl(target); /* flush */
 629 }
 630
 631 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 632 {
 633         void __iomem *bbar = tbl->bbar;
 634         void __iomem *target;
 635         u64 val64;
 636         u32 val;
 637         int i = 0;
 638         int count = 1;
 639         unsigned char bus = tbl->it_busno;
 640
 641 begin:
 642         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 643                "sequence - count %d\n", bus, count);
 644
 645         /* 1. using the Page Migration Control reg set SoftStop */
 646         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 647         val = be32_to_cpu(readl(target));
 648         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 649         val |= PMR_SOFTSTOP;
 650         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 651         writel(cpu_to_be32(val), target);
 652
 653         /* 2. poll split queues until all DMA activity is done */
 654         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 655         target = calgary_reg(bbar, split_queue_offset(bus));
 656         do {
 657                 val64 = readq(target);
 658                 i++;
 659         } while ((val64 & 0xff) != 0xff && i < 100);
 660         if (i == 100)
 661                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 662                        "continuing anyway\n");
 663
 664         /* 3. poll Page Migration DEBUG for SoftStopFault */
 665         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 666         val = be32_to_cpu(readl(target));
 667         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 668
 669         /* 4. if SoftStopFault - goto (1) */
 670         if (val & PMR_SOFTSTOPFAULT) {
 671                 if (++count < 100)
 672                         goto begin;
 673                 else {
 674                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 675                                "aborting TCE cache flush sequence!\n");
 676                         return; /* pray for the best */
 677                 }
 678         }
 679
 680         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 681         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 682         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 683         val = be32_to_cpu(readl(target));
 684         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 685         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 686         val = be32_to_cpu(readl(target));
 687         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 688
 689         /* 6. invalidate TCE cache */
 690         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 691         target = calgary_reg(bbar, tar_offset(bus));
 692         writeq(tbl->tar_val, target);
 693
 694         /* 7. Re-read PMCR */
 695         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 696         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 697         val = be32_to_cpu(readl(target));
 698         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 699
 700         /* 8. Remove HardStop */
 701         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 702         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 703         val = 0;
 704         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 705         writel(cpu_to_be32(val), target);
 706         val = be32_to_cpu(readl(target));
 707         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 708 }
 709
 710 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 711         u64 limit)
 712 {
 713         unsigned int numpages;
 714
 715         limit = limit | 0xfffff;
 716         limit++;
 717
 718         numpages = ((limit - start) >> PAGE_SHIFT);
 719         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 720 }
 721
 722 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 723 {
 724         void __iomem *target;
 725         u64 low, high, sizelow;
 726         u64 start, limit;
 727         struct iommu_table *tbl = pci_iommu(dev->bus);
 728         unsigned char busnum = dev->bus->number;
 729         void __iomem *bbar = tbl->bbar;
 730
 731         /* peripheral MEM_1 region */
 732         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 733         low = be32_to_cpu(readl(target));
 734         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 735         high = be32_to_cpu(readl(target));
 736         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 737         sizelow = be32_to_cpu(readl(target));
 738
 739         start = (high << 32) | low;
 740         limit = sizelow;
 741
 742         calgary_reserve_mem_region(dev, start, limit);
 743 }
 744
 745 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 746 {
 747         void __iomem *target;
 748         u32 val32;
 749         u64 low, high, sizelow, sizehigh;
 750         u64 start, limit;
 751         struct iommu_table *tbl = pci_iommu(dev->bus);
 752         unsigned char busnum = dev->bus->number;
 753         void __iomem *bbar = tbl->bbar;
 754
 755         /* is it enabled? */
 756         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 757         val32 = be32_to_cpu(readl(target));
 758         if (!(val32 & PHB_MEM2_ENABLE))
 759                 return;
 760
 761         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 762         low = be32_to_cpu(readl(target));
 763         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 764         high = be32_to_cpu(readl(target));
 765         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 766         sizelow = be32_to_cpu(readl(target));
 767         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 768         sizehigh = be32_to_cpu(readl(target));
 769
 770         start = (high << 32) | low;
 771         limit = (sizehigh << 32) | sizelow;
 772
 773         calgary_reserve_mem_region(dev, start, limit);
 774 }
 775
 776 /*
 777  * some regions of the IO address space do not get translated, so we
 778  * must not give devices IO addresses in those regions. The regions
 779  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 780  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 781  * later.
 782  */
 783 static void __init calgary_reserve_regions(struct pci_dev *dev)
 784 {
 785         unsigned int npages;
 786         u64 start;
 787         struct iommu_table *tbl = pci_iommu(dev->bus);
 788
 789         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 790         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 791
 792         /* avoid the BIOS/VGA first 640KB-1MB region */
 793         /* for CalIOC2 - avoid the entire first MB */
 794         if (is_calgary(dev->device)) {
 795                 start = (640 * 1024);
 796                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 797         } else { /* calioc2 */
 798                 start = 0;
 799                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 800         }
 801         iommu_range_reserve(tbl, start, npages);
 802
 803         /* reserve the two PCI peripheral memory regions in IO space */
 804         calgary_reserve_peripheral_mem_1(dev);
 805         calgary_reserve_peripheral_mem_2(dev);
 806 }
 807
 808 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 809 {
 810         u64 val64;
 811         u64 table_phys;
 812         void __iomem *target;
 813         int ret;
 814         struct iommu_table *tbl;
 815
 816         /* build TCE tables for each PHB */
 817         ret = build_tce_table(dev, bbar);
 818         if (ret)
 819                 return ret;
 820
 821         tbl = pci_iommu(dev->bus);
 822         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 823         tce_free(tbl, 0, tbl->it_size);
 824
 825         if (is_calgary(dev->device))
 826                 tbl->chip_ops = &calgary_chip_ops;
 827         else if (is_calioc2(dev->device))
 828                 tbl->chip_ops = &calioc2_chip_ops;
 829         else
 830                 BUG();
 831
 832         calgary_reserve_regions(dev);
 833
 834         /* set TARs for each PHB */
 835         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 836         val64 = be64_to_cpu(readq(target));
 837
 838         /* zero out all TAR bits under sw control */
 839         val64 &= ~TAR_SW_BITS;
 840         table_phys = (u64)__pa(tbl->it_base);
 841
 842         val64 |= table_phys;
 843
 844         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 845         val64 |= (u64) specified_table_size;
 846
 847         tbl->tar_val = cpu_to_be64(val64);
 848
 849         writeq(tbl->tar_val, target);
 850         readq(target); /* flush */
 851
 852         return 0;
 853 }
 854
 855 static void __init calgary_free_bus(struct pci_dev *dev)
 856 {
 857         u64 val64;
 858         struct iommu_table *tbl = pci_iommu(dev->bus);
 859         void __iomem *target;
 860         unsigned int bitmapsz;
 861
 862         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 863         val64 = be64_to_cpu(readq(target));
 864         val64 &= ~TAR_SW_BITS;
 865         writeq(cpu_to_be64(val64), target);
 866         readq(target); /* flush */
 867
 868         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 869         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 870         tbl->it_map = NULL;
 871
 872         kfree(tbl);
 873
 874         set_pci_iommu(dev->bus, NULL);
 875
 876         /* Can't free bootmem allocated memory after system is up :-( */
 877         bus_info[dev->bus->number].tce_space = NULL;
 878 }
 879
 880 static void calgary_dump_error_regs(struct iommu_table *tbl)
 881 {
 882         void __iomem *bbar = tbl->bbar;
 883         void __iomem *target;
 884         u32 csr, plssr;
 885
 886         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 887         csr = be32_to_cpu(readl(target));
 888
 889         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 890         plssr = be32_to_cpu(readl(target));
 891
 892         /* If no error, the agent ID in the CSR is not valid */
 893         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 894                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 895 }
 896
 897 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 898 {
 899         void __iomem *bbar = tbl->bbar;
 900         u32 csr, csmr, plssr, mck, rcstat;
 901         void __iomem *target;
 902         unsigned long phboff = phb_offset(tbl->it_busno);
 903         unsigned long erroff;
 904         u32 errregs[7];
 905         int i;
 906
 907         /* dump CSR */
 908         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 909         csr = be32_to_cpu(readl(target));
 910         /* dump PLSSR */
 911         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 912         plssr = be32_to_cpu(readl(target));
 913         /* dump CSMR */
 914         target = calgary_reg(bbar, phboff | 0x290);
 915         csmr = be32_to_cpu(readl(target));
 916         /* dump mck */
 917         target = calgary_reg(bbar, phboff | 0x800);
 918         mck = be32_to_cpu(readl(target));
 919
 920         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 921                tbl->it_busno);
 922
 923         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 924                csr, plssr, csmr, mck);
 925
 926         /* dump rest of error regs */
 927         printk(KERN_EMERG "Calgary: ");
 928         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 929                 /* err regs are at 0x810 - 0x870 */
 930                 erroff = (0x810 + (i * 0x10));
 931                 target = calgary_reg(bbar, phboff | erroff);
 932                 errregs[i] = be32_to_cpu(readl(target));
 933                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 934         }
 935         printk("\n");
 936
 937         /* root complex status */
 938         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 939         rcstat = be32_to_cpu(readl(target));
 940         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 941                PHB_ROOT_COMPLEX_STATUS);
 942 }
 943
 944 static void calgary_watchdog(unsigned long data)
 945 {
 946         struct pci_dev *dev = (struct pci_dev *)data;
 947         struct iommu_table *tbl = pci_iommu(dev->bus);
 948         void __iomem *bbar = tbl->bbar;
 949         u32 val32;
 950         void __iomem *target;
 951
 952         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 953         val32 = be32_to_cpu(readl(target));
 954
 955         /* If no error, the agent ID in the CSR is not valid */
 956         if (val32 & CSR_AGENT_MASK) {
 957                 tbl->chip_ops->dump_error_regs(tbl);
 958
 959                 /* reset error */
 960                 writel(0, target);
 961
 962                 /* Disable bus that caused the error */
 963                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 964                                      PHB_CONFIG_RW_OFFSET);
 965                 val32 = be32_to_cpu(readl(target));
 966                 val32 |= PHB_SLOT_DISABLE;
 967                 writel(cpu_to_be32(val32), target);
 968                 readl(target); /* flush */
 969         } else {
 970                 /* Reset the timer */
 971                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 972         }
 973 }
 974
 975 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 976         unsigned char busnum, unsigned long timeout)
 977 {
 978         u64 val64;
 979         void __iomem *target;
 980         unsigned int phb_shift = ~0; /* silence gcc */
 981         u64 mask;
 982
 983         switch (busno_to_phbid(busnum)) {
 984         case 0: phb_shift = (63 - 19);
 985                 break;
 986         case 1: phb_shift = (63 - 23);
 987                 break;
 988         case 2: phb_shift = (63 - 27);
 989                 break;
 990         case 3: phb_shift = (63 - 35);
 991                 break;
 992         default:
 993                 BUG_ON(busno_to_phbid(busnum));
 994         }
 995
 996         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 997         val64 = be64_to_cpu(readq(target));
 998
 999         /* zero out this PHB's timer bits */
1000         mask = ~(0xFUL << phb_shift);
1001         val64 &= mask;
1002         val64 |= (timeout << phb_shift);
1003         writeq(cpu_to_be64(val64), target);
1004         readq(target); /* flush */
1005 }
1006
1007 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1008 {
1009         unsigned char busnum = dev->bus->number;
1010         void __iomem *bbar = tbl->bbar;
1011         void __iomem *target;
1012         u32 val;
1013
1014         /*
1015          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1016          */
1017         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1018         val = cpu_to_be32(readl(target));
1019         val |= 0x00800000;
1020         writel(cpu_to_be32(val), target);
1021 }
1022
1023 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1024 {
1025         unsigned char busnum = dev->bus->number;
1026
1027         /*
1028          * Give split completion a longer timeout on bus 1 for aic94xx
1029          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1030          */
1031         if (is_calgary(dev->device) && (busnum == 1))
1032                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1033                                                      CCR_2SEC_TIMEOUT);
1034 }
1035
1036 static void __init calgary_enable_translation(struct pci_dev *dev)
1037 {
1038         u32 val32;
1039         unsigned char busnum;
1040         void __iomem *target;
1041         void __iomem *bbar;
1042         struct iommu_table *tbl;
1043
1044         busnum = dev->bus->number;
1045         tbl = pci_iommu(dev->bus);
1046         bbar = tbl->bbar;
1047
1048         /* enable TCE in PHB Config Register */
1049         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1050         val32 = be32_to_cpu(readl(target));
1051         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1052
1053         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1054                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1055                "Calgary" : "CalIOC2", busnum);
1056         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1057                "bus.\n");
1058
1059         writel(cpu_to_be32(val32), target);
1060         readl(target); /* flush */
1061
1062         init_timer(&tbl->watchdog_timer);
1063         tbl->watchdog_timer.function = &calgary_watchdog;
1064         tbl->watchdog_timer.data = (unsigned long)dev;
1065         mod_timer(&tbl->watchdog_timer, jiffies);
1066 }
1067
1068 static void __init calgary_disable_translation(struct pci_dev *dev)
1069 {
1070         u32 val32;
1071         unsigned char busnum;
1072         void __iomem *target;
1073         void __iomem *bbar;
1074         struct iommu_table *tbl;
1075
1076         busnum = dev->bus->number;
1077         tbl = pci_iommu(dev->bus);
1078         bbar = tbl->bbar;
1079
1080         /* disable TCE in PHB Config Register */
1081         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1082         val32 = be32_to_cpu(readl(target));
1083         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1084
1085         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1086         writel(cpu_to_be32(val32), target);
1087         readl(target); /* flush */
1088
1089         del_timer_sync(&tbl->watchdog_timer);
1090 }
1091
1092 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1093 {
1094         pci_dev_get(dev);
1095         set_pci_iommu(dev->bus, NULL);
1096
1097         /* is the device behind a bridge? */
1098         if (dev->bus->parent)
1099                 dev->bus->parent->self = dev;
1100         else
1101                 dev->bus->self = dev;
1102 }
1103
1104 static int __init calgary_init_one(struct pci_dev *dev)
1105 {
1106         void __iomem *bbar;
1107         struct iommu_table *tbl;
1108         int ret;
1109
1110         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1111
1112         bbar = busno_to_bbar(dev->bus->number);
1113         ret = calgary_setup_tar(dev, bbar);
1114         if (ret)
1115                 goto done;
1116
1117         pci_dev_get(dev);
1118
1119         if (dev->bus->parent) {
1120                 if (dev->bus->parent->self)
1121                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1122                                "bus->parent->self!\n", dev);
1123                 dev->bus->parent->self = dev;
1124         } else
1125                 dev->bus->self = dev;
1126
1127         tbl = pci_iommu(dev->bus);
1128         tbl->chip_ops->handle_quirks(tbl, dev);
1129
1130         calgary_enable_translation(dev);
1131
1132         return 0;
1133
1134 done:
1135         return ret;
1136 }
1137
1138 static int __init calgary_locate_bbars(void)
1139 {
1140         int ret;
1141         int rioidx, phb, bus;
1142         void __iomem *bbar;
1143         void __iomem *target;
1144         unsigned long offset;
1145         u8 start_bus, end_bus;
1146         u32 val;
1147
1148         ret = -ENODATA;
1149         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1150                 struct rio_detail *rio = rio_devs[rioidx];
1151
1152                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1153                         continue;
1154
1155                 /* map entire 1MB of Calgary config space */
1156                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1157                 if (!bbar)
1158                         goto error;
1159
1160                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1161                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1162                         target = calgary_reg(bbar, offset);
1163
1164                         val = be32_to_cpu(readl(target));
1165
1166                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1167                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1168
1169                         if (end_bus) {
1170                                 for (bus = start_bus; bus <= end_bus; bus++) {
1171                                         bus_info[bus].bbar = bbar;
1172                                         bus_info[bus].phbid = phb;
1173                                 }
1174                         } else {
1175                                 bus_info[start_bus].bbar = bbar;
1176                                 bus_info[start_bus].phbid = phb;
1177                         }
1178                 }
1179         }
1180
1181         return 0;
1182
1183 error:
1184         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1185         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1186                 if (bus_info[bus].bbar)
1187                         iounmap(bus_info[bus].bbar);
1188
1189         return ret;
1190 }
1191
1192 static int __init calgary_init(void)
1193 {
1194         int ret;
1195         struct pci_dev *dev = NULL;
1196         void *tce_space;
1197
1198         ret = calgary_locate_bbars();
1199         if (ret)
1200                 return ret;
1201
1202         do {
1203                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1204                 if (!dev)
1205                         break;
1206                 if (!is_cal_pci_dev(dev->device))
1207                         continue;
1208                 if (!translate_phb(dev)) {
1209                         calgary_init_one_nontraslated(dev);
1210                         continue;
1211                 }
1212                 tce_space = bus_info[dev->bus->number].tce_space;
1213                 if (!tce_space && !translate_empty_slots)
1214                         continue;
1215
1216                 ret = calgary_init_one(dev);
1217                 if (ret)
1218                         goto error;
1219         } while (1);
1220
1221         return ret;
1222
1223 error:
1224         do {
1225                 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
1226                                              PCI_ANY_ID, dev);
1227                 if (!dev)
1228                         break;
1229                 if (!is_cal_pci_dev(dev->device))
1230                         continue;
1231                 if (!translate_phb(dev)) {
1232                         pci_dev_put(dev);
1233                         continue;
1234                 }
1235                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
1236                         continue;
1237
1238                 calgary_disable_translation(dev);
1239                 calgary_free_bus(dev);
1240                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1241         } while (1);
1242
1243         return ret;
1244 }
1245
1246 static inline int __init determine_tce_table_size(u64 ram)
1247 {
1248         int ret;
1249
1250         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1251                 return specified_table_size;
1252
1253         /*
1254          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1255          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1256          * larger table size has twice as many entries, so shift the
1257          * max ram address by 13 to divide by 8K and then look at the
1258          * order of the result to choose between 0-7.
1259          */
1260         ret = get_order(ram >> 13);
1261         if (ret > TCE_TABLE_SIZE_8M)
1262                 ret = TCE_TABLE_SIZE_8M;
1263
1264         return ret;
1265 }
1266
1267 static int __init build_detail_arrays(void)
1268 {
1269         unsigned long ptr;
1270         int i, scal_detail_size, rio_detail_size;
1271
1272         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1273                 printk(KERN_WARNING
1274                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1275                         "but system has %d nodes.\n",
1276                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1277                 return -ENODEV;
1278         }
1279
1280         switch (rio_table_hdr->version){
1281         case 2:
1282                 scal_detail_size = 11;
1283                 rio_detail_size = 13;
1284                 break;
1285         case 3:
1286                 scal_detail_size = 12;
1287                 rio_detail_size = 15;
1288                 break;
1289         default:
1290                 printk(KERN_WARNING
1291                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1292                        rio_table_hdr->version);
1293                 return -EPROTO;
1294         }
1295
1296         ptr = ((unsigned long)rio_table_hdr) + 3;
1297         for (i = 0; i < rio_table_hdr->num_scal_dev;
1298                     i++, ptr += scal_detail_size)
1299                 scal_devs[i] = (struct scal_detail *)ptr;
1300
1301         for (i = 0; i < rio_table_hdr->num_rio_dev;
1302                     i++, ptr += rio_detail_size)
1303                 rio_devs[i] = (struct rio_detail *)ptr;
1304
1305         return 0;
1306 }
1307
1308 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1309 {
1310         int dev;
1311         u32 val;
1312
1313         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1314                 /*
1315                  * FIXME: properly scan for devices accross the
1316                  * PCI-to-PCI bridge on every CalIOC2 port.
1317                  */
1318                 return 1;
1319         }
1320
1321         for (dev = 1; dev < 8; dev++) {
1322                 val = read_pci_config(bus, dev, 0, 0);
1323                 if (val != 0xffffffff)
1324                         break;
1325         }
1326         return (val != 0xffffffff);
1327 }
1328
1329 void __init detect_calgary(void)
1330 {
1331         int bus;
1332         void *tbl;
1333         int calgary_found = 0;
1334         unsigned long ptr;
1335         unsigned int offset, prev_offset;
1336         int ret;
1337
1338         /*
1339          * if the user specified iommu=off or iommu=soft or we found
1340          * another HW IOMMU already, bail out.
1341          */
1342         if (swiotlb || no_iommu || iommu_detected)
1343                 return;
1344
1345         if (!use_calgary)
1346                 return;
1347
1348         if (!early_pci_allowed())
1349                 return;
1350
1351         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1352
1353         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1354
1355         rio_table_hdr = NULL;
1356         prev_offset = 0;
1357         offset = 0x180;
1358         /*
1359          * The next offset is stored in the 1st word.
1360          * Only parse up until the offset increases:
1361          */
1362         while (offset > prev_offset) {
1363                 /* The block id is stored in the 2nd word */
1364                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1365                         /* set the pointer past the offset & block id */
1366                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1367                         break;
1368                 }
1369                 prev_offset = offset;
1370                 offset = *((unsigned short *)(ptr + offset));
1371         }
1372         if (!rio_table_hdr) {
1373                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1374                        "in EBDA - bailing!\n");
1375                 return;
1376         }
1377
1378         ret = build_detail_arrays();
1379         if (ret) {
1380                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1381                 return;
1382         }
1383
1384         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1385
1386         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1387                 struct calgary_bus_info *info = &bus_info[bus];
1388                 unsigned short pci_device;
1389                 u32 val;
1390
1391                 val = read_pci_config(bus, 0, 0, 0);
1392                 pci_device = (val & 0xFFFF0000) >> 16;
1393
1394                 if (!is_cal_pci_dev(pci_device))
1395                         continue;
1396
1397                 if (info->translation_disabled)
1398                         continue;
1399
1400                 if (calgary_bus_has_devices(bus, pci_device) ||
1401                     translate_empty_slots) {
1402                         tbl = alloc_tce_table();
1403                         if (!tbl)
1404                                 goto cleanup;
1405                         info->tce_space = tbl;
1406                         calgary_found = 1;
1407                 }
1408         }
1409
1410         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1411                calgary_found ? "found" : "not found");
1412
1413         if (calgary_found) {
1414                 iommu_detected = 1;
1415                 calgary_detected = 1;
1416                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1417                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1418                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1419                        debugging ? "enabled" : "disabled");
1420         }
1421         return;
1422
1423 cleanup:
1424         for (--bus; bus >= 0; --bus) {
1425                 struct calgary_bus_info *info = &bus_info[bus];
1426
1427                 if (info->tce_space)
1428                         free_tce_table(info->tce_space);
1429         }
1430 }
1431
1432 int __init calgary_iommu_init(void)
1433 {
1434         int ret;
1435
1436         if (no_iommu || swiotlb)
1437                 return -ENODEV;
1438
1439         if (!calgary_detected)
1440                 return -ENODEV;
1441
1442         /* ok, we're trying to use Calgary - let's roll */
1443         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1444
1445         ret = calgary_init();
1446         if (ret) {
1447                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1448                        "falling back to no_iommu\n", ret);
1449                 if (end_pfn > MAX_DMA32_PFN)
1450                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1451                                         "32bit PCI may malfunction.\n");
1452                 return ret;
1453         }
1454
1455         force_iommu = 1;
1456         bad_dma_address = 0x0;
1457         dma_ops = &calgary_dma_ops;
1458
1459         return 0;
1460 }
1461
1462 static int __init calgary_parse_options(char *p)
1463 {
1464         unsigned int bridge;
1465         size_t len;
1466         char* endp;
1467
1468         while (*p) {
1469                 if (!strncmp(p, "64k", 3))
1470                         specified_table_size = TCE_TABLE_SIZE_64K;
1471                 else if (!strncmp(p, "128k", 4))
1472                         specified_table_size = TCE_TABLE_SIZE_128K;
1473                 else if (!strncmp(p, "256k", 4))
1474                         specified_table_size = TCE_TABLE_SIZE_256K;
1475                 else if (!strncmp(p, "512k", 4))
1476                         specified_table_size = TCE_TABLE_SIZE_512K;
1477                 else if (!strncmp(p, "1M", 2))
1478                         specified_table_size = TCE_TABLE_SIZE_1M;
1479                 else if (!strncmp(p, "2M", 2))
1480                         specified_table_size = TCE_TABLE_SIZE_2M;
1481                 else if (!strncmp(p, "4M", 2))
1482                         specified_table_size = TCE_TABLE_SIZE_4M;
1483                 else if (!strncmp(p, "8M", 2))
1484                         specified_table_size = TCE_TABLE_SIZE_8M;
1485
1486                 len = strlen("translate_empty_slots");
1487                 if (!strncmp(p, "translate_empty_slots", len))
1488                         translate_empty_slots = 1;
1489
1490                 len = strlen("disable");
1491                 if (!strncmp(p, "disable", len)) {
1492                         p += len;
1493                         if (*p == '=')
1494                                 ++p;
1495                         if (*p == '\0')
1496                                 break;
1497                         bridge = simple_strtol(p, &endp, 0);
1498                         if (p == endp)
1499                                 break;
1500
1501                         if (bridge < MAX_PHB_BUS_NUM) {
1502                                 printk(KERN_INFO "Calgary: disabling "
1503                                        "translation for PHB %#x\n", bridge);
1504                                 bus_info[bridge].translation_disabled = 1;
1505                         }
1506                 }
1507
1508                 p = strpbrk(p, ",");
1509                 if (!p)
1510                         break;
1511
1512                 p++; /* skip ',' */
1513         }
1514         return 1;
1515 }
1516 __setup("calgary=", calgary_parse_options);
1517
1518 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1519 {
1520         struct iommu_table *tbl;
1521         unsigned int npages;
1522         int i;
1523
1524         tbl = pci_iommu(dev->bus);
1525
1526         for (i = 0; i < 4; i++) {
1527                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1528
1529                 /* Don't give out TCEs that map MEM resources */
1530                 if (!(r->flags & IORESOURCE_MEM))
1531                         continue;
1532
1533                 /* 0-based? we reserve the whole 1st MB anyway */
1534                 if (!r->start)
1535                         continue;
1536
1537                 /* cover the whole region */
1538                 npages = (r->end - r->start) >> PAGE_SHIFT;
1539                 npages++;
1540
1541                 iommu_range_reserve(tbl, r->start, npages);
1542         }
1543 }
1544
1545 static int __init calgary_fixup_tce_spaces(void)
1546 {
1547         struct pci_dev *dev = NULL;
1548         void *tce_space;
1549
1550         if (no_iommu || swiotlb || !calgary_detected)
1551                 return -ENODEV;
1552
1553         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1554
1555         do {
1556                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1557                 if (!dev)
1558                         break;
1559                 if (!is_cal_pci_dev(dev->device))
1560                         continue;
1561                 if (!translate_phb(dev))
1562                         continue;
1563
1564                 tce_space = bus_info[dev->bus->number].tce_space;
1565                 if (!tce_space)
1566                         continue;
1567
1568                 calgary_fixup_one_tce_space(dev);
1569
1570         } while (1);
1571
1572         return 0;
1573 }
1574
1575 /*
1576  * We need to be call after pcibios_assign_resources (fs_initcall level)
1577  * and before device_initcall.
1578  */
1579 rootfs_initcall(calgary_fixup_tce_spaces);