arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33
  34 #include <asm/io.h>
  35 #include <asm/smp.h>
  36 #include <asm/desc.h>
  37 #include <asm/proto.h>
  38 #include <asm/mach_apic.h>
  39 #include <asm/acpi.h>
  40
  41 #define __apicdebuginit  __init
  42
  43 int sis_apic_bug; /* not actually supported, dummy for compile */
  44
  45 static int no_timer_check;
  46
  47 static DEFINE_SPINLOCK(ioapic_lock);
  48
  49 /*
  50  * # of IRQ routing registers
  51  */
  52 int nr_ioapic_registers[MAX_IO_APICS];
  53
  54 /*
  55  * Rough estimation of how many shared IRQs there are, can
  56  * be changed anytime.
  57  */
  58 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  59 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  60
  61 /*
  62  * This is performance-critical, we want to do it O(1)
  63  *
  64  * the indexing order of this array favors 1:1 mappings
  65  * between pins and IRQs.
  66  */
  67
  68 static struct irq_pin_list {
  69         short apic, pin, next;
  70 } irq_2_pin[PIN_MAP_SIZE];
  71
  72 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  73 #ifdef CONFIG_PCI_MSI
  74 #define vector_to_irq(vector)   \
  75         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  76 #else
  77 #define vector_to_irq(vector)   (vector)
  78 #endif
  79
  80 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  81                                                                         \
  82 {                                                                       \
  83         int pin;                                                        \
  84         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  85                                                                         \
  86         for (;;) {                                                      \
  87                 unsigned int reg;                                       \
  88                 pin = entry->pin;                                       \
  89                 if (pin == -1)                                          \
  90                         break;                                          \
  91                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
  92                 reg ACTION;                                             \
  93                 io_apic_modify(entry->apic, reg);                       \
  94                 if (!entry->next)                                       \
  95                         break;                                          \
  96                 entry = irq_2_pin + entry->next;                        \
  97         }                                                               \
  98         FINAL;                                                          \
  99 }
 100
 101 #ifdef CONFIG_SMP
 102 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 103 {
 104         unsigned long flags;
 105         unsigned int dest;
 106         cpumask_t tmp;
 107
 108         cpus_and(tmp, mask, cpu_online_map);
 109         if (cpus_empty(tmp))
 110                 tmp = TARGET_CPUS;
 111
 112         cpus_and(mask, tmp, CPU_MASK_ALL);
 113
 114         dest = cpu_mask_to_apicid(mask);
 115
 116         /*
 117          * Only the high 8 bits are valid.
 118          */
 119         dest = SET_APIC_LOGICAL_ID(dest);
 120
 121         spin_lock_irqsave(&ioapic_lock, flags);
 122         __DO_ACTION(1, = dest, )
 123         set_irq_info(irq, mask);
 124         spin_unlock_irqrestore(&ioapic_lock, flags);
 125 }
 126 #endif
 127
 128 /*
 129  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 130  * shared ISA-space IRQs, so we have to support them. We are super
 131  * fast in the common case, and fast for shared ISA-space IRQs.
 132  */
 133 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 134 {
 135         static int first_free_entry = NR_IRQS;
 136         struct irq_pin_list *entry = irq_2_pin + irq;
 137
 138         while (entry->next)
 139                 entry = irq_2_pin + entry->next;
 140
 141         if (entry->pin != -1) {
 142                 entry->next = first_free_entry;
 143                 entry = irq_2_pin + entry->next;
 144                 if (++first_free_entry >= PIN_MAP_SIZE)
 145                         panic("io_apic.c: whoops");
 146         }
 147         entry->apic = apic;
 148         entry->pin = pin;
 149 }
 150
 151
 152 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 153                                                                         \
 154         static void name##_IO_APIC_irq (unsigned int irq)               \
 155         __DO_ACTION(R, ACTION, FINAL)
 156
 157 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 158                                                 /* mask = 1 */
 159 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 160                                                 /* mask = 0 */
 161
 162 static void mask_IO_APIC_irq (unsigned int irq)
 163 {
 164         unsigned long flags;
 165
 166         spin_lock_irqsave(&ioapic_lock, flags);
 167         __mask_IO_APIC_irq(irq);
 168         spin_unlock_irqrestore(&ioapic_lock, flags);
 169 }
 170
 171 static void unmask_IO_APIC_irq (unsigned int irq)
 172 {
 173         unsigned long flags;
 174
 175         spin_lock_irqsave(&ioapic_lock, flags);
 176         __unmask_IO_APIC_irq(irq);
 177         spin_unlock_irqrestore(&ioapic_lock, flags);
 178 }
 179
 180 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 181 {
 182         struct IO_APIC_route_entry entry;
 183         unsigned long flags;
 184
 185         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 186         spin_lock_irqsave(&ioapic_lock, flags);
 187         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 188         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 189         spin_unlock_irqrestore(&ioapic_lock, flags);
 190         if (entry.delivery_mode == dest_SMI)
 191                 return;
 192         /*
 193          * Disable it in the IO-APIC irq-routing table:
 194          */
 195         memset(&entry, 0, sizeof(entry));
 196         entry.mask = 1;
 197         spin_lock_irqsave(&ioapic_lock, flags);
 198         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 199         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 200         spin_unlock_irqrestore(&ioapic_lock, flags);
 201 }
 202
 203 static void clear_IO_APIC (void)
 204 {
 205         int apic, pin;
 206
 207         for (apic = 0; apic < nr_ioapics; apic++)
 208                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 209                         clear_IO_APIC_pin(apic, pin);
 210 }
 211
 212 /*
 213  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 214  * specific CPU-side IRQs.
 215  */
 216
 217 #define MAX_PIRQS 8
 218 static int pirq_entries [MAX_PIRQS];
 219 static int pirqs_enabled;
 220 int skip_ioapic_setup;
 221 int ioapic_force;
 222
 223 /* dummy parsing: see setup.c */
 224
 225 static int __init disable_ioapic_setup(char *str)
 226 {
 227         skip_ioapic_setup = 1;
 228         return 1;
 229 }
 230
 231 static int __init enable_ioapic_setup(char *str)
 232 {
 233         ioapic_force = 1;
 234         skip_ioapic_setup = 0;
 235         return 1;
 236 }
 237
 238 __setup("noapic", disable_ioapic_setup);
 239 __setup("apic", enable_ioapic_setup);
 240
 241 #include <asm/pci-direct.h>
 242 #include <linux/pci_ids.h>
 243 #include <linux/pci.h>
 244
 245 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 246    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 247    Use pci direct infrastructure because this runs before the PCI subsystem.
 248
 249    Can be overwritten with "apic"
 250
 251    And another hack to disable the IOMMU on VIA chipsets.
 252
 253    Kludge-O-Rama. */
 254 void __init check_ioapic(void)
 255 {
 256         int num,slot,func;
 257         if (ioapic_force)
 258                 return;
 259
 260         /* Poor man's PCI discovery */
 261         for (num = 0; num < 32; num++) {
 262                 for (slot = 0; slot < 32; slot++) {
 263                         for (func = 0; func < 8; func++) {
 264                                 u32 class;
 265                                 u32 vendor;
 266                                 u8 type;
 267                                 class = read_pci_config(num,slot,func,
 268                                                         PCI_CLASS_REVISION);
 269                                 if (class == 0xffffffff)
 270                                         break;
 271
 272                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 273                                         continue;
 274
 275                                 vendor = read_pci_config(num, slot, func,
 276                                                          PCI_VENDOR_ID);
 277                                 vendor &= 0xffff;
 278                                 switch (vendor) {
 279                                 case PCI_VENDOR_ID_VIA:
 280 #ifdef CONFIG_GART_IOMMU
 281                                         if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
 282                                              force_iommu) &&
 283                                             !iommu_aperture_allowed) {
 284                                                 printk(KERN_INFO
 285     "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
 286                                                 iommu_aperture_disabled = 1;
 287                                         }
 288 #endif
 289                                         return;
 290                                 case PCI_VENDOR_ID_NVIDIA:
 291 #ifdef CONFIG_ACPI
 292                                         /* All timer overrides on Nvidia
 293                                            seem to be wrong. Skip them. */
 294                                         acpi_skip_timer_override = 1;
 295                                         printk(KERN_INFO
 296              "Nvidia board detected. Ignoring ACPI timer override.\n");
 297 #endif
 298                                         /* RED-PEN skip them on mptables too? */
 299                                         return;
 300                                 }
 301
 302                                 /* No multi-function device? */
 303                                 type = read_pci_config_byte(num,slot,func,
 304                                                             PCI_HEADER_TYPE);
 305                                 if (!(type & 0x80))
 306                                         break;
 307                         }
 308                 }
 309         }
 310 }
 311
 312 static int __init ioapic_pirq_setup(char *str)
 313 {
 314         int i, max;
 315         int ints[MAX_PIRQS+1];
 316
 317         get_options(str, ARRAY_SIZE(ints), ints);
 318
 319         for (i = 0; i < MAX_PIRQS; i++)
 320                 pirq_entries[i] = -1;
 321
 322         pirqs_enabled = 1;
 323         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 324         max = MAX_PIRQS;
 325         if (ints[0] < MAX_PIRQS)
 326                 max = ints[0];
 327
 328         for (i = 0; i < max; i++) {
 329                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 330                 /*
 331                  * PIRQs are mapped upside down, usually.
 332                  */
 333                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 334         }
 335         return 1;
 336 }
 337
 338 __setup("pirq=", ioapic_pirq_setup);
 339
 340 /*
 341  * Find the IRQ entry number of a certain pin.
 342  */
 343 static int find_irq_entry(int apic, int pin, int type)
 344 {
 345         int i;
 346
 347         for (i = 0; i < mp_irq_entries; i++)
 348                 if (mp_irqs[i].mpc_irqtype == type &&
 349                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 350                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 351                     mp_irqs[i].mpc_dstirq == pin)
 352                         return i;
 353
 354         return -1;
 355 }
 356
 357 /*
 358  * Find the pin to which IRQ[irq] (ISA) is connected
 359  */
 360 static int find_isa_irq_pin(int irq, int type)
 361 {
 362         int i;
 363
 364         for (i = 0; i < mp_irq_entries; i++) {
 365                 int lbus = mp_irqs[i].mpc_srcbus;
 366
 367                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 368                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 369                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 370                     (mp_irqs[i].mpc_irqtype == type) &&
 371                     (mp_irqs[i].mpc_srcbusirq == irq))
 372
 373                         return mp_irqs[i].mpc_dstirq;
 374         }
 375         return -1;
 376 }
 377
 378 /*
 379  * Find a specific PCI IRQ entry.
 380  * Not an __init, possibly needed by modules
 381  */
 382 static int pin_2_irq(int idx, int apic, int pin);
 383
 384 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 385 {
 386         int apic, i, best_guess = -1;
 387
 388         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 389                 bus, slot, pin);
 390         if (mp_bus_id_to_pci_bus[bus] == -1) {
 391                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 392                 return -1;
 393         }
 394         for (i = 0; i < mp_irq_entries; i++) {
 395                 int lbus = mp_irqs[i].mpc_srcbus;
 396
 397                 for (apic = 0; apic < nr_ioapics; apic++)
 398                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 399                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 400                                 break;
 401
 402                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 403                     !mp_irqs[i].mpc_irqtype &&
 404                     (bus == lbus) &&
 405                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 406                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 407
 408                         if (!(apic || IO_APIC_IRQ(irq)))
 409                                 continue;
 410
 411                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 412                                 return irq;
 413                         /*
 414                          * Use the first all-but-pin matching entry as a
 415                          * best-guess fuzzy result for broken mptables.
 416                          */
 417                         if (best_guess < 0)
 418                                 best_guess = irq;
 419                 }
 420         }
 421         return best_guess;
 422 }
 423
 424 /*
 425  * EISA Edge/Level control register, ELCR
 426  */
 427 static int EISA_ELCR(unsigned int irq)
 428 {
 429         if (irq < 16) {
 430                 unsigned int port = 0x4d0 + (irq >> 3);
 431                 return (inb(port) >> (irq & 7)) & 1;
 432         }
 433         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 434         return 0;
 435 }
 436
 437 /* EISA interrupts are always polarity zero and can be edge or level
 438  * trigger depending on the ELCR value.  If an interrupt is listed as
 439  * EISA conforming in the MP table, that means its trigger type must
 440  * be read in from the ELCR */
 441
 442 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 443 #define default_EISA_polarity(idx)      (0)
 444
 445 /* ISA interrupts are always polarity zero edge triggered,
 446  * when listed as conforming in the MP table. */
 447
 448 #define default_ISA_trigger(idx)        (0)
 449 #define default_ISA_polarity(idx)       (0)
 450
 451 /* PCI interrupts are always polarity one level triggered,
 452  * when listed as conforming in the MP table. */
 453
 454 #define default_PCI_trigger(idx)        (1)
 455 #define default_PCI_polarity(idx)       (1)
 456
 457 /* MCA interrupts are always polarity zero level triggered,
 458  * when listed as conforming in the MP table. */
 459
 460 #define default_MCA_trigger(idx)        (1)
 461 #define default_MCA_polarity(idx)       (0)
 462
 463 static int __init MPBIOS_polarity(int idx)
 464 {
 465         int bus = mp_irqs[idx].mpc_srcbus;
 466         int polarity;
 467
 468         /*
 469          * Determine IRQ line polarity (high active or low active):
 470          */
 471         switch (mp_irqs[idx].mpc_irqflag & 3)
 472         {
 473                 case 0: /* conforms, ie. bus-type dependent polarity */
 474                 {
 475                         switch (mp_bus_id_to_type[bus])
 476                         {
 477                                 case MP_BUS_ISA: /* ISA pin */
 478                                 {
 479                                         polarity = default_ISA_polarity(idx);
 480                                         break;
 481                                 }
 482                                 case MP_BUS_EISA: /* EISA pin */
 483                                 {
 484                                         polarity = default_EISA_polarity(idx);
 485                                         break;
 486                                 }
 487                                 case MP_BUS_PCI: /* PCI pin */
 488                                 {
 489                                         polarity = default_PCI_polarity(idx);
 490                                         break;
 491                                 }
 492                                 case MP_BUS_MCA: /* MCA pin */
 493                                 {
 494                                         polarity = default_MCA_polarity(idx);
 495                                         break;
 496                                 }
 497                                 default:
 498                                 {
 499                                         printk(KERN_WARNING "broken BIOS!!\n");
 500                                         polarity = 1;
 501                                         break;
 502                                 }
 503                         }
 504                         break;
 505                 }
 506                 case 1: /* high active */
 507                 {
 508                         polarity = 0;
 509                         break;
 510                 }
 511                 case 2: /* reserved */
 512                 {
 513                         printk(KERN_WARNING "broken BIOS!!\n");
 514                         polarity = 1;
 515                         break;
 516                 }
 517                 case 3: /* low active */
 518                 {
 519                         polarity = 1;
 520                         break;
 521                 }
 522                 default: /* invalid */
 523                 {
 524                         printk(KERN_WARNING "broken BIOS!!\n");
 525                         polarity = 1;
 526                         break;
 527                 }
 528         }
 529         return polarity;
 530 }
 531
 532 static int MPBIOS_trigger(int idx)
 533 {
 534         int bus = mp_irqs[idx].mpc_srcbus;
 535         int trigger;
 536
 537         /*
 538          * Determine IRQ trigger mode (edge or level sensitive):
 539          */
 540         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 541         {
 542                 case 0: /* conforms, ie. bus-type dependent */
 543                 {
 544                         switch (mp_bus_id_to_type[bus])
 545                         {
 546                                 case MP_BUS_ISA: /* ISA pin */
 547                                 {
 548                                         trigger = default_ISA_trigger(idx);
 549                                         break;
 550                                 }
 551                                 case MP_BUS_EISA: /* EISA pin */
 552                                 {
 553                                         trigger = default_EISA_trigger(idx);
 554                                         break;
 555                                 }
 556                                 case MP_BUS_PCI: /* PCI pin */
 557                                 {
 558                                         trigger = default_PCI_trigger(idx);
 559                                         break;
 560                                 }
 561                                 case MP_BUS_MCA: /* MCA pin */
 562                                 {
 563                                         trigger = default_MCA_trigger(idx);
 564                                         break;
 565                                 }
 566                                 default:
 567                                 {
 568                                         printk(KERN_WARNING "broken BIOS!!\n");
 569                                         trigger = 1;
 570                                         break;
 571                                 }
 572                         }
 573                         break;
 574                 }
 575                 case 1: /* edge */
 576                 {
 577                         trigger = 0;
 578                         break;
 579                 }
 580                 case 2: /* reserved */
 581                 {
 582                         printk(KERN_WARNING "broken BIOS!!\n");
 583                         trigger = 1;
 584                         break;
 585                 }
 586                 case 3: /* level */
 587                 {
 588                         trigger = 1;
 589                         break;
 590                 }
 591                 default: /* invalid */
 592                 {
 593                         printk(KERN_WARNING "broken BIOS!!\n");
 594                         trigger = 0;
 595                         break;
 596                 }
 597         }
 598         return trigger;
 599 }
 600
 601 static inline int irq_polarity(int idx)
 602 {
 603         return MPBIOS_polarity(idx);
 604 }
 605
 606 static inline int irq_trigger(int idx)
 607 {
 608         return MPBIOS_trigger(idx);
 609 }
 610
 611 static int pin_2_irq(int idx, int apic, int pin)
 612 {
 613         int irq, i;
 614         int bus = mp_irqs[idx].mpc_srcbus;
 615
 616         /*
 617          * Debugging check, we are in big trouble if this message pops up!
 618          */
 619         if (mp_irqs[idx].mpc_dstirq != pin)
 620                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 621
 622         switch (mp_bus_id_to_type[bus])
 623         {
 624                 case MP_BUS_ISA: /* ISA pin */
 625                 case MP_BUS_EISA:
 626                 case MP_BUS_MCA:
 627                 {
 628                         irq = mp_irqs[idx].mpc_srcbusirq;
 629                         break;
 630                 }
 631                 case MP_BUS_PCI: /* PCI pin */
 632                 {
 633                         /*
 634                          * PCI IRQs are mapped in order
 635                          */
 636                         i = irq = 0;
 637                         while (i < apic)
 638                                 irq += nr_ioapic_registers[i++];
 639                         irq += pin;
 640                         break;
 641                 }
 642                 default:
 643                 {
 644                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 645                         irq = 0;
 646                         break;
 647                 }
 648         }
 649
 650         /*
 651          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 652          */
 653         if ((pin >= 16) && (pin <= 23)) {
 654                 if (pirq_entries[pin-16] != -1) {
 655                         if (!pirq_entries[pin-16]) {
 656                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 657                         } else {
 658                                 irq = pirq_entries[pin-16];
 659                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 660                                                 pin-16, irq);
 661                         }
 662                 }
 663         }
 664         return irq;
 665 }
 666
 667 static inline int IO_APIC_irq_trigger(int irq)
 668 {
 669         int apic, idx, pin;
 670
 671         for (apic = 0; apic < nr_ioapics; apic++) {
 672                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 673                         idx = find_irq_entry(apic,pin,mp_INT);
 674                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 675                                 return irq_trigger(idx);
 676                 }
 677         }
 678         /*
 679          * nonexistent IRQs are edge default
 680          */
 681         return 0;
 682 }
 683
 684 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 685 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 686
 687 int assign_irq_vector(int irq)
 688 {
 689         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 690
 691         BUG_ON(irq >= NR_IRQ_VECTORS);
 692         if (IO_APIC_VECTOR(irq) > 0)
 693                 return IO_APIC_VECTOR(irq);
 694 next:
 695         current_vector += 8;
 696         if (current_vector == IA32_SYSCALL_VECTOR)
 697                 goto next;
 698
 699         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 700                 offset++;
 701                 if (!(offset%8))
 702                         return -ENOSPC;
 703                 current_vector = FIRST_DEVICE_VECTOR + offset;
 704         }
 705
 706         vector_irq[current_vector] = irq;
 707         if (irq != AUTO_ASSIGN)
 708                 IO_APIC_VECTOR(irq) = current_vector;
 709
 710         return current_vector;
 711 }
 712
 713 extern void (*interrupt[NR_IRQS])(void);
 714 static struct hw_interrupt_type ioapic_level_type;
 715 static struct hw_interrupt_type ioapic_edge_type;
 716
 717 #define IOAPIC_AUTO     -1
 718 #define IOAPIC_EDGE     0
 719 #define IOAPIC_LEVEL    1
 720
 721 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 722 {
 723         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 724                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 725                                 trigger == IOAPIC_LEVEL)
 726                         irq_desc[vector].handler = &ioapic_level_type;
 727                 else
 728                         irq_desc[vector].handler = &ioapic_edge_type;
 729                 set_intr_gate(vector, interrupt[vector]);
 730         } else  {
 731                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 732                                 trigger == IOAPIC_LEVEL)
 733                         irq_desc[irq].handler = &ioapic_level_type;
 734                 else
 735                         irq_desc[irq].handler = &ioapic_edge_type;
 736                 set_intr_gate(vector, interrupt[irq]);
 737         }
 738 }
 739
 740 static void __init setup_IO_APIC_irqs(void)
 741 {
 742         struct IO_APIC_route_entry entry;
 743         int apic, pin, idx, irq, first_notcon = 1, vector;
 744         unsigned long flags;
 745
 746         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 747
 748         for (apic = 0; apic < nr_ioapics; apic++) {
 749         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 750
 751                 /*
 752                  * add it to the IO-APIC irq-routing table:
 753                  */
 754                 memset(&entry,0,sizeof(entry));
 755
 756                 entry.delivery_mode = INT_DELIVERY_MODE;
 757                 entry.dest_mode = INT_DEST_MODE;
 758                 entry.mask = 0;                         /* enable IRQ */
 759                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 760
 761                 idx = find_irq_entry(apic,pin,mp_INT);
 762                 if (idx == -1) {
 763                         if (first_notcon) {
 764                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 765                                 first_notcon = 0;
 766                         } else
 767                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 768                         continue;
 769                 }
 770
 771                 entry.trigger = irq_trigger(idx);
 772                 entry.polarity = irq_polarity(idx);
 773
 774                 if (irq_trigger(idx)) {
 775                         entry.trigger = 1;
 776                         entry.mask = 1;
 777                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 778                 }
 779
 780                 irq = pin_2_irq(idx, apic, pin);
 781                 add_pin_to_irq(irq, apic, pin);
 782
 783                 if (!apic && !IO_APIC_IRQ(irq))
 784                         continue;
 785
 786                 if (IO_APIC_IRQ(irq)) {
 787                         vector = assign_irq_vector(irq);
 788                         entry.vector = vector;
 789
 790                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 791                         if (!apic && (irq < 16))
 792                                 disable_8259A_irq(irq);
 793                 }
 794                 spin_lock_irqsave(&ioapic_lock, flags);
 795                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 796                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 797                 set_native_irq_info(irq, TARGET_CPUS);
 798                 spin_unlock_irqrestore(&ioapic_lock, flags);
 799         }
 800         }
 801
 802         if (!first_notcon)
 803                 apic_printk(APIC_VERBOSE," not connected.\n");
 804 }
 805
 806 /*
 807  * Set up the 8259A-master output pin as broadcast to all
 808  * CPUs.
 809  */
 810 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
 811 {
 812         struct IO_APIC_route_entry entry;
 813         unsigned long flags;
 814
 815         memset(&entry,0,sizeof(entry));
 816
 817         disable_8259A_irq(0);
 818
 819         /* mask LVT0 */
 820         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 821
 822         /*
 823          * We use logical delivery to get the timer IRQ
 824          * to the first CPU.
 825          */
 826         entry.dest_mode = INT_DEST_MODE;
 827         entry.mask = 0;                                 /* unmask IRQ now */
 828         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 829         entry.delivery_mode = INT_DELIVERY_MODE;
 830         entry.polarity = 0;
 831         entry.trigger = 0;
 832         entry.vector = vector;
 833
 834         /*
 835          * The timer IRQ doesn't have to know that behind the
 836          * scene we have a 8259A-master in AEOI mode ...
 837          */
 838         irq_desc[0].handler = &ioapic_edge_type;
 839
 840         /*
 841          * Add it to the IO-APIC irq-routing table:
 842          */
 843         spin_lock_irqsave(&ioapic_lock, flags);
 844         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
 845         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
 846         spin_unlock_irqrestore(&ioapic_lock, flags);
 847
 848         enable_8259A_irq(0);
 849 }
 850
 851 void __init UNEXPECTED_IO_APIC(void)
 852 {
 853 }
 854
 855 void __apicdebuginit print_IO_APIC(void)
 856 {
 857         int apic, i;
 858         union IO_APIC_reg_00 reg_00;
 859         union IO_APIC_reg_01 reg_01;
 860         union IO_APIC_reg_02 reg_02;
 861         unsigned long flags;
 862
 863         if (apic_verbosity == APIC_QUIET)
 864                 return;
 865
 866         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 867         for (i = 0; i < nr_ioapics; i++)
 868                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 869                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 870
 871         /*
 872          * We are a bit conservative about what we expect.  We have to
 873          * know about every hardware change ASAP.
 874          */
 875         printk(KERN_INFO "testing the IO APIC.......................\n");
 876
 877         for (apic = 0; apic < nr_ioapics; apic++) {
 878
 879         spin_lock_irqsave(&ioapic_lock, flags);
 880         reg_00.raw = io_apic_read(apic, 0);
 881         reg_01.raw = io_apic_read(apic, 1);
 882         if (reg_01.bits.version >= 0x10)
 883                 reg_02.raw = io_apic_read(apic, 2);
 884         spin_unlock_irqrestore(&ioapic_lock, flags);
 885
 886         printk("\n");
 887         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 888         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 889         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 890         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 891                 UNEXPECTED_IO_APIC();
 892
 893         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 894         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 895         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 896                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 897                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 898                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 899                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 900                 (reg_01.bits.entries != 0x2E) &&
 901                 (reg_01.bits.entries != 0x3F) &&
 902                 (reg_01.bits.entries != 0x03)
 903         )
 904                 UNEXPECTED_IO_APIC();
 905
 906         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 907         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 908         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 909                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 910                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 911                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 912                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 913                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 914         )
 915                 UNEXPECTED_IO_APIC();
 916         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 917                 UNEXPECTED_IO_APIC();
 918
 919         if (reg_01.bits.version >= 0x10) {
 920                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 921                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 922                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 923                         UNEXPECTED_IO_APIC();
 924         }
 925
 926         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 927
 928         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 929                           " Stat Dest Deli Vect:   \n");
 930
 931         for (i = 0; i <= reg_01.bits.entries; i++) {
 932                 struct IO_APIC_route_entry entry;
 933
 934                 spin_lock_irqsave(&ioapic_lock, flags);
 935                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
 936                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
 937                 spin_unlock_irqrestore(&ioapic_lock, flags);
 938
 939                 printk(KERN_DEBUG " %02x %03X %02X  ",
 940                         i,
 941                         entry.dest.logical.logical_dest,
 942                         entry.dest.physical.physical_dest
 943                 );
 944
 945                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 946                         entry.mask,
 947                         entry.trigger,
 948                         entry.irr,
 949                         entry.polarity,
 950                         entry.delivery_status,
 951                         entry.dest_mode,
 952                         entry.delivery_mode,
 953                         entry.vector
 954                 );
 955         }
 956         }
 957         if (use_pci_vector())
 958                 printk(KERN_INFO "Using vector-based indexing\n");
 959         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 960         for (i = 0; i < NR_IRQS; i++) {
 961                 struct irq_pin_list *entry = irq_2_pin + i;
 962                 if (entry->pin < 0)
 963                         continue;
 964                 if (use_pci_vector() && !platform_legacy_irq(i))
 965                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
 966                 else
 967                         printk(KERN_DEBUG "IRQ%d ", i);
 968                 for (;;) {
 969                         printk("-> %d:%d", entry->apic, entry->pin);
 970                         if (!entry->next)
 971                                 break;
 972                         entry = irq_2_pin + entry->next;
 973                 }
 974                 printk("\n");
 975         }
 976
 977         printk(KERN_INFO ".................................... done.\n");
 978
 979         return;
 980 }
 981
 982 #if 0
 983
 984 static __apicdebuginit void print_APIC_bitfield (int base)
 985 {
 986         unsigned int v;
 987         int i, j;
 988
 989         if (apic_verbosity == APIC_QUIET)
 990                 return;
 991
 992         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 993         for (i = 0; i < 8; i++) {
 994                 v = apic_read(base + i*0x10);
 995                 for (j = 0; j < 32; j++) {
 996                         if (v & (1<<j))
 997                                 printk("1");
 998                         else
 999                                 printk("0");
1000                 }
1001                 printk("\n");
1002         }
1003 }
1004
1005 void __apicdebuginit print_local_APIC(void * dummy)
1006 {
1007         unsigned int v, ver, maxlvt;
1008
1009         if (apic_verbosity == APIC_QUIET)
1010                 return;
1011
1012         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1013                 smp_processor_id(), hard_smp_processor_id());
1014         v = apic_read(APIC_ID);
1015         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1016         v = apic_read(APIC_LVR);
1017         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1018         ver = GET_APIC_VERSION(v);
1019         maxlvt = get_maxlvt();
1020
1021         v = apic_read(APIC_TASKPRI);
1022         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1023
1024         v = apic_read(APIC_ARBPRI);
1025         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1026                 v & APIC_ARBPRI_MASK);
1027         v = apic_read(APIC_PROCPRI);
1028         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1029
1030         v = apic_read(APIC_EOI);
1031         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1032         v = apic_read(APIC_RRR);
1033         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1034         v = apic_read(APIC_LDR);
1035         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1036         v = apic_read(APIC_DFR);
1037         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1038         v = apic_read(APIC_SPIV);
1039         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1040
1041         printk(KERN_DEBUG "... APIC ISR field:\n");
1042         print_APIC_bitfield(APIC_ISR);
1043         printk(KERN_DEBUG "... APIC TMR field:\n");
1044         print_APIC_bitfield(APIC_TMR);
1045         printk(KERN_DEBUG "... APIC IRR field:\n");
1046         print_APIC_bitfield(APIC_IRR);
1047
1048         v = apic_read(APIC_ESR);
1049         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1050
1051         v = apic_read(APIC_ICR);
1052         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1053         v = apic_read(APIC_ICR2);
1054         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1055
1056         v = apic_read(APIC_LVTT);
1057         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1058
1059         if (maxlvt > 3) {                       /* PC is LVT#4. */
1060                 v = apic_read(APIC_LVTPC);
1061                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1062         }
1063         v = apic_read(APIC_LVT0);
1064         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1065         v = apic_read(APIC_LVT1);
1066         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1067
1068         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1069                 v = apic_read(APIC_LVTERR);
1070                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1071         }
1072
1073         v = apic_read(APIC_TMICT);
1074         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1075         v = apic_read(APIC_TMCCT);
1076         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1077         v = apic_read(APIC_TDCR);
1078         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1079         printk("\n");
1080 }
1081
1082 void print_all_local_APICs (void)
1083 {
1084         on_each_cpu(print_local_APIC, NULL, 1, 1);
1085 }
1086
1087 void __apicdebuginit print_PIC(void)
1088 {
1089         unsigned int v;
1090         unsigned long flags;
1091
1092         if (apic_verbosity == APIC_QUIET)
1093                 return;
1094
1095         printk(KERN_DEBUG "\nprinting PIC contents\n");
1096
1097         spin_lock_irqsave(&i8259A_lock, flags);
1098
1099         v = inb(0xa1) << 8 | inb(0x21);
1100         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1101
1102         v = inb(0xa0) << 8 | inb(0x20);
1103         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1104
1105         outb(0x0b,0xa0);
1106         outb(0x0b,0x20);
1107         v = inb(0xa0) << 8 | inb(0x20);
1108         outb(0x0a,0xa0);
1109         outb(0x0a,0x20);
1110
1111         spin_unlock_irqrestore(&i8259A_lock, flags);
1112
1113         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1114
1115         v = inb(0x4d1) << 8 | inb(0x4d0);
1116         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1117 }
1118
1119 #endif  /*  0  */
1120
1121 static void __init enable_IO_APIC(void)
1122 {
1123         union IO_APIC_reg_01 reg_01;
1124         int i;
1125         unsigned long flags;
1126
1127         for (i = 0; i < PIN_MAP_SIZE; i++) {
1128                 irq_2_pin[i].pin = -1;
1129                 irq_2_pin[i].next = 0;
1130         }
1131         if (!pirqs_enabled)
1132                 for (i = 0; i < MAX_PIRQS; i++)
1133                         pirq_entries[i] = -1;
1134
1135         /*
1136          * The number of IO-APIC IRQ registers (== #pins):
1137          */
1138         for (i = 0; i < nr_ioapics; i++) {
1139                 spin_lock_irqsave(&ioapic_lock, flags);
1140                 reg_01.raw = io_apic_read(i, 1);
1141                 spin_unlock_irqrestore(&ioapic_lock, flags);
1142                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1143         }
1144
1145         /*
1146          * Do not trust the IO-APIC being empty at bootup
1147          */
1148         clear_IO_APIC();
1149 }
1150
1151 /*
1152  * Not an __init, needed by the reboot code
1153  */
1154 void disable_IO_APIC(void)
1155 {
1156         int pin;
1157         /*
1158          * Clear the IO-APIC before rebooting:
1159          */
1160         clear_IO_APIC();
1161
1162         /*
1163          * If the i8259 is routed through an IOAPIC
1164          * Put that IOAPIC in virtual wire mode
1165          * so legacy interrupts can be delivered.
1166          */
1167         pin = find_isa_irq_pin(0, mp_ExtINT);
1168         if (pin != -1) {
1169                 struct IO_APIC_route_entry entry;
1170                 unsigned long flags;
1171
1172                 memset(&entry, 0, sizeof(entry));
1173                 entry.mask            = 0; /* Enabled */
1174                 entry.trigger         = 0; /* Edge */
1175                 entry.irr             = 0;
1176                 entry.polarity        = 0; /* High */
1177                 entry.delivery_status = 0;
1178                 entry.dest_mode       = 0; /* Physical */
1179                 entry.delivery_mode   = 7; /* ExtInt */
1180                 entry.vector          = 0;
1181                 entry.dest.physical.physical_dest = 0;
1182
1183
1184                 /*
1185                  * Add it to the IO-APIC irq-routing table:
1186                  */
1187                 spin_lock_irqsave(&ioapic_lock, flags);
1188                 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1189                 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1190                 spin_unlock_irqrestore(&ioapic_lock, flags);
1191         }
1192
1193         disconnect_bsp_APIC(pin != -1);
1194 }
1195
1196 /*
1197  * function to set the IO-APIC physical IDs based on the
1198  * values stored in the MPC table.
1199  *
1200  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1201  */
1202
1203 static void __init setup_ioapic_ids_from_mpc (void)
1204 {
1205         union IO_APIC_reg_00 reg_00;
1206         int apic;
1207         int i;
1208         unsigned char old_id;
1209         unsigned long flags;
1210
1211         /*
1212          * Set the IOAPIC ID to the value stored in the MPC table.
1213          */
1214         for (apic = 0; apic < nr_ioapics; apic++) {
1215
1216                 /* Read the register 0 value */
1217                 spin_lock_irqsave(&ioapic_lock, flags);
1218                 reg_00.raw = io_apic_read(apic, 0);
1219                 spin_unlock_irqrestore(&ioapic_lock, flags);
1220
1221                 old_id = mp_ioapics[apic].mpc_apicid;
1222
1223
1224                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1225
1226
1227                 /*
1228                  * We need to adjust the IRQ routing table
1229                  * if the ID changed.
1230                  */
1231                 if (old_id != mp_ioapics[apic].mpc_apicid)
1232                         for (i = 0; i < mp_irq_entries; i++)
1233                                 if (mp_irqs[i].mpc_dstapic == old_id)
1234                                         mp_irqs[i].mpc_dstapic
1235                                                 = mp_ioapics[apic].mpc_apicid;
1236
1237                 /*
1238                  * Read the right value from the MPC table and
1239                  * write it into the ID register.
1240                  */
1241                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1242                                 mp_ioapics[apic].mpc_apicid);
1243
1244                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1245                 spin_lock_irqsave(&ioapic_lock, flags);
1246                 io_apic_write(apic, 0, reg_00.raw);
1247                 spin_unlock_irqrestore(&ioapic_lock, flags);
1248
1249                 /*
1250                  * Sanity check
1251                  */
1252                 spin_lock_irqsave(&ioapic_lock, flags);
1253                 reg_00.raw = io_apic_read(apic, 0);
1254                 spin_unlock_irqrestore(&ioapic_lock, flags);
1255                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1256                         printk("could not set ID!\n");
1257                 else
1258                         apic_printk(APIC_VERBOSE," ok.\n");
1259         }
1260 }
1261
1262 /*
1263  * There is a nasty bug in some older SMP boards, their mptable lies
1264  * about the timer IRQ. We do the following to work around the situation:
1265  *
1266  *      - timer IRQ defaults to IO-APIC IRQ
1267  *      - if this function detects that timer IRQs are defunct, then we fall
1268  *        back to ISA timer IRQs
1269  */
1270 static int __init timer_irq_works(void)
1271 {
1272         unsigned long t1 = jiffies;
1273
1274         local_irq_enable();
1275         /* Let ten ticks pass... */
1276         mdelay((10 * 1000) / HZ);
1277
1278         /*
1279          * Expect a few ticks at least, to be sure some possible
1280          * glue logic does not lock up after one or two first
1281          * ticks in a non-ExtINT mode.  Also the local APIC
1282          * might have cached one ExtINT interrupt.  Finally, at
1283          * least one tick may be lost due to delays.
1284          */
1285
1286         /* jiffies wrap? */
1287         if (jiffies - t1 > 4)
1288                 return 1;
1289         return 0;
1290 }
1291
1292 /*
1293  * In the SMP+IOAPIC case it might happen that there are an unspecified
1294  * number of pending IRQ events unhandled. These cases are very rare,
1295  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1296  * better to do it this way as thus we do not have to be aware of
1297  * 'pending' interrupts in the IRQ path, except at this point.
1298  */
1299 /*
1300  * Edge triggered needs to resend any interrupt
1301  * that was delayed but this is now handled in the device
1302  * independent code.
1303  */
1304
1305 /*
1306  * Starting up a edge-triggered IO-APIC interrupt is
1307  * nasty - we need to make sure that we get the edge.
1308  * If it is already asserted for some reason, we need
1309  * return 1 to indicate that is was pending.
1310  *
1311  * This is not complete - we should be able to fake
1312  * an edge even if it isn't on the 8259A...
1313  */
1314
1315 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1316 {
1317         int was_pending = 0;
1318         unsigned long flags;
1319
1320         spin_lock_irqsave(&ioapic_lock, flags);
1321         if (irq < 16) {
1322                 disable_8259A_irq(irq);
1323                 if (i8259A_irq_pending(irq))
1324                         was_pending = 1;
1325         }
1326         __unmask_IO_APIC_irq(irq);
1327         spin_unlock_irqrestore(&ioapic_lock, flags);
1328
1329         return was_pending;
1330 }
1331
1332 /*
1333  * Once we have recorded IRQ_PENDING already, we can mask the
1334  * interrupt for real. This prevents IRQ storms from unhandled
1335  * devices.
1336  */
1337 static void ack_edge_ioapic_irq(unsigned int irq)
1338 {
1339         move_irq(irq);
1340         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1341                                         == (IRQ_PENDING | IRQ_DISABLED))
1342                 mask_IO_APIC_irq(irq);
1343         ack_APIC_irq();
1344 }
1345
1346 /*
1347  * Level triggered interrupts can just be masked,
1348  * and shutting down and starting up the interrupt
1349  * is the same as enabling and disabling them -- except
1350  * with a startup need to return a "was pending" value.
1351  *
1352  * Level triggered interrupts are special because we
1353  * do not touch any IO-APIC register while handling
1354  * them. We ack the APIC in the end-IRQ handler, not
1355  * in the start-IRQ-handler. Protection against reentrance
1356  * from the same interrupt is still provided, both by the
1357  * generic IRQ layer and by the fact that an unacked local
1358  * APIC does not accept IRQs.
1359  */
1360 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1361 {
1362         unmask_IO_APIC_irq(irq);
1363
1364         return 0; /* don't check for pending */
1365 }
1366
1367 static void end_level_ioapic_irq (unsigned int irq)
1368 {
1369         move_irq(irq);
1370         ack_APIC_irq();
1371 }
1372
1373 #ifdef CONFIG_PCI_MSI
1374 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1375 {
1376         int irq = vector_to_irq(vector);
1377
1378         return startup_edge_ioapic_irq(irq);
1379 }
1380
1381 static void ack_edge_ioapic_vector(unsigned int vector)
1382 {
1383         int irq = vector_to_irq(vector);
1384
1385         move_native_irq(vector);
1386         ack_edge_ioapic_irq(irq);
1387 }
1388
1389 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1390 {
1391         int irq = vector_to_irq(vector);
1392
1393         return startup_level_ioapic_irq (irq);
1394 }
1395
1396 static void end_level_ioapic_vector (unsigned int vector)
1397 {
1398         int irq = vector_to_irq(vector);
1399
1400         move_native_irq(vector);
1401         end_level_ioapic_irq(irq);
1402 }
1403
1404 static void mask_IO_APIC_vector (unsigned int vector)
1405 {
1406         int irq = vector_to_irq(vector);
1407
1408         mask_IO_APIC_irq(irq);
1409 }
1410
1411 static void unmask_IO_APIC_vector (unsigned int vector)
1412 {
1413         int irq = vector_to_irq(vector);
1414
1415         unmask_IO_APIC_irq(irq);
1416 }
1417
1418 #ifdef CONFIG_SMP
1419 static void set_ioapic_affinity_vector (unsigned int vector,
1420                                         cpumask_t cpu_mask)
1421 {
1422         int irq = vector_to_irq(vector);
1423
1424         set_native_irq_info(vector, cpu_mask);
1425         set_ioapic_affinity_irq(irq, cpu_mask);
1426 }
1427 #endif // CONFIG_SMP
1428 #endif // CONFIG_PCI_MSI
1429
1430 /*
1431  * Level and edge triggered IO-APIC interrupts need different handling,
1432  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1433  * handled with the level-triggered descriptor, but that one has slightly
1434  * more overhead. Level-triggered interrupts cannot be handled with the
1435  * edge-triggered handler, without risking IRQ storms and other ugly
1436  * races.
1437  */
1438
1439 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1440         .typename = "IO-APIC-edge",
1441         .startup        = startup_edge_ioapic,
1442         .shutdown       = shutdown_edge_ioapic,
1443         .enable         = enable_edge_ioapic,
1444         .disable        = disable_edge_ioapic,
1445         .ack            = ack_edge_ioapic,
1446         .end            = end_edge_ioapic,
1447 #ifdef CONFIG_SMP
1448         .set_affinity = set_ioapic_affinity,
1449 #endif
1450 };
1451
1452 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1453         .typename = "IO-APIC-level",
1454         .startup        = startup_level_ioapic,
1455         .shutdown       = shutdown_level_ioapic,
1456         .enable         = enable_level_ioapic,
1457         .disable        = disable_level_ioapic,
1458         .ack            = mask_and_ack_level_ioapic,
1459         .end            = end_level_ioapic,
1460 #ifdef CONFIG_SMP
1461         .set_affinity = set_ioapic_affinity,
1462 #endif
1463 };
1464
1465 static inline void init_IO_APIC_traps(void)
1466 {
1467         int irq;
1468
1469         /*
1470          * NOTE! The local APIC isn't very good at handling
1471          * multiple interrupts at the same interrupt level.
1472          * As the interrupt level is determined by taking the
1473          * vector number and shifting that right by 4, we
1474          * want to spread these out a bit so that they don't
1475          * all fall in the same interrupt level.
1476          *
1477          * Also, we've got to be careful not to trash gate
1478          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1479          */
1480         for (irq = 0; irq < NR_IRQS ; irq++) {
1481                 int tmp = irq;
1482                 if (use_pci_vector()) {
1483                         if (!platform_legacy_irq(tmp))
1484                                 if ((tmp = vector_to_irq(tmp)) == -1)
1485                                         continue;
1486                 }
1487                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1488                         /*
1489                          * Hmm.. We don't have an entry for this,
1490                          * so default to an old-fashioned 8259
1491                          * interrupt if we can..
1492                          */
1493                         if (irq < 16)
1494                                 make_8259A_irq(irq);
1495                         else
1496                                 /* Strange. Oh, well.. */
1497                                 irq_desc[irq].handler = &no_irq_type;
1498                 }
1499         }
1500 }
1501
1502 static void enable_lapic_irq (unsigned int irq)
1503 {
1504         unsigned long v;
1505
1506         v = apic_read(APIC_LVT0);
1507         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1508 }
1509
1510 static void disable_lapic_irq (unsigned int irq)
1511 {
1512         unsigned long v;
1513
1514         v = apic_read(APIC_LVT0);
1515         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1516 }
1517
1518 static void ack_lapic_irq (unsigned int irq)
1519 {
1520         ack_APIC_irq();
1521 }
1522
1523 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1524
1525 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1526         .typename = "local-APIC-edge",
1527         .startup = NULL, /* startup_irq() not used for IRQ0 */
1528         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1529         .enable = enable_lapic_irq,
1530         .disable = disable_lapic_irq,
1531         .ack = ack_lapic_irq,
1532         .end = end_lapic_irq,
1533 };
1534
1535 static void setup_nmi (void)
1536 {
1537         /*
1538          * Dirty trick to enable the NMI watchdog ...
1539          * We put the 8259A master into AEOI mode and
1540          * unmask on all local APICs LVT0 as NMI.
1541          *
1542          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1543          * is from Maciej W. Rozycki - so we do not have to EOI from
1544          * the NMI handler or the timer interrupt.
1545          */
1546         printk(KERN_INFO "activating NMI Watchdog ...");
1547
1548         enable_NMI_through_LVT0(NULL);
1549
1550         printk(" done.\n");
1551 }
1552
1553 /*
1554  * This looks a bit hackish but it's about the only one way of sending
1555  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1556  * not support the ExtINT mode, unfortunately.  We need to send these
1557  * cycles as some i82489DX-based boards have glue logic that keeps the
1558  * 8259A interrupt line asserted until INTA.  --macro
1559  */
1560 static inline void unlock_ExtINT_logic(void)
1561 {
1562         int pin, i;
1563         struct IO_APIC_route_entry entry0, entry1;
1564         unsigned char save_control, save_freq_select;
1565         unsigned long flags;
1566
1567         pin = find_isa_irq_pin(8, mp_INT);
1568         if (pin == -1)
1569                 return;
1570
1571         spin_lock_irqsave(&ioapic_lock, flags);
1572         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1573         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1574         spin_unlock_irqrestore(&ioapic_lock, flags);
1575         clear_IO_APIC_pin(0, pin);
1576
1577         memset(&entry1, 0, sizeof(entry1));
1578
1579         entry1.dest_mode = 0;                   /* physical delivery */
1580         entry1.mask = 0;                        /* unmask IRQ now */
1581         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1582         entry1.delivery_mode = dest_ExtINT;
1583         entry1.polarity = entry0.polarity;
1584         entry1.trigger = 0;
1585         entry1.vector = 0;
1586
1587         spin_lock_irqsave(&ioapic_lock, flags);
1588         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1589         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1590         spin_unlock_irqrestore(&ioapic_lock, flags);
1591
1592         save_control = CMOS_READ(RTC_CONTROL);
1593         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1594         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1595                    RTC_FREQ_SELECT);
1596         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1597
1598         i = 100;
1599         while (i-- > 0) {
1600                 mdelay(10);
1601                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1602                         i -= 10;
1603         }
1604
1605         CMOS_WRITE(save_control, RTC_CONTROL);
1606         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1607         clear_IO_APIC_pin(0, pin);
1608
1609         spin_lock_irqsave(&ioapic_lock, flags);
1610         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1611         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1612         spin_unlock_irqrestore(&ioapic_lock, flags);
1613 }
1614
1615 /*
1616  * This code may look a bit paranoid, but it's supposed to cooperate with
1617  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1618  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1619  * fanatically on his truly buggy board.
1620  */
1621 static inline void check_timer(void)
1622 {
1623         int pin1, pin2;
1624         int vector;
1625
1626         /*
1627          * get/set the timer IRQ vector:
1628          */
1629         disable_8259A_irq(0);
1630         vector = assign_irq_vector(0);
1631         set_intr_gate(vector, interrupt[0]);
1632
1633         /*
1634          * Subtle, code in do_timer_interrupt() expects an AEOI
1635          * mode for the 8259A whenever interrupts are routed
1636          * through I/O APICs.  Also IRQ0 has to be enabled in
1637          * the 8259A which implies the virtual wire has to be
1638          * disabled in the local APIC.
1639          */
1640         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1641         init_8259A(1);
1642         enable_8259A_irq(0);
1643
1644         pin1 = find_isa_irq_pin(0, mp_INT);
1645         pin2 = find_isa_irq_pin(0, mp_ExtINT);
1646
1647         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1648
1649         if (pin1 != -1) {
1650                 /*
1651                  * Ok, does IRQ0 through the IOAPIC work?
1652                  */
1653                 unmask_IO_APIC_irq(0);
1654                 if (!no_timer_check && timer_irq_works()) {
1655                         nmi_watchdog_default();
1656                         if (nmi_watchdog == NMI_IO_APIC) {
1657                                 disable_8259A_irq(0);
1658                                 setup_nmi();
1659                                 enable_8259A_irq(0);
1660                         }
1661                         return;
1662                 }
1663                 clear_IO_APIC_pin(0, pin1);
1664                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1665         }
1666
1667         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1668         if (pin2 != -1) {
1669                 apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2);
1670                 /*
1671                  * legacy devices should be connected to IO APIC #0
1672                  */
1673                 setup_ExtINT_IRQ0_pin(pin2, vector);
1674                 if (timer_irq_works()) {
1675                         printk("works.\n");
1676                         nmi_watchdog_default();
1677                         if (nmi_watchdog == NMI_IO_APIC) {
1678                                 setup_nmi();
1679                         }
1680                         return;
1681                 }
1682                 /*
1683                  * Cleanup, just in case ...
1684                  */
1685                 clear_IO_APIC_pin(0, pin2);
1686         }
1687         printk(" failed.\n");
1688
1689         if (nmi_watchdog) {
1690                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1691                 nmi_watchdog = 0;
1692         }
1693
1694         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1695
1696         disable_8259A_irq(0);
1697         irq_desc[0].handler = &lapic_irq_type;
1698         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
1699         enable_8259A_irq(0);
1700
1701         if (timer_irq_works()) {
1702                 apic_printk(APIC_QUIET, " works.\n");
1703                 return;
1704         }
1705         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1706         apic_printk(APIC_VERBOSE," failed.\n");
1707
1708         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1709
1710         init_8259A(0);
1711         make_8259A_irq(0);
1712         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1713
1714         unlock_ExtINT_logic();
1715
1716         if (timer_irq_works()) {
1717                 apic_printk(APIC_VERBOSE," works.\n");
1718                 return;
1719         }
1720         apic_printk(APIC_VERBOSE," failed :(.\n");
1721         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1722 }
1723
1724 static int __init notimercheck(char *s)
1725 {
1726         no_timer_check = 1;
1727         return 1;
1728 }
1729 __setup("no_timer_check", notimercheck);
1730
1731 /*
1732  *
1733  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1734  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1735  *   Linux doesn't really care, as it's not actually used
1736  *   for any interrupt handling anyway.
1737  */
1738 #define PIC_IRQS        (1<<2)
1739
1740 void __init setup_IO_APIC(void)
1741 {
1742         enable_IO_APIC();
1743
1744         if (acpi_ioapic)
1745                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1746         else
1747                 io_apic_irqs = ~PIC_IRQS;
1748
1749         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1750
1751         /*
1752          * Set up the IO-APIC IRQ routing table.
1753          */
1754         if (!acpi_ioapic)
1755                 setup_ioapic_ids_from_mpc();
1756         sync_Arb_IDs();
1757         setup_IO_APIC_irqs();
1758         init_IO_APIC_traps();
1759         check_timer();
1760         if (!acpi_ioapic)
1761                 print_IO_APIC();
1762 }
1763
1764 struct sysfs_ioapic_data {
1765         struct sys_device dev;
1766         struct IO_APIC_route_entry entry[0];
1767 };
1768 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1769
1770 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1771 {
1772         struct IO_APIC_route_entry *entry;
1773         struct sysfs_ioapic_data *data;
1774         unsigned long flags;
1775         int i;
1776
1777         data = container_of(dev, struct sysfs_ioapic_data, dev);
1778         entry = data->entry;
1779         spin_lock_irqsave(&ioapic_lock, flags);
1780         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1781                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1782                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1783         }
1784         spin_unlock_irqrestore(&ioapic_lock, flags);
1785
1786         return 0;
1787 }
1788
1789 static int ioapic_resume(struct sys_device *dev)
1790 {
1791         struct IO_APIC_route_entry *entry;
1792         struct sysfs_ioapic_data *data;
1793         unsigned long flags;
1794         union IO_APIC_reg_00 reg_00;
1795         int i;
1796
1797         data = container_of(dev, struct sysfs_ioapic_data, dev);
1798         entry = data->entry;
1799
1800         spin_lock_irqsave(&ioapic_lock, flags);
1801         reg_00.raw = io_apic_read(dev->id, 0);
1802         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1803                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1804                 io_apic_write(dev->id, 0, reg_00.raw);
1805         }
1806         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1807                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1808                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1809         }
1810         spin_unlock_irqrestore(&ioapic_lock, flags);
1811
1812         return 0;
1813 }
1814
1815 static struct sysdev_class ioapic_sysdev_class = {
1816         set_kset_name("ioapic"),
1817         .suspend = ioapic_suspend,
1818         .resume = ioapic_resume,
1819 };
1820
1821 static int __init ioapic_init_sysfs(void)
1822 {
1823         struct sys_device * dev;
1824         int i, size, error = 0;
1825
1826         error = sysdev_class_register(&ioapic_sysdev_class);
1827         if (error)
1828                 return error;
1829
1830         for (i = 0; i < nr_ioapics; i++ ) {
1831                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1832                         * sizeof(struct IO_APIC_route_entry);
1833                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1834                 if (!mp_ioapic_data[i]) {
1835                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1836                         continue;
1837                 }
1838                 memset(mp_ioapic_data[i], 0, size);
1839                 dev = &mp_ioapic_data[i]->dev;
1840                 dev->id = i;
1841                 dev->cls = &ioapic_sysdev_class;
1842                 error = sysdev_register(dev);
1843                 if (error) {
1844                         kfree(mp_ioapic_data[i]);
1845                         mp_ioapic_data[i] = NULL;
1846                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1847                         continue;
1848                 }
1849         }
1850
1851         return 0;
1852 }
1853
1854 device_initcall(ioapic_init_sysfs);
1855
1856 /* --------------------------------------------------------------------------
1857                           ACPI-based IOAPIC Configuration
1858    -------------------------------------------------------------------------- */
1859
1860 #ifdef CONFIG_ACPI
1861
1862 #define IO_APIC_MAX_ID          0xFE
1863
1864 int __init io_apic_get_version (int ioapic)
1865 {
1866         union IO_APIC_reg_01    reg_01;
1867         unsigned long flags;
1868
1869         spin_lock_irqsave(&ioapic_lock, flags);
1870         reg_01.raw = io_apic_read(ioapic, 1);
1871         spin_unlock_irqrestore(&ioapic_lock, flags);
1872
1873         return reg_01.bits.version;
1874 }
1875
1876
1877 int __init io_apic_get_redir_entries (int ioapic)
1878 {
1879         union IO_APIC_reg_01    reg_01;
1880         unsigned long flags;
1881
1882         spin_lock_irqsave(&ioapic_lock, flags);
1883         reg_01.raw = io_apic_read(ioapic, 1);
1884         spin_unlock_irqrestore(&ioapic_lock, flags);
1885
1886         return reg_01.bits.entries;
1887 }
1888
1889
1890 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1891 {
1892         struct IO_APIC_route_entry entry;
1893         unsigned long flags;
1894
1895         if (!IO_APIC_IRQ(irq)) {
1896                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1897                         ioapic);
1898                 return -EINVAL;
1899         }
1900
1901         /*
1902          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1903          * Note that we mask (disable) IRQs now -- these get enabled when the
1904          * corresponding device driver registers for this IRQ.
1905          */
1906
1907         memset(&entry,0,sizeof(entry));
1908
1909         entry.delivery_mode = INT_DELIVERY_MODE;
1910         entry.dest_mode = INT_DEST_MODE;
1911         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1912         entry.trigger = edge_level;
1913         entry.polarity = active_high_low;
1914         entry.mask = 1;                                  /* Disabled (masked) */
1915
1916         /*
1917          * IRQs < 16 are already in the irq_2_pin[] map
1918          */
1919         if (irq >= 16)
1920                 add_pin_to_irq(irq, ioapic, pin);
1921
1922         entry.vector = assign_irq_vector(irq);
1923
1924         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1925                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1926                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1927                edge_level, active_high_low);
1928
1929         ioapic_register_intr(irq, entry.vector, edge_level);
1930
1931         if (!ioapic && (irq < 16))
1932                 disable_8259A_irq(irq);
1933
1934         spin_lock_irqsave(&ioapic_lock, flags);
1935         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1936         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1937         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
1938         spin_unlock_irqrestore(&ioapic_lock, flags);
1939
1940         return 0;
1941 }
1942
1943 #endif /* CONFIG_ACPI */
1944
1945
1946 /*
1947  * This function currently is only a helper for the i386 smp boot process where
1948  * we need to reprogram the ioredtbls to cater for the cpus which have come online
1949  * so mask in all cases should simply be TARGET_CPUS
1950  */
1951 #ifdef CONFIG_SMP
1952 void __init setup_ioapic_dest(void)
1953 {
1954         int pin, ioapic, irq, irq_entry;
1955
1956         if (skip_ioapic_setup == 1)
1957                 return;
1958
1959         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1960                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1961                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1962                         if (irq_entry == -1)
1963                                 continue;
1964                         irq = pin_2_irq(irq_entry, ioapic, pin);
1965                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
1966                 }
1967
1968         }
1969 }
1970 #endif