2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
13 #include <asm/processor.h>
14 #include <asm/tlbflush.h>
15 #include <asm/sections.h>
16 #include <asm/uaccess.h>
17 #include <asm/pgalloc.h>
20 * The current flushing context - we pass it instead of 5 arguments:
31 within(unsigned long addr, unsigned long start, unsigned long end)
33 return addr >= start && addr < end;
41 * clflush_cache_range - flush a cache range with clflush
42 * @addr: virtual start address
43 * @size: number of bytes to flush
45 * clflush is an unordered instruction which needs fencing with mfence
46 * to avoid ordering issues.
48 void clflush_cache_range(void *vaddr, unsigned int size)
50 void *vend = vaddr + size - 1;
54 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
57 * Flush any possible final partial cacheline:
64 static void __cpa_flush_all(void *arg)
66 unsigned long cache = (unsigned long)arg;
69 * Flush all to work around Errata in early athlons regarding
70 * large page flushing.
74 if (cache && boot_cpu_data.x86_model >= 4)
78 static void cpa_flush_all(unsigned long cache)
80 BUG_ON(irqs_disabled());
82 on_each_cpu(__cpa_flush_all, (void *) cache, 1, 1);
85 static void __cpa_flush_range(void *arg)
88 * We could optimize that further and do individual per page
89 * tlb invalidates for a low number of pages. Caveat: we must
90 * flush the high aliases on 64bit as well.
95 static void cpa_flush_range(unsigned long start, int numpages, int cache)
97 unsigned int i, level;
100 BUG_ON(irqs_disabled());
101 WARN_ON(PAGE_ALIGN(start) != start);
103 on_each_cpu(__cpa_flush_range, NULL, 1, 1);
109 * We only need to flush on one CPU,
110 * clflush is a MESI-coherent instruction that
111 * will cause all other CPUs to flush the same
114 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
115 pte_t *pte = lookup_address(addr, &level);
118 * Only flush present addresses:
120 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
121 clflush_cache_range((void *) addr, PAGE_SIZE);
125 #define HIGH_MAP_START __START_KERNEL_map
126 #define HIGH_MAP_END (__START_KERNEL_map + KERNEL_TEXT_SIZE)
130 * Converts a virtual address to a X86-64 highmap address
132 static unsigned long virt_to_highmap(void *address)
135 return __pa((unsigned long)address) + HIGH_MAP_START - phys_base;
137 return (unsigned long)address;
142 * Certain areas of memory on x86 require very specific protection flags,
143 * for example the BIOS area or kernel text. Callers don't always get this
144 * right (again, ioremap() on BIOS memory is not uncommon) so this function
145 * checks and fixes these known static required protection bits.
147 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address)
149 pgprot_t forbidden = __pgprot(0);
152 * The BIOS area between 640k and 1Mb needs to be executable for
153 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
155 if (within(__pa(address), BIOS_BEGIN, BIOS_END))
156 pgprot_val(forbidden) |= _PAGE_NX;
159 * The kernel text needs to be executable for obvious reasons
160 * Does not cover __inittext since that is gone later on
162 if (within(address, (unsigned long)_text, (unsigned long)_etext))
163 pgprot_val(forbidden) |= _PAGE_NX;
165 * Do the same for the x86-64 high kernel mapping
167 if (within(address, virt_to_highmap(_text), virt_to_highmap(_etext)))
168 pgprot_val(forbidden) |= _PAGE_NX;
171 #ifdef CONFIG_DEBUG_RODATA
172 /* The .rodata section needs to be read-only */
173 if (within(address, (unsigned long)__start_rodata,
174 (unsigned long)__end_rodata))
175 pgprot_val(forbidden) |= _PAGE_RW;
177 * Do the same for the x86-64 high kernel mapping
179 if (within(address, virt_to_highmap(__start_rodata),
180 virt_to_highmap(__end_rodata)))
181 pgprot_val(forbidden) |= _PAGE_RW;
184 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
190 * Lookup the page table entry for a virtual address. Return a pointer
191 * to the entry and the level of the mapping.
193 * Note: We return pud and pmd either when the entry is marked large
194 * or when the present bit is not set. Otherwise we would return a
195 * pointer to a nonexisting mapping.
197 pte_t *lookup_address(unsigned long address, int *level)
199 pgd_t *pgd = pgd_offset_k(address);
203 *level = PG_LEVEL_NONE;
208 pud = pud_offset(pgd, address);
212 *level = PG_LEVEL_1G;
213 if (pud_large(*pud) || !pud_present(*pud))
216 pmd = pmd_offset(pud, address);
220 *level = PG_LEVEL_2M;
221 if (pmd_large(*pmd) || !pmd_present(*pmd))
224 *level = PG_LEVEL_4K;
226 return pte_offset_kernel(pmd, address);
230 * Set the new pmd in all the pgds we know about:
232 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
235 set_pte_atomic(kpte, pte);
237 if (!SHARED_KERNEL_PMD) {
240 list_for_each_entry(page, &pgd_list, lru) {
245 pgd = (pgd_t *)page_address(page) + pgd_index(address);
246 pud = pud_offset(pgd, address);
247 pmd = pmd_offset(pud, address);
248 set_pte_atomic((pte_t *)pmd, pte);
255 try_preserve_large_page(pte_t *kpte, unsigned long address,
256 struct cpa_data *cpa)
258 unsigned long nextpage_addr, numpages, pmask, psize, flags;
259 pte_t new_pte, old_pte, *tmp;
260 pgprot_t old_prot, new_prot;
261 int level, do_split = 1;
264 * An Athlon 64 X2 showed hard hangs if we tried to preserve
265 * largepages and changed the PSE entry from RW to RO.
267 * As AMD CPUs have a long series of erratas in this area,
268 * (and none of the known ones seem to explain this hang),
269 * disable this code until the hang can be debugged:
271 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
274 spin_lock_irqsave(&pgd_lock, flags);
276 * Check for races, another CPU might have split this page
279 tmp = lookup_address(address, &level);
285 psize = PMD_PAGE_SIZE;
286 pmask = PMD_PAGE_MASK;
290 psize = PMD_PAGE_SIZE;
291 pmask = PMD_PAGE_MASK;
300 * Calculate the number of pages, which fit into this large
301 * page starting at address:
303 nextpage_addr = (address + psize) & pmask;
304 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
305 if (numpages < cpa->numpages)
306 cpa->numpages = numpages;
309 * We are safe now. Check whether the new pgprot is the same:
312 old_prot = new_prot = pte_pgprot(old_pte);
314 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
315 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
316 new_prot = static_protections(new_prot, address);
319 * If there are no changes, return. maxpages has been updated
322 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
328 * We need to change the attributes. Check, whether we can
329 * change the large page in one go. We request a split, when
330 * the address is not aligned and the number of pages is
331 * smaller than the number of pages in the large page. Note
332 * that we limited the number of possible pages already to
333 * the number of pages in the large page.
335 if (address == (nextpage_addr - psize) && cpa->numpages == numpages) {
337 * The address is aligned and the number of pages
338 * covers the full page.
340 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
341 __set_pmd_pte(kpte, address, new_pte);
347 spin_unlock_irqrestore(&pgd_lock, flags);
352 static int split_large_page(pte_t *kpte, unsigned long address)
354 unsigned long flags, pfn, pfninc = 1;
355 gfp_t gfp_flags = GFP_KERNEL;
356 unsigned int i, level;
361 #ifdef CONFIG_DEBUG_PAGEALLOC
362 gfp_flags = GFP_ATOMIC | __GFP_NOWARN;
364 base = alloc_pages(gfp_flags, 0);
368 spin_lock_irqsave(&pgd_lock, flags);
370 * Check for races, another CPU might have split this page
373 tmp = lookup_address(address, &level);
377 pbase = (pte_t *)page_address(base);
379 paravirt_alloc_pt(&init_mm, page_to_pfn(base));
381 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
384 if (level == PG_LEVEL_1G) {
385 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
386 pgprot_val(ref_prot) |= _PAGE_PSE;
391 * Get the target pfn from the original entry:
393 pfn = pte_pfn(*kpte);
394 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
395 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
398 * Install the new, split up pagetable. Important details here:
400 * On Intel the NX bit of all levels must be cleared to make a
401 * page executable. See section 4.13.2 of Intel 64 and IA-32
402 * Architectures Software Developer's Manual).
404 * Mark the entry present. The current mapping might be
405 * set to not present, which we preserved above.
407 ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte)));
408 pgprot_val(ref_prot) |= _PAGE_PRESENT;
409 __set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
413 spin_unlock_irqrestore(&pgd_lock, flags);
416 __free_pages(base, 0);
421 static int __change_page_attr(unsigned long address, struct cpa_data *cpa)
423 int level, do_split, err;
424 struct page *kpte_page;
428 kpte = lookup_address(address, &level);
432 kpte_page = virt_to_page(kpte);
433 BUG_ON(PageLRU(kpte_page));
434 BUG_ON(PageCompound(kpte_page));
436 if (level == PG_LEVEL_4K) {
437 pte_t new_pte, old_pte = *kpte;
438 pgprot_t new_prot = pte_pgprot(old_pte);
440 if(!pte_val(old_pte)) {
441 printk(KERN_WARNING "CPA: called for zero pte. "
442 "vaddr = %lx cpa->vaddr = %lx\n", address,
448 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
449 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
451 new_prot = static_protections(new_prot, address);
454 * We need to keep the pfn from the existing PTE,
455 * after all we're only going to change it's attributes
456 * not the memory it points to
458 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
461 * Do we really change anything ?
463 if (pte_val(old_pte) != pte_val(new_pte)) {
464 set_pte_atomic(kpte, new_pte);
472 * Check, whether we can keep the large page intact
473 * and just change the pte:
475 do_split = try_preserve_large_page(kpte, address, cpa);
477 * When the range fits into the existing large page,
478 * return. cp->numpages and cpa->tlbflush have been updated in
485 * We have to split the large page:
487 err = split_large_page(kpte, address);
497 * change_page_attr_addr - Change page table attributes in linear mapping
498 * @address: Virtual address in linear mapping.
499 * @prot: New page table attribute (PAGE_*)
501 * Change page attributes of a page in the direct mapping. This is a variant
502 * of change_page_attr() that also works on memory holes that do not have
503 * mem_map entry (pfn_valid() is false).
505 * See change_page_attr() documentation for more details.
507 * Modules and drivers should use the set_memory_* APIs instead.
509 static int change_page_attr_addr(struct cpa_data *cpa)
512 unsigned long address = cpa->vaddr;
515 unsigned long phys_addr = __pa(address);
518 * If we are inside the high mapped kernel range, then we
519 * fixup the low mapping first. __va() returns the virtual
520 * address in the linear mapping:
522 if (within(address, HIGH_MAP_START, HIGH_MAP_END))
523 address = (unsigned long) __va(phys_addr);
526 err = __change_page_attr(address, cpa);
532 * If the physical address is inside the kernel map, we need
533 * to touch the high mapped kernel as well:
535 if (within(phys_addr, 0, KERNEL_TEXT_SIZE)) {
537 * Calc the high mapping address. See __phys_addr()
538 * for the non obvious details.
540 * Note that NX and other required permissions are
541 * checked in static_protections().
543 address = phys_addr + HIGH_MAP_START - phys_base;
546 * Our high aliases are imprecise, because we check
547 * everything between 0 and KERNEL_TEXT_SIZE, so do
548 * not propagate lookup failures back to users:
550 __change_page_attr(address, cpa);
556 static int __change_page_attr_set_clr(struct cpa_data *cpa)
558 int ret, numpages = cpa->numpages;
562 * Store the remaining nr of pages for the large page
563 * preservation check.
565 cpa->numpages = numpages;
566 ret = change_page_attr_addr(cpa);
571 * Adjust the number of pages with the result of the
572 * CPA operation. Either a large page has been
573 * preserved or a single page update happened.
575 BUG_ON(cpa->numpages > numpages);
576 numpages -= cpa->numpages;
577 cpa->vaddr += cpa->numpages * PAGE_SIZE;
582 static inline int cache_attr(pgprot_t attr)
584 return pgprot_val(attr) &
585 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
588 static int change_page_attr_set_clr(unsigned long addr, int numpages,
589 pgprot_t mask_set, pgprot_t mask_clr)
595 * Check, if we are requested to change a not supported
598 mask_set = canon_pgprot(mask_set);
599 mask_clr = canon_pgprot(mask_clr);
600 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr))
604 cpa.numpages = numpages;
605 cpa.mask_set = mask_set;
606 cpa.mask_clr = mask_clr;
609 ret = __change_page_attr_set_clr(&cpa);
612 * Check whether we really changed something:
618 * No need to flush, when we did not set any of the caching
621 cache = cache_attr(mask_set);
624 * On success we use clflush, when the CPU supports it to
625 * avoid the wbindv. If the CPU does not support it and in the
626 * error case we fall back to cpa_flush_all (which uses
629 if (!ret && cpu_has_clflush)
630 cpa_flush_range(addr, numpages, cache);
632 cpa_flush_all(cache);
637 static inline int change_page_attr_set(unsigned long addr, int numpages,
640 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
643 static inline int change_page_attr_clear(unsigned long addr, int numpages,
646 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);
649 int set_memory_uc(unsigned long addr, int numpages)
651 return change_page_attr_set(addr, numpages,
652 __pgprot(_PAGE_PCD | _PAGE_PWT));
654 EXPORT_SYMBOL(set_memory_uc);
656 int set_memory_wb(unsigned long addr, int numpages)
658 return change_page_attr_clear(addr, numpages,
659 __pgprot(_PAGE_PCD | _PAGE_PWT));
661 EXPORT_SYMBOL(set_memory_wb);
663 int set_memory_x(unsigned long addr, int numpages)
665 return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_NX));
667 EXPORT_SYMBOL(set_memory_x);
669 int set_memory_nx(unsigned long addr, int numpages)
671 return change_page_attr_set(addr, numpages, __pgprot(_PAGE_NX));
673 EXPORT_SYMBOL(set_memory_nx);
675 int set_memory_ro(unsigned long addr, int numpages)
677 return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_RW));
680 int set_memory_rw(unsigned long addr, int numpages)
682 return change_page_attr_set(addr, numpages, __pgprot(_PAGE_RW));
685 int set_memory_np(unsigned long addr, int numpages)
687 return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_PRESENT));
690 int set_pages_uc(struct page *page, int numpages)
692 unsigned long addr = (unsigned long)page_address(page);
694 return set_memory_uc(addr, numpages);
696 EXPORT_SYMBOL(set_pages_uc);
698 int set_pages_wb(struct page *page, int numpages)
700 unsigned long addr = (unsigned long)page_address(page);
702 return set_memory_wb(addr, numpages);
704 EXPORT_SYMBOL(set_pages_wb);
706 int set_pages_x(struct page *page, int numpages)
708 unsigned long addr = (unsigned long)page_address(page);
710 return set_memory_x(addr, numpages);
712 EXPORT_SYMBOL(set_pages_x);
714 int set_pages_nx(struct page *page, int numpages)
716 unsigned long addr = (unsigned long)page_address(page);
718 return set_memory_nx(addr, numpages);
720 EXPORT_SYMBOL(set_pages_nx);
722 int set_pages_ro(struct page *page, int numpages)
724 unsigned long addr = (unsigned long)page_address(page);
726 return set_memory_ro(addr, numpages);
729 int set_pages_rw(struct page *page, int numpages)
731 unsigned long addr = (unsigned long)page_address(page);
733 return set_memory_rw(addr, numpages);
736 #ifdef CONFIG_DEBUG_PAGEALLOC
738 static int __set_pages_p(struct page *page, int numpages)
740 struct cpa_data cpa = { .vaddr = (unsigned long) page_address(page),
741 .numpages = numpages,
742 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
743 .mask_clr = __pgprot(0)};
745 return __change_page_attr_set_clr(&cpa);
748 static int __set_pages_np(struct page *page, int numpages)
750 struct cpa_data cpa = { .vaddr = (unsigned long) page_address(page),
751 .numpages = numpages,
752 .mask_set = __pgprot(0),
753 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW)};
755 return __change_page_attr_set_clr(&cpa);
758 void kernel_map_pages(struct page *page, int numpages, int enable)
760 if (PageHighMem(page))
763 debug_check_no_locks_freed(page_address(page),
764 numpages * PAGE_SIZE);
768 * If page allocator is not up yet then do not call c_p_a():
770 if (!debug_pagealloc_enabled)
774 * The return value is ignored - the calls cannot fail,
775 * large pages are disabled at boot time:
778 __set_pages_p(page, numpages);
780 __set_pages_np(page, numpages);
783 * We should perform an IPI and flush all tlbs,
784 * but that can deadlock->flush only current cpu:
791 * The testcases use internal knowledge of the implementation that shouldn't
792 * be exposed to the rest of the kernel. Include these directly here.
794 #ifdef CONFIG_CPA_DEBUG
795 #include "pageattr-test.c"