arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "vmx.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 static int bypass_guest_pf = 1;
  41 module_param(bypass_guest_pf, bool, 0);
  42
  43 static int enable_vpid = 1;
  44 module_param(enable_vpid, bool, 0);
  45
  46 static int flexpriority_enabled = 1;
  47 module_param(flexpriority_enabled, bool, 0);
  48
  49 static int enable_ept = 1;
  50 module_param(enable_ept, bool, 0);
  51
  52 static int emulate_invalid_guest_state = 0;
  53 module_param(emulate_invalid_guest_state, bool, 0);
  54
  55 struct vmcs {
  56         u32 revision_id;
  57         u32 abort;
  58         char data[0];
  59 };
  60
  61 struct vcpu_vmx {
  62         struct kvm_vcpu       vcpu;
  63         struct list_head      local_vcpus_link;
  64         unsigned long         host_rsp;
  65         int                   launched;
  66         u8                    fail;
  67         u32                   idt_vectoring_info;
  68         struct kvm_msr_entry *guest_msrs;
  69         struct kvm_msr_entry *host_msrs;
  70         int                   nmsrs;
  71         int                   save_nmsrs;
  72         int                   msr_offset_efer;
  73 #ifdef CONFIG_X86_64
  74         int                   msr_offset_kernel_gs_base;
  75 #endif
  76         struct vmcs          *vmcs;
  77         struct {
  78                 int           loaded;
  79                 u16           fs_sel, gs_sel, ldt_sel;
  80                 int           gs_ldt_reload_needed;
  81                 int           fs_reload_needed;
  82                 int           guest_efer_loaded;
  83         } host_state;
  84         struct {
  85                 struct {
  86                         bool pending;
  87                         u8 vector;
  88                         unsigned rip;
  89                 } irq;
  90         } rmode;
  91         int vpid;
  92         bool emulation_required;
  93 };
  94
  95 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  96 {
  97         return container_of(vcpu, struct vcpu_vmx, vcpu);
  98 }
  99
 100 static int init_rmode(struct kvm *kvm);
 101 static u64 construct_eptp(unsigned long root_hpa);
 102
 103 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 104 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 105 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 106
 107 static struct page *vmx_io_bitmap_a;
 108 static struct page *vmx_io_bitmap_b;
 109 static struct page *vmx_msr_bitmap;
 110
 111 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 112 static DEFINE_SPINLOCK(vmx_vpid_lock);
 113
 114 static struct vmcs_config {
 115         int size;
 116         int order;
 117         u32 revision_id;
 118         u32 pin_based_exec_ctrl;
 119         u32 cpu_based_exec_ctrl;
 120         u32 cpu_based_2nd_exec_ctrl;
 121         u32 vmexit_ctrl;
 122         u32 vmentry_ctrl;
 123 } vmcs_config;
 124
 125 struct vmx_capability {
 126         u32 ept;
 127         u32 vpid;
 128 } vmx_capability;
 129
 130 #define VMX_SEGMENT_FIELD(seg)                                  \
 131         [VCPU_SREG_##seg] = {                                   \
 132                 .selector = GUEST_##seg##_SELECTOR,             \
 133                 .base = GUEST_##seg##_BASE,                     \
 134                 .limit = GUEST_##seg##_LIMIT,                   \
 135                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 136         }
 137
 138 static struct kvm_vmx_segment_field {
 139         unsigned selector;
 140         unsigned base;
 141         unsigned limit;
 142         unsigned ar_bytes;
 143 } kvm_vmx_segment_fields[] = {
 144         VMX_SEGMENT_FIELD(CS),
 145         VMX_SEGMENT_FIELD(DS),
 146         VMX_SEGMENT_FIELD(ES),
 147         VMX_SEGMENT_FIELD(FS),
 148         VMX_SEGMENT_FIELD(GS),
 149         VMX_SEGMENT_FIELD(SS),
 150         VMX_SEGMENT_FIELD(TR),
 151         VMX_SEGMENT_FIELD(LDTR),
 152 };
 153
 154 /*
 155  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 156  * away by decrementing the array size.
 157  */
 158 static const u32 vmx_msr_index[] = {
 159 #ifdef CONFIG_X86_64
 160         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 161 #endif
 162         MSR_EFER, MSR_K6_STAR,
 163 };
 164 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 165
 166 static void load_msrs(struct kvm_msr_entry *e, int n)
 167 {
 168         int i;
 169
 170         for (i = 0; i < n; ++i)
 171                 wrmsrl(e[i].index, e[i].data);
 172 }
 173
 174 static void save_msrs(struct kvm_msr_entry *e, int n)
 175 {
 176         int i;
 177
 178         for (i = 0; i < n; ++i)
 179                 rdmsrl(e[i].index, e[i].data);
 180 }
 181
 182 static inline int is_page_fault(u32 intr_info)
 183 {
 184         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 185                              INTR_INFO_VALID_MASK)) ==
 186                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 187 }
 188
 189 static inline int is_no_device(u32 intr_info)
 190 {
 191         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 192                              INTR_INFO_VALID_MASK)) ==
 193                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 194 }
 195
 196 static inline int is_invalid_opcode(u32 intr_info)
 197 {
 198         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 199                              INTR_INFO_VALID_MASK)) ==
 200                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 201 }
 202
 203 static inline int is_external_interrupt(u32 intr_info)
 204 {
 205         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 206                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 207 }
 208
 209 static inline int cpu_has_vmx_msr_bitmap(void)
 210 {
 211         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
 212 }
 213
 214 static inline int cpu_has_vmx_tpr_shadow(void)
 215 {
 216         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 217 }
 218
 219 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 220 {
 221         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 222 }
 223
 224 static inline int cpu_has_secondary_exec_ctrls(void)
 225 {
 226         return (vmcs_config.cpu_based_exec_ctrl &
 227                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 228 }
 229
 230 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 231 {
 232         return flexpriority_enabled
 233                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 234                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 235 }
 236
 237 static inline int cpu_has_vmx_invept_individual_addr(void)
 238 {
 239         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
 240 }
 241
 242 static inline int cpu_has_vmx_invept_context(void)
 243 {
 244         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
 245 }
 246
 247 static inline int cpu_has_vmx_invept_global(void)
 248 {
 249         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
 250 }
 251
 252 static inline int cpu_has_vmx_ept(void)
 253 {
 254         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 255                 SECONDARY_EXEC_ENABLE_EPT);
 256 }
 257
 258 static inline int vm_need_ept(void)
 259 {
 260         return (cpu_has_vmx_ept() && enable_ept);
 261 }
 262
 263 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 264 {
 265         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 266                 (irqchip_in_kernel(kvm)));
 267 }
 268
 269 static inline int cpu_has_vmx_vpid(void)
 270 {
 271         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 272                 SECONDARY_EXEC_ENABLE_VPID);
 273 }
 274
 275 static inline int cpu_has_virtual_nmis(void)
 276 {
 277         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 278 }
 279
 280 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 281 {
 282         int i;
 283
 284         for (i = 0; i < vmx->nmsrs; ++i)
 285                 if (vmx->guest_msrs[i].index == msr)
 286                         return i;
 287         return -1;
 288 }
 289
 290 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 291 {
 292     struct {
 293         u64 vpid : 16;
 294         u64 rsvd : 48;
 295         u64 gva;
 296     } operand = { vpid, 0, gva };
 297
 298     asm volatile (__ex(ASM_VMX_INVVPID)
 299                   /* CF==1 or ZF==1 --> rc = -1 */
 300                   "; ja 1f ; ud2 ; 1:"
 301                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 302 }
 303
 304 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 305 {
 306         struct {
 307                 u64 eptp, gpa;
 308         } operand = {eptp, gpa};
 309
 310         asm volatile (__ex(ASM_VMX_INVEPT)
 311                         /* CF==1 or ZF==1 --> rc = -1 */
 312                         "; ja 1f ; ud2 ; 1:\n"
 313                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 314 }
 315
 316 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 317 {
 318         int i;
 319
 320         i = __find_msr_index(vmx, msr);
 321         if (i >= 0)
 322                 return &vmx->guest_msrs[i];
 323         return NULL;
 324 }
 325
 326 static void vmcs_clear(struct vmcs *vmcs)
 327 {
 328         u64 phys_addr = __pa(vmcs);
 329         u8 error;
 330
 331         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 332                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 333                       : "cc", "memory");
 334         if (error)
 335                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 336                        vmcs, phys_addr);
 337 }
 338
 339 static void __vcpu_clear(void *arg)
 340 {
 341         struct vcpu_vmx *vmx = arg;
 342         int cpu = raw_smp_processor_id();
 343
 344         if (vmx->vcpu.cpu == cpu)
 345                 vmcs_clear(vmx->vmcs);
 346         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 347                 per_cpu(current_vmcs, cpu) = NULL;
 348         rdtscll(vmx->vcpu.arch.host_tsc);
 349         list_del(&vmx->local_vcpus_link);
 350         vmx->vcpu.cpu = -1;
 351         vmx->launched = 0;
 352 }
 353
 354 static void vcpu_clear(struct vcpu_vmx *vmx)
 355 {
 356         if (vmx->vcpu.cpu == -1)
 357                 return;
 358         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 359 }
 360
 361 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 362 {
 363         if (vmx->vpid == 0)
 364                 return;
 365
 366         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 367 }
 368
 369 static inline void ept_sync_global(void)
 370 {
 371         if (cpu_has_vmx_invept_global())
 372                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 373 }
 374
 375 static inline void ept_sync_context(u64 eptp)
 376 {
 377         if (vm_need_ept()) {
 378                 if (cpu_has_vmx_invept_context())
 379                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 380                 else
 381                         ept_sync_global();
 382         }
 383 }
 384
 385 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 386 {
 387         if (vm_need_ept()) {
 388                 if (cpu_has_vmx_invept_individual_addr())
 389                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 390                                         eptp, gpa);
 391                 else
 392                         ept_sync_context(eptp);
 393         }
 394 }
 395
 396 static unsigned long vmcs_readl(unsigned long field)
 397 {
 398         unsigned long value;
 399
 400         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 401                       : "=a"(value) : "d"(field) : "cc");
 402         return value;
 403 }
 404
 405 static u16 vmcs_read16(unsigned long field)
 406 {
 407         return vmcs_readl(field);
 408 }
 409
 410 static u32 vmcs_read32(unsigned long field)
 411 {
 412         return vmcs_readl(field);
 413 }
 414
 415 static u64 vmcs_read64(unsigned long field)
 416 {
 417 #ifdef CONFIG_X86_64
 418         return vmcs_readl(field);
 419 #else
 420         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 421 #endif
 422 }
 423
 424 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 425 {
 426         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 427                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 428         dump_stack();
 429 }
 430
 431 static void vmcs_writel(unsigned long field, unsigned long value)
 432 {
 433         u8 error;
 434
 435         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 436                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 437         if (unlikely(error))
 438                 vmwrite_error(field, value);
 439 }
 440
 441 static void vmcs_write16(unsigned long field, u16 value)
 442 {
 443         vmcs_writel(field, value);
 444 }
 445
 446 static void vmcs_write32(unsigned long field, u32 value)
 447 {
 448         vmcs_writel(field, value);
 449 }
 450
 451 static void vmcs_write64(unsigned long field, u64 value)
 452 {
 453         vmcs_writel(field, value);
 454 #ifndef CONFIG_X86_64
 455         asm volatile ("");
 456         vmcs_writel(field+1, value >> 32);
 457 #endif
 458 }
 459
 460 static void vmcs_clear_bits(unsigned long field, u32 mask)
 461 {
 462         vmcs_writel(field, vmcs_readl(field) & ~mask);
 463 }
 464
 465 static void vmcs_set_bits(unsigned long field, u32 mask)
 466 {
 467         vmcs_writel(field, vmcs_readl(field) | mask);
 468 }
 469
 470 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 471 {
 472         u32 eb;
 473
 474         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 475         if (!vcpu->fpu_active)
 476                 eb |= 1u << NM_VECTOR;
 477         if (vcpu->guest_debug.enabled)
 478                 eb |= 1u << DB_VECTOR;
 479         if (vcpu->arch.rmode.active)
 480                 eb = ~0;
 481         if (vm_need_ept())
 482                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 483         vmcs_write32(EXCEPTION_BITMAP, eb);
 484 }
 485
 486 static void reload_tss(void)
 487 {
 488         /*
 489          * VT restores TR but not its size.  Useless.
 490          */
 491         struct descriptor_table gdt;
 492         struct desc_struct *descs;
 493
 494         kvm_get_gdt(&gdt);
 495         descs = (void *)gdt.base;
 496         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 497         load_TR_desc();
 498 }
 499
 500 static void load_transition_efer(struct vcpu_vmx *vmx)
 501 {
 502         int efer_offset = vmx->msr_offset_efer;
 503         u64 host_efer = vmx->host_msrs[efer_offset].data;
 504         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 505         u64 ignore_bits;
 506
 507         if (efer_offset < 0)
 508                 return;
 509         /*
 510          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 511          * outside long mode
 512          */
 513         ignore_bits = EFER_NX | EFER_SCE;
 514 #ifdef CONFIG_X86_64
 515         ignore_bits |= EFER_LMA | EFER_LME;
 516         /* SCE is meaningful only in long mode on Intel */
 517         if (guest_efer & EFER_LMA)
 518                 ignore_bits &= ~(u64)EFER_SCE;
 519 #endif
 520         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 521                 return;
 522
 523         vmx->host_state.guest_efer_loaded = 1;
 524         guest_efer &= ~ignore_bits;
 525         guest_efer |= host_efer & ignore_bits;
 526         wrmsrl(MSR_EFER, guest_efer);
 527         vmx->vcpu.stat.efer_reload++;
 528 }
 529
 530 static void reload_host_efer(struct vcpu_vmx *vmx)
 531 {
 532         if (vmx->host_state.guest_efer_loaded) {
 533                 vmx->host_state.guest_efer_loaded = 0;
 534                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 535         }
 536 }
 537
 538 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 539 {
 540         struct vcpu_vmx *vmx = to_vmx(vcpu);
 541
 542         if (vmx->host_state.loaded)
 543                 return;
 544
 545         vmx->host_state.loaded = 1;
 546         /*
 547          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 548          * allow segment selectors with cpl > 0 or ti == 1.
 549          */
 550         vmx->host_state.ldt_sel = kvm_read_ldt();
 551         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 552         vmx->host_state.fs_sel = kvm_read_fs();
 553         if (!(vmx->host_state.fs_sel & 7)) {
 554                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 555                 vmx->host_state.fs_reload_needed = 0;
 556         } else {
 557                 vmcs_write16(HOST_FS_SELECTOR, 0);
 558                 vmx->host_state.fs_reload_needed = 1;
 559         }
 560         vmx->host_state.gs_sel = kvm_read_gs();
 561         if (!(vmx->host_state.gs_sel & 7))
 562                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 563         else {
 564                 vmcs_write16(HOST_GS_SELECTOR, 0);
 565                 vmx->host_state.gs_ldt_reload_needed = 1;
 566         }
 567
 568 #ifdef CONFIG_X86_64
 569         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 570         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 571 #else
 572         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 573         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 574 #endif
 575
 576 #ifdef CONFIG_X86_64
 577         if (is_long_mode(&vmx->vcpu))
 578                 save_msrs(vmx->host_msrs +
 579                           vmx->msr_offset_kernel_gs_base, 1);
 580
 581 #endif
 582         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 583         load_transition_efer(vmx);
 584 }
 585
 586 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 587 {
 588         unsigned long flags;
 589
 590         if (!vmx->host_state.loaded)
 591                 return;
 592
 593         ++vmx->vcpu.stat.host_state_reload;
 594         vmx->host_state.loaded = 0;
 595         if (vmx->host_state.fs_reload_needed)
 596                 kvm_load_fs(vmx->host_state.fs_sel);
 597         if (vmx->host_state.gs_ldt_reload_needed) {
 598                 kvm_load_ldt(vmx->host_state.ldt_sel);
 599                 /*
 600                  * If we have to reload gs, we must take care to
 601                  * preserve our gs base.
 602                  */
 603                 local_irq_save(flags);
 604                 kvm_load_gs(vmx->host_state.gs_sel);
 605 #ifdef CONFIG_X86_64
 606                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 607 #endif
 608                 local_irq_restore(flags);
 609         }
 610         reload_tss();
 611         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 612         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 613         reload_host_efer(vmx);
 614 }
 615
 616 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 617 {
 618         preempt_disable();
 619         __vmx_load_host_state(vmx);
 620         preempt_enable();
 621 }
 622
 623 /*
 624  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 625  * vcpu mutex is already taken.
 626  */
 627 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 628 {
 629         struct vcpu_vmx *vmx = to_vmx(vcpu);
 630         u64 phys_addr = __pa(vmx->vmcs);
 631         u64 tsc_this, delta, new_offset;
 632
 633         if (vcpu->cpu != cpu) {
 634                 vcpu_clear(vmx);
 635                 kvm_migrate_timers(vcpu);
 636                 vpid_sync_vcpu_all(vmx);
 637                 local_irq_disable();
 638                 list_add(&vmx->local_vcpus_link,
 639                          &per_cpu(vcpus_on_cpu, cpu));
 640                 local_irq_enable();
 641         }
 642
 643         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 644                 u8 error;
 645
 646                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 647                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 648                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 649                               : "cc");
 650                 if (error)
 651                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 652                                vmx->vmcs, phys_addr);
 653         }
 654
 655         if (vcpu->cpu != cpu) {
 656                 struct descriptor_table dt;
 657                 unsigned long sysenter_esp;
 658
 659                 vcpu->cpu = cpu;
 660                 /*
 661                  * Linux uses per-cpu TSS and GDT, so set these when switching
 662                  * processors.
 663                  */
 664                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 665                 kvm_get_gdt(&dt);
 666                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 667
 668                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 669                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 670
 671                 /*
 672                  * Make sure the time stamp counter is monotonous.
 673                  */
 674                 rdtscll(tsc_this);
 675                 if (tsc_this < vcpu->arch.host_tsc) {
 676                         delta = vcpu->arch.host_tsc - tsc_this;
 677                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 678                         vmcs_write64(TSC_OFFSET, new_offset);
 679                 }
 680         }
 681 }
 682
 683 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 684 {
 685         __vmx_load_host_state(to_vmx(vcpu));
 686 }
 687
 688 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 689 {
 690         if (vcpu->fpu_active)
 691                 return;
 692         vcpu->fpu_active = 1;
 693         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 694         if (vcpu->arch.cr0 & X86_CR0_TS)
 695                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 696         update_exception_bitmap(vcpu);
 697 }
 698
 699 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 700 {
 701         if (!vcpu->fpu_active)
 702                 return;
 703         vcpu->fpu_active = 0;
 704         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 705         update_exception_bitmap(vcpu);
 706 }
 707
 708 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 709 {
 710         return vmcs_readl(GUEST_RFLAGS);
 711 }
 712
 713 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 714 {
 715         if (vcpu->arch.rmode.active)
 716                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 717         vmcs_writel(GUEST_RFLAGS, rflags);
 718 }
 719
 720 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 721 {
 722         unsigned long rip;
 723         u32 interruptibility;
 724
 725         rip = kvm_rip_read(vcpu);
 726         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 727         kvm_rip_write(vcpu, rip);
 728
 729         /*
 730          * We emulated an instruction, so temporary interrupt blocking
 731          * should be removed, if set.
 732          */
 733         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 734         if (interruptibility & 3)
 735                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 736                              interruptibility & ~3);
 737         vcpu->arch.interrupt_window_open = 1;
 738 }
 739
 740 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 741                                 bool has_error_code, u32 error_code)
 742 {
 743         struct vcpu_vmx *vmx = to_vmx(vcpu);
 744
 745         if (has_error_code)
 746                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 747
 748         if (vcpu->arch.rmode.active) {
 749                 vmx->rmode.irq.pending = true;
 750                 vmx->rmode.irq.vector = nr;
 751                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 752                 if (nr == BP_VECTOR)
 753                         vmx->rmode.irq.rip++;
 754                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 755                              nr | INTR_TYPE_SOFT_INTR
 756                              | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
 757                              | INTR_INFO_VALID_MASK);
 758                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 759                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 760                 return;
 761         }
 762
 763         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 764                      nr | INTR_TYPE_EXCEPTION
 765                      | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
 766                      | INTR_INFO_VALID_MASK);
 767 }
 768
 769 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 770 {
 771         return false;
 772 }
 773
 774 /*
 775  * Swap MSR entry in host/guest MSR entry array.
 776  */
 777 #ifdef CONFIG_X86_64
 778 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 779 {
 780         struct kvm_msr_entry tmp;
 781
 782         tmp = vmx->guest_msrs[to];
 783         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 784         vmx->guest_msrs[from] = tmp;
 785         tmp = vmx->host_msrs[to];
 786         vmx->host_msrs[to] = vmx->host_msrs[from];
 787         vmx->host_msrs[from] = tmp;
 788 }
 789 #endif
 790
 791 /*
 792  * Set up the vmcs to automatically save and restore system
 793  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 794  * mode, as fiddling with msrs is very expensive.
 795  */
 796 static void setup_msrs(struct vcpu_vmx *vmx)
 797 {
 798         int save_nmsrs;
 799
 800         vmx_load_host_state(vmx);
 801         save_nmsrs = 0;
 802 #ifdef CONFIG_X86_64
 803         if (is_long_mode(&vmx->vcpu)) {
 804                 int index;
 805
 806                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 807                 if (index >= 0)
 808                         move_msr_up(vmx, index, save_nmsrs++);
 809                 index = __find_msr_index(vmx, MSR_LSTAR);
 810                 if (index >= 0)
 811                         move_msr_up(vmx, index, save_nmsrs++);
 812                 index = __find_msr_index(vmx, MSR_CSTAR);
 813                 if (index >= 0)
 814                         move_msr_up(vmx, index, save_nmsrs++);
 815                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 816                 if (index >= 0)
 817                         move_msr_up(vmx, index, save_nmsrs++);
 818                 /*
 819                  * MSR_K6_STAR is only needed on long mode guests, and only
 820                  * if efer.sce is enabled.
 821                  */
 822                 index = __find_msr_index(vmx, MSR_K6_STAR);
 823                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 824                         move_msr_up(vmx, index, save_nmsrs++);
 825         }
 826 #endif
 827         vmx->save_nmsrs = save_nmsrs;
 828
 829 #ifdef CONFIG_X86_64
 830         vmx->msr_offset_kernel_gs_base =
 831                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 832 #endif
 833         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 834 }
 835
 836 /*
 837  * reads and returns guest's timestamp counter "register"
 838  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 839  */
 840 static u64 guest_read_tsc(void)
 841 {
 842         u64 host_tsc, tsc_offset;
 843
 844         rdtscll(host_tsc);
 845         tsc_offset = vmcs_read64(TSC_OFFSET);
 846         return host_tsc + tsc_offset;
 847 }
 848
 849 /*
 850  * writes 'guest_tsc' into guest's timestamp counter "register"
 851  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 852  */
 853 static void guest_write_tsc(u64 guest_tsc)
 854 {
 855         u64 host_tsc;
 856
 857         rdtscll(host_tsc);
 858         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 859 }
 860
 861 /*
 862  * Reads an msr value (of 'msr_index') into 'pdata'.
 863  * Returns 0 on success, non-0 otherwise.
 864  * Assumes vcpu_load() was already called.
 865  */
 866 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 867 {
 868         u64 data;
 869         struct kvm_msr_entry *msr;
 870
 871         if (!pdata) {
 872                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 873                 return -EINVAL;
 874         }
 875
 876         switch (msr_index) {
 877 #ifdef CONFIG_X86_64
 878         case MSR_FS_BASE:
 879                 data = vmcs_readl(GUEST_FS_BASE);
 880                 break;
 881         case MSR_GS_BASE:
 882                 data = vmcs_readl(GUEST_GS_BASE);
 883                 break;
 884         case MSR_EFER:
 885                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 886 #endif
 887         case MSR_IA32_TIME_STAMP_COUNTER:
 888                 data = guest_read_tsc();
 889                 break;
 890         case MSR_IA32_SYSENTER_CS:
 891                 data = vmcs_read32(GUEST_SYSENTER_CS);
 892                 break;
 893         case MSR_IA32_SYSENTER_EIP:
 894                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 895                 break;
 896         case MSR_IA32_SYSENTER_ESP:
 897                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 898                 break;
 899         default:
 900                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 901                 if (msr) {
 902                         data = msr->data;
 903                         break;
 904                 }
 905                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 906         }
 907
 908         *pdata = data;
 909         return 0;
 910 }
 911
 912 /*
 913  * Writes msr value into into the appropriate "register".
 914  * Returns 0 on success, non-0 otherwise.
 915  * Assumes vcpu_load() was already called.
 916  */
 917 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 918 {
 919         struct vcpu_vmx *vmx = to_vmx(vcpu);
 920         struct kvm_msr_entry *msr;
 921         int ret = 0;
 922
 923         switch (msr_index) {
 924 #ifdef CONFIG_X86_64
 925         case MSR_EFER:
 926                 vmx_load_host_state(vmx);
 927                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 928                 break;
 929         case MSR_FS_BASE:
 930                 vmcs_writel(GUEST_FS_BASE, data);
 931                 break;
 932         case MSR_GS_BASE:
 933                 vmcs_writel(GUEST_GS_BASE, data);
 934                 break;
 935 #endif
 936         case MSR_IA32_SYSENTER_CS:
 937                 vmcs_write32(GUEST_SYSENTER_CS, data);
 938                 break;
 939         case MSR_IA32_SYSENTER_EIP:
 940                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 941                 break;
 942         case MSR_IA32_SYSENTER_ESP:
 943                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 944                 break;
 945         case MSR_IA32_TIME_STAMP_COUNTER:
 946                 guest_write_tsc(data);
 947                 break;
 948         case MSR_P6_PERFCTR0:
 949         case MSR_P6_PERFCTR1:
 950         case MSR_P6_EVNTSEL0:
 951         case MSR_P6_EVNTSEL1:
 952                 /*
 953                  * Just discard all writes to the performance counters; this
 954                  * should keep both older linux and windows 64-bit guests
 955                  * happy
 956                  */
 957                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
 958
 959                 break;
 960         default:
 961                 vmx_load_host_state(vmx);
 962                 msr = find_msr_entry(vmx, msr_index);
 963                 if (msr) {
 964                         msr->data = data;
 965                         break;
 966                 }
 967                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 968         }
 969
 970         return ret;
 971 }
 972
 973 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 974 {
 975         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
 976         switch (reg) {
 977         case VCPU_REGS_RSP:
 978                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 979                 break;
 980         case VCPU_REGS_RIP:
 981                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
 982                 break;
 983         default:
 984                 break;
 985         }
 986 }
 987
 988 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 989 {
 990         unsigned long dr7 = 0x400;
 991         int old_singlestep;
 992
 993         old_singlestep = vcpu->guest_debug.singlestep;
 994
 995         vcpu->guest_debug.enabled = dbg->enabled;
 996         if (vcpu->guest_debug.enabled) {
 997                 int i;
 998
 999                 dr7 |= 0x200;  /* exact */
1000                 for (i = 0; i < 4; ++i) {
1001                         if (!dbg->breakpoints[i].enabled)
1002                                 continue;
1003                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
1004                         dr7 |= 2 << (i*2);    /* global enable */
1005                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
1006                 }
1007
1008                 vcpu->guest_debug.singlestep = dbg->singlestep;
1009         } else
1010                 vcpu->guest_debug.singlestep = 0;
1011
1012         if (old_singlestep && !vcpu->guest_debug.singlestep) {
1013                 unsigned long flags;
1014
1015                 flags = vmcs_readl(GUEST_RFLAGS);
1016                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1017                 vmcs_writel(GUEST_RFLAGS, flags);
1018         }
1019
1020         update_exception_bitmap(vcpu);
1021         vmcs_writel(GUEST_DR7, dr7);
1022
1023         return 0;
1024 }
1025
1026 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1027 {
1028         if (!vcpu->arch.interrupt.pending)
1029                 return -1;
1030         return vcpu->arch.interrupt.nr;
1031 }
1032
1033 static __init int cpu_has_kvm_support(void)
1034 {
1035         unsigned long ecx = cpuid_ecx(1);
1036         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1037 }
1038
1039 static __init int vmx_disabled_by_bios(void)
1040 {
1041         u64 msr;
1042
1043         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1044         return (msr & (FEATURE_CONTROL_LOCKED |
1045                        FEATURE_CONTROL_VMXON_ENABLED))
1046             == FEATURE_CONTROL_LOCKED;
1047         /* locked but not enabled */
1048 }
1049
1050 static void hardware_enable(void *garbage)
1051 {
1052         int cpu = raw_smp_processor_id();
1053         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1054         u64 old;
1055
1056         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1057         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1058         if ((old & (FEATURE_CONTROL_LOCKED |
1059                     FEATURE_CONTROL_VMXON_ENABLED))
1060             != (FEATURE_CONTROL_LOCKED |
1061                 FEATURE_CONTROL_VMXON_ENABLED))
1062                 /* enable and lock */
1063                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1064                        FEATURE_CONTROL_LOCKED |
1065                        FEATURE_CONTROL_VMXON_ENABLED);
1066         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1067         asm volatile (ASM_VMX_VMXON_RAX
1068                       : : "a"(&phys_addr), "m"(phys_addr)
1069                       : "memory", "cc");
1070 }
1071
1072 static void vmclear_local_vcpus(void)
1073 {
1074         int cpu = raw_smp_processor_id();
1075         struct vcpu_vmx *vmx, *n;
1076
1077         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1078                                  local_vcpus_link)
1079                 __vcpu_clear(vmx);
1080 }
1081
1082 static void hardware_disable(void *garbage)
1083 {
1084         vmclear_local_vcpus();
1085         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1086         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1087 }
1088
1089 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1090                                       u32 msr, u32 *result)
1091 {
1092         u32 vmx_msr_low, vmx_msr_high;
1093         u32 ctl = ctl_min | ctl_opt;
1094
1095         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1096
1097         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1098         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1099
1100         /* Ensure minimum (required) set of control bits are supported. */
1101         if (ctl_min & ~ctl)
1102                 return -EIO;
1103
1104         *result = ctl;
1105         return 0;
1106 }
1107
1108 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1109 {
1110         u32 vmx_msr_low, vmx_msr_high;
1111         u32 min, opt, min2, opt2;
1112         u32 _pin_based_exec_control = 0;
1113         u32 _cpu_based_exec_control = 0;
1114         u32 _cpu_based_2nd_exec_control = 0;
1115         u32 _vmexit_control = 0;
1116         u32 _vmentry_control = 0;
1117
1118         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1119         opt = PIN_BASED_VIRTUAL_NMIS;
1120         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1121                                 &_pin_based_exec_control) < 0)
1122                 return -EIO;
1123
1124         min = CPU_BASED_HLT_EXITING |
1125 #ifdef CONFIG_X86_64
1126               CPU_BASED_CR8_LOAD_EXITING |
1127               CPU_BASED_CR8_STORE_EXITING |
1128 #endif
1129               CPU_BASED_CR3_LOAD_EXITING |
1130               CPU_BASED_CR3_STORE_EXITING |
1131               CPU_BASED_USE_IO_BITMAPS |
1132               CPU_BASED_MOV_DR_EXITING |
1133               CPU_BASED_USE_TSC_OFFSETING;
1134         opt = CPU_BASED_TPR_SHADOW |
1135               CPU_BASED_USE_MSR_BITMAPS |
1136               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1137         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1138                                 &_cpu_based_exec_control) < 0)
1139                 return -EIO;
1140 #ifdef CONFIG_X86_64
1141         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1142                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1143                                            ~CPU_BASED_CR8_STORE_EXITING;
1144 #endif
1145         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1146                 min2 = 0;
1147                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1148                         SECONDARY_EXEC_WBINVD_EXITING |
1149                         SECONDARY_EXEC_ENABLE_VPID |
1150                         SECONDARY_EXEC_ENABLE_EPT;
1151                 if (adjust_vmx_controls(min2, opt2,
1152                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1153                                         &_cpu_based_2nd_exec_control) < 0)
1154                         return -EIO;
1155         }
1156 #ifndef CONFIG_X86_64
1157         if (!(_cpu_based_2nd_exec_control &
1158                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1159                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1160 #endif
1161         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1162                 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1163                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1164                          CPU_BASED_CR3_STORE_EXITING);
1165                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1166                                         &_cpu_based_exec_control) < 0)
1167                         return -EIO;
1168                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1169                       vmx_capability.ept, vmx_capability.vpid);
1170         }
1171
1172         min = 0;
1173 #ifdef CONFIG_X86_64
1174         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1175 #endif
1176         opt = 0;
1177         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1178                                 &_vmexit_control) < 0)
1179                 return -EIO;
1180
1181         min = opt = 0;
1182         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1183                                 &_vmentry_control) < 0)
1184                 return -EIO;
1185
1186         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1187
1188         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1189         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1190                 return -EIO;
1191
1192 #ifdef CONFIG_X86_64
1193         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1194         if (vmx_msr_high & (1u<<16))
1195                 return -EIO;
1196 #endif
1197
1198         /* Require Write-Back (WB) memory type for VMCS accesses. */
1199         if (((vmx_msr_high >> 18) & 15) != 6)
1200                 return -EIO;
1201
1202         vmcs_conf->size = vmx_msr_high & 0x1fff;
1203         vmcs_conf->order = get_order(vmcs_config.size);
1204         vmcs_conf->revision_id = vmx_msr_low;
1205
1206         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1207         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1208         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1209         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1210         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1211
1212         return 0;
1213 }
1214
1215 static struct vmcs *alloc_vmcs_cpu(int cpu)
1216 {
1217         int node = cpu_to_node(cpu);
1218         struct page *pages;
1219         struct vmcs *vmcs;
1220
1221         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1222         if (!pages)
1223                 return NULL;
1224         vmcs = page_address(pages);
1225         memset(vmcs, 0, vmcs_config.size);
1226         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1227         return vmcs;
1228 }
1229
1230 static struct vmcs *alloc_vmcs(void)
1231 {
1232         return alloc_vmcs_cpu(raw_smp_processor_id());
1233 }
1234
1235 static void free_vmcs(struct vmcs *vmcs)
1236 {
1237         free_pages((unsigned long)vmcs, vmcs_config.order);
1238 }
1239
1240 static void free_kvm_area(void)
1241 {
1242         int cpu;
1243
1244         for_each_online_cpu(cpu)
1245                 free_vmcs(per_cpu(vmxarea, cpu));
1246 }
1247
1248 static __init int alloc_kvm_area(void)
1249 {
1250         int cpu;
1251
1252         for_each_online_cpu(cpu) {
1253                 struct vmcs *vmcs;
1254
1255                 vmcs = alloc_vmcs_cpu(cpu);
1256                 if (!vmcs) {
1257                         free_kvm_area();
1258                         return -ENOMEM;
1259                 }
1260
1261                 per_cpu(vmxarea, cpu) = vmcs;
1262         }
1263         return 0;
1264 }
1265
1266 static __init int hardware_setup(void)
1267 {
1268         if (setup_vmcs_config(&vmcs_config) < 0)
1269                 return -EIO;
1270
1271         if (boot_cpu_has(X86_FEATURE_NX))
1272                 kvm_enable_efer_bits(EFER_NX);
1273
1274         return alloc_kvm_area();
1275 }
1276
1277 static __exit void hardware_unsetup(void)
1278 {
1279         free_kvm_area();
1280 }
1281
1282 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1283 {
1284         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1285
1286         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1287                 vmcs_write16(sf->selector, save->selector);
1288                 vmcs_writel(sf->base, save->base);
1289                 vmcs_write32(sf->limit, save->limit);
1290                 vmcs_write32(sf->ar_bytes, save->ar);
1291         } else {
1292                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1293                         << AR_DPL_SHIFT;
1294                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1295         }
1296 }
1297
1298 static void enter_pmode(struct kvm_vcpu *vcpu)
1299 {
1300         unsigned long flags;
1301         struct vcpu_vmx *vmx = to_vmx(vcpu);
1302
1303         vmx->emulation_required = 1;
1304         vcpu->arch.rmode.active = 0;
1305
1306         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1307         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1308         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1309
1310         flags = vmcs_readl(GUEST_RFLAGS);
1311         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1312         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1313         vmcs_writel(GUEST_RFLAGS, flags);
1314
1315         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1316                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1317
1318         update_exception_bitmap(vcpu);
1319
1320         if (emulate_invalid_guest_state)
1321                 return;
1322
1323         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1324         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1325         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1326         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1327
1328         vmcs_write16(GUEST_SS_SELECTOR, 0);
1329         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1330
1331         vmcs_write16(GUEST_CS_SELECTOR,
1332                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1333         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1334 }
1335
1336 static gva_t rmode_tss_base(struct kvm *kvm)
1337 {
1338         if (!kvm->arch.tss_addr) {
1339                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1340                                  kvm->memslots[0].npages - 3;
1341                 return base_gfn << PAGE_SHIFT;
1342         }
1343         return kvm->arch.tss_addr;
1344 }
1345
1346 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1347 {
1348         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1349
1350         save->selector = vmcs_read16(sf->selector);
1351         save->base = vmcs_readl(sf->base);
1352         save->limit = vmcs_read32(sf->limit);
1353         save->ar = vmcs_read32(sf->ar_bytes);
1354         vmcs_write16(sf->selector, save->base >> 4);
1355         vmcs_write32(sf->base, save->base & 0xfffff);
1356         vmcs_write32(sf->limit, 0xffff);
1357         vmcs_write32(sf->ar_bytes, 0xf3);
1358 }
1359
1360 static void enter_rmode(struct kvm_vcpu *vcpu)
1361 {
1362         unsigned long flags;
1363         struct vcpu_vmx *vmx = to_vmx(vcpu);
1364
1365         vmx->emulation_required = 1;
1366         vcpu->arch.rmode.active = 1;
1367
1368         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1369         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1370
1371         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1372         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1373
1374         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1375         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1376
1377         flags = vmcs_readl(GUEST_RFLAGS);
1378         vcpu->arch.rmode.save_iopl
1379                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1380
1381         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1382
1383         vmcs_writel(GUEST_RFLAGS, flags);
1384         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1385         update_exception_bitmap(vcpu);
1386
1387         if (emulate_invalid_guest_state)
1388                 goto continue_rmode;
1389
1390         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1391         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1392         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1393
1394         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1395         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1396         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1397                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1398         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1399
1400         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1401         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1402         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1403         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1404
1405 continue_rmode:
1406         kvm_mmu_reset_context(vcpu);
1407         init_rmode(vcpu->kvm);
1408 }
1409
1410 #ifdef CONFIG_X86_64
1411
1412 static void enter_lmode(struct kvm_vcpu *vcpu)
1413 {
1414         u32 guest_tr_ar;
1415
1416         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1417         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1418                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1419                        __func__);
1420                 vmcs_write32(GUEST_TR_AR_BYTES,
1421                              (guest_tr_ar & ~AR_TYPE_MASK)
1422                              | AR_TYPE_BUSY_64_TSS);
1423         }
1424
1425         vcpu->arch.shadow_efer |= EFER_LMA;
1426
1427         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1428         vmcs_write32(VM_ENTRY_CONTROLS,
1429                      vmcs_read32(VM_ENTRY_CONTROLS)
1430                      | VM_ENTRY_IA32E_MODE);
1431 }
1432
1433 static void exit_lmode(struct kvm_vcpu *vcpu)
1434 {
1435         vcpu->arch.shadow_efer &= ~EFER_LMA;
1436
1437         vmcs_write32(VM_ENTRY_CONTROLS,
1438                      vmcs_read32(VM_ENTRY_CONTROLS)
1439                      & ~VM_ENTRY_IA32E_MODE);
1440 }
1441
1442 #endif
1443
1444 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1445 {
1446         vpid_sync_vcpu_all(to_vmx(vcpu));
1447         if (vm_need_ept())
1448                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1449 }
1450
1451 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1452 {
1453         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1454         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1455 }
1456
1457 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1458 {
1459         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1460                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1461                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1462                         return;
1463                 }
1464                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1465                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1466                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1467                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1468         }
1469 }
1470
1471 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1472
1473 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1474                                         unsigned long cr0,
1475                                         struct kvm_vcpu *vcpu)
1476 {
1477         if (!(cr0 & X86_CR0_PG)) {
1478                 /* From paging/starting to nonpaging */
1479                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1480                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1481                              (CPU_BASED_CR3_LOAD_EXITING |
1482                               CPU_BASED_CR3_STORE_EXITING));
1483                 vcpu->arch.cr0 = cr0;
1484                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1485                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1486                 *hw_cr0 &= ~X86_CR0_WP;
1487         } else if (!is_paging(vcpu)) {
1488                 /* From nonpaging to paging */
1489                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1490                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1491                              ~(CPU_BASED_CR3_LOAD_EXITING |
1492                                CPU_BASED_CR3_STORE_EXITING));
1493                 vcpu->arch.cr0 = cr0;
1494                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1495                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1496                         *hw_cr0 &= ~X86_CR0_WP;
1497         }
1498 }
1499
1500 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1501                                         struct kvm_vcpu *vcpu)
1502 {
1503         if (!is_paging(vcpu)) {
1504                 *hw_cr4 &= ~X86_CR4_PAE;
1505                 *hw_cr4 |= X86_CR4_PSE;
1506         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1507                 *hw_cr4 &= ~X86_CR4_PAE;
1508 }
1509
1510 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1511 {
1512         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1513                                 KVM_VM_CR0_ALWAYS_ON;
1514
1515         vmx_fpu_deactivate(vcpu);
1516
1517         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1518                 enter_pmode(vcpu);
1519
1520         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1521                 enter_rmode(vcpu);
1522
1523 #ifdef CONFIG_X86_64
1524         if (vcpu->arch.shadow_efer & EFER_LME) {
1525                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1526                         enter_lmode(vcpu);
1527                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1528                         exit_lmode(vcpu);
1529         }
1530 #endif
1531
1532         if (vm_need_ept())
1533                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1534
1535         vmcs_writel(CR0_READ_SHADOW, cr0);
1536         vmcs_writel(GUEST_CR0, hw_cr0);
1537         vcpu->arch.cr0 = cr0;
1538
1539         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1540                 vmx_fpu_activate(vcpu);
1541 }
1542
1543 static u64 construct_eptp(unsigned long root_hpa)
1544 {
1545         u64 eptp;
1546
1547         /* TODO write the value reading from MSR */
1548         eptp = VMX_EPT_DEFAULT_MT |
1549                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1550         eptp |= (root_hpa & PAGE_MASK);
1551
1552         return eptp;
1553 }
1554
1555 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1556 {
1557         unsigned long guest_cr3;
1558         u64 eptp;
1559
1560         guest_cr3 = cr3;
1561         if (vm_need_ept()) {
1562                 eptp = construct_eptp(cr3);
1563                 vmcs_write64(EPT_POINTER, eptp);
1564                 ept_sync_context(eptp);
1565                 ept_load_pdptrs(vcpu);
1566                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1567                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1568         }
1569
1570         vmx_flush_tlb(vcpu);
1571         vmcs_writel(GUEST_CR3, guest_cr3);
1572         if (vcpu->arch.cr0 & X86_CR0_PE)
1573                 vmx_fpu_deactivate(vcpu);
1574 }
1575
1576 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1577 {
1578         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1579                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1580
1581         vcpu->arch.cr4 = cr4;
1582         if (vm_need_ept())
1583                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1584
1585         vmcs_writel(CR4_READ_SHADOW, cr4);
1586         vmcs_writel(GUEST_CR4, hw_cr4);
1587 }
1588
1589 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1590 {
1591         struct vcpu_vmx *vmx = to_vmx(vcpu);
1592         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1593
1594         vcpu->arch.shadow_efer = efer;
1595         if (!msr)
1596                 return;
1597         if (efer & EFER_LMA) {
1598                 vmcs_write32(VM_ENTRY_CONTROLS,
1599                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1600                                      VM_ENTRY_IA32E_MODE);
1601                 msr->data = efer;
1602
1603         } else {
1604                 vmcs_write32(VM_ENTRY_CONTROLS,
1605                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1606                                      ~VM_ENTRY_IA32E_MODE);
1607
1608                 msr->data = efer & ~EFER_LME;
1609         }
1610         setup_msrs(vmx);
1611 }
1612
1613 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1614 {
1615         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1616
1617         return vmcs_readl(sf->base);
1618 }
1619
1620 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1621                             struct kvm_segment *var, int seg)
1622 {
1623         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1624         u32 ar;
1625
1626         var->base = vmcs_readl(sf->base);
1627         var->limit = vmcs_read32(sf->limit);
1628         var->selector = vmcs_read16(sf->selector);
1629         ar = vmcs_read32(sf->ar_bytes);
1630         if (ar & AR_UNUSABLE_MASK)
1631                 ar = 0;
1632         var->type = ar & 15;
1633         var->s = (ar >> 4) & 1;
1634         var->dpl = (ar >> 5) & 3;
1635         var->present = (ar >> 7) & 1;
1636         var->avl = (ar >> 12) & 1;
1637         var->l = (ar >> 13) & 1;
1638         var->db = (ar >> 14) & 1;
1639         var->g = (ar >> 15) & 1;
1640         var->unusable = (ar >> 16) & 1;
1641 }
1642
1643 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1644 {
1645         struct kvm_segment kvm_seg;
1646
1647         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1648                 return 0;
1649
1650         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1651                 return 3;
1652
1653         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1654         return kvm_seg.selector & 3;
1655 }
1656
1657 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1658 {
1659         u32 ar;
1660
1661         if (var->unusable)
1662                 ar = 1 << 16;
1663         else {
1664                 ar = var->type & 15;
1665                 ar |= (var->s & 1) << 4;
1666                 ar |= (var->dpl & 3) << 5;
1667                 ar |= (var->present & 1) << 7;
1668                 ar |= (var->avl & 1) << 12;
1669                 ar |= (var->l & 1) << 13;
1670                 ar |= (var->db & 1) << 14;
1671                 ar |= (var->g & 1) << 15;
1672         }
1673         if (ar == 0) /* a 0 value means unusable */
1674                 ar = AR_UNUSABLE_MASK;
1675
1676         return ar;
1677 }
1678
1679 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1680                             struct kvm_segment *var, int seg)
1681 {
1682         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1683         u32 ar;
1684
1685         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1686                 vcpu->arch.rmode.tr.selector = var->selector;
1687                 vcpu->arch.rmode.tr.base = var->base;
1688                 vcpu->arch.rmode.tr.limit = var->limit;
1689                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1690                 return;
1691         }
1692         vmcs_writel(sf->base, var->base);
1693         vmcs_write32(sf->limit, var->limit);
1694         vmcs_write16(sf->selector, var->selector);
1695         if (vcpu->arch.rmode.active && var->s) {
1696                 /*
1697                  * Hack real-mode segments into vm86 compatibility.
1698                  */
1699                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1700                         vmcs_writel(sf->base, 0xf0000);
1701                 ar = 0xf3;
1702         } else
1703                 ar = vmx_segment_access_rights(var);
1704         vmcs_write32(sf->ar_bytes, ar);
1705 }
1706
1707 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1708 {
1709         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1710
1711         *db = (ar >> 14) & 1;
1712         *l = (ar >> 13) & 1;
1713 }
1714
1715 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1716 {
1717         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1718         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1719 }
1720
1721 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1722 {
1723         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1724         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1725 }
1726
1727 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1728 {
1729         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1730         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1731 }
1732
1733 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1734 {
1735         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1736         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1737 }
1738
1739 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1740 {
1741         struct kvm_segment var;
1742         u32 ar;
1743
1744         vmx_get_segment(vcpu, &var, seg);
1745         ar = vmx_segment_access_rights(&var);
1746
1747         if (var.base != (var.selector << 4))
1748                 return false;
1749         if (var.limit != 0xffff)
1750                 return false;
1751         if (ar != 0xf3)
1752                 return false;
1753
1754         return true;
1755 }
1756
1757 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1758 {
1759         struct kvm_segment cs;
1760         unsigned int cs_rpl;
1761
1762         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1763         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1764
1765         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1766                 return false;
1767         if (!cs.s)
1768                 return false;
1769         if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1770                 if (cs.dpl > cs_rpl)
1771                         return false;
1772         } else if (cs.type & AR_TYPE_CODE_MASK) {
1773                 if (cs.dpl != cs_rpl)
1774                         return false;
1775         }
1776         if (!cs.present)
1777                 return false;
1778
1779         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1780         return true;
1781 }
1782
1783 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1784 {
1785         struct kvm_segment ss;
1786         unsigned int ss_rpl;
1787
1788         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1789         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1790
1791         if ((ss.type != 3) || (ss.type != 7))
1792                 return false;
1793         if (!ss.s)
1794                 return false;
1795         if (ss.dpl != ss_rpl) /* DPL != RPL */
1796                 return false;
1797         if (!ss.present)
1798                 return false;
1799
1800         return true;
1801 }
1802
1803 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1804 {
1805         struct kvm_segment var;
1806         unsigned int rpl;
1807
1808         vmx_get_segment(vcpu, &var, seg);
1809         rpl = var.selector & SELECTOR_RPL_MASK;
1810
1811         if (!var.s)
1812                 return false;
1813         if (!var.present)
1814                 return false;
1815         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1816                 if (var.dpl < rpl) /* DPL < RPL */
1817                         return false;
1818         }
1819
1820         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1821          * rights flags
1822          */
1823         return true;
1824 }
1825
1826 static bool tr_valid(struct kvm_vcpu *vcpu)
1827 {
1828         struct kvm_segment tr;
1829
1830         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1831
1832         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1833                 return false;
1834         if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1835                 return false;
1836         if (!tr.present)
1837                 return false;
1838
1839         return true;
1840 }
1841
1842 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1843 {
1844         struct kvm_segment ldtr;
1845
1846         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1847
1848         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
1849                 return false;
1850         if (ldtr.type != 2)
1851                 return false;
1852         if (!ldtr.present)
1853                 return false;
1854
1855         return true;
1856 }
1857
1858 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1859 {
1860         struct kvm_segment cs, ss;
1861
1862         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1863         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1864
1865         return ((cs.selector & SELECTOR_RPL_MASK) ==
1866                  (ss.selector & SELECTOR_RPL_MASK));
1867 }
1868
1869 /*
1870  * Check if guest state is valid. Returns true if valid, false if
1871  * not.
1872  * We assume that registers are always usable
1873  */
1874 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1875 {
1876         /* real mode guest state checks */
1877         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1878                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1879                         return false;
1880                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1881                         return false;
1882                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1883                         return false;
1884                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1885                         return false;
1886                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1887                         return false;
1888                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1889                         return false;
1890         } else {
1891         /* protected mode guest state checks */
1892                 if (!cs_ss_rpl_check(vcpu))
1893                         return false;
1894                 if (!code_segment_valid(vcpu))
1895                         return false;
1896                 if (!stack_segment_valid(vcpu))
1897                         return false;
1898                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1899                         return false;
1900                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1901                         return false;
1902                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1903                         return false;
1904                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1905                         return false;
1906                 if (!tr_valid(vcpu))
1907                         return false;
1908                 if (!ldtr_valid(vcpu))
1909                         return false;
1910         }
1911         /* TODO:
1912          * - Add checks on RIP
1913          * - Add checks on RFLAGS
1914          */
1915
1916         return true;
1917 }
1918
1919 static int init_rmode_tss(struct kvm *kvm)
1920 {
1921         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1922         u16 data = 0;
1923         int ret = 0;
1924         int r;
1925
1926         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1927         if (r < 0)
1928                 goto out;
1929         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1930         r = kvm_write_guest_page(kvm, fn++, &data,
1931                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
1932         if (r < 0)
1933                 goto out;
1934         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1935         if (r < 0)
1936                 goto out;
1937         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1938         if (r < 0)
1939                 goto out;
1940         data = ~0;
1941         r = kvm_write_guest_page(kvm, fn, &data,
1942                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1943                                  sizeof(u8));
1944         if (r < 0)
1945                 goto out;
1946
1947         ret = 1;
1948 out:
1949         return ret;
1950 }
1951
1952 static int init_rmode_identity_map(struct kvm *kvm)
1953 {
1954         int i, r, ret;
1955         pfn_t identity_map_pfn;
1956         u32 tmp;
1957
1958         if (!vm_need_ept())
1959                 return 1;
1960         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1961                 printk(KERN_ERR "EPT: identity-mapping pagetable "
1962                         "haven't been allocated!\n");
1963                 return 0;
1964         }
1965         if (likely(kvm->arch.ept_identity_pagetable_done))
1966                 return 1;
1967         ret = 0;
1968         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1969         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1970         if (r < 0)
1971                 goto out;
1972         /* Set up identity-mapping pagetable for EPT in real mode */
1973         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1974                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1975                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1976                 r = kvm_write_guest_page(kvm, identity_map_pfn,
1977                                 &tmp, i * sizeof(tmp), sizeof(tmp));
1978                 if (r < 0)
1979                         goto out;
1980         }
1981         kvm->arch.ept_identity_pagetable_done = true;
1982         ret = 1;
1983 out:
1984         return ret;
1985 }
1986
1987 static void seg_setup(int seg)
1988 {
1989         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1990
1991         vmcs_write16(sf->selector, 0);
1992         vmcs_writel(sf->base, 0);
1993         vmcs_write32(sf->limit, 0xffff);
1994         vmcs_write32(sf->ar_bytes, 0xf3);
1995 }
1996
1997 static int alloc_apic_access_page(struct kvm *kvm)
1998 {
1999         struct kvm_userspace_memory_region kvm_userspace_mem;
2000         int r = 0;
2001
2002         down_write(&kvm->slots_lock);
2003         if (kvm->arch.apic_access_page)
2004                 goto out;
2005         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2006         kvm_userspace_mem.flags = 0;
2007         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2008         kvm_userspace_mem.memory_size = PAGE_SIZE;
2009         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2010         if (r)
2011                 goto out;
2012
2013         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2014 out:
2015         up_write(&kvm->slots_lock);
2016         return r;
2017 }
2018
2019 static int alloc_identity_pagetable(struct kvm *kvm)
2020 {
2021         struct kvm_userspace_memory_region kvm_userspace_mem;
2022         int r = 0;
2023
2024         down_write(&kvm->slots_lock);
2025         if (kvm->arch.ept_identity_pagetable)
2026                 goto out;
2027         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2028         kvm_userspace_mem.flags = 0;
2029         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2030         kvm_userspace_mem.memory_size = PAGE_SIZE;
2031         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2032         if (r)
2033                 goto out;
2034
2035         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2036                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2037 out:
2038         up_write(&kvm->slots_lock);
2039         return r;
2040 }
2041
2042 static void allocate_vpid(struct vcpu_vmx *vmx)
2043 {
2044         int vpid;
2045
2046         vmx->vpid = 0;
2047         if (!enable_vpid || !cpu_has_vmx_vpid())
2048                 return;
2049         spin_lock(&vmx_vpid_lock);
2050         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2051         if (vpid < VMX_NR_VPIDS) {
2052                 vmx->vpid = vpid;
2053                 __set_bit(vpid, vmx_vpid_bitmap);
2054         }
2055         spin_unlock(&vmx_vpid_lock);
2056 }
2057
2058 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2059 {
2060         void *va;
2061
2062         if (!cpu_has_vmx_msr_bitmap())
2063                 return;
2064
2065         /*
2066          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2067          * have the write-low and read-high bitmap offsets the wrong way round.
2068          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2069          */
2070         va = kmap(msr_bitmap);
2071         if (msr <= 0x1fff) {
2072                 __clear_bit(msr, va + 0x000); /* read-low */
2073                 __clear_bit(msr, va + 0x800); /* write-low */
2074         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2075                 msr &= 0x1fff;
2076                 __clear_bit(msr, va + 0x400); /* read-high */
2077                 __clear_bit(msr, va + 0xc00); /* write-high */
2078         }
2079         kunmap(msr_bitmap);
2080 }
2081
2082 /*
2083  * Sets up the vmcs for emulated real mode.
2084  */
2085 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2086 {
2087         u32 host_sysenter_cs;
2088         u32 junk;
2089         unsigned long a;
2090         struct descriptor_table dt;
2091         int i;
2092         unsigned long kvm_vmx_return;
2093         u32 exec_control;
2094
2095         /* I/O */
2096         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2097         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2098
2099         if (cpu_has_vmx_msr_bitmap())
2100                 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2101
2102         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2103
2104         /* Control */
2105         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2106                 vmcs_config.pin_based_exec_ctrl);
2107
2108         exec_control = vmcs_config.cpu_based_exec_ctrl;
2109         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2110                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2111 #ifdef CONFIG_X86_64
2112                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2113                                 CPU_BASED_CR8_LOAD_EXITING;
2114 #endif
2115         }
2116         if (!vm_need_ept())
2117                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2118                                 CPU_BASED_CR3_LOAD_EXITING;
2119         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2120
2121         if (cpu_has_secondary_exec_ctrls()) {
2122                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2123                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2124                         exec_control &=
2125                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2126                 if (vmx->vpid == 0)
2127                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2128                 if (!vm_need_ept())
2129                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2130                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2131         }
2132
2133         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2134         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2135         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2136
2137         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2138         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2139         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2140
2141         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2142         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2143         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2144         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2145         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2146         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2147 #ifdef CONFIG_X86_64
2148         rdmsrl(MSR_FS_BASE, a);
2149         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2150         rdmsrl(MSR_GS_BASE, a);
2151         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2152 #else
2153         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2154         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2155 #endif
2156
2157         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2158
2159         kvm_get_idt(&dt);
2160         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2161
2162         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2163         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2164         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2165         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2166         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2167
2168         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2169         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2170         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2171         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2172         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2173         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2174
2175         for (i = 0; i < NR_VMX_MSR; ++i) {
2176                 u32 index = vmx_msr_index[i];
2177                 u32 data_low, data_high;
2178                 u64 data;
2179                 int j = vmx->nmsrs;
2180
2181                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2182                         continue;
2183                 if (wrmsr_safe(index, data_low, data_high) < 0)
2184                         continue;
2185                 data = data_low | ((u64)data_high << 32);
2186                 vmx->host_msrs[j].index = index;
2187                 vmx->host_msrs[j].reserved = 0;
2188                 vmx->host_msrs[j].data = data;
2189                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2190                 ++vmx->nmsrs;
2191         }
2192
2193         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2194
2195         /* 22.2.1, 20.8.1 */
2196         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2197
2198         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2199         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2200
2201
2202         return 0;
2203 }
2204
2205 static int init_rmode(struct kvm *kvm)
2206 {
2207         if (!init_rmode_tss(kvm))
2208                 return 0;
2209         if (!init_rmode_identity_map(kvm))
2210                 return 0;
2211         return 1;
2212 }
2213
2214 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2215 {
2216         struct vcpu_vmx *vmx = to_vmx(vcpu);
2217         u64 msr;
2218         int ret;
2219
2220         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2221         down_read(&vcpu->kvm->slots_lock);
2222         if (!init_rmode(vmx->vcpu.kvm)) {
2223                 ret = -ENOMEM;
2224                 goto out;
2225         }
2226
2227         vmx->vcpu.arch.rmode.active = 0;
2228
2229         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2230         kvm_set_cr8(&vmx->vcpu, 0);
2231         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2232         if (vmx->vcpu.vcpu_id == 0)
2233                 msr |= MSR_IA32_APICBASE_BSP;
2234         kvm_set_apic_base(&vmx->vcpu, msr);
2235
2236         fx_init(&vmx->vcpu);
2237
2238         seg_setup(VCPU_SREG_CS);
2239         /*
2240          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2241          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2242          */
2243         if (vmx->vcpu.vcpu_id == 0) {
2244                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2245                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2246         } else {
2247                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2248                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2249         }
2250
2251         seg_setup(VCPU_SREG_DS);
2252         seg_setup(VCPU_SREG_ES);
2253         seg_setup(VCPU_SREG_FS);
2254         seg_setup(VCPU_SREG_GS);
2255         seg_setup(VCPU_SREG_SS);
2256
2257         vmcs_write16(GUEST_TR_SELECTOR, 0);
2258         vmcs_writel(GUEST_TR_BASE, 0);
2259         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2260         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2261
2262         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2263         vmcs_writel(GUEST_LDTR_BASE, 0);
2264         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2265         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2266
2267         vmcs_write32(GUEST_SYSENTER_CS, 0);
2268         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2269         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2270
2271         vmcs_writel(GUEST_RFLAGS, 0x02);
2272         if (vmx->vcpu.vcpu_id == 0)
2273                 kvm_rip_write(vcpu, 0xfff0);
2274         else
2275                 kvm_rip_write(vcpu, 0);
2276         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2277
2278         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2279         vmcs_writel(GUEST_DR7, 0x400);
2280
2281         vmcs_writel(GUEST_GDTR_BASE, 0);
2282         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2283
2284         vmcs_writel(GUEST_IDTR_BASE, 0);
2285         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2286
2287         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2288         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2289         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2290
2291         guest_write_tsc(0);
2292
2293         /* Special registers */
2294         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2295
2296         setup_msrs(vmx);
2297
2298         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2299
2300         if (cpu_has_vmx_tpr_shadow()) {
2301                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2302                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2303                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2304                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2305                 vmcs_write32(TPR_THRESHOLD, 0);
2306         }
2307
2308         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2309                 vmcs_write64(APIC_ACCESS_ADDR,
2310                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2311
2312         if (vmx->vpid != 0)
2313                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2314
2315         vmx->vcpu.arch.cr0 = 0x60000010;
2316         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2317         vmx_set_cr4(&vmx->vcpu, 0);
2318         vmx_set_efer(&vmx->vcpu, 0);
2319         vmx_fpu_activate(&vmx->vcpu);
2320         update_exception_bitmap(&vmx->vcpu);
2321
2322         vpid_sync_vcpu_all(vmx);
2323
2324         ret = 0;
2325
2326         /* HACK: Don't enable emulation on guest boot/reset */
2327         vmx->emulation_required = 0;
2328
2329 out:
2330         up_read(&vcpu->kvm->slots_lock);
2331         return ret;
2332 }
2333
2334 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2335 {
2336         struct vcpu_vmx *vmx = to_vmx(vcpu);
2337
2338         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2339
2340         ++vcpu->stat.irq_injections;
2341         if (vcpu->arch.rmode.active) {
2342                 vmx->rmode.irq.pending = true;
2343                 vmx->rmode.irq.vector = irq;
2344                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2345                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2346                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2347                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2348                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2349                 return;
2350         }
2351         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2352                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2353 }
2354
2355 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2356 {
2357         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2358                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2359 }
2360
2361 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2362 {
2363         int word_index = __ffs(vcpu->arch.irq_summary);
2364         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2365         int irq = word_index * BITS_PER_LONG + bit_index;
2366
2367         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2368         if (!vcpu->arch.irq_pending[word_index])
2369                 clear_bit(word_index, &vcpu->arch.irq_summary);
2370         kvm_queue_interrupt(vcpu, irq);
2371 }
2372
2373
2374 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2375                                        struct kvm_run *kvm_run)
2376 {
2377         u32 cpu_based_vm_exec_control;
2378
2379         vcpu->arch.interrupt_window_open =
2380                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2381                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2382
2383         if (vcpu->arch.interrupt_window_open &&
2384             vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2385                 kvm_do_inject_irq(vcpu);
2386
2387         if (vcpu->arch.interrupt_window_open && vcpu->arch.interrupt.pending)
2388                 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2389
2390         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2391         if (!vcpu->arch.interrupt_window_open &&
2392             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2393                 /*
2394                  * Interrupts blocked.  Wait for unblock.
2395                  */
2396                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2397         else
2398                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2399         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2400 }
2401
2402 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2403 {
2404         int ret;
2405         struct kvm_userspace_memory_region tss_mem = {
2406                 .slot = 8,
2407                 .guest_phys_addr = addr,
2408                 .memory_size = PAGE_SIZE * 3,
2409                 .flags = 0,
2410         };
2411
2412         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2413         if (ret)
2414                 return ret;
2415         kvm->arch.tss_addr = addr;
2416         return 0;
2417 }
2418
2419 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2420 {
2421         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2422
2423         set_debugreg(dbg->bp[0], 0);
2424         set_debugreg(dbg->bp[1], 1);
2425         set_debugreg(dbg->bp[2], 2);
2426         set_debugreg(dbg->bp[3], 3);
2427
2428         if (dbg->singlestep) {
2429                 unsigned long flags;
2430
2431                 flags = vmcs_readl(GUEST_RFLAGS);
2432                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2433                 vmcs_writel(GUEST_RFLAGS, flags);
2434         }
2435 }
2436
2437 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2438                                   int vec, u32 err_code)
2439 {
2440         /*
2441          * Instruction with address size override prefix opcode 0x67
2442          * Cause the #SS fault with 0 error code in VM86 mode.
2443          */
2444         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2445                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2446                         return 1;
2447         /*
2448          * Forward all other exceptions that are valid in real mode.
2449          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2450          *        the required debugging infrastructure rework.
2451          */
2452         switch (vec) {
2453         case DE_VECTOR:
2454         case DB_VECTOR:
2455         case BP_VECTOR:
2456         case OF_VECTOR:
2457         case BR_VECTOR:
2458         case UD_VECTOR:
2459         case DF_VECTOR:
2460         case SS_VECTOR:
2461         case GP_VECTOR:
2462         case MF_VECTOR:
2463                 kvm_queue_exception(vcpu, vec);
2464                 return 1;
2465         }
2466         return 0;
2467 }
2468
2469 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2470 {
2471         struct vcpu_vmx *vmx = to_vmx(vcpu);
2472         u32 intr_info, error_code;
2473         unsigned long cr2, rip;
2474         u32 vect_info;
2475         enum emulation_result er;
2476
2477         vect_info = vmx->idt_vectoring_info;
2478         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2479
2480         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2481                                                 !is_page_fault(intr_info))
2482                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2483                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2484
2485         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2486                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2487                 set_bit(irq, vcpu->arch.irq_pending);
2488                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2489         }
2490
2491         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2492                 return 1;  /* already handled by vmx_vcpu_run() */
2493
2494         if (is_no_device(intr_info)) {
2495                 vmx_fpu_activate(vcpu);
2496                 return 1;
2497         }
2498
2499         if (is_invalid_opcode(intr_info)) {
2500                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2501                 if (er != EMULATE_DONE)
2502                         kvm_queue_exception(vcpu, UD_VECTOR);
2503                 return 1;
2504         }
2505
2506         error_code = 0;
2507         rip = kvm_rip_read(vcpu);
2508         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2509                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2510         if (is_page_fault(intr_info)) {
2511                 /* EPT won't cause page fault directly */
2512                 if (vm_need_ept())
2513                         BUG();
2514                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2515                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2516                             (u32)((u64)cr2 >> 32), handler);
2517                 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2518                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2519                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2520         }
2521
2522         if (vcpu->arch.rmode.active &&
2523             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2524                                                                 error_code)) {
2525                 if (vcpu->arch.halt_request) {
2526                         vcpu->arch.halt_request = 0;
2527                         return kvm_emulate_halt(vcpu);
2528                 }
2529                 return 1;
2530         }
2531
2532         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2533             (INTR_TYPE_EXCEPTION | 1)) {
2534                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2535                 return 0;
2536         }
2537         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2538         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2539         kvm_run->ex.error_code = error_code;
2540         return 0;
2541 }
2542
2543 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2544                                      struct kvm_run *kvm_run)
2545 {
2546         ++vcpu->stat.irq_exits;
2547         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2548         return 1;
2549 }
2550
2551 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2552 {
2553         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2554         return 0;
2555 }
2556
2557 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2558 {
2559         unsigned long exit_qualification;
2560         int size, down, in, string, rep;
2561         unsigned port;
2562
2563         ++vcpu->stat.io_exits;
2564         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2565         string = (exit_qualification & 16) != 0;
2566
2567         if (string) {
2568                 if (emulate_instruction(vcpu,
2569                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2570                         return 0;
2571                 return 1;
2572         }
2573
2574         size = (exit_qualification & 7) + 1;
2575         in = (exit_qualification & 8) != 0;
2576         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2577         rep = (exit_qualification & 32) != 0;
2578         port = exit_qualification >> 16;
2579
2580         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2581 }
2582
2583 static void
2584 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2585 {
2586         /*
2587          * Patch in the VMCALL instruction:
2588          */
2589         hypercall[0] = 0x0f;
2590         hypercall[1] = 0x01;
2591         hypercall[2] = 0xc1;
2592 }
2593
2594 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2595 {
2596         unsigned long exit_qualification;
2597         int cr;
2598         int reg;
2599
2600         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2601         cr = exit_qualification & 15;
2602         reg = (exit_qualification >> 8) & 15;
2603         switch ((exit_qualification >> 4) & 3) {
2604         case 0: /* mov to cr */
2605                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2606                             (u32)kvm_register_read(vcpu, reg),
2607                             (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2608                             handler);
2609                 switch (cr) {
2610                 case 0:
2611                         kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2612                         skip_emulated_instruction(vcpu);
2613                         return 1;
2614                 case 3:
2615                         kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2616                         skip_emulated_instruction(vcpu);
2617                         return 1;
2618                 case 4:
2619                         kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2620                         skip_emulated_instruction(vcpu);
2621                         return 1;
2622                 case 8:
2623                         kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2624                         skip_emulated_instruction(vcpu);
2625                         if (irqchip_in_kernel(vcpu->kvm))
2626                                 return 1;
2627                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2628                         return 0;
2629                 };
2630                 break;
2631         case 2: /* clts */
2632                 vmx_fpu_deactivate(vcpu);
2633                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2634                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2635                 vmx_fpu_activate(vcpu);
2636                 KVMTRACE_0D(CLTS, vcpu, handler);
2637                 skip_emulated_instruction(vcpu);
2638                 return 1;
2639         case 1: /*mov from cr*/
2640                 switch (cr) {
2641                 case 3:
2642                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2643                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2644                                     (u32)kvm_register_read(vcpu, reg),
2645                                     (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2646                                     handler);
2647                         skip_emulated_instruction(vcpu);
2648                         return 1;
2649                 case 8:
2650                         kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2651                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2652                                     (u32)kvm_register_read(vcpu, reg), handler);
2653                         skip_emulated_instruction(vcpu);
2654                         return 1;
2655                 }
2656                 break;
2657         case 3: /* lmsw */
2658                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2659
2660                 skip_emulated_instruction(vcpu);
2661                 return 1;
2662         default:
2663                 break;
2664         }
2665         kvm_run->exit_reason = 0;
2666         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2667                (int)(exit_qualification >> 4) & 3, cr);
2668         return 0;
2669 }
2670
2671 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2672 {
2673         unsigned long exit_qualification;
2674         unsigned long val;
2675         int dr, reg;
2676
2677         /*
2678          * FIXME: this code assumes the host is debugging the guest.
2679          *        need to deal with guest debugging itself too.
2680          */
2681         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2682         dr = exit_qualification & 7;
2683         reg = (exit_qualification >> 8) & 15;
2684         if (exit_qualification & 16) {
2685                 /* mov from dr */
2686                 switch (dr) {
2687                 case 6:
2688                         val = 0xffff0ff0;
2689                         break;
2690                 case 7:
2691                         val = 0x400;
2692                         break;
2693                 default:
2694                         val = 0;
2695                 }
2696                 kvm_register_write(vcpu, reg, val);
2697                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2698         } else {
2699                 /* mov to dr */
2700         }
2701         skip_emulated_instruction(vcpu);
2702         return 1;
2703 }
2704
2705 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2706 {
2707         kvm_emulate_cpuid(vcpu);
2708         return 1;
2709 }
2710
2711 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2712 {
2713         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2714         u64 data;
2715
2716         if (vmx_get_msr(vcpu, ecx, &data)) {
2717                 kvm_inject_gp(vcpu, 0);
2718                 return 1;
2719         }
2720
2721         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2722                     handler);
2723
2724         /* FIXME: handling of bits 32:63 of rax, rdx */
2725         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2726         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2727         skip_emulated_instruction(vcpu);
2728         return 1;
2729 }
2730
2731 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2732 {
2733         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2734         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2735                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2736
2737         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2738                     handler);
2739
2740         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2741                 kvm_inject_gp(vcpu, 0);
2742                 return 1;
2743         }
2744
2745         skip_emulated_instruction(vcpu);
2746         return 1;
2747 }
2748
2749 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2750                                       struct kvm_run *kvm_run)
2751 {
2752         return 1;
2753 }
2754
2755 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2756                                    struct kvm_run *kvm_run)
2757 {
2758         u32 cpu_based_vm_exec_control;
2759
2760         /* clear pending irq */
2761         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2762         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2763         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2764
2765         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2766
2767         /*
2768          * If the user space waits to inject interrupts, exit as soon as
2769          * possible
2770          */
2771         if (kvm_run->request_interrupt_window &&
2772             !vcpu->arch.irq_summary) {
2773                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2774                 ++vcpu->stat.irq_window_exits;
2775                 return 0;
2776         }
2777         return 1;
2778 }
2779
2780 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2781 {
2782         skip_emulated_instruction(vcpu);
2783         return kvm_emulate_halt(vcpu);
2784 }
2785
2786 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2787 {
2788         skip_emulated_instruction(vcpu);
2789         kvm_emulate_hypercall(vcpu);
2790         return 1;
2791 }
2792
2793 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2794 {
2795         skip_emulated_instruction(vcpu);
2796         /* TODO: Add support for VT-d/pass-through device */
2797         return 1;
2798 }
2799
2800 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2801 {
2802         u64 exit_qualification;
2803         enum emulation_result er;
2804         unsigned long offset;
2805
2806         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2807         offset = exit_qualification & 0xffful;
2808
2809         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2810
2811         if (er !=  EMULATE_DONE) {
2812                 printk(KERN_ERR
2813                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2814                        offset);
2815                 return -ENOTSUPP;
2816         }
2817         return 1;
2818 }
2819
2820 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2821 {
2822         unsigned long exit_qualification;
2823         u16 tss_selector;
2824         int reason;
2825
2826         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2827
2828         reason = (u32)exit_qualification >> 30;
2829         tss_selector = exit_qualification;
2830
2831         return kvm_task_switch(vcpu, tss_selector, reason);
2832 }
2833
2834 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2835 {
2836         u64 exit_qualification;
2837         enum emulation_result er;
2838         gpa_t gpa;
2839         unsigned long hva;
2840         int gla_validity;
2841         int r;
2842
2843         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2844
2845         if (exit_qualification & (1 << 6)) {
2846                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2847                 return -ENOTSUPP;
2848         }
2849
2850         gla_validity = (exit_qualification >> 7) & 0x3;
2851         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2852                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2853                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2854                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2855                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2856                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2857                         (long unsigned int)exit_qualification);
2858                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2859                 kvm_run->hw.hardware_exit_reason = 0;
2860                 return -ENOTSUPP;
2861         }
2862
2863         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2864         hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2865         if (!kvm_is_error_hva(hva)) {
2866                 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2867                 if (r < 0) {
2868                         printk(KERN_ERR "EPT: Not enough memory!\n");
2869                         return -ENOMEM;
2870                 }
2871                 return 1;
2872         } else {
2873                 /* must be MMIO */
2874                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2875
2876                 if (er == EMULATE_FAIL) {
2877                         printk(KERN_ERR
2878                          "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2879                          er);
2880                         printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2881                          (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2882                          (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2883                         printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2884                                 (long unsigned int)exit_qualification);
2885                         return -ENOTSUPP;
2886                 } else if (er == EMULATE_DO_MMIO)
2887                         return 0;
2888         }
2889         return 1;
2890 }
2891
2892 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2893 {
2894         u32 cpu_based_vm_exec_control;
2895
2896         /* clear pending NMI */
2897         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2898         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
2899         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2900         ++vcpu->stat.nmi_window_exits;
2901
2902         return 1;
2903 }
2904
2905 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
2906                                 struct kvm_run *kvm_run)
2907 {
2908         struct vcpu_vmx *vmx = to_vmx(vcpu);
2909         int err;
2910
2911         preempt_enable();
2912         local_irq_enable();
2913
2914         while (!guest_state_valid(vcpu)) {
2915                 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2916
2917                 switch (err) {
2918                         case EMULATE_DONE:
2919                                 break;
2920                         case EMULATE_DO_MMIO:
2921                                 kvm_report_emulation_failure(vcpu, "mmio");
2922                                 /* TODO: Handle MMIO */
2923                                 return;
2924                         default:
2925                                 kvm_report_emulation_failure(vcpu, "emulation failure");
2926                                 return;
2927                 }
2928
2929                 if (signal_pending(current))
2930                         break;
2931                 if (need_resched())
2932                         schedule();
2933         }
2934
2935         local_irq_disable();
2936         preempt_disable();
2937
2938         /* Guest state should be valid now, no more emulation should be needed */
2939         vmx->emulation_required = 0;
2940 }
2941
2942 /*
2943  * The exit handlers return 1 if the exit was handled fully and guest execution
2944  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2945  * to be done to userspace and return 0.
2946  */
2947 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2948                                       struct kvm_run *kvm_run) = {
2949         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2950         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2951         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2952         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
2953         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2954         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2955         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2956         [EXIT_REASON_CPUID]                   = handle_cpuid,
2957         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2958         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2959         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2960         [EXIT_REASON_HLT]                     = handle_halt,
2961         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2962         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2963         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2964         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2965         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
2966         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
2967 };
2968
2969 static const int kvm_vmx_max_exit_handlers =
2970         ARRAY_SIZE(kvm_vmx_exit_handlers);
2971
2972 /*
2973  * The guest has exited.  See if we can fix it or if we need userspace
2974  * assistance.
2975  */
2976 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2977 {
2978         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2979         struct vcpu_vmx *vmx = to_vmx(vcpu);
2980         u32 vectoring_info = vmx->idt_vectoring_info;
2981
2982         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
2983                     (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2984
2985         /* Access CR3 don't cause VMExit in paging mode, so we need
2986          * to sync with guest real CR3. */
2987         if (vm_need_ept() && is_paging(vcpu)) {
2988                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2989                 ept_load_pdptrs(vcpu);
2990         }
2991
2992         if (unlikely(vmx->fail)) {
2993                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2994                 kvm_run->fail_entry.hardware_entry_failure_reason
2995                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2996                 return 0;
2997         }
2998
2999         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3000                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3001                         exit_reason != EXIT_REASON_EPT_VIOLATION))
3002                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
3003                        "exit reason is 0x%x\n", __func__, exit_reason);
3004         if (exit_reason < kvm_vmx_max_exit_handlers
3005             && kvm_vmx_exit_handlers[exit_reason])
3006                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3007         else {
3008                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3009                 kvm_run->hw.hardware_exit_reason = exit_reason;
3010         }
3011         return 0;
3012 }
3013
3014 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3015 {
3016         int max_irr, tpr;
3017
3018         if (!vm_need_tpr_shadow(vcpu->kvm))
3019                 return;
3020
3021         if (!kvm_lapic_enabled(vcpu) ||
3022             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3023                 vmcs_write32(TPR_THRESHOLD, 0);
3024                 return;
3025         }
3026
3027         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3028         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3029 }
3030
3031 static void enable_irq_window(struct kvm_vcpu *vcpu)
3032 {
3033         u32 cpu_based_vm_exec_control;
3034
3035         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3036         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3037         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3038 }
3039
3040 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3041 {
3042         u32 cpu_based_vm_exec_control;
3043
3044         if (!cpu_has_virtual_nmis())
3045                 return;
3046
3047         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3048         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3049         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3050 }
3051
3052 static int vmx_nmi_enabled(struct kvm_vcpu *vcpu)
3053 {
3054         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3055         return !(guest_intr & (GUEST_INTR_STATE_NMI |
3056                                GUEST_INTR_STATE_MOV_SS |
3057                                GUEST_INTR_STATE_STI));
3058 }
3059
3060 static int vmx_irq_enabled(struct kvm_vcpu *vcpu)
3061 {
3062         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3063         return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS |
3064                                GUEST_INTR_STATE_STI)) &&
3065                 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
3066 }
3067
3068 static void enable_intr_window(struct kvm_vcpu *vcpu)
3069 {
3070         if (vcpu->arch.nmi_pending)
3071                 enable_nmi_window(vcpu);
3072         else if (kvm_cpu_has_interrupt(vcpu))
3073                 enable_irq_window(vcpu);
3074 }
3075
3076 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3077 {
3078         u32 exit_intr_info;
3079         u32 idt_vectoring_info;
3080         bool unblock_nmi;
3081         u8 vector;
3082         int type;
3083         bool idtv_info_valid;
3084         u32 error;
3085
3086         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3087         if (cpu_has_virtual_nmis()) {
3088                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3089                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3090                 /*
3091                  * SDM 3: 25.7.1.2
3092                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3093                  * a guest IRET fault.
3094                  */
3095                 if (unblock_nmi && vector != DF_VECTOR)
3096                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3097                                       GUEST_INTR_STATE_NMI);
3098         }
3099
3100         idt_vectoring_info = vmx->idt_vectoring_info;
3101         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3102         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3103         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3104         if (vmx->vcpu.arch.nmi_injected) {
3105                 /*
3106                  * SDM 3: 25.7.1.2
3107                  * Clear bit "block by NMI" before VM entry if a NMI delivery
3108                  * faulted.
3109                  */
3110                 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3111                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3112                                         GUEST_INTR_STATE_NMI);
3113                 else
3114                         vmx->vcpu.arch.nmi_injected = false;
3115         }
3116         kvm_clear_exception_queue(&vmx->vcpu);
3117         if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) {
3118                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3119                         error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3120                         kvm_queue_exception_e(&vmx->vcpu, vector, error);
3121                 } else
3122                         kvm_queue_exception(&vmx->vcpu, vector);
3123                 vmx->idt_vectoring_info = 0;
3124         }
3125         kvm_clear_interrupt_queue(&vmx->vcpu);
3126         if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3127                 kvm_queue_interrupt(&vmx->vcpu, vector);
3128                 vmx->idt_vectoring_info = 0;
3129         }
3130 }
3131
3132 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3133 {
3134         update_tpr_threshold(vcpu);
3135
3136         if (cpu_has_virtual_nmis()) {
3137                 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3138                         if (vmx_nmi_enabled(vcpu)) {
3139                                 vcpu->arch.nmi_pending = false;
3140                                 vcpu->arch.nmi_injected = true;
3141                         } else {
3142                                 enable_intr_window(vcpu);
3143                                 return;
3144                         }
3145                 }
3146                 if (vcpu->arch.nmi_injected) {
3147                         vmx_inject_nmi(vcpu);
3148                         enable_intr_window(vcpu);
3149                         return;
3150                 }
3151         }
3152         if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3153                 if (vmx_irq_enabled(vcpu))
3154                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3155                 else
3156                         enable_irq_window(vcpu);
3157         }
3158         if (vcpu->arch.interrupt.pending) {
3159                 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3160                 kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr);
3161         }
3162 }
3163
3164 /*
3165  * Failure to inject an interrupt should give us the information
3166  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3167  * when fetching the interrupt redirection bitmap in the real-mode
3168  * tss, this doesn't happen.  So we do it ourselves.
3169  */
3170 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3171 {
3172         vmx->rmode.irq.pending = 0;
3173         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3174                 return;
3175         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3176         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3177                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3178                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3179                 return;
3180         }
3181         vmx->idt_vectoring_info =
3182                 VECTORING_INFO_VALID_MASK
3183                 | INTR_TYPE_EXT_INTR
3184                 | vmx->rmode.irq.vector;
3185 }
3186
3187 #ifdef CONFIG_X86_64
3188 #define R "r"
3189 #define Q "q"
3190 #else
3191 #define R "e"
3192 #define Q "l"
3193 #endif
3194
3195 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3196 {
3197         struct vcpu_vmx *vmx = to_vmx(vcpu);
3198         u32 intr_info;
3199
3200         /* Handle invalid guest state instead of entering VMX */
3201         if (vmx->emulation_required && emulate_invalid_guest_state) {
3202                 handle_invalid_guest_state(vcpu, kvm_run);
3203                 return;
3204         }
3205
3206         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3207                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3208         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3209                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3210
3211         /*
3212          * Loading guest fpu may have cleared host cr0.ts
3213          */
3214         vmcs_writel(HOST_CR0, read_cr0());
3215
3216         asm(
3217                 /* Store host registers */
3218                 "push %%"R"dx; push %%"R"bp;"
3219                 "push %%"R"cx \n\t"
3220                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3221                 "je 1f \n\t"
3222                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3223                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3224                 "1: \n\t"
3225                 /* Check if vmlaunch of vmresume is needed */
3226                 "cmpl $0, %c[launched](%0) \n\t"
3227                 /* Load guest registers.  Don't clobber flags. */
3228                 "mov %c[cr2](%0), %%"R"ax \n\t"
3229                 "mov %%"R"ax, %%cr2 \n\t"
3230                 "mov %c[rax](%0), %%"R"ax \n\t"
3231                 "mov %c[rbx](%0), %%"R"bx \n\t"
3232                 "mov %c[rdx](%0), %%"R"dx \n\t"
3233                 "mov %c[rsi](%0), %%"R"si \n\t"
3234                 "mov %c[rdi](%0), %%"R"di \n\t"
3235                 "mov %c[rbp](%0), %%"R"bp \n\t"
3236 #ifdef CONFIG_X86_64
3237                 "mov %c[r8](%0),  %%r8  \n\t"
3238                 "mov %c[r9](%0),  %%r9  \n\t"
3239                 "mov %c[r10](%0), %%r10 \n\t"
3240                 "mov %c[r11](%0), %%r11 \n\t"
3241                 "mov %c[r12](%0), %%r12 \n\t"
3242                 "mov %c[r13](%0), %%r13 \n\t"
3243                 "mov %c[r14](%0), %%r14 \n\t"
3244                 "mov %c[r15](%0), %%r15 \n\t"
3245 #endif
3246                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3247
3248                 /* Enter guest mode */
3249                 "jne .Llaunched \n\t"
3250                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3251                 "jmp .Lkvm_vmx_return \n\t"
3252                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3253                 ".Lkvm_vmx_return: "
3254                 /* Save guest registers, load host registers, keep flags */
3255                 "xchg %0,     (%%"R"sp) \n\t"
3256                 "mov %%"R"ax, %c[rax](%0) \n\t"
3257                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3258                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3259                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3260                 "mov %%"R"si, %c[rsi](%0) \n\t"
3261                 "mov %%"R"di, %c[rdi](%0) \n\t"
3262                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3263 #ifdef CONFIG_X86_64
3264                 "mov %%r8,  %c[r8](%0) \n\t"
3265                 "mov %%r9,  %c[r9](%0) \n\t"
3266                 "mov %%r10, %c[r10](%0) \n\t"
3267                 "mov %%r11, %c[r11](%0) \n\t"
3268                 "mov %%r12, %c[r12](%0) \n\t"
3269                 "mov %%r13, %c[r13](%0) \n\t"
3270                 "mov %%r14, %c[r14](%0) \n\t"
3271                 "mov %%r15, %c[r15](%0) \n\t"
3272 #endif
3273                 "mov %%cr2, %%"R"ax   \n\t"
3274                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3275
3276                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3277                 "setbe %c[fail](%0) \n\t"
3278               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3279                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3280                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3281                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3282                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3283                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3284                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3285                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3286                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3287                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3288                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3289 #ifdef CONFIG_X86_64
3290                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3291                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3292                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3293                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3294                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3295                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3296                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3297                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3298 #endif
3299                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3300               : "cc", "memory"
3301                 , R"bx", R"di", R"si"
3302 #ifdef CONFIG_X86_64
3303                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3304 #endif
3305               );
3306
3307         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3308         vcpu->arch.regs_dirty = 0;
3309
3310         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3311         if (vmx->rmode.irq.pending)
3312                 fixup_rmode_irq(vmx);
3313
3314         vcpu->arch.interrupt_window_open =
3315                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3316                  (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0;
3317
3318         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3319         vmx->launched = 1;
3320
3321         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3322
3323         /* We need to handle NMIs before interrupts are enabled */
3324         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 &&
3325             (intr_info & INTR_INFO_VALID_MASK)) {
3326                 KVMTRACE_0D(NMI, vcpu, handler);
3327                 asm("int $2");
3328         }
3329
3330         vmx_complete_interrupts(vmx);
3331 }
3332
3333 #undef R
3334 #undef Q
3335
3336 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3337 {
3338         struct vcpu_vmx *vmx = to_vmx(vcpu);
3339
3340         if (vmx->vmcs) {
3341                 vcpu_clear(vmx);
3342                 free_vmcs(vmx->vmcs);
3343                 vmx->vmcs = NULL;
3344         }
3345 }
3346
3347 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3348 {
3349         struct vcpu_vmx *vmx = to_vmx(vcpu);
3350
3351         spin_lock(&vmx_vpid_lock);
3352         if (vmx->vpid != 0)
3353                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3354         spin_unlock(&vmx_vpid_lock);
3355         vmx_free_vmcs(vcpu);
3356         kfree(vmx->host_msrs);
3357         kfree(vmx->guest_msrs);
3358         kvm_vcpu_uninit(vcpu);
3359         kmem_cache_free(kvm_vcpu_cache, vmx);
3360 }
3361
3362 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3363 {
3364         int err;
3365         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3366         int cpu;
3367
3368         if (!vmx)
3369                 return ERR_PTR(-ENOMEM);
3370
3371         allocate_vpid(vmx);
3372
3373         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3374         if (err)
3375                 goto free_vcpu;
3376
3377         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3378         if (!vmx->guest_msrs) {
3379                 err = -ENOMEM;
3380                 goto uninit_vcpu;
3381         }
3382
3383         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3384         if (!vmx->host_msrs)
3385                 goto free_guest_msrs;
3386
3387         vmx->vmcs = alloc_vmcs();
3388         if (!vmx->vmcs)
3389                 goto free_msrs;
3390
3391         vmcs_clear(vmx->vmcs);
3392
3393         cpu = get_cpu();
3394         vmx_vcpu_load(&vmx->vcpu, cpu);
3395         err = vmx_vcpu_setup(vmx);
3396         vmx_vcpu_put(&vmx->vcpu);
3397         put_cpu();
3398         if (err)
3399                 goto free_vmcs;
3400         if (vm_need_virtualize_apic_accesses(kvm))
3401                 if (alloc_apic_access_page(kvm) != 0)
3402                         goto free_vmcs;
3403
3404         if (vm_need_ept())
3405                 if (alloc_identity_pagetable(kvm) != 0)
3406                         goto free_vmcs;
3407
3408         return &vmx->vcpu;
3409
3410 free_vmcs:
3411         free_vmcs(vmx->vmcs);
3412 free_msrs:
3413         kfree(vmx->host_msrs);
3414 free_guest_msrs:
3415         kfree(vmx->guest_msrs);
3416 uninit_vcpu:
3417         kvm_vcpu_uninit(&vmx->vcpu);
3418 free_vcpu:
3419         kmem_cache_free(kvm_vcpu_cache, vmx);
3420         return ERR_PTR(err);
3421 }
3422
3423 static void __init vmx_check_processor_compat(void *rtn)
3424 {
3425         struct vmcs_config vmcs_conf;
3426
3427         *(int *)rtn = 0;
3428         if (setup_vmcs_config(&vmcs_conf) < 0)
3429                 *(int *)rtn = -EIO;
3430         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3431                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3432                                 smp_processor_id());
3433                 *(int *)rtn = -EIO;
3434         }
3435 }
3436
3437 static int get_ept_level(void)
3438 {
3439         return VMX_EPT_DEFAULT_GAW + 1;
3440 }
3441
3442 static struct kvm_x86_ops vmx_x86_ops = {
3443         .cpu_has_kvm_support = cpu_has_kvm_support,
3444         .disabled_by_bios = vmx_disabled_by_bios,
3445         .hardware_setup = hardware_setup,
3446         .hardware_unsetup = hardware_unsetup,
3447         .check_processor_compatibility = vmx_check_processor_compat,
3448         .hardware_enable = hardware_enable,
3449         .hardware_disable = hardware_disable,
3450         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3451
3452         .vcpu_create = vmx_create_vcpu,
3453         .vcpu_free = vmx_free_vcpu,
3454         .vcpu_reset = vmx_vcpu_reset,
3455
3456         .prepare_guest_switch = vmx_save_host_state,
3457         .vcpu_load = vmx_vcpu_load,
3458         .vcpu_put = vmx_vcpu_put,
3459
3460         .set_guest_debug = set_guest_debug,
3461         .guest_debug_pre = kvm_guest_debug_pre,
3462         .get_msr = vmx_get_msr,
3463         .set_msr = vmx_set_msr,
3464         .get_segment_base = vmx_get_segment_base,
3465         .get_segment = vmx_get_segment,
3466         .set_segment = vmx_set_segment,
3467         .get_cpl = vmx_get_cpl,
3468         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3469         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3470         .set_cr0 = vmx_set_cr0,
3471         .set_cr3 = vmx_set_cr3,
3472         .set_cr4 = vmx_set_cr4,
3473         .set_efer = vmx_set_efer,
3474         .get_idt = vmx_get_idt,
3475         .set_idt = vmx_set_idt,
3476         .get_gdt = vmx_get_gdt,
3477         .set_gdt = vmx_set_gdt,
3478         .cache_reg = vmx_cache_reg,
3479         .get_rflags = vmx_get_rflags,
3480         .set_rflags = vmx_set_rflags,
3481
3482         .tlb_flush = vmx_flush_tlb,
3483
3484         .run = vmx_vcpu_run,
3485         .handle_exit = kvm_handle_exit,
3486         .skip_emulated_instruction = skip_emulated_instruction,
3487         .patch_hypercall = vmx_patch_hypercall,
3488         .get_irq = vmx_get_irq,
3489         .set_irq = vmx_inject_irq,
3490         .queue_exception = vmx_queue_exception,
3491         .exception_injected = vmx_exception_injected,
3492         .inject_pending_irq = vmx_intr_assist,
3493         .inject_pending_vectors = do_interrupt_requests,
3494
3495         .set_tss_addr = vmx_set_tss_addr,
3496         .get_tdp_level = get_ept_level,
3497 };
3498
3499 static int __init vmx_init(void)
3500 {
3501         void *va;
3502         int r;
3503
3504         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3505         if (!vmx_io_bitmap_a)
3506                 return -ENOMEM;
3507
3508         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3509         if (!vmx_io_bitmap_b) {
3510                 r = -ENOMEM;
3511                 goto out;
3512         }
3513
3514         vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3515         if (!vmx_msr_bitmap) {
3516                 r = -ENOMEM;
3517                 goto out1;
3518         }
3519
3520         /*
3521          * Allow direct access to the PC debug port (it is often used for I/O
3522          * delays, but the vmexits simply slow things down).
3523          */
3524         va = kmap(vmx_io_bitmap_a);
3525         memset(va, 0xff, PAGE_SIZE);
3526         clear_bit(0x80, va);
3527         kunmap(vmx_io_bitmap_a);
3528
3529         va = kmap(vmx_io_bitmap_b);
3530         memset(va, 0xff, PAGE_SIZE);
3531         kunmap(vmx_io_bitmap_b);
3532
3533         va = kmap(vmx_msr_bitmap);
3534         memset(va, 0xff, PAGE_SIZE);
3535         kunmap(vmx_msr_bitmap);
3536
3537         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3538
3539         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3540         if (r)
3541                 goto out2;
3542
3543         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3544         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3545         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3546         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3547         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3548
3549         if (vm_need_ept()) {
3550                 bypass_guest_pf = 0;
3551                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3552                         VMX_EPT_WRITABLE_MASK |
3553                         VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3554                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3555                                 VMX_EPT_EXECUTABLE_MASK);
3556                 kvm_enable_tdp();
3557         } else
3558                 kvm_disable_tdp();
3559
3560         if (bypass_guest_pf)
3561                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3562
3563         ept_sync_global();
3564
3565         return 0;
3566
3567 out2:
3568         __free_page(vmx_msr_bitmap);
3569 out1:
3570         __free_page(vmx_io_bitmap_b);
3571 out:
3572         __free_page(vmx_io_bitmap_a);
3573         return r;
3574 }
3575
3576 static void __exit vmx_exit(void)
3577 {
3578         __free_page(vmx_msr_bitmap);
3579         __free_page(vmx_io_bitmap_b);
3580         __free_page(vmx_io_bitmap_a);
3581
3582         kvm_exit();
3583 }
3584
3585 module_init(vmx_init)
3586 module_exit(vmx_exit)