arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  31
  32 MODULE_AUTHOR("Qumranet");
  33 MODULE_LICENSE("GPL");
  34
  35 #define IOPM_ALLOC_ORDER 2
  36 #define MSRPM_ALLOC_ORDER 1
  37
  38 #define DB_VECTOR 1
  39 #define UD_VECTOR 6
  40 #define GP_VECTOR 13
  41
  42 #define DR7_GD_MASK (1 << 13)
  43 #define DR6_BD_MASK (1 << 13)
  44
  45 #define SEG_TYPE_LDT 2
  46 #define SEG_TYPE_BUSY_TSS16 3
  47
  48 #define SVM_FEATURE_NPT  (1 << 0)
  49 #define SVM_FEATURE_LBRV (1 << 1)
  50 #define SVM_DEATURE_SVML (1 << 2)
  51
  52 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  53
  54 /* enable NPT for AMD64 and X86 with PAE */
  55 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  56 static bool npt_enabled = true;
  57 #else
  58 static bool npt_enabled = false;
  59 #endif
  60 static int npt = 1;
  61
  62 module_param(npt, int, S_IRUGO);
  63
  64 static void kvm_reput_irq(struct vcpu_svm *svm);
  65
  66 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  67 {
  68         return container_of(vcpu, struct vcpu_svm, vcpu);
  69 }
  70
  71 static unsigned long iopm_base;
  72
  73 struct kvm_ldttss_desc {
  74         u16 limit0;
  75         u16 base0;
  76         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  77         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  78         u32 base3;
  79         u32 zero1;
  80 } __attribute__((packed));
  81
  82 struct svm_cpu_data {
  83         int cpu;
  84
  85         u64 asid_generation;
  86         u32 max_asid;
  87         u32 next_asid;
  88         struct kvm_ldttss_desc *tss_desc;
  89
  90         struct page *save_area;
  91 };
  92
  93 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  94 static uint32_t svm_features;
  95
  96 struct svm_init_data {
  97         int cpu;
  98         int r;
  99 };
 100
 101 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 102
 103 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 104 #define MSRS_RANGE_SIZE 2048
 105 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 106
 107 #define MAX_INST_SIZE 15
 108
 109 static inline u32 svm_has(u32 feat)
 110 {
 111         return svm_features & feat;
 112 }
 113
 114 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 115 {
 116         int word_index = __ffs(vcpu->arch.irq_summary);
 117         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 118         int irq = word_index * BITS_PER_LONG + bit_index;
 119
 120         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 121         if (!vcpu->arch.irq_pending[word_index])
 122                 clear_bit(word_index, &vcpu->arch.irq_summary);
 123         return irq;
 124 }
 125
 126 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 127 {
 128         set_bit(irq, vcpu->arch.irq_pending);
 129         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 130 }
 131
 132 static inline void clgi(void)
 133 {
 134         asm volatile (__ex(SVM_CLGI));
 135 }
 136
 137 static inline void stgi(void)
 138 {
 139         asm volatile (__ex(SVM_STGI));
 140 }
 141
 142 static inline void invlpga(unsigned long addr, u32 asid)
 143 {
 144         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 145 }
 146
 147 static inline unsigned long kvm_read_cr2(void)
 148 {
 149         unsigned long cr2;
 150
 151         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 152         return cr2;
 153 }
 154
 155 static inline void kvm_write_cr2(unsigned long val)
 156 {
 157         asm volatile ("mov %0, %%cr2" :: "r" (val));
 158 }
 159
 160 static inline unsigned long read_dr6(void)
 161 {
 162         unsigned long dr6;
 163
 164         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 165         return dr6;
 166 }
 167
 168 static inline void write_dr6(unsigned long val)
 169 {
 170         asm volatile ("mov %0, %%dr6" :: "r" (val));
 171 }
 172
 173 static inline unsigned long read_dr7(void)
 174 {
 175         unsigned long dr7;
 176
 177         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 178         return dr7;
 179 }
 180
 181 static inline void write_dr7(unsigned long val)
 182 {
 183         asm volatile ("mov %0, %%dr7" :: "r" (val));
 184 }
 185
 186 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 187 {
 188         to_svm(vcpu)->asid_generation--;
 189 }
 190
 191 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 192 {
 193         force_new_asid(vcpu);
 194 }
 195
 196 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 197 {
 198         if (!npt_enabled && !(efer & EFER_LMA))
 199                 efer &= ~EFER_LME;
 200
 201         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 202         vcpu->arch.shadow_efer = efer;
 203 }
 204
 205 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 206                                 bool has_error_code, u32 error_code)
 207 {
 208         struct vcpu_svm *svm = to_svm(vcpu);
 209
 210         svm->vmcb->control.event_inj = nr
 211                 | SVM_EVTINJ_VALID
 212                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 213                 | SVM_EVTINJ_TYPE_EXEPT;
 214         svm->vmcb->control.event_inj_err = error_code;
 215 }
 216
 217 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 218 {
 219         struct vcpu_svm *svm = to_svm(vcpu);
 220
 221         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 222 }
 223
 224 static int is_external_interrupt(u32 info)
 225 {
 226         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 227         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 228 }
 229
 230 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 231 {
 232         struct vcpu_svm *svm = to_svm(vcpu);
 233
 234         if (!svm->next_rip) {
 235                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 236                 return;
 237         }
 238         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 239                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 240                        __func__,
 241                        svm->vmcb->save.rip,
 242                        svm->next_rip);
 243
 244         vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 245         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 246
 247         vcpu->arch.interrupt_window_open = 1;
 248 }
 249
 250 static int has_svm(void)
 251 {
 252         uint32_t eax, ebx, ecx, edx;
 253
 254         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 255                 printk(KERN_INFO "has_svm: not amd\n");
 256                 return 0;
 257         }
 258
 259         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 260         if (eax < SVM_CPUID_FUNC) {
 261                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 262                 return 0;
 263         }
 264
 265         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 266         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 267                 printk(KERN_DEBUG "has_svm: svm not available\n");
 268                 return 0;
 269         }
 270         return 1;
 271 }
 272
 273 static void svm_hardware_disable(void *garbage)
 274 {
 275         uint64_t efer;
 276
 277         wrmsrl(MSR_VM_HSAVE_PA, 0);
 278         rdmsrl(MSR_EFER, efer);
 279         wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 280 }
 281
 282 static void svm_hardware_enable(void *garbage)
 283 {
 284
 285         struct svm_cpu_data *svm_data;
 286         uint64_t efer;
 287         struct desc_ptr gdt_descr;
 288         struct desc_struct *gdt;
 289         int me = raw_smp_processor_id();
 290
 291         if (!has_svm()) {
 292                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 293                 return;
 294         }
 295         svm_data = per_cpu(svm_data, me);
 296
 297         if (!svm_data) {
 298                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 299                        me);
 300                 return;
 301         }
 302
 303         svm_data->asid_generation = 1;
 304         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 305         svm_data->next_asid = svm_data->max_asid + 1;
 306
 307         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 308         gdt = (struct desc_struct *)gdt_descr.address;
 309         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 310
 311         rdmsrl(MSR_EFER, efer);
 312         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 313
 314         wrmsrl(MSR_VM_HSAVE_PA,
 315                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 316 }
 317
 318 static void svm_cpu_uninit(int cpu)
 319 {
 320         struct svm_cpu_data *svm_data
 321                 = per_cpu(svm_data, raw_smp_processor_id());
 322
 323         if (!svm_data)
 324                 return;
 325
 326         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 327         __free_page(svm_data->save_area);
 328         kfree(svm_data);
 329 }
 330
 331 static int svm_cpu_init(int cpu)
 332 {
 333         struct svm_cpu_data *svm_data;
 334         int r;
 335
 336         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 337         if (!svm_data)
 338                 return -ENOMEM;
 339         svm_data->cpu = cpu;
 340         svm_data->save_area = alloc_page(GFP_KERNEL);
 341         r = -ENOMEM;
 342         if (!svm_data->save_area)
 343                 goto err_1;
 344
 345         per_cpu(svm_data, cpu) = svm_data;
 346
 347         return 0;
 348
 349 err_1:
 350         kfree(svm_data);
 351         return r;
 352
 353 }
 354
 355 static void set_msr_interception(u32 *msrpm, unsigned msr,
 356                                  int read, int write)
 357 {
 358         int i;
 359
 360         for (i = 0; i < NUM_MSR_MAPS; i++) {
 361                 if (msr >= msrpm_ranges[i] &&
 362                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 363                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 364                                           msrpm_ranges[i]) * 2;
 365
 366                         u32 *base = msrpm + (msr_offset / 32);
 367                         u32 msr_shift = msr_offset % 32;
 368                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 369                         *base = (*base & ~(0x3 << msr_shift)) |
 370                                 (mask << msr_shift);
 371                         return;
 372                 }
 373         }
 374         BUG();
 375 }
 376
 377 static void svm_vcpu_init_msrpm(u32 *msrpm)
 378 {
 379         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 380
 381 #ifdef CONFIG_X86_64
 382         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 383         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 384         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 385         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 386         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 387         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 388 #endif
 389         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 390         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 391         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 392         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 393 }
 394
 395 static void svm_enable_lbrv(struct vcpu_svm *svm)
 396 {
 397         u32 *msrpm = svm->msrpm;
 398
 399         svm->vmcb->control.lbr_ctl = 1;
 400         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 401         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 402         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 403         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 404 }
 405
 406 static void svm_disable_lbrv(struct vcpu_svm *svm)
 407 {
 408         u32 *msrpm = svm->msrpm;
 409
 410         svm->vmcb->control.lbr_ctl = 0;
 411         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 412         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 413         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 414         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 415 }
 416
 417 static __init int svm_hardware_setup(void)
 418 {
 419         int cpu;
 420         struct page *iopm_pages;
 421         void *iopm_va;
 422         int r;
 423
 424         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 425
 426         if (!iopm_pages)
 427                 return -ENOMEM;
 428
 429         iopm_va = page_address(iopm_pages);
 430         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 431         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 432         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 433
 434         if (boot_cpu_has(X86_FEATURE_NX))
 435                 kvm_enable_efer_bits(EFER_NX);
 436
 437         for_each_online_cpu(cpu) {
 438                 r = svm_cpu_init(cpu);
 439                 if (r)
 440                         goto err;
 441         }
 442
 443         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 444
 445         if (!svm_has(SVM_FEATURE_NPT))
 446                 npt_enabled = false;
 447
 448         if (npt_enabled && !npt) {
 449                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 450                 npt_enabled = false;
 451         }
 452
 453         if (npt_enabled) {
 454                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 455                 kvm_enable_tdp();
 456         } else
 457                 kvm_disable_tdp();
 458
 459         return 0;
 460
 461 err:
 462         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 463         iopm_base = 0;
 464         return r;
 465 }
 466
 467 static __exit void svm_hardware_unsetup(void)
 468 {
 469         int cpu;
 470
 471         for_each_online_cpu(cpu)
 472                 svm_cpu_uninit(cpu);
 473
 474         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 475         iopm_base = 0;
 476 }
 477
 478 static void init_seg(struct vmcb_seg *seg)
 479 {
 480         seg->selector = 0;
 481         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 482                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 483         seg->limit = 0xffff;
 484         seg->base = 0;
 485 }
 486
 487 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 488 {
 489         seg->selector = 0;
 490         seg->attrib = SVM_SELECTOR_P_MASK | type;
 491         seg->limit = 0xffff;
 492         seg->base = 0;
 493 }
 494
 495 static void init_vmcb(struct vcpu_svm *svm)
 496 {
 497         struct vmcb_control_area *control = &svm->vmcb->control;
 498         struct vmcb_save_area *save = &svm->vmcb->save;
 499
 500         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 501                                         INTERCEPT_CR3_MASK |
 502                                         INTERCEPT_CR4_MASK;
 503
 504         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 505                                         INTERCEPT_CR3_MASK |
 506                                         INTERCEPT_CR4_MASK |
 507                                         INTERCEPT_CR8_MASK;
 508
 509         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 510                                         INTERCEPT_DR1_MASK |
 511                                         INTERCEPT_DR2_MASK |
 512                                         INTERCEPT_DR3_MASK;
 513
 514         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 515                                         INTERCEPT_DR1_MASK |
 516                                         INTERCEPT_DR2_MASK |
 517                                         INTERCEPT_DR3_MASK |
 518                                         INTERCEPT_DR5_MASK |
 519                                         INTERCEPT_DR7_MASK;
 520
 521         control->intercept_exceptions = (1 << PF_VECTOR) |
 522                                         (1 << UD_VECTOR) |
 523                                         (1 << MC_VECTOR);
 524
 525
 526         control->intercept =    (1ULL << INTERCEPT_INTR) |
 527                                 (1ULL << INTERCEPT_NMI) |
 528                                 (1ULL << INTERCEPT_SMI) |
 529                                 (1ULL << INTERCEPT_CPUID) |
 530                                 (1ULL << INTERCEPT_INVD) |
 531                                 (1ULL << INTERCEPT_HLT) |
 532                                 (1ULL << INTERCEPT_INVLPGA) |
 533                                 (1ULL << INTERCEPT_IOIO_PROT) |
 534                                 (1ULL << INTERCEPT_MSR_PROT) |
 535                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 536                                 (1ULL << INTERCEPT_SHUTDOWN) |
 537                                 (1ULL << INTERCEPT_VMRUN) |
 538                                 (1ULL << INTERCEPT_VMMCALL) |
 539                                 (1ULL << INTERCEPT_VMLOAD) |
 540                                 (1ULL << INTERCEPT_VMSAVE) |
 541                                 (1ULL << INTERCEPT_STGI) |
 542                                 (1ULL << INTERCEPT_CLGI) |
 543                                 (1ULL << INTERCEPT_SKINIT) |
 544                                 (1ULL << INTERCEPT_WBINVD) |
 545                                 (1ULL << INTERCEPT_MONITOR) |
 546                                 (1ULL << INTERCEPT_MWAIT);
 547
 548         control->iopm_base_pa = iopm_base;
 549         control->msrpm_base_pa = __pa(svm->msrpm);
 550         control->tsc_offset = 0;
 551         control->int_ctl = V_INTR_MASKING_MASK;
 552
 553         init_seg(&save->es);
 554         init_seg(&save->ss);
 555         init_seg(&save->ds);
 556         init_seg(&save->fs);
 557         init_seg(&save->gs);
 558
 559         save->cs.selector = 0xf000;
 560         /* Executable/Readable Code Segment */
 561         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 562                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 563         save->cs.limit = 0xffff;
 564         /*
 565          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 566          * be consistent with it.
 567          *
 568          * Replace when we have real mode working for vmx.
 569          */
 570         save->cs.base = 0xf0000;
 571
 572         save->gdtr.limit = 0xffff;
 573         save->idtr.limit = 0xffff;
 574
 575         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 576         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 577
 578         save->efer = MSR_EFER_SVME_MASK;
 579         save->dr6 = 0xffff0ff0;
 580         save->dr7 = 0x400;
 581         save->rflags = 2;
 582         save->rip = 0x0000fff0;
 583
 584         /*
 585          * cr0 val on cpu init should be 0x60000010, we enable cpu
 586          * cache by default. the orderly way is to enable cache in bios.
 587          */
 588         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 589         save->cr4 = X86_CR4_PAE;
 590         /* rdx = ?? */
 591
 592         if (npt_enabled) {
 593                 /* Setup VMCB for Nested Paging */
 594                 control->nested_ctl = 1;
 595                 control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH);
 596                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 597                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 598                                                 INTERCEPT_CR3_MASK);
 599                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 600                                                  INTERCEPT_CR3_MASK);
 601                 save->g_pat = 0x0007040600070406ULL;
 602                 /* enable caching because the QEMU Bios doesn't enable it */
 603                 save->cr0 = X86_CR0_ET;
 604                 save->cr3 = 0;
 605                 save->cr4 = 0;
 606         }
 607         force_new_asid(&svm->vcpu);
 608 }
 609
 610 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 611 {
 612         struct vcpu_svm *svm = to_svm(vcpu);
 613
 614         init_vmcb(svm);
 615
 616         if (vcpu->vcpu_id != 0) {
 617                 svm->vmcb->save.rip = 0;
 618                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 619                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 620         }
 621
 622         return 0;
 623 }
 624
 625 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 626 {
 627         struct vcpu_svm *svm;
 628         struct page *page;
 629         struct page *msrpm_pages;
 630         int err;
 631
 632         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 633         if (!svm) {
 634                 err = -ENOMEM;
 635                 goto out;
 636         }
 637
 638         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 639         if (err)
 640                 goto free_svm;
 641
 642         page = alloc_page(GFP_KERNEL);
 643         if (!page) {
 644                 err = -ENOMEM;
 645                 goto uninit;
 646         }
 647
 648         err = -ENOMEM;
 649         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 650         if (!msrpm_pages)
 651                 goto uninit;
 652         svm->msrpm = page_address(msrpm_pages);
 653         svm_vcpu_init_msrpm(svm->msrpm);
 654
 655         svm->vmcb = page_address(page);
 656         clear_page(svm->vmcb);
 657         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 658         svm->asid_generation = 0;
 659         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 660         init_vmcb(svm);
 661
 662         fx_init(&svm->vcpu);
 663         svm->vcpu.fpu_active = 1;
 664         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 665         if (svm->vcpu.vcpu_id == 0)
 666                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 667
 668         return &svm->vcpu;
 669
 670 uninit:
 671         kvm_vcpu_uninit(&svm->vcpu);
 672 free_svm:
 673         kmem_cache_free(kvm_vcpu_cache, svm);
 674 out:
 675         return ERR_PTR(err);
 676 }
 677
 678 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 679 {
 680         struct vcpu_svm *svm = to_svm(vcpu);
 681
 682         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 683         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 684         kvm_vcpu_uninit(vcpu);
 685         kmem_cache_free(kvm_vcpu_cache, svm);
 686 }
 687
 688 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 689 {
 690         struct vcpu_svm *svm = to_svm(vcpu);
 691         int i;
 692
 693         if (unlikely(cpu != vcpu->cpu)) {
 694                 u64 tsc_this, delta;
 695
 696                 /*
 697                  * Make sure that the guest sees a monotonically
 698                  * increasing TSC.
 699                  */
 700                 rdtscll(tsc_this);
 701                 delta = vcpu->arch.host_tsc - tsc_this;
 702                 svm->vmcb->control.tsc_offset += delta;
 703                 vcpu->cpu = cpu;
 704                 kvm_migrate_timers(vcpu);
 705         }
 706
 707         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 708                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 709 }
 710
 711 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 712 {
 713         struct vcpu_svm *svm = to_svm(vcpu);
 714         int i;
 715
 716         ++vcpu->stat.host_state_reload;
 717         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 718                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 719
 720         rdtscll(vcpu->arch.host_tsc);
 721 }
 722
 723 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 724 {
 725         struct vcpu_svm *svm = to_svm(vcpu);
 726
 727         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 728         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 729         vcpu->arch.rip = svm->vmcb->save.rip;
 730 }
 731
 732 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 733 {
 734         struct vcpu_svm *svm = to_svm(vcpu);
 735         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 736         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 737         svm->vmcb->save.rip = vcpu->arch.rip;
 738 }
 739
 740 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 741 {
 742         return to_svm(vcpu)->vmcb->save.rflags;
 743 }
 744
 745 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 746 {
 747         to_svm(vcpu)->vmcb->save.rflags = rflags;
 748 }
 749
 750 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 751 {
 752         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 753
 754         switch (seg) {
 755         case VCPU_SREG_CS: return &save->cs;
 756         case VCPU_SREG_DS: return &save->ds;
 757         case VCPU_SREG_ES: return &save->es;
 758         case VCPU_SREG_FS: return &save->fs;
 759         case VCPU_SREG_GS: return &save->gs;
 760         case VCPU_SREG_SS: return &save->ss;
 761         case VCPU_SREG_TR: return &save->tr;
 762         case VCPU_SREG_LDTR: return &save->ldtr;
 763         }
 764         BUG();
 765         return NULL;
 766 }
 767
 768 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 769 {
 770         struct vmcb_seg *s = svm_seg(vcpu, seg);
 771
 772         return s->base;
 773 }
 774
 775 static void svm_get_segment(struct kvm_vcpu *vcpu,
 776                             struct kvm_segment *var, int seg)
 777 {
 778         struct vmcb_seg *s = svm_seg(vcpu, seg);
 779
 780         var->base = s->base;
 781         var->limit = s->limit;
 782         var->selector = s->selector;
 783         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 784         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 785         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 786         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 787         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 788         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 789         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 790         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 791         var->unusable = !var->present;
 792 }
 793
 794 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 795 {
 796         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 797
 798         return save->cpl;
 799 }
 800
 801 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 802 {
 803         struct vcpu_svm *svm = to_svm(vcpu);
 804
 805         dt->limit = svm->vmcb->save.idtr.limit;
 806         dt->base = svm->vmcb->save.idtr.base;
 807 }
 808
 809 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 810 {
 811         struct vcpu_svm *svm = to_svm(vcpu);
 812
 813         svm->vmcb->save.idtr.limit = dt->limit;
 814         svm->vmcb->save.idtr.base = dt->base ;
 815 }
 816
 817 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 818 {
 819         struct vcpu_svm *svm = to_svm(vcpu);
 820
 821         dt->limit = svm->vmcb->save.gdtr.limit;
 822         dt->base = svm->vmcb->save.gdtr.base;
 823 }
 824
 825 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 826 {
 827         struct vcpu_svm *svm = to_svm(vcpu);
 828
 829         svm->vmcb->save.gdtr.limit = dt->limit;
 830         svm->vmcb->save.gdtr.base = dt->base ;
 831 }
 832
 833 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 834 {
 835 }
 836
 837 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 838 {
 839         struct vcpu_svm *svm = to_svm(vcpu);
 840
 841 #ifdef CONFIG_X86_64
 842         if (vcpu->arch.shadow_efer & EFER_LME) {
 843                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 844                         vcpu->arch.shadow_efer |= EFER_LMA;
 845                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 846                 }
 847
 848                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 849                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 850                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 851                 }
 852         }
 853 #endif
 854         if (npt_enabled)
 855                 goto set;
 856
 857         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 858                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 859                 vcpu->fpu_active = 1;
 860         }
 861
 862         vcpu->arch.cr0 = cr0;
 863         cr0 |= X86_CR0_PG | X86_CR0_WP;
 864         if (!vcpu->fpu_active) {
 865                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 866                 cr0 |= X86_CR0_TS;
 867         }
 868 set:
 869         /*
 870          * re-enable caching here because the QEMU bios
 871          * does not do it - this results in some delay at
 872          * reboot
 873          */
 874         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 875         svm->vmcb->save.cr0 = cr0;
 876 }
 877
 878 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 879 {
 880         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 881
 882         vcpu->arch.cr4 = cr4;
 883         if (!npt_enabled)
 884                 cr4 |= X86_CR4_PAE;
 885         cr4 |= host_cr4_mce;
 886         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 887 }
 888
 889 static void svm_set_segment(struct kvm_vcpu *vcpu,
 890                             struct kvm_segment *var, int seg)
 891 {
 892         struct vcpu_svm *svm = to_svm(vcpu);
 893         struct vmcb_seg *s = svm_seg(vcpu, seg);
 894
 895         s->base = var->base;
 896         s->limit = var->limit;
 897         s->selector = var->selector;
 898         if (var->unusable)
 899                 s->attrib = 0;
 900         else {
 901                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 902                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 903                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 904                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 905                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 906                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 907                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 908                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 909         }
 910         if (seg == VCPU_SREG_CS)
 911                 svm->vmcb->save.cpl
 912                         = (svm->vmcb->save.cs.attrib
 913                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 914
 915 }
 916
 917 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 918 {
 919         return -EOPNOTSUPP;
 920 }
 921
 922 static int svm_get_irq(struct kvm_vcpu *vcpu)
 923 {
 924         struct vcpu_svm *svm = to_svm(vcpu);
 925         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 926
 927         if (is_external_interrupt(exit_int_info))
 928                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 929         return -1;
 930 }
 931
 932 static void load_host_msrs(struct kvm_vcpu *vcpu)
 933 {
 934 #ifdef CONFIG_X86_64
 935         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 936 #endif
 937 }
 938
 939 static void save_host_msrs(struct kvm_vcpu *vcpu)
 940 {
 941 #ifdef CONFIG_X86_64
 942         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 943 #endif
 944 }
 945
 946 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 947 {
 948         if (svm_data->next_asid > svm_data->max_asid) {
 949                 ++svm_data->asid_generation;
 950                 svm_data->next_asid = 1;
 951                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 952         }
 953
 954         svm->vcpu.cpu = svm_data->cpu;
 955         svm->asid_generation = svm_data->asid_generation;
 956         svm->vmcb->control.asid = svm_data->next_asid++;
 957 }
 958
 959 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 960 {
 961         unsigned long val = to_svm(vcpu)->db_regs[dr];
 962         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 963         return val;
 964 }
 965
 966 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 967                        int *exception)
 968 {
 969         struct vcpu_svm *svm = to_svm(vcpu);
 970
 971         *exception = 0;
 972
 973         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 974                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 975                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 976                 *exception = DB_VECTOR;
 977                 return;
 978         }
 979
 980         switch (dr) {
 981         case 0 ... 3:
 982                 svm->db_regs[dr] = value;
 983                 return;
 984         case 4 ... 5:
 985                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 986                         *exception = UD_VECTOR;
 987                         return;
 988                 }
 989         case 7: {
 990                 if (value & ~((1ULL << 32) - 1)) {
 991                         *exception = GP_VECTOR;
 992                         return;
 993                 }
 994                 svm->vmcb->save.dr7 = value;
 995                 return;
 996         }
 997         default:
 998                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 999                        __func__, dr);
1000                 *exception = UD_VECTOR;
1001                 return;
1002         }
1003 }
1004
1005 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1006 {
1007         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1008         struct kvm *kvm = svm->vcpu.kvm;
1009         u64 fault_address;
1010         u32 error_code;
1011
1012         if (!irqchip_in_kernel(kvm) &&
1013                 is_external_interrupt(exit_int_info))
1014                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1015
1016         fault_address  = svm->vmcb->control.exit_info_2;
1017         error_code = svm->vmcb->control.exit_info_1;
1018
1019         if (!npt_enabled)
1020                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1021                             (u32)fault_address, (u32)(fault_address >> 32),
1022                             handler);
1023         else
1024                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1025                             (u32)fault_address, (u32)(fault_address >> 32),
1026                             handler);
1027
1028         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1029 }
1030
1031 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1032 {
1033         int er;
1034
1035         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1036         if (er != EMULATE_DONE)
1037                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1038         return 1;
1039 }
1040
1041 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1042 {
1043         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1044         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1045                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1046         svm->vcpu.fpu_active = 1;
1047
1048         return 1;
1049 }
1050
1051 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1052 {
1053         /*
1054          * On an #MC intercept the MCE handler is not called automatically in
1055          * the host. So do it by hand here.
1056          */
1057         asm volatile (
1058                 "int $0x12\n");
1059         /* not sure if we ever come back to this point */
1060
1061         return 1;
1062 }
1063
1064 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1065 {
1066         /*
1067          * VMCB is undefined after a SHUTDOWN intercept
1068          * so reinitialize it.
1069          */
1070         clear_page(svm->vmcb);
1071         init_vmcb(svm);
1072
1073         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1074         return 0;
1075 }
1076
1077 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1078 {
1079         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1080         int size, down, in, string, rep;
1081         unsigned port;
1082
1083         ++svm->vcpu.stat.io_exits;
1084
1085         svm->next_rip = svm->vmcb->control.exit_info_2;
1086
1087         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1088
1089         if (string) {
1090                 if (emulate_instruction(&svm->vcpu,
1091                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1092                         return 0;
1093                 return 1;
1094         }
1095
1096         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1097         port = io_info >> 16;
1098         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1099         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1100         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1101
1102         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1103 }
1104
1105 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1106 {
1107         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1108         return 1;
1109 }
1110
1111 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1112 {
1113         ++svm->vcpu.stat.irq_exits;
1114         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1115         return 1;
1116 }
1117
1118 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1119 {
1120         return 1;
1121 }
1122
1123 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1124 {
1125         svm->next_rip = svm->vmcb->save.rip + 1;
1126         skip_emulated_instruction(&svm->vcpu);
1127         return kvm_emulate_halt(&svm->vcpu);
1128 }
1129
1130 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1131 {
1132         svm->next_rip = svm->vmcb->save.rip + 3;
1133         skip_emulated_instruction(&svm->vcpu);
1134         kvm_emulate_hypercall(&svm->vcpu);
1135         return 1;
1136 }
1137
1138 static int invalid_op_interception(struct vcpu_svm *svm,
1139                                    struct kvm_run *kvm_run)
1140 {
1141         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1142         return 1;
1143 }
1144
1145 static int task_switch_interception(struct vcpu_svm *svm,
1146                                     struct kvm_run *kvm_run)
1147 {
1148         u16 tss_selector;
1149
1150         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1151         if (svm->vmcb->control.exit_info_2 &
1152             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1153                 return kvm_task_switch(&svm->vcpu, tss_selector,
1154                                        TASK_SWITCH_IRET);
1155         if (svm->vmcb->control.exit_info_2 &
1156             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1157                 return kvm_task_switch(&svm->vcpu, tss_selector,
1158                                        TASK_SWITCH_JMP);
1159         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1160 }
1161
1162 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1163 {
1164         svm->next_rip = svm->vmcb->save.rip + 2;
1165         kvm_emulate_cpuid(&svm->vcpu);
1166         return 1;
1167 }
1168
1169 static int emulate_on_interception(struct vcpu_svm *svm,
1170                                    struct kvm_run *kvm_run)
1171 {
1172         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1173                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1174         return 1;
1175 }
1176
1177 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1178 {
1179         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1180         if (irqchip_in_kernel(svm->vcpu.kvm))
1181                 return 1;
1182         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1183         return 0;
1184 }
1185
1186 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1187 {
1188         struct vcpu_svm *svm = to_svm(vcpu);
1189
1190         switch (ecx) {
1191         case MSR_IA32_TIME_STAMP_COUNTER: {
1192                 u64 tsc;
1193
1194                 rdtscll(tsc);
1195                 *data = svm->vmcb->control.tsc_offset + tsc;
1196                 break;
1197         }
1198         case MSR_K6_STAR:
1199                 *data = svm->vmcb->save.star;
1200                 break;
1201 #ifdef CONFIG_X86_64
1202         case MSR_LSTAR:
1203                 *data = svm->vmcb->save.lstar;
1204                 break;
1205         case MSR_CSTAR:
1206                 *data = svm->vmcb->save.cstar;
1207                 break;
1208         case MSR_KERNEL_GS_BASE:
1209                 *data = svm->vmcb->save.kernel_gs_base;
1210                 break;
1211         case MSR_SYSCALL_MASK:
1212                 *data = svm->vmcb->save.sfmask;
1213                 break;
1214 #endif
1215         case MSR_IA32_SYSENTER_CS:
1216                 *data = svm->vmcb->save.sysenter_cs;
1217                 break;
1218         case MSR_IA32_SYSENTER_EIP:
1219                 *data = svm->vmcb->save.sysenter_eip;
1220                 break;
1221         case MSR_IA32_SYSENTER_ESP:
1222                 *data = svm->vmcb->save.sysenter_esp;
1223                 break;
1224         /* Nobody will change the following 5 values in the VMCB so
1225            we can safely return them on rdmsr. They will always be 0
1226            until LBRV is implemented. */
1227         case MSR_IA32_DEBUGCTLMSR:
1228                 *data = svm->vmcb->save.dbgctl;
1229                 break;
1230         case MSR_IA32_LASTBRANCHFROMIP:
1231                 *data = svm->vmcb->save.br_from;
1232                 break;
1233         case MSR_IA32_LASTBRANCHTOIP:
1234                 *data = svm->vmcb->save.br_to;
1235                 break;
1236         case MSR_IA32_LASTINTFROMIP:
1237                 *data = svm->vmcb->save.last_excp_from;
1238                 break;
1239         case MSR_IA32_LASTINTTOIP:
1240                 *data = svm->vmcb->save.last_excp_to;
1241                 break;
1242         default:
1243                 return kvm_get_msr_common(vcpu, ecx, data);
1244         }
1245         return 0;
1246 }
1247
1248 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1249 {
1250         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1251         u64 data;
1252
1253         if (svm_get_msr(&svm->vcpu, ecx, &data))
1254                 kvm_inject_gp(&svm->vcpu, 0);
1255         else {
1256                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1257                             (u32)(data >> 32), handler);
1258
1259                 svm->vmcb->save.rax = data & 0xffffffff;
1260                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1261                 svm->next_rip = svm->vmcb->save.rip + 2;
1262                 skip_emulated_instruction(&svm->vcpu);
1263         }
1264         return 1;
1265 }
1266
1267 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1268 {
1269         struct vcpu_svm *svm = to_svm(vcpu);
1270
1271         switch (ecx) {
1272         case MSR_IA32_TIME_STAMP_COUNTER: {
1273                 u64 tsc;
1274
1275                 rdtscll(tsc);
1276                 svm->vmcb->control.tsc_offset = data - tsc;
1277                 break;
1278         }
1279         case MSR_K6_STAR:
1280                 svm->vmcb->save.star = data;
1281                 break;
1282 #ifdef CONFIG_X86_64
1283         case MSR_LSTAR:
1284                 svm->vmcb->save.lstar = data;
1285                 break;
1286         case MSR_CSTAR:
1287                 svm->vmcb->save.cstar = data;
1288                 break;
1289         case MSR_KERNEL_GS_BASE:
1290                 svm->vmcb->save.kernel_gs_base = data;
1291                 break;
1292         case MSR_SYSCALL_MASK:
1293                 svm->vmcb->save.sfmask = data;
1294                 break;
1295 #endif
1296         case MSR_IA32_SYSENTER_CS:
1297                 svm->vmcb->save.sysenter_cs = data;
1298                 break;
1299         case MSR_IA32_SYSENTER_EIP:
1300                 svm->vmcb->save.sysenter_eip = data;
1301                 break;
1302         case MSR_IA32_SYSENTER_ESP:
1303                 svm->vmcb->save.sysenter_esp = data;
1304                 break;
1305         case MSR_IA32_DEBUGCTLMSR:
1306                 if (!svm_has(SVM_FEATURE_LBRV)) {
1307                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1308                                         __func__, data);
1309                         break;
1310                 }
1311                 if (data & DEBUGCTL_RESERVED_BITS)
1312                         return 1;
1313
1314                 svm->vmcb->save.dbgctl = data;
1315                 if (data & (1ULL<<0))
1316                         svm_enable_lbrv(svm);
1317                 else
1318                         svm_disable_lbrv(svm);
1319                 break;
1320         case MSR_K7_EVNTSEL0:
1321         case MSR_K7_EVNTSEL1:
1322         case MSR_K7_EVNTSEL2:
1323         case MSR_K7_EVNTSEL3:
1324         case MSR_K7_PERFCTR0:
1325         case MSR_K7_PERFCTR1:
1326         case MSR_K7_PERFCTR2:
1327         case MSR_K7_PERFCTR3:
1328                 /*
1329                  * Just discard all writes to the performance counters; this
1330                  * should keep both older linux and windows 64-bit guests
1331                  * happy
1332                  */
1333                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1334
1335                 break;
1336         default:
1337                 return kvm_set_msr_common(vcpu, ecx, data);
1338         }
1339         return 0;
1340 }
1341
1342 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1343 {
1344         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1345         u64 data = (svm->vmcb->save.rax & -1u)
1346                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1347
1348         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1349                     handler);
1350
1351         svm->next_rip = svm->vmcb->save.rip + 2;
1352         if (svm_set_msr(&svm->vcpu, ecx, data))
1353                 kvm_inject_gp(&svm->vcpu, 0);
1354         else
1355                 skip_emulated_instruction(&svm->vcpu);
1356         return 1;
1357 }
1358
1359 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1360 {
1361         if (svm->vmcb->control.exit_info_1)
1362                 return wrmsr_interception(svm, kvm_run);
1363         else
1364                 return rdmsr_interception(svm, kvm_run);
1365 }
1366
1367 static int interrupt_window_interception(struct vcpu_svm *svm,
1368                                    struct kvm_run *kvm_run)
1369 {
1370         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1371
1372         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1373         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1374         /*
1375          * If the user space waits to inject interrupts, exit as soon as
1376          * possible
1377          */
1378         if (kvm_run->request_interrupt_window &&
1379             !svm->vcpu.arch.irq_summary) {
1380                 ++svm->vcpu.stat.irq_window_exits;
1381                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1382                 return 0;
1383         }
1384
1385         return 1;
1386 }
1387
1388 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1389                                       struct kvm_run *kvm_run) = {
1390         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1391         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1392         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1393         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1394         /* for now: */
1395         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1396         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1397         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1398         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1399         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1400         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1401         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1402         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1403         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1404         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1405         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1406         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1407         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1408         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1409         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1410         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1411         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1412         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1413         [SVM_EXIT_INTR]                         = intr_interception,
1414         [SVM_EXIT_NMI]                          = nmi_interception,
1415         [SVM_EXIT_SMI]                          = nop_on_interception,
1416         [SVM_EXIT_INIT]                         = nop_on_interception,
1417         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1418         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1419         [SVM_EXIT_CPUID]                        = cpuid_interception,
1420         [SVM_EXIT_INVD]                         = emulate_on_interception,
1421         [SVM_EXIT_HLT]                          = halt_interception,
1422         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1423         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1424         [SVM_EXIT_IOIO]                         = io_interception,
1425         [SVM_EXIT_MSR]                          = msr_interception,
1426         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1427         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1428         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1429         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1430         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1431         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1432         [SVM_EXIT_STGI]                         = invalid_op_interception,
1433         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1434         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1435         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1436         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1437         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1438         [SVM_EXIT_NPF]                          = pf_interception,
1439 };
1440
1441 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1442 {
1443         struct vcpu_svm *svm = to_svm(vcpu);
1444         u32 exit_code = svm->vmcb->control.exit_code;
1445
1446         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1447                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1448
1449         if (npt_enabled) {
1450                 int mmu_reload = 0;
1451                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1452                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1453                         mmu_reload = 1;
1454                 }
1455                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1456                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1457                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1458                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1459                                 kvm_inject_gp(vcpu, 0);
1460                                 return 1;
1461                         }
1462                 }
1463                 if (mmu_reload) {
1464                         kvm_mmu_reset_context(vcpu);
1465                         kvm_mmu_load(vcpu);
1466                 }
1467         }
1468
1469         kvm_reput_irq(svm);
1470
1471         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1472                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1473                 kvm_run->fail_entry.hardware_entry_failure_reason
1474                         = svm->vmcb->control.exit_code;
1475                 return 0;
1476         }
1477
1478         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1479             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1480             exit_code != SVM_EXIT_NPF)
1481                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1482                        "exit_code 0x%x\n",
1483                        __func__, svm->vmcb->control.exit_int_info,
1484                        exit_code);
1485
1486         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1487             || !svm_exit_handlers[exit_code]) {
1488                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1489                 kvm_run->hw.hardware_exit_reason = exit_code;
1490                 return 0;
1491         }
1492
1493         return svm_exit_handlers[exit_code](svm, kvm_run);
1494 }
1495
1496 static void reload_tss(struct kvm_vcpu *vcpu)
1497 {
1498         int cpu = raw_smp_processor_id();
1499
1500         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1501         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1502         load_TR_desc();
1503 }
1504
1505 static void pre_svm_run(struct vcpu_svm *svm)
1506 {
1507         int cpu = raw_smp_processor_id();
1508
1509         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1510
1511         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1512         if (svm->vcpu.cpu != cpu ||
1513             svm->asid_generation != svm_data->asid_generation)
1514                 new_asid(svm, svm_data);
1515 }
1516
1517
1518 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1519 {
1520         struct vmcb_control_area *control;
1521
1522         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1523
1524         control = &svm->vmcb->control;
1525         control->int_vector = irq;
1526         control->int_ctl &= ~V_INTR_PRIO_MASK;
1527         control->int_ctl |= V_IRQ_MASK |
1528                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1529 }
1530
1531 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1532 {
1533         struct vcpu_svm *svm = to_svm(vcpu);
1534
1535         svm_inject_irq(svm, irq);
1536 }
1537
1538 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1539 {
1540         struct vcpu_svm *svm = to_svm(vcpu);
1541         struct vmcb *vmcb = svm->vmcb;
1542         int max_irr, tpr;
1543
1544         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1545                 return;
1546
1547         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1548
1549         max_irr = kvm_lapic_find_highest_irr(vcpu);
1550         if (max_irr == -1)
1551                 return;
1552
1553         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1554
1555         if (tpr >= (max_irr & 0xf0))
1556                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1557 }
1558
1559 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1560 {
1561         struct vcpu_svm *svm = to_svm(vcpu);
1562         struct vmcb *vmcb = svm->vmcb;
1563         int intr_vector = -1;
1564
1565         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1566             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1567                 intr_vector = vmcb->control.exit_int_info &
1568                               SVM_EVTINJ_VEC_MASK;
1569                 vmcb->control.exit_int_info = 0;
1570                 svm_inject_irq(svm, intr_vector);
1571                 goto out;
1572         }
1573
1574         if (vmcb->control.int_ctl & V_IRQ_MASK)
1575                 goto out;
1576
1577         if (!kvm_cpu_has_interrupt(vcpu))
1578                 goto out;
1579
1580         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1581             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1582             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1583                 /* unable to deliver irq, set pending irq */
1584                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1585                 svm_inject_irq(svm, 0x0);
1586                 goto out;
1587         }
1588         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1589         intr_vector = kvm_cpu_get_interrupt(vcpu);
1590         svm_inject_irq(svm, intr_vector);
1591         kvm_timer_intr_post(vcpu, intr_vector);
1592 out:
1593         update_cr8_intercept(vcpu);
1594 }
1595
1596 static void kvm_reput_irq(struct vcpu_svm *svm)
1597 {
1598         struct vmcb_control_area *control = &svm->vmcb->control;
1599
1600         if ((control->int_ctl & V_IRQ_MASK)
1601             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1602                 control->int_ctl &= ~V_IRQ_MASK;
1603                 push_irq(&svm->vcpu, control->int_vector);
1604         }
1605
1606         svm->vcpu.arch.interrupt_window_open =
1607                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1608 }
1609
1610 static void svm_do_inject_vector(struct vcpu_svm *svm)
1611 {
1612         struct kvm_vcpu *vcpu = &svm->vcpu;
1613         int word_index = __ffs(vcpu->arch.irq_summary);
1614         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1615         int irq = word_index * BITS_PER_LONG + bit_index;
1616
1617         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1618         if (!vcpu->arch.irq_pending[word_index])
1619                 clear_bit(word_index, &vcpu->arch.irq_summary);
1620         svm_inject_irq(svm, irq);
1621 }
1622
1623 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1624                                        struct kvm_run *kvm_run)
1625 {
1626         struct vcpu_svm *svm = to_svm(vcpu);
1627         struct vmcb_control_area *control = &svm->vmcb->control;
1628
1629         svm->vcpu.arch.interrupt_window_open =
1630                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1631                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1632
1633         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1634                 /*
1635                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1636                  */
1637                 svm_do_inject_vector(svm);
1638
1639         /*
1640          * Interrupts blocked.  Wait for unblock.
1641          */
1642         if (!svm->vcpu.arch.interrupt_window_open &&
1643             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1644                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1645          else
1646                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1647 }
1648
1649 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1650 {
1651         return 0;
1652 }
1653
1654 static void save_db_regs(unsigned long *db_regs)
1655 {
1656         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1657         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1658         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1659         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1660 }
1661
1662 static void load_db_regs(unsigned long *db_regs)
1663 {
1664         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1665         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1666         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1667         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1668 }
1669
1670 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1671 {
1672         force_new_asid(vcpu);
1673 }
1674
1675 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1676 {
1677 }
1678
1679 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1680 {
1681         struct vcpu_svm *svm = to_svm(vcpu);
1682
1683         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1684                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1685                 kvm_lapic_set_tpr(vcpu, cr8);
1686         }
1687 }
1688
1689 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1690 {
1691         struct vcpu_svm *svm = to_svm(vcpu);
1692         u64 cr8;
1693
1694         if (!irqchip_in_kernel(vcpu->kvm))
1695                 return;
1696
1697         cr8 = kvm_get_cr8(vcpu);
1698         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1699         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1700 }
1701
1702 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1703 {
1704         struct vcpu_svm *svm = to_svm(vcpu);
1705         u16 fs_selector;
1706         u16 gs_selector;
1707         u16 ldt_selector;
1708
1709         pre_svm_run(svm);
1710
1711         sync_lapic_to_cr8(vcpu);
1712
1713         save_host_msrs(vcpu);
1714         fs_selector = kvm_read_fs();
1715         gs_selector = kvm_read_gs();
1716         ldt_selector = kvm_read_ldt();
1717         svm->host_cr2 = kvm_read_cr2();
1718         svm->host_dr6 = read_dr6();
1719         svm->host_dr7 = read_dr7();
1720         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1721         /* required for live migration with NPT */
1722         if (npt_enabled)
1723                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1724
1725         if (svm->vmcb->save.dr7 & 0xff) {
1726                 write_dr7(0);
1727                 save_db_regs(svm->host_db_regs);
1728                 load_db_regs(svm->db_regs);
1729         }
1730
1731         clgi();
1732
1733         local_irq_enable();
1734
1735         asm volatile (
1736 #ifdef CONFIG_X86_64
1737                 "push %%rbp; \n\t"
1738 #else
1739                 "push %%ebp; \n\t"
1740 #endif
1741
1742 #ifdef CONFIG_X86_64
1743                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1744                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1745                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1746                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1747                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1748                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1749                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1750                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1751                 "mov %c[r10](%[svm]), %%r10 \n\t"
1752                 "mov %c[r11](%[svm]), %%r11 \n\t"
1753                 "mov %c[r12](%[svm]), %%r12 \n\t"
1754                 "mov %c[r13](%[svm]), %%r13 \n\t"
1755                 "mov %c[r14](%[svm]), %%r14 \n\t"
1756                 "mov %c[r15](%[svm]), %%r15 \n\t"
1757 #else
1758                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1759                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1760                 "mov %c[rdx](%[svm]), %%edx \n\t"
1761                 "mov %c[rsi](%[svm]), %%esi \n\t"
1762                 "mov %c[rdi](%[svm]), %%edi \n\t"
1763                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1764 #endif
1765
1766 #ifdef CONFIG_X86_64
1767                 /* Enter guest mode */
1768                 "push %%rax \n\t"
1769                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1770                 __ex(SVM_VMLOAD) "\n\t"
1771                 __ex(SVM_VMRUN) "\n\t"
1772                 __ex(SVM_VMSAVE) "\n\t"
1773                 "pop %%rax \n\t"
1774 #else
1775                 /* Enter guest mode */
1776                 "push %%eax \n\t"
1777                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1778                 __ex(SVM_VMLOAD) "\n\t"
1779                 __ex(SVM_VMRUN) "\n\t"
1780                 __ex(SVM_VMSAVE) "\n\t"
1781                 "pop %%eax \n\t"
1782 #endif
1783
1784                 /* Save guest registers, load host registers */
1785 #ifdef CONFIG_X86_64
1786                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1787                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1788                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1789                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1790                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1791                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1792                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1793                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1794                 "mov %%r10, %c[r10](%[svm]) \n\t"
1795                 "mov %%r11, %c[r11](%[svm]) \n\t"
1796                 "mov %%r12, %c[r12](%[svm]) \n\t"
1797                 "mov %%r13, %c[r13](%[svm]) \n\t"
1798                 "mov %%r14, %c[r14](%[svm]) \n\t"
1799                 "mov %%r15, %c[r15](%[svm]) \n\t"
1800
1801                 "pop  %%rbp; \n\t"
1802 #else
1803                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1804                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1805                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1806                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1807                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1808                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1809
1810                 "pop  %%ebp; \n\t"
1811 #endif
1812                 :
1813                 : [svm]"a"(svm),
1814                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1815                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1816                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1817                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1818                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1819                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1820                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1821 #ifdef CONFIG_X86_64
1822                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1823                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1824                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1825                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1826                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1827                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1828                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1829                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1830 #endif
1831                 : "cc", "memory"
1832 #ifdef CONFIG_X86_64
1833                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1834                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1835 #else
1836                 , "ebx", "ecx", "edx" , "esi", "edi"
1837 #endif
1838                 );
1839
1840         if ((svm->vmcb->save.dr7 & 0xff))
1841                 load_db_regs(svm->host_db_regs);
1842
1843         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1844
1845         write_dr6(svm->host_dr6);
1846         write_dr7(svm->host_dr7);
1847         kvm_write_cr2(svm->host_cr2);
1848
1849         kvm_load_fs(fs_selector);
1850         kvm_load_gs(gs_selector);
1851         kvm_load_ldt(ldt_selector);
1852         load_host_msrs(vcpu);
1853
1854         reload_tss(vcpu);
1855
1856         local_irq_disable();
1857
1858         stgi();
1859
1860         sync_cr8_to_lapic(vcpu);
1861
1862         svm->next_rip = 0;
1863 }
1864
1865 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1866 {
1867         struct vcpu_svm *svm = to_svm(vcpu);
1868
1869         if (npt_enabled) {
1870                 svm->vmcb->control.nested_cr3 = root;
1871                 force_new_asid(vcpu);
1872                 return;
1873         }
1874
1875         svm->vmcb->save.cr3 = root;
1876         force_new_asid(vcpu);
1877
1878         if (vcpu->fpu_active) {
1879                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1880                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1881                 vcpu->fpu_active = 0;
1882         }
1883 }
1884
1885 static int is_disabled(void)
1886 {
1887         u64 vm_cr;
1888
1889         rdmsrl(MSR_VM_CR, vm_cr);
1890         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1891                 return 1;
1892
1893         return 0;
1894 }
1895
1896 static void
1897 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1898 {
1899         /*
1900          * Patch in the VMMCALL instruction:
1901          */
1902         hypercall[0] = 0x0f;
1903         hypercall[1] = 0x01;
1904         hypercall[2] = 0xd9;
1905 }
1906
1907 static void svm_check_processor_compat(void *rtn)
1908 {
1909         *(int *)rtn = 0;
1910 }
1911
1912 static bool svm_cpu_has_accelerated_tpr(void)
1913 {
1914         return false;
1915 }
1916
1917 static int get_npt_level(void)
1918 {
1919 #ifdef CONFIG_X86_64
1920         return PT64_ROOT_LEVEL;
1921 #else
1922         return PT32E_ROOT_LEVEL;
1923 #endif
1924 }
1925
1926 static struct kvm_x86_ops svm_x86_ops = {
1927         .cpu_has_kvm_support = has_svm,
1928         .disabled_by_bios = is_disabled,
1929         .hardware_setup = svm_hardware_setup,
1930         .hardware_unsetup = svm_hardware_unsetup,
1931         .check_processor_compatibility = svm_check_processor_compat,
1932         .hardware_enable = svm_hardware_enable,
1933         .hardware_disable = svm_hardware_disable,
1934         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1935
1936         .vcpu_create = svm_create_vcpu,
1937         .vcpu_free = svm_free_vcpu,
1938         .vcpu_reset = svm_vcpu_reset,
1939
1940         .prepare_guest_switch = svm_prepare_guest_switch,
1941         .vcpu_load = svm_vcpu_load,
1942         .vcpu_put = svm_vcpu_put,
1943
1944         .set_guest_debug = svm_guest_debug,
1945         .get_msr = svm_get_msr,
1946         .set_msr = svm_set_msr,
1947         .get_segment_base = svm_get_segment_base,
1948         .get_segment = svm_get_segment,
1949         .set_segment = svm_set_segment,
1950         .get_cpl = svm_get_cpl,
1951         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1952         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1953         .set_cr0 = svm_set_cr0,
1954         .set_cr3 = svm_set_cr3,
1955         .set_cr4 = svm_set_cr4,
1956         .set_efer = svm_set_efer,
1957         .get_idt = svm_get_idt,
1958         .set_idt = svm_set_idt,
1959         .get_gdt = svm_get_gdt,
1960         .set_gdt = svm_set_gdt,
1961         .get_dr = svm_get_dr,
1962         .set_dr = svm_set_dr,
1963         .cache_regs = svm_cache_regs,
1964         .decache_regs = svm_decache_regs,
1965         .get_rflags = svm_get_rflags,
1966         .set_rflags = svm_set_rflags,
1967
1968         .tlb_flush = svm_flush_tlb,
1969
1970         .run = svm_vcpu_run,
1971         .handle_exit = handle_exit,
1972         .skip_emulated_instruction = skip_emulated_instruction,
1973         .patch_hypercall = svm_patch_hypercall,
1974         .get_irq = svm_get_irq,
1975         .set_irq = svm_set_irq,
1976         .queue_exception = svm_queue_exception,
1977         .exception_injected = svm_exception_injected,
1978         .inject_pending_irq = svm_intr_assist,
1979         .inject_pending_vectors = do_interrupt_requests,
1980
1981         .set_tss_addr = svm_set_tss_addr,
1982         .get_tdp_level = get_npt_level,
1983 };
1984
1985 static int __init svm_init(void)
1986 {
1987         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1988                               THIS_MODULE);
1989 }
1990
1991 static void __exit svm_exit(void)
1992 {
1993         kvm_exit();
1994 }
1995
1996 module_init(svm_init)
1997 module_exit(svm_exit)