2 * This file contains work-arounds for x86 and x86_64 platform bugs.
9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
16 /* BIOS may enable hardware IRQ balancing for
17 * E7520/E7320/E7525(revision ID 0x9 and below)
19 * Disable SW irqbalance/affinity on those platforms.
21 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
25 /* enable access to config space*/
26 pci_read_config_byte(dev, 0xf4, &config);
27 pci_write_config_byte(dev, 0xf4, config|0x2);
30 * read xTPR register. We may not have a pci_dev for device 8
31 * because it might be hidden until the above write.
33 pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
35 if (!(word & (1 << 13))) {
36 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
37 "disabling irq balancing and affinity\n");
44 /* put back the original value for config space*/
46 pci_write_config_byte(dev, 0xf4, config);
48 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
49 quirk_intel_irqbalance);
50 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
51 quirk_intel_irqbalance);
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
53 quirk_intel_irqbalance);
56 #if defined(CONFIG_HPET_TIMER)
57 unsigned long force_hpet_address;
60 NONE_FORCE_HPET_RESUME,
61 OLD_ICH_FORCE_HPET_RESUME,
62 ICH_FORCE_HPET_RESUME,
63 VT8237_FORCE_HPET_RESUME,
64 NVIDIA_FORCE_HPET_RESUME,
65 ATI_FORCE_HPET_RESUME,
66 } force_hpet_resume_type;
68 static void __iomem *rcba_base;
70 static void ich_force_hpet_resume(void)
74 if (!force_hpet_address)
77 BUG_ON(rcba_base == NULL);
79 /* read the Function Disable register, dword mode only */
80 val = readl(rcba_base + 0x3404);
82 /* HPET disabled in HPTC. Trying to enable */
83 writel(val | 0x80, rcba_base + 0x3404);
86 val = readl(rcba_base + 0x3404);
90 printk(KERN_DEBUG "Force enabled HPET at resume\n");
95 static void ich_force_enable_hpet(struct pci_dev *dev)
98 u32 uninitialized_var(rcba);
101 if (hpet_address || force_hpet_address)
104 pci_read_config_dword(dev, 0xF0, &rcba);
107 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
108 "cannot force enable HPET\n");
112 /* use bits 31:14, 16 kB aligned */
113 rcba_base = ioremap_nocache(rcba, 0x4000);
114 if (rcba_base == NULL) {
115 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
116 "cannot force enable HPET\n");
120 /* read the Function Disable register, dword mode only */
121 val = readl(rcba_base + 0x3404);
124 /* HPET is enabled in HPTC. Just not reported by BIOS */
126 force_hpet_address = 0xFED00000 | (val << 12);
127 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
128 "0x%lx\n", force_hpet_address);
133 /* HPET disabled in HPTC. Trying to enable */
134 writel(val | 0x80, rcba_base + 0x3404);
136 val = readl(rcba_base + 0x3404);
141 force_hpet_address = 0xFED00000 | (val << 12);
145 force_hpet_address = 0;
147 dev_printk(KERN_DEBUG, &dev->dev,
148 "Failed to force enable HPET\n");
150 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
151 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
152 "0x%lx\n", force_hpet_address);
156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
157 ich_force_enable_hpet);
158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
159 ich_force_enable_hpet);
160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
161 ich_force_enable_hpet);
162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
163 ich_force_enable_hpet);
164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
165 ich_force_enable_hpet);
166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
167 ich_force_enable_hpet);
168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
169 ich_force_enable_hpet);
170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4,
171 ich_force_enable_hpet);
172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
173 ich_force_enable_hpet);
176 static struct pci_dev *cached_dev;
178 static void hpet_print_force_info(void)
180 printk(KERN_INFO "HPET not enabled in BIOS. "
181 "You might try hpet=force boot option\n");
184 static void old_ich_force_hpet_resume(void)
187 u32 uninitialized_var(gen_cntl);
189 if (!force_hpet_address || !cached_dev)
192 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
193 gen_cntl &= (~(0x7 << 15));
194 gen_cntl |= (0x4 << 15);
196 pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
197 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
198 val = gen_cntl >> 15;
201 printk(KERN_DEBUG "Force enabled HPET at resume\n");
206 static void old_ich_force_enable_hpet(struct pci_dev *dev)
209 u32 uninitialized_var(gen_cntl);
211 if (hpet_address || force_hpet_address)
214 pci_read_config_dword(dev, 0xD0, &gen_cntl);
216 * Bit 17 is HPET enable bit.
217 * Bit 16:15 control the HPET base address.
219 val = gen_cntl >> 15;
223 force_hpet_address = 0xFED00000 | (val << 12);
224 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
230 * HPET is disabled. Trying enabling at FED00000 and check
233 gen_cntl &= (~(0x7 << 15));
234 gen_cntl |= (0x4 << 15);
235 pci_write_config_dword(dev, 0xD0, gen_cntl);
237 pci_read_config_dword(dev, 0xD0, &gen_cntl);
239 val = gen_cntl >> 15;
242 /* HPET is enabled in HPTC. Just not reported by BIOS */
244 force_hpet_address = 0xFED00000 | (val << 12);
245 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
246 "0x%lx\n", force_hpet_address);
248 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
252 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
256 * Undocumented chipset features. Make sure that the user enforced
259 static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
262 old_ich_force_enable_hpet(dev);
264 hpet_print_force_info();
267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
268 old_ich_force_enable_hpet_user);
269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
270 old_ich_force_enable_hpet_user);
271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
272 old_ich_force_enable_hpet_user);
273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
274 old_ich_force_enable_hpet_user);
275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
276 old_ich_force_enable_hpet_user);
277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
278 old_ich_force_enable_hpet);
279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
280 old_ich_force_enable_hpet);
283 static void vt8237_force_hpet_resume(void)
287 if (!force_hpet_address || !cached_dev)
290 val = 0xfed00000 | 0x80;
291 pci_write_config_dword(cached_dev, 0x68, val);
293 pci_read_config_dword(cached_dev, 0x68, &val);
295 printk(KERN_DEBUG "Force enabled HPET at resume\n");
300 static void vt8237_force_enable_hpet(struct pci_dev *dev)
302 u32 uninitialized_var(val);
304 if (hpet_address || force_hpet_address)
307 if (!hpet_force_user) {
308 hpet_print_force_info();
312 pci_read_config_dword(dev, 0x68, &val);
314 * Bit 7 is HPET enable bit.
315 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
318 force_hpet_address = (val & ~0x3ff);
319 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
325 * HPET is disabled. Trying enabling at FED00000 and check
328 val = 0xfed00000 | 0x80;
329 pci_write_config_dword(dev, 0x68, val);
331 pci_read_config_dword(dev, 0x68, &val);
333 force_hpet_address = (val & ~0x3ff);
334 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
335 "0x%lx\n", force_hpet_address);
337 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
341 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
345 vt8237_force_enable_hpet);
346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
347 vt8237_force_enable_hpet);
349 static void ati_force_hpet_resume(void)
351 pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
352 printk(KERN_DEBUG "Force enabled HPET at resume\n");
355 static u32 ati_ixp4x0_rev(struct pci_dev *dev)
360 pci_read_config_byte(dev, 0xac, &b);
362 pci_write_config_byte(dev, 0xac, b);
363 pci_read_config_dword(dev, 0x70, &d);
365 pci_write_config_dword(dev, 0x70, d);
366 pci_read_config_dword(dev, 0x8, &d);
368 dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
372 static void ati_force_enable_hpet(struct pci_dev *dev)
377 if (hpet_address || force_hpet_address)
380 if (!hpet_force_user) {
381 hpet_print_force_info();
385 d = ati_ixp4x0_rev(dev);
390 pci_write_config_dword(dev, 0x14, 0xfed00000);
391 pci_read_config_dword(dev, 0x14, &val);
393 /* enable interrupt */
394 outb(0x72, 0xcd6); b = inb(0xcd7);
396 outb(0x72, 0xcd6); outb(b, 0xcd7);
397 outb(0x72, 0xcd6); b = inb(0xcd7);
400 pci_read_config_dword(dev, 0x64, &d);
402 pci_write_config_dword(dev, 0x64, d);
403 pci_read_config_dword(dev, 0x64, &d);
407 force_hpet_address = val;
408 force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
409 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
414 ati_force_enable_hpet);
417 * Undocumented chipset feature taken from LinuxBIOS.
419 static void nvidia_force_hpet_resume(void)
421 pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
422 printk(KERN_DEBUG "Force enabled HPET at resume\n");
425 static void nvidia_force_enable_hpet(struct pci_dev *dev)
427 u32 uninitialized_var(val);
429 if (hpet_address || force_hpet_address)
432 if (!hpet_force_user) {
433 hpet_print_force_info();
437 pci_write_config_dword(dev, 0x44, 0xfed00001);
438 pci_read_config_dword(dev, 0x44, &val);
439 force_hpet_address = val & 0xfffffffe;
440 force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
441 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
448 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
449 nvidia_force_enable_hpet);
450 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
451 nvidia_force_enable_hpet);
454 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
455 nvidia_force_enable_hpet);
456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
457 nvidia_force_enable_hpet);
458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
459 nvidia_force_enable_hpet);
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
461 nvidia_force_enable_hpet);
462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
463 nvidia_force_enable_hpet);
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
465 nvidia_force_enable_hpet);
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
467 nvidia_force_enable_hpet);
468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
469 nvidia_force_enable_hpet);
470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
471 nvidia_force_enable_hpet);
473 void force_hpet_resume(void)
475 switch (force_hpet_resume_type) {
476 case ICH_FORCE_HPET_RESUME:
477 ich_force_hpet_resume();
479 case OLD_ICH_FORCE_HPET_RESUME:
480 old_ich_force_hpet_resume();
482 case VT8237_FORCE_HPET_RESUME:
483 vt8237_force_hpet_resume();
485 case NVIDIA_FORCE_HPET_RESUME:
486 nvidia_force_hpet_resume();
488 case ATI_FORCE_HPET_RESUME:
489 ati_force_hpet_resume();