arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/crash_dump.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <linux/scatterlist.h>
  39 #include <linux/iommu-helper.h>
  40
  41 #include <asm/iommu.h>
  42 #include <asm/calgary.h>
  43 #include <asm/tce.h>
  44 #include <asm/pci-direct.h>
  45 #include <asm/system.h>
  46 #include <asm/dma.h>
  47 #include <asm/rio.h>
  48 #include <asm/bios_ebda.h>
  49
  50 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  51 int use_calgary __read_mostly = 1;
  52 #else
  53 int use_calgary __read_mostly = 0;
  54 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  55
  56 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  57 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  58
  59 /* register offsets inside the host bridge space */
  60 #define CALGARY_CONFIG_REG      0x0108
  61 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  62 #define PHB_PLSSR_OFFSET        0x0120
  63 #define PHB_CONFIG_RW_OFFSET    0x0160
  64 #define PHB_IOBASE_BAR_LOW      0x0170
  65 #define PHB_IOBASE_BAR_HIGH     0x0180
  66 #define PHB_MEM_1_LOW           0x0190
  67 #define PHB_MEM_1_HIGH          0x01A0
  68 #define PHB_IO_ADDR_SIZE        0x01B0
  69 #define PHB_MEM_1_SIZE          0x01C0
  70 #define PHB_MEM_ST_OFFSET       0x01D0
  71 #define PHB_AER_OFFSET          0x0200
  72 #define PHB_CONFIG_0_HIGH       0x0220
  73 #define PHB_CONFIG_0_LOW        0x0230
  74 #define PHB_CONFIG_0_END        0x0240
  75 #define PHB_MEM_2_LOW           0x02B0
  76 #define PHB_MEM_2_HIGH          0x02C0
  77 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  78 #define PHB_MEM_2_SIZE_LOW      0x02E0
  79 #define PHB_DOSHOLE_OFFSET      0x08E0
  80
  81 /* CalIOC2 specific */
  82 #define PHB_SAVIOR_L2           0x0DB0
  83 #define PHB_PAGE_MIG_CTRL       0x0DA8
  84 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  85 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  86
  87 /* PHB_CONFIG_RW */
  88 #define PHB_TCE_ENABLE          0x20000000
  89 #define PHB_SLOT_DISABLE        0x1C000000
  90 #define PHB_DAC_DISABLE         0x01000000
  91 #define PHB_MEM2_ENABLE         0x00400000
  92 #define PHB_MCSR_ENABLE         0x00100000
  93 /* TAR (Table Address Register) */
  94 #define TAR_SW_BITS             0x0000ffffffff800fUL
  95 #define TAR_VALID               0x0000000000000008UL
  96 /* CSR (Channel/DMA Status Register) */
  97 #define CSR_AGENT_MASK          0xffe0ffff
  98 /* CCR (Calgary Configuration Register) */
  99 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
 100 /* PMCR/PMDR (Page Migration Control/Debug Registers */
 101 #define PMR_SOFTSTOP            0x80000000
 102 #define PMR_SOFTSTOPFAULT       0x40000000
 103 #define PMR_HARDSTOP            0x20000000
 104
 105 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 106 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 107 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 108 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 109 #define PHBS_PER_CALGARY        4
 110
 111 /* register offsets in Calgary's internal register space */
 112 static const unsigned long tar_offsets[] = {
 113         0x0580 /* TAR0 */,
 114         0x0588 /* TAR1 */,
 115         0x0590 /* TAR2 */,
 116         0x0598 /* TAR3 */
 117 };
 118
 119 static const unsigned long split_queue_offsets[] = {
 120         0x4870 /* SPLIT QUEUE 0 */,
 121         0x5870 /* SPLIT QUEUE 1 */,
 122         0x6870 /* SPLIT QUEUE 2 */,
 123         0x7870 /* SPLIT QUEUE 3 */
 124 };
 125
 126 static const unsigned long phb_offsets[] = {
 127         0x8000 /* PHB0 */,
 128         0x9000 /* PHB1 */,
 129         0xA000 /* PHB2 */,
 130         0xB000 /* PHB3 */
 131 };
 132
 133 /* PHB debug registers */
 134
 135 static const unsigned long phb_debug_offsets[] = {
 136         0x4000  /* PHB 0 DEBUG */,
 137         0x5000  /* PHB 1 DEBUG */,
 138         0x6000  /* PHB 2 DEBUG */,
 139         0x7000  /* PHB 3 DEBUG */
 140 };
 141
 142 /*
 143  * STUFF register for each debug PHB,
 144  * byte 1 = start bus number, byte 2 = end bus number
 145  */
 146
 147 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 148
 149 #define EMERGENCY_PAGES 32 /* = 128KB */
 150
 151 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 152 static int translate_empty_slots __read_mostly = 0;
 153 static int calgary_detected __read_mostly = 0;
 154
 155 static struct rio_table_hdr     *rio_table_hdr __initdata;
 156 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 157 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 158
 159 struct calgary_bus_info {
 160         void *tce_space;
 161         unsigned char translation_disabled;
 162         signed char phbid;
 163         void __iomem *bbar;
 164 };
 165
 166 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 167 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 168 static void calgary_dump_error_regs(struct iommu_table *tbl);
 169 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 170 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 171 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 172 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 173 static void get_tce_space_from_tar(void);
 174
 175 static struct cal_chipset_ops calgary_chip_ops = {
 176         .handle_quirks = calgary_handle_quirks,
 177         .tce_cache_blast = calgary_tce_cache_blast,
 178         .dump_error_regs = calgary_dump_error_regs
 179 };
 180
 181 static struct cal_chipset_ops calioc2_chip_ops = {
 182         .handle_quirks = calioc2_handle_quirks,
 183         .tce_cache_blast = calioc2_tce_cache_blast,
 184         .dump_error_regs = calioc2_dump_error_regs
 185 };
 186
 187 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 188
 189 /* enable this to stress test the chip's TCE cache */
 190 #ifdef CONFIG_IOMMU_DEBUG
 191 static int debugging = 1;
 192
 193 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 194         int expected, unsigned long start, unsigned long end)
 195 {
 196         unsigned long idx = start;
 197
 198         BUG_ON(start >= end);
 199
 200         while (idx < end) {
 201                 if (!!test_bit(idx, bitmap) != expected)
 202                         return idx;
 203                 ++idx;
 204         }
 205
 206         /* all bits have the expected value */
 207         return ~0UL;
 208 }
 209 #else /* debugging is disabled */
 210 static int debugging;
 211
 212 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 213         int expected, unsigned long start, unsigned long end)
 214 {
 215         return ~0UL;
 216 }
 217
 218 #endif /* CONFIG_IOMMU_DEBUG */
 219
 220 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 221 {
 222         unsigned int npages;
 223
 224         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 225         npages >>= PAGE_SHIFT;
 226
 227         return npages;
 228 }
 229
 230 static inline int translation_enabled(struct iommu_table *tbl)
 231 {
 232         /* only PHBs with translation enabled have an IOMMU table */
 233         return (tbl != NULL);
 234 }
 235
 236 static void iommu_range_reserve(struct iommu_table *tbl,
 237         unsigned long start_addr, unsigned int npages)
 238 {
 239         unsigned long index;
 240         unsigned long end;
 241         unsigned long badbit;
 242         unsigned long flags;
 243
 244         index = start_addr >> PAGE_SHIFT;
 245
 246         /* bail out if we're asked to reserve a region we don't cover */
 247         if (index >= tbl->it_size)
 248                 return;
 249
 250         end = index + npages;
 251         if (end > tbl->it_size) /* don't go off the table */
 252                 end = tbl->it_size;
 253
 254         spin_lock_irqsave(&tbl->it_lock, flags);
 255
 256         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 257         if (badbit != ~0UL) {
 258                 if (printk_ratelimit())
 259                         printk(KERN_ERR "Calgary: entry already allocated at "
 260                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 261                                badbit, tbl, start_addr, npages);
 262         }
 263
 264         set_bit_string(tbl->it_map, index, npages);
 265
 266         spin_unlock_irqrestore(&tbl->it_lock, flags);
 267 }
 268
 269 static unsigned long iommu_range_alloc(struct device *dev,
 270                                        struct iommu_table *tbl,
 271                                        unsigned int npages)
 272 {
 273         unsigned long flags;
 274         unsigned long offset;
 275         unsigned long boundary_size;
 276
 277         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 278                               PAGE_SIZE) >> PAGE_SHIFT;
 279
 280         BUG_ON(npages == 0);
 281
 282         spin_lock_irqsave(&tbl->it_lock, flags);
 283
 284         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 285                                   npages, 0, boundary_size, 0);
 286         if (offset == ~0UL) {
 287                 tbl->chip_ops->tce_cache_blast(tbl);
 288
 289                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 290                                           npages, 0, boundary_size, 0);
 291                 if (offset == ~0UL) {
 292                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 293                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 294                         if (panic_on_overflow)
 295                                 panic("Calgary: fix the allocator.\n");
 296                         else
 297                                 return bad_dma_address;
 298                 }
 299         }
 300
 301         tbl->it_hint = offset + npages;
 302         BUG_ON(tbl->it_hint > tbl->it_size);
 303
 304         spin_unlock_irqrestore(&tbl->it_lock, flags);
 305
 306         return offset;
 307 }
 308
 309 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 310                               void *vaddr, unsigned int npages, int direction)
 311 {
 312         unsigned long entry;
 313         dma_addr_t ret = bad_dma_address;
 314
 315         entry = iommu_range_alloc(dev, tbl, npages);
 316
 317         if (unlikely(entry == bad_dma_address))
 318                 goto error;
 319
 320         /* set the return dma address */
 321         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 322
 323         /* put the TCEs in the HW table */
 324         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 325                   direction);
 326
 327         return ret;
 328
 329 error:
 330         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 331                "iommu %p\n", npages, tbl);
 332         return bad_dma_address;
 333 }
 334
 335 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 336         unsigned int npages)
 337 {
 338         unsigned long entry;
 339         unsigned long badbit;
 340         unsigned long badend;
 341         unsigned long flags;
 342
 343         /* were we called with bad_dma_address? */
 344         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 345         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 346                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
 347                        "address 0x%Lx\n", dma_addr);
 348                 return;
 349         }
 350
 351         entry = dma_addr >> PAGE_SHIFT;
 352
 353         BUG_ON(entry + npages > tbl->it_size);
 354
 355         tce_free(tbl, entry, npages);
 356
 357         spin_lock_irqsave(&tbl->it_lock, flags);
 358
 359         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 360         if (badbit != ~0UL) {
 361                 if (printk_ratelimit())
 362                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 363                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 364                                badbit, tbl, dma_addr, entry, npages);
 365         }
 366
 367         iommu_area_free(tbl->it_map, entry, npages);
 368
 369         spin_unlock_irqrestore(&tbl->it_lock, flags);
 370 }
 371
 372 static inline struct iommu_table *find_iommu_table(struct device *dev)
 373 {
 374         struct pci_dev *pdev;
 375         struct pci_bus *pbus;
 376         struct iommu_table *tbl;
 377
 378         pdev = to_pci_dev(dev);
 379
 380         pbus = pdev->bus;
 381
 382         /* is the device behind a bridge? Look for the root bus */
 383         while (pbus->parent)
 384                 pbus = pbus->parent;
 385
 386         tbl = pci_iommu(pbus);
 387
 388         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 389
 390         return tbl;
 391 }
 392
 393 static void calgary_unmap_sg(struct device *dev,
 394         struct scatterlist *sglist, int nelems, int direction)
 395 {
 396         struct iommu_table *tbl = find_iommu_table(dev);
 397         struct scatterlist *s;
 398         int i;
 399
 400         if (!translation_enabled(tbl))
 401                 return;
 402
 403         for_each_sg(sglist, s, nelems, i) {
 404                 unsigned int npages;
 405                 dma_addr_t dma = s->dma_address;
 406                 unsigned int dmalen = s->dma_length;
 407
 408                 if (dmalen == 0)
 409                         break;
 410
 411                 npages = num_dma_pages(dma, dmalen);
 412                 iommu_free(tbl, dma, npages);
 413         }
 414 }
 415
 416 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 417         int nelems, int direction)
 418 {
 419         struct iommu_table *tbl = find_iommu_table(dev);
 420         struct scatterlist *s;
 421         unsigned long vaddr;
 422         unsigned int npages;
 423         unsigned long entry;
 424         int i;
 425
 426         for_each_sg(sg, s, nelems, i) {
 427                 BUG_ON(!sg_page(s));
 428
 429                 vaddr = (unsigned long) sg_virt(s);
 430                 npages = num_dma_pages(vaddr, s->length);
 431
 432                 entry = iommu_range_alloc(dev, tbl, npages);
 433                 if (entry == bad_dma_address) {
 434                         /* makes sure unmap knows to stop */
 435                         s->dma_length = 0;
 436                         goto error;
 437                 }
 438
 439                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 440
 441                 /* insert into HW table */
 442                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 443                           direction);
 444
 445                 s->dma_length = s->length;
 446         }
 447
 448         return nelems;
 449 error:
 450         calgary_unmap_sg(dev, sg, nelems, direction);
 451         for_each_sg(sg, s, nelems, i) {
 452                 sg->dma_address = bad_dma_address;
 453                 sg->dma_length = 0;
 454         }
 455         return 0;
 456 }
 457
 458 static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr,
 459         size_t size, int direction)
 460 {
 461         void *vaddr = phys_to_virt(paddr);
 462         unsigned long uaddr;
 463         unsigned int npages;
 464         struct iommu_table *tbl = find_iommu_table(dev);
 465
 466         uaddr = (unsigned long)vaddr;
 467         npages = num_dma_pages(uaddr, size);
 468
 469         return iommu_alloc(dev, tbl, vaddr, npages, direction);
 470 }
 471
 472 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 473         size_t size, int direction)
 474 {
 475         struct iommu_table *tbl = find_iommu_table(dev);
 476         unsigned int npages;
 477
 478         npages = num_dma_pages(dma_handle, size);
 479         iommu_free(tbl, dma_handle, npages);
 480 }
 481
 482 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 483         dma_addr_t *dma_handle, gfp_t flag)
 484 {
 485         void *ret = NULL;
 486         dma_addr_t mapping;
 487         unsigned int npages, order;
 488         struct iommu_table *tbl = find_iommu_table(dev);
 489
 490         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 491         npages = size >> PAGE_SHIFT;
 492         order = get_order(size);
 493
 494         flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
 495
 496         /* alloc enough pages (and possibly more) */
 497         ret = (void *)__get_free_pages(flag, order);
 498         if (!ret)
 499                 goto error;
 500         memset(ret, 0, size);
 501
 502         /* set up tces to cover the allocated range */
 503         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 504         if (mapping == bad_dma_address)
 505                 goto free;
 506         *dma_handle = mapping;
 507         return ret;
 508 free:
 509         free_pages((unsigned long)ret, get_order(size));
 510         ret = NULL;
 511 error:
 512         return ret;
 513 }
 514
 515 static void calgary_free_coherent(struct device *dev, size_t size,
 516                                   void *vaddr, dma_addr_t dma_handle)
 517 {
 518         unsigned int npages;
 519         struct iommu_table *tbl = find_iommu_table(dev);
 520
 521         size = PAGE_ALIGN(size);
 522         npages = size >> PAGE_SHIFT;
 523
 524         iommu_free(tbl, dma_handle, npages);
 525         free_pages((unsigned long)vaddr, get_order(size));
 526 }
 527
 528 static struct dma_mapping_ops calgary_dma_ops = {
 529         .alloc_coherent = calgary_alloc_coherent,
 530         .free_coherent = calgary_free_coherent,
 531         .map_single = calgary_map_single,
 532         .unmap_single = calgary_unmap_single,
 533         .map_sg = calgary_map_sg,
 534         .unmap_sg = calgary_unmap_sg,
 535 };
 536
 537 static inline void __iomem * busno_to_bbar(unsigned char num)
 538 {
 539         return bus_info[num].bbar;
 540 }
 541
 542 static inline int busno_to_phbid(unsigned char num)
 543 {
 544         return bus_info[num].phbid;
 545 }
 546
 547 static inline unsigned long split_queue_offset(unsigned char num)
 548 {
 549         size_t idx = busno_to_phbid(num);
 550
 551         return split_queue_offsets[idx];
 552 }
 553
 554 static inline unsigned long tar_offset(unsigned char num)
 555 {
 556         size_t idx = busno_to_phbid(num);
 557
 558         return tar_offsets[idx];
 559 }
 560
 561 static inline unsigned long phb_offset(unsigned char num)
 562 {
 563         size_t idx = busno_to_phbid(num);
 564
 565         return phb_offsets[idx];
 566 }
 567
 568 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 569 {
 570         unsigned long target = ((unsigned long)bar) | offset;
 571         return (void __iomem*)target;
 572 }
 573
 574 static inline int is_calioc2(unsigned short device)
 575 {
 576         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 577 }
 578
 579 static inline int is_calgary(unsigned short device)
 580 {
 581         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 582 }
 583
 584 static inline int is_cal_pci_dev(unsigned short device)
 585 {
 586         return (is_calgary(device) || is_calioc2(device));
 587 }
 588
 589 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 590 {
 591         u64 val;
 592         u32 aer;
 593         int i = 0;
 594         void __iomem *bbar = tbl->bbar;
 595         void __iomem *target;
 596
 597         /* disable arbitration on the bus */
 598         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 599         aer = readl(target);
 600         writel(0, target);
 601
 602         /* read plssr to ensure it got there */
 603         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 604         val = readl(target);
 605
 606         /* poll split queues until all DMA activity is done */
 607         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 608         do {
 609                 val = readq(target);
 610                 i++;
 611         } while ((val & 0xff) != 0xff && i < 100);
 612         if (i == 100)
 613                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 614                        "continuing anyway\n");
 615
 616         /* invalidate TCE cache */
 617         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 618         writeq(tbl->tar_val, target);
 619
 620         /* enable arbitration */
 621         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 622         writel(aer, target);
 623         (void)readl(target); /* flush */
 624 }
 625
 626 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 627 {
 628         void __iomem *bbar = tbl->bbar;
 629         void __iomem *target;
 630         u64 val64;
 631         u32 val;
 632         int i = 0;
 633         int count = 1;
 634         unsigned char bus = tbl->it_busno;
 635
 636 begin:
 637         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 638                "sequence - count %d\n", bus, count);
 639
 640         /* 1. using the Page Migration Control reg set SoftStop */
 641         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 642         val = be32_to_cpu(readl(target));
 643         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 644         val |= PMR_SOFTSTOP;
 645         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 646         writel(cpu_to_be32(val), target);
 647
 648         /* 2. poll split queues until all DMA activity is done */
 649         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 650         target = calgary_reg(bbar, split_queue_offset(bus));
 651         do {
 652                 val64 = readq(target);
 653                 i++;
 654         } while ((val64 & 0xff) != 0xff && i < 100);
 655         if (i == 100)
 656                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 657                        "continuing anyway\n");
 658
 659         /* 3. poll Page Migration DEBUG for SoftStopFault */
 660         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 661         val = be32_to_cpu(readl(target));
 662         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 663
 664         /* 4. if SoftStopFault - goto (1) */
 665         if (val & PMR_SOFTSTOPFAULT) {
 666                 if (++count < 100)
 667                         goto begin;
 668                 else {
 669                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 670                                "aborting TCE cache flush sequence!\n");
 671                         return; /* pray for the best */
 672                 }
 673         }
 674
 675         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 676         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 677         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 678         val = be32_to_cpu(readl(target));
 679         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 680         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 681         val = be32_to_cpu(readl(target));
 682         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 683
 684         /* 6. invalidate TCE cache */
 685         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 686         target = calgary_reg(bbar, tar_offset(bus));
 687         writeq(tbl->tar_val, target);
 688
 689         /* 7. Re-read PMCR */
 690         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 691         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 692         val = be32_to_cpu(readl(target));
 693         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 694
 695         /* 8. Remove HardStop */
 696         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 697         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 698         val = 0;
 699         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 700         writel(cpu_to_be32(val), target);
 701         val = be32_to_cpu(readl(target));
 702         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 703 }
 704
 705 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 706         u64 limit)
 707 {
 708         unsigned int numpages;
 709
 710         limit = limit | 0xfffff;
 711         limit++;
 712
 713         numpages = ((limit - start) >> PAGE_SHIFT);
 714         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 715 }
 716
 717 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 718 {
 719         void __iomem *target;
 720         u64 low, high, sizelow;
 721         u64 start, limit;
 722         struct iommu_table *tbl = pci_iommu(dev->bus);
 723         unsigned char busnum = dev->bus->number;
 724         void __iomem *bbar = tbl->bbar;
 725
 726         /* peripheral MEM_1 region */
 727         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 728         low = be32_to_cpu(readl(target));
 729         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 730         high = be32_to_cpu(readl(target));
 731         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 732         sizelow = be32_to_cpu(readl(target));
 733
 734         start = (high << 32) | low;
 735         limit = sizelow;
 736
 737         calgary_reserve_mem_region(dev, start, limit);
 738 }
 739
 740 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 741 {
 742         void __iomem *target;
 743         u32 val32;
 744         u64 low, high, sizelow, sizehigh;
 745         u64 start, limit;
 746         struct iommu_table *tbl = pci_iommu(dev->bus);
 747         unsigned char busnum = dev->bus->number;
 748         void __iomem *bbar = tbl->bbar;
 749
 750         /* is it enabled? */
 751         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 752         val32 = be32_to_cpu(readl(target));
 753         if (!(val32 & PHB_MEM2_ENABLE))
 754                 return;
 755
 756         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 757         low = be32_to_cpu(readl(target));
 758         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 759         high = be32_to_cpu(readl(target));
 760         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 761         sizelow = be32_to_cpu(readl(target));
 762         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 763         sizehigh = be32_to_cpu(readl(target));
 764
 765         start = (high << 32) | low;
 766         limit = (sizehigh << 32) | sizelow;
 767
 768         calgary_reserve_mem_region(dev, start, limit);
 769 }
 770
 771 /*
 772  * some regions of the IO address space do not get translated, so we
 773  * must not give devices IO addresses in those regions. The regions
 774  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 775  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 776  * later.
 777  */
 778 static void __init calgary_reserve_regions(struct pci_dev *dev)
 779 {
 780         unsigned int npages;
 781         u64 start;
 782         struct iommu_table *tbl = pci_iommu(dev->bus);
 783
 784         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 785         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 786
 787         /* avoid the BIOS/VGA first 640KB-1MB region */
 788         /* for CalIOC2 - avoid the entire first MB */
 789         if (is_calgary(dev->device)) {
 790                 start = (640 * 1024);
 791                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 792         } else { /* calioc2 */
 793                 start = 0;
 794                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 795         }
 796         iommu_range_reserve(tbl, start, npages);
 797
 798         /* reserve the two PCI peripheral memory regions in IO space */
 799         calgary_reserve_peripheral_mem_1(dev);
 800         calgary_reserve_peripheral_mem_2(dev);
 801 }
 802
 803 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 804 {
 805         u64 val64;
 806         u64 table_phys;
 807         void __iomem *target;
 808         int ret;
 809         struct iommu_table *tbl;
 810
 811         /* build TCE tables for each PHB */
 812         ret = build_tce_table(dev, bbar);
 813         if (ret)
 814                 return ret;
 815
 816         tbl = pci_iommu(dev->bus);
 817         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 818
 819         if (is_kdump_kernel())
 820                 calgary_init_bitmap_from_tce_table(tbl);
 821         else
 822                 tce_free(tbl, 0, tbl->it_size);
 823
 824         if (is_calgary(dev->device))
 825                 tbl->chip_ops = &calgary_chip_ops;
 826         else if (is_calioc2(dev->device))
 827                 tbl->chip_ops = &calioc2_chip_ops;
 828         else
 829                 BUG();
 830
 831         calgary_reserve_regions(dev);
 832
 833         /* set TARs for each PHB */
 834         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 835         val64 = be64_to_cpu(readq(target));
 836
 837         /* zero out all TAR bits under sw control */
 838         val64 &= ~TAR_SW_BITS;
 839         table_phys = (u64)__pa(tbl->it_base);
 840
 841         val64 |= table_phys;
 842
 843         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 844         val64 |= (u64) specified_table_size;
 845
 846         tbl->tar_val = cpu_to_be64(val64);
 847
 848         writeq(tbl->tar_val, target);
 849         readq(target); /* flush */
 850
 851         return 0;
 852 }
 853
 854 static void __init calgary_free_bus(struct pci_dev *dev)
 855 {
 856         u64 val64;
 857         struct iommu_table *tbl = pci_iommu(dev->bus);
 858         void __iomem *target;
 859         unsigned int bitmapsz;
 860
 861         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 862         val64 = be64_to_cpu(readq(target));
 863         val64 &= ~TAR_SW_BITS;
 864         writeq(cpu_to_be64(val64), target);
 865         readq(target); /* flush */
 866
 867         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 868         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 869         tbl->it_map = NULL;
 870
 871         kfree(tbl);
 872
 873         set_pci_iommu(dev->bus, NULL);
 874
 875         /* Can't free bootmem allocated memory after system is up :-( */
 876         bus_info[dev->bus->number].tce_space = NULL;
 877 }
 878
 879 static void calgary_dump_error_regs(struct iommu_table *tbl)
 880 {
 881         void __iomem *bbar = tbl->bbar;
 882         void __iomem *target;
 883         u32 csr, plssr;
 884
 885         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 886         csr = be32_to_cpu(readl(target));
 887
 888         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 889         plssr = be32_to_cpu(readl(target));
 890
 891         /* If no error, the agent ID in the CSR is not valid */
 892         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 893                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 894 }
 895
 896 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 897 {
 898         void __iomem *bbar = tbl->bbar;
 899         u32 csr, csmr, plssr, mck, rcstat;
 900         void __iomem *target;
 901         unsigned long phboff = phb_offset(tbl->it_busno);
 902         unsigned long erroff;
 903         u32 errregs[7];
 904         int i;
 905
 906         /* dump CSR */
 907         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 908         csr = be32_to_cpu(readl(target));
 909         /* dump PLSSR */
 910         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 911         plssr = be32_to_cpu(readl(target));
 912         /* dump CSMR */
 913         target = calgary_reg(bbar, phboff | 0x290);
 914         csmr = be32_to_cpu(readl(target));
 915         /* dump mck */
 916         target = calgary_reg(bbar, phboff | 0x800);
 917         mck = be32_to_cpu(readl(target));
 918
 919         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 920                tbl->it_busno);
 921
 922         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 923                csr, plssr, csmr, mck);
 924
 925         /* dump rest of error regs */
 926         printk(KERN_EMERG "Calgary: ");
 927         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 928                 /* err regs are at 0x810 - 0x870 */
 929                 erroff = (0x810 + (i * 0x10));
 930                 target = calgary_reg(bbar, phboff | erroff);
 931                 errregs[i] = be32_to_cpu(readl(target));
 932                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 933         }
 934         printk("\n");
 935
 936         /* root complex status */
 937         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 938         rcstat = be32_to_cpu(readl(target));
 939         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 940                PHB_ROOT_COMPLEX_STATUS);
 941 }
 942
 943 static void calgary_watchdog(unsigned long data)
 944 {
 945         struct pci_dev *dev = (struct pci_dev *)data;
 946         struct iommu_table *tbl = pci_iommu(dev->bus);
 947         void __iomem *bbar = tbl->bbar;
 948         u32 val32;
 949         void __iomem *target;
 950
 951         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 952         val32 = be32_to_cpu(readl(target));
 953
 954         /* If no error, the agent ID in the CSR is not valid */
 955         if (val32 & CSR_AGENT_MASK) {
 956                 tbl->chip_ops->dump_error_regs(tbl);
 957
 958                 /* reset error */
 959                 writel(0, target);
 960
 961                 /* Disable bus that caused the error */
 962                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 963                                      PHB_CONFIG_RW_OFFSET);
 964                 val32 = be32_to_cpu(readl(target));
 965                 val32 |= PHB_SLOT_DISABLE;
 966                 writel(cpu_to_be32(val32), target);
 967                 readl(target); /* flush */
 968         } else {
 969                 /* Reset the timer */
 970                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 971         }
 972 }
 973
 974 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 975         unsigned char busnum, unsigned long timeout)
 976 {
 977         u64 val64;
 978         void __iomem *target;
 979         unsigned int phb_shift = ~0; /* silence gcc */
 980         u64 mask;
 981
 982         switch (busno_to_phbid(busnum)) {
 983         case 0: phb_shift = (63 - 19);
 984                 break;
 985         case 1: phb_shift = (63 - 23);
 986                 break;
 987         case 2: phb_shift = (63 - 27);
 988                 break;
 989         case 3: phb_shift = (63 - 35);
 990                 break;
 991         default:
 992                 BUG_ON(busno_to_phbid(busnum));
 993         }
 994
 995         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 996         val64 = be64_to_cpu(readq(target));
 997
 998         /* zero out this PHB's timer bits */
 999         mask = ~(0xFUL << phb_shift);
1000         val64 &= mask;
1001         val64 |= (timeout << phb_shift);
1002         writeq(cpu_to_be64(val64), target);
1003         readq(target); /* flush */
1004 }
1005
1006 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1007 {
1008         unsigned char busnum = dev->bus->number;
1009         void __iomem *bbar = tbl->bbar;
1010         void __iomem *target;
1011         u32 val;
1012
1013         /*
1014          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1015          */
1016         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1017         val = cpu_to_be32(readl(target));
1018         val |= 0x00800000;
1019         writel(cpu_to_be32(val), target);
1020 }
1021
1022 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1023 {
1024         unsigned char busnum = dev->bus->number;
1025
1026         /*
1027          * Give split completion a longer timeout on bus 1 for aic94xx
1028          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1029          */
1030         if (is_calgary(dev->device) && (busnum == 1))
1031                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1032                                                      CCR_2SEC_TIMEOUT);
1033 }
1034
1035 static void __init calgary_enable_translation(struct pci_dev *dev)
1036 {
1037         u32 val32;
1038         unsigned char busnum;
1039         void __iomem *target;
1040         void __iomem *bbar;
1041         struct iommu_table *tbl;
1042
1043         busnum = dev->bus->number;
1044         tbl = pci_iommu(dev->bus);
1045         bbar = tbl->bbar;
1046
1047         /* enable TCE in PHB Config Register */
1048         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1049         val32 = be32_to_cpu(readl(target));
1050         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1051
1052         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1053                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1054                "Calgary" : "CalIOC2", busnum);
1055         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1056                "bus.\n");
1057
1058         writel(cpu_to_be32(val32), target);
1059         readl(target); /* flush */
1060
1061         init_timer(&tbl->watchdog_timer);
1062         tbl->watchdog_timer.function = &calgary_watchdog;
1063         tbl->watchdog_timer.data = (unsigned long)dev;
1064         mod_timer(&tbl->watchdog_timer, jiffies);
1065 }
1066
1067 static void __init calgary_disable_translation(struct pci_dev *dev)
1068 {
1069         u32 val32;
1070         unsigned char busnum;
1071         void __iomem *target;
1072         void __iomem *bbar;
1073         struct iommu_table *tbl;
1074
1075         busnum = dev->bus->number;
1076         tbl = pci_iommu(dev->bus);
1077         bbar = tbl->bbar;
1078
1079         /* disable TCE in PHB Config Register */
1080         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1081         val32 = be32_to_cpu(readl(target));
1082         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1083
1084         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1085         writel(cpu_to_be32(val32), target);
1086         readl(target); /* flush */
1087
1088         del_timer_sync(&tbl->watchdog_timer);
1089 }
1090
1091 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1092 {
1093         pci_dev_get(dev);
1094         set_pci_iommu(dev->bus, NULL);
1095
1096         /* is the device behind a bridge? */
1097         if (dev->bus->parent)
1098                 dev->bus->parent->self = dev;
1099         else
1100                 dev->bus->self = dev;
1101 }
1102
1103 static int __init calgary_init_one(struct pci_dev *dev)
1104 {
1105         void __iomem *bbar;
1106         struct iommu_table *tbl;
1107         int ret;
1108
1109         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1110
1111         bbar = busno_to_bbar(dev->bus->number);
1112         ret = calgary_setup_tar(dev, bbar);
1113         if (ret)
1114                 goto done;
1115
1116         pci_dev_get(dev);
1117
1118         if (dev->bus->parent) {
1119                 if (dev->bus->parent->self)
1120                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1121                                "bus->parent->self!\n", dev);
1122                 dev->bus->parent->self = dev;
1123         } else
1124                 dev->bus->self = dev;
1125
1126         tbl = pci_iommu(dev->bus);
1127         tbl->chip_ops->handle_quirks(tbl, dev);
1128
1129         calgary_enable_translation(dev);
1130
1131         return 0;
1132
1133 done:
1134         return ret;
1135 }
1136
1137 static int __init calgary_locate_bbars(void)
1138 {
1139         int ret;
1140         int rioidx, phb, bus;
1141         void __iomem *bbar;
1142         void __iomem *target;
1143         unsigned long offset;
1144         u8 start_bus, end_bus;
1145         u32 val;
1146
1147         ret = -ENODATA;
1148         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1149                 struct rio_detail *rio = rio_devs[rioidx];
1150
1151                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1152                         continue;
1153
1154                 /* map entire 1MB of Calgary config space */
1155                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1156                 if (!bbar)
1157                         goto error;
1158
1159                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1160                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1161                         target = calgary_reg(bbar, offset);
1162
1163                         val = be32_to_cpu(readl(target));
1164
1165                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1166                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1167
1168                         if (end_bus) {
1169                                 for (bus = start_bus; bus <= end_bus; bus++) {
1170                                         bus_info[bus].bbar = bbar;
1171                                         bus_info[bus].phbid = phb;
1172                                 }
1173                         } else {
1174                                 bus_info[start_bus].bbar = bbar;
1175                                 bus_info[start_bus].phbid = phb;
1176                         }
1177                 }
1178         }
1179
1180         return 0;
1181
1182 error:
1183         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1184         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1185                 if (bus_info[bus].bbar)
1186                         iounmap(bus_info[bus].bbar);
1187
1188         return ret;
1189 }
1190
1191 static int __init calgary_init(void)
1192 {
1193         int ret;
1194         struct pci_dev *dev = NULL;
1195         struct calgary_bus_info *info;
1196
1197         ret = calgary_locate_bbars();
1198         if (ret)
1199                 return ret;
1200
1201         /* Purely for kdump kernel case */
1202         if (is_kdump_kernel())
1203                 get_tce_space_from_tar();
1204
1205         do {
1206                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1207                 if (!dev)
1208                         break;
1209                 if (!is_cal_pci_dev(dev->device))
1210                         continue;
1211
1212                 info = &bus_info[dev->bus->number];
1213                 if (info->translation_disabled) {
1214                         calgary_init_one_nontraslated(dev);
1215                         continue;
1216                 }
1217
1218                 if (!info->tce_space && !translate_empty_slots)
1219                         continue;
1220
1221                 ret = calgary_init_one(dev);
1222                 if (ret)
1223                         goto error;
1224         } while (1);
1225
1226         dev = NULL;
1227         for_each_pci_dev(dev) {
1228                 struct iommu_table *tbl;
1229
1230                 tbl = find_iommu_table(&dev->dev);
1231
1232                 if (translation_enabled(tbl))
1233                         dev->dev.archdata.dma_ops = &calgary_dma_ops;
1234         }
1235
1236         return ret;
1237
1238 error:
1239         do {
1240                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1241                 if (!dev)
1242                         break;
1243                 if (!is_cal_pci_dev(dev->device))
1244                         continue;
1245
1246                 info = &bus_info[dev->bus->number];
1247                 if (info->translation_disabled) {
1248                         pci_dev_put(dev);
1249                         continue;
1250                 }
1251                 if (!info->tce_space && !translate_empty_slots)
1252                         continue;
1253
1254                 calgary_disable_translation(dev);
1255                 calgary_free_bus(dev);
1256                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1257                 dev->dev.archdata.dma_ops = NULL;
1258         } while (1);
1259
1260         return ret;
1261 }
1262
1263 static inline int __init determine_tce_table_size(u64 ram)
1264 {
1265         int ret;
1266
1267         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1268                 return specified_table_size;
1269
1270         /*
1271          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1272          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1273          * larger table size has twice as many entries, so shift the
1274          * max ram address by 13 to divide by 8K and then look at the
1275          * order of the result to choose between 0-7.
1276          */
1277         ret = get_order(ram >> 13);
1278         if (ret > TCE_TABLE_SIZE_8M)
1279                 ret = TCE_TABLE_SIZE_8M;
1280
1281         return ret;
1282 }
1283
1284 static int __init build_detail_arrays(void)
1285 {
1286         unsigned long ptr;
1287         unsigned numnodes, i;
1288         int scal_detail_size, rio_detail_size;
1289
1290         numnodes = rio_table_hdr->num_scal_dev;
1291         if (numnodes > MAX_NUMNODES){
1292                 printk(KERN_WARNING
1293                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1294                         "but system has %d nodes.\n",
1295                         MAX_NUMNODES, numnodes);
1296                 return -ENODEV;
1297         }
1298
1299         switch (rio_table_hdr->version){
1300         case 2:
1301                 scal_detail_size = 11;
1302                 rio_detail_size = 13;
1303                 break;
1304         case 3:
1305                 scal_detail_size = 12;
1306                 rio_detail_size = 15;
1307                 break;
1308         default:
1309                 printk(KERN_WARNING
1310                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1311                        rio_table_hdr->version);
1312                 return -EPROTO;
1313         }
1314
1315         ptr = ((unsigned long)rio_table_hdr) + 3;
1316         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1317                 scal_devs[i] = (struct scal_detail *)ptr;
1318
1319         for (i = 0; i < rio_table_hdr->num_rio_dev;
1320                     i++, ptr += rio_detail_size)
1321                 rio_devs[i] = (struct rio_detail *)ptr;
1322
1323         return 0;
1324 }
1325
1326 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1327 {
1328         int dev;
1329         u32 val;
1330
1331         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1332                 /*
1333                  * FIXME: properly scan for devices accross the
1334                  * PCI-to-PCI bridge on every CalIOC2 port.
1335                  */
1336                 return 1;
1337         }
1338
1339         for (dev = 1; dev < 8; dev++) {
1340                 val = read_pci_config(bus, dev, 0, 0);
1341                 if (val != 0xffffffff)
1342                         break;
1343         }
1344         return (val != 0xffffffff);
1345 }
1346
1347 /*
1348  * calgary_init_bitmap_from_tce_table():
1349  * Funtion for kdump case. In the second/kdump kernel initialize
1350  * the bitmap based on the tce table entries obtained from first kernel
1351  */
1352 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1353 {
1354         u64 *tp;
1355         unsigned int index;
1356         tp = ((u64 *)tbl->it_base);
1357         for (index = 0 ; index < tbl->it_size; index++) {
1358                 if (*tp != 0x0)
1359                         set_bit(index, tbl->it_map);
1360                 tp++;
1361         }
1362 }
1363
1364 /*
1365  * get_tce_space_from_tar():
1366  * Function for kdump case. Get the tce tables from first kernel
1367  * by reading the contents of the base adress register of calgary iommu
1368  */
1369 static void __init get_tce_space_from_tar(void)
1370 {
1371         int bus;
1372         void __iomem *target;
1373         unsigned long tce_space;
1374
1375         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1376                 struct calgary_bus_info *info = &bus_info[bus];
1377                 unsigned short pci_device;
1378                 u32 val;
1379
1380                 val = read_pci_config(bus, 0, 0, 0);
1381                 pci_device = (val & 0xFFFF0000) >> 16;
1382
1383                 if (!is_cal_pci_dev(pci_device))
1384                         continue;
1385                 if (info->translation_disabled)
1386                         continue;
1387
1388                 if (calgary_bus_has_devices(bus, pci_device) ||
1389                                                 translate_empty_slots) {
1390                         target = calgary_reg(bus_info[bus].bbar,
1391                                                 tar_offset(bus));
1392                         tce_space = be64_to_cpu(readq(target));
1393                         tce_space = tce_space & TAR_SW_BITS;
1394
1395                         tce_space = tce_space & (~specified_table_size);
1396                         info->tce_space = (u64 *)__va(tce_space);
1397                 }
1398         }
1399         return;
1400 }
1401
1402 void __init detect_calgary(void)
1403 {
1404         int bus;
1405         void *tbl;
1406         int calgary_found = 0;
1407         unsigned long ptr;
1408         unsigned int offset, prev_offset;
1409         int ret;
1410
1411         /*
1412          * if the user specified iommu=off or iommu=soft or we found
1413          * another HW IOMMU already, bail out.
1414          */
1415         if (swiotlb || no_iommu || iommu_detected)
1416                 return;
1417
1418         if (!use_calgary)
1419                 return;
1420
1421         if (!early_pci_allowed())
1422                 return;
1423
1424         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1425
1426         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1427
1428         rio_table_hdr = NULL;
1429         prev_offset = 0;
1430         offset = 0x180;
1431         /*
1432          * The next offset is stored in the 1st word.
1433          * Only parse up until the offset increases:
1434          */
1435         while (offset > prev_offset) {
1436                 /* The block id is stored in the 2nd word */
1437                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1438                         /* set the pointer past the offset & block id */
1439                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1440                         break;
1441                 }
1442                 prev_offset = offset;
1443                 offset = *((unsigned short *)(ptr + offset));
1444         }
1445         if (!rio_table_hdr) {
1446                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1447                        "in EBDA - bailing!\n");
1448                 return;
1449         }
1450
1451         ret = build_detail_arrays();
1452         if (ret) {
1453                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1454                 return;
1455         }
1456
1457         specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1458                                         saved_max_pfn : max_pfn) * PAGE_SIZE);
1459
1460         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1461                 struct calgary_bus_info *info = &bus_info[bus];
1462                 unsigned short pci_device;
1463                 u32 val;
1464
1465                 val = read_pci_config(bus, 0, 0, 0);
1466                 pci_device = (val & 0xFFFF0000) >> 16;
1467
1468                 if (!is_cal_pci_dev(pci_device))
1469                         continue;
1470
1471                 if (info->translation_disabled)
1472                         continue;
1473
1474                 if (calgary_bus_has_devices(bus, pci_device) ||
1475                     translate_empty_slots) {
1476                         /*
1477                          * If it is kdump kernel, find and use tce tables
1478                          * from first kernel, else allocate tce tables here
1479                          */
1480                         if (!is_kdump_kernel()) {
1481                                 tbl = alloc_tce_table();
1482                                 if (!tbl)
1483                                         goto cleanup;
1484                                 info->tce_space = tbl;
1485                         }
1486                         calgary_found = 1;
1487                 }
1488         }
1489
1490         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1491                calgary_found ? "found" : "not found");
1492
1493         if (calgary_found) {
1494                 iommu_detected = 1;
1495                 calgary_detected = 1;
1496                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1497                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1498                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1499                        debugging ? "enabled" : "disabled");
1500
1501                 /* swiotlb for devices that aren't behind the Calgary. */
1502                 if (max_pfn > MAX_DMA32_PFN)
1503                         swiotlb = 1;
1504         }
1505         return;
1506
1507 cleanup:
1508         for (--bus; bus >= 0; --bus) {
1509                 struct calgary_bus_info *info = &bus_info[bus];
1510
1511                 if (info->tce_space)
1512                         free_tce_table(info->tce_space);
1513         }
1514 }
1515
1516 int __init calgary_iommu_init(void)
1517 {
1518         int ret;
1519
1520         if (no_iommu || (swiotlb && !calgary_detected))
1521                 return -ENODEV;
1522
1523         if (!calgary_detected)
1524                 return -ENODEV;
1525
1526         /* ok, we're trying to use Calgary - let's roll */
1527         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1528
1529         ret = calgary_init();
1530         if (ret) {
1531                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1532                        "falling back to no_iommu\n", ret);
1533                 return ret;
1534         }
1535
1536         force_iommu = 1;
1537         bad_dma_address = 0x0;
1538         /* dma_ops is set to swiotlb or nommu */
1539         if (!dma_ops)
1540                 dma_ops = &nommu_dma_ops;
1541
1542         return 0;
1543 }
1544
1545 static int __init calgary_parse_options(char *p)
1546 {
1547         unsigned int bridge;
1548         size_t len;
1549         char* endp;
1550
1551         while (*p) {
1552                 if (!strncmp(p, "64k", 3))
1553                         specified_table_size = TCE_TABLE_SIZE_64K;
1554                 else if (!strncmp(p, "128k", 4))
1555                         specified_table_size = TCE_TABLE_SIZE_128K;
1556                 else if (!strncmp(p, "256k", 4))
1557                         specified_table_size = TCE_TABLE_SIZE_256K;
1558                 else if (!strncmp(p, "512k", 4))
1559                         specified_table_size = TCE_TABLE_SIZE_512K;
1560                 else if (!strncmp(p, "1M", 2))
1561                         specified_table_size = TCE_TABLE_SIZE_1M;
1562                 else if (!strncmp(p, "2M", 2))
1563                         specified_table_size = TCE_TABLE_SIZE_2M;
1564                 else if (!strncmp(p, "4M", 2))
1565                         specified_table_size = TCE_TABLE_SIZE_4M;
1566                 else if (!strncmp(p, "8M", 2))
1567                         specified_table_size = TCE_TABLE_SIZE_8M;
1568
1569                 len = strlen("translate_empty_slots");
1570                 if (!strncmp(p, "translate_empty_slots", len))
1571                         translate_empty_slots = 1;
1572
1573                 len = strlen("disable");
1574                 if (!strncmp(p, "disable", len)) {
1575                         p += len;
1576                         if (*p == '=')
1577                                 ++p;
1578                         if (*p == '\0')
1579                                 break;
1580                         bridge = simple_strtol(p, &endp, 0);
1581                         if (p == endp)
1582                                 break;
1583
1584                         if (bridge < MAX_PHB_BUS_NUM) {
1585                                 printk(KERN_INFO "Calgary: disabling "
1586                                        "translation for PHB %#x\n", bridge);
1587                                 bus_info[bridge].translation_disabled = 1;
1588                         }
1589                 }
1590
1591                 p = strpbrk(p, ",");
1592                 if (!p)
1593                         break;
1594
1595                 p++; /* skip ',' */
1596         }
1597         return 1;
1598 }
1599 __setup("calgary=", calgary_parse_options);
1600
1601 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1602 {
1603         struct iommu_table *tbl;
1604         unsigned int npages;
1605         int i;
1606
1607         tbl = pci_iommu(dev->bus);
1608
1609         for (i = 0; i < 4; i++) {
1610                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1611
1612                 /* Don't give out TCEs that map MEM resources */
1613                 if (!(r->flags & IORESOURCE_MEM))
1614                         continue;
1615
1616                 /* 0-based? we reserve the whole 1st MB anyway */
1617                 if (!r->start)
1618                         continue;
1619
1620                 /* cover the whole region */
1621                 npages = (r->end - r->start) >> PAGE_SHIFT;
1622                 npages++;
1623
1624                 iommu_range_reserve(tbl, r->start, npages);
1625         }
1626 }
1627
1628 static int __init calgary_fixup_tce_spaces(void)
1629 {
1630         struct pci_dev *dev = NULL;
1631         struct calgary_bus_info *info;
1632
1633         if (no_iommu || swiotlb || !calgary_detected)
1634                 return -ENODEV;
1635
1636         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1637
1638         do {
1639                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1640                 if (!dev)
1641                         break;
1642                 if (!is_cal_pci_dev(dev->device))
1643                         continue;
1644
1645                 info = &bus_info[dev->bus->number];
1646                 if (info->translation_disabled)
1647                         continue;
1648
1649                 if (!info->tce_space)
1650                         continue;
1651
1652                 calgary_fixup_one_tce_space(dev);
1653
1654         } while (1);
1655
1656         return 0;
1657 }
1658
1659 /*
1660  * We need to be call after pcibios_assign_resources (fs_initcall level)
1661  * and before device_initcall.
1662  */
1663 rootfs_initcall(calgary_fixup_tce_spaces);