arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <linux/scatterlist.h>
  39 #include <asm/iommu.h>
  40 #include <asm/calgary.h>
  41 #include <asm/tce.h>
  42 #include <asm/pci-direct.h>
  43 #include <asm/system.h>
  44 #include <asm/dma.h>
  45 #include <asm/rio.h>
  46
  47 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  48 int use_calgary __read_mostly = 1;
  49 #else
  50 int use_calgary __read_mostly = 0;
  51 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  52
  53 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  54 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  55
  56 /* register offsets inside the host bridge space */
  57 #define CALGARY_CONFIG_REG      0x0108
  58 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  59 #define PHB_PLSSR_OFFSET        0x0120
  60 #define PHB_CONFIG_RW_OFFSET    0x0160
  61 #define PHB_IOBASE_BAR_LOW      0x0170
  62 #define PHB_IOBASE_BAR_HIGH     0x0180
  63 #define PHB_MEM_1_LOW           0x0190
  64 #define PHB_MEM_1_HIGH          0x01A0
  65 #define PHB_IO_ADDR_SIZE        0x01B0
  66 #define PHB_MEM_1_SIZE          0x01C0
  67 #define PHB_MEM_ST_OFFSET       0x01D0
  68 #define PHB_AER_OFFSET          0x0200
  69 #define PHB_CONFIG_0_HIGH       0x0220
  70 #define PHB_CONFIG_0_LOW        0x0230
  71 #define PHB_CONFIG_0_END        0x0240
  72 #define PHB_MEM_2_LOW           0x02B0
  73 #define PHB_MEM_2_HIGH          0x02C0
  74 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  75 #define PHB_MEM_2_SIZE_LOW      0x02E0
  76 #define PHB_DOSHOLE_OFFSET      0x08E0
  77
  78 /* CalIOC2 specific */
  79 #define PHB_SAVIOR_L2           0x0DB0
  80 #define PHB_PAGE_MIG_CTRL       0x0DA8
  81 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  82 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  83
  84 /* PHB_CONFIG_RW */
  85 #define PHB_TCE_ENABLE          0x20000000
  86 #define PHB_SLOT_DISABLE        0x1C000000
  87 #define PHB_DAC_DISABLE         0x01000000
  88 #define PHB_MEM2_ENABLE         0x00400000
  89 #define PHB_MCSR_ENABLE         0x00100000
  90 /* TAR (Table Address Register) */
  91 #define TAR_SW_BITS             0x0000ffffffff800fUL
  92 #define TAR_VALID               0x0000000000000008UL
  93 /* CSR (Channel/DMA Status Register) */
  94 #define CSR_AGENT_MASK          0xffe0ffff
  95 /* CCR (Calgary Configuration Register) */
  96 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  97 /* PMCR/PMDR (Page Migration Control/Debug Registers */
  98 #define PMR_SOFTSTOP            0x80000000
  99 #define PMR_SOFTSTOPFAULT       0x40000000
 100 #define PMR_HARDSTOP            0x20000000
 101
 102 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 103 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 104 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 105 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 106 #define PHBS_PER_CALGARY        4
 107
 108 /* register offsets in Calgary's internal register space */
 109 static const unsigned long tar_offsets[] = {
 110         0x0580 /* TAR0 */,
 111         0x0588 /* TAR1 */,
 112         0x0590 /* TAR2 */,
 113         0x0598 /* TAR3 */
 114 };
 115
 116 static const unsigned long split_queue_offsets[] = {
 117         0x4870 /* SPLIT QUEUE 0 */,
 118         0x5870 /* SPLIT QUEUE 1 */,
 119         0x6870 /* SPLIT QUEUE 2 */,
 120         0x7870 /* SPLIT QUEUE 3 */
 121 };
 122
 123 static const unsigned long phb_offsets[] = {
 124         0x8000 /* PHB0 */,
 125         0x9000 /* PHB1 */,
 126         0xA000 /* PHB2 */,
 127         0xB000 /* PHB3 */
 128 };
 129
 130 /* PHB debug registers */
 131
 132 static const unsigned long phb_debug_offsets[] = {
 133         0x4000  /* PHB 0 DEBUG */,
 134         0x5000  /* PHB 1 DEBUG */,
 135         0x6000  /* PHB 2 DEBUG */,
 136         0x7000  /* PHB 3 DEBUG */
 137 };
 138
 139 /*
 140  * STUFF register for each debug PHB,
 141  * byte 1 = start bus number, byte 2 = end bus number
 142  */
 143
 144 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 145
 146 #define EMERGENCY_PAGES 32 /* = 128KB */
 147
 148 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 149 static int translate_empty_slots __read_mostly = 0;
 150 static int calgary_detected __read_mostly = 0;
 151
 152 static struct rio_table_hdr     *rio_table_hdr __initdata;
 153 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 154 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 155
 156 struct calgary_bus_info {
 157         void *tce_space;
 158         unsigned char translation_disabled;
 159         signed char phbid;
 160         void __iomem *bbar;
 161 };
 162
 163 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 164 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 165 static void calgary_dump_error_regs(struct iommu_table *tbl);
 166 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 167 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 168 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 169
 170 static struct cal_chipset_ops calgary_chip_ops = {
 171         .handle_quirks = calgary_handle_quirks,
 172         .tce_cache_blast = calgary_tce_cache_blast,
 173         .dump_error_regs = calgary_dump_error_regs
 174 };
 175
 176 static struct cal_chipset_ops calioc2_chip_ops = {
 177         .handle_quirks = calioc2_handle_quirks,
 178         .tce_cache_blast = calioc2_tce_cache_blast,
 179         .dump_error_regs = calioc2_dump_error_regs
 180 };
 181
 182 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 183
 184 /* enable this to stress test the chip's TCE cache */
 185 #ifdef CONFIG_IOMMU_DEBUG
 186 int debugging __read_mostly = 1;
 187
 188 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 189         int expected, unsigned long start, unsigned long end)
 190 {
 191         unsigned long idx = start;
 192
 193         BUG_ON(start >= end);
 194
 195         while (idx < end) {
 196                 if (!!test_bit(idx, bitmap) != expected)
 197                         return idx;
 198                 ++idx;
 199         }
 200
 201         /* all bits have the expected value */
 202         return ~0UL;
 203 }
 204 #else /* debugging is disabled */
 205 int debugging __read_mostly = 0;
 206
 207 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 208         int expected, unsigned long start, unsigned long end)
 209 {
 210         return ~0UL;
 211 }
 212
 213 #endif /* CONFIG_IOMMU_DEBUG */
 214
 215 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 216 {
 217         unsigned int npages;
 218
 219         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 220         npages >>= PAGE_SHIFT;
 221
 222         return npages;
 223 }
 224
 225 static inline int translate_phb(struct pci_dev* dev)
 226 {
 227         int disabled = bus_info[dev->bus->number].translation_disabled;
 228         return !disabled;
 229 }
 230
 231 static void iommu_range_reserve(struct iommu_table *tbl,
 232         unsigned long start_addr, unsigned int npages)
 233 {
 234         unsigned long index;
 235         unsigned long end;
 236         unsigned long badbit;
 237         unsigned long flags;
 238
 239         index = start_addr >> PAGE_SHIFT;
 240
 241         /* bail out if we're asked to reserve a region we don't cover */
 242         if (index >= tbl->it_size)
 243                 return;
 244
 245         end = index + npages;
 246         if (end > tbl->it_size) /* don't go off the table */
 247                 end = tbl->it_size;
 248
 249         spin_lock_irqsave(&tbl->it_lock, flags);
 250
 251         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 252         if (badbit != ~0UL) {
 253                 if (printk_ratelimit())
 254                         printk(KERN_ERR "Calgary: entry already allocated at "
 255                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 256                                badbit, tbl, start_addr, npages);
 257         }
 258
 259         set_bit_string(tbl->it_map, index, npages);
 260
 261         spin_unlock_irqrestore(&tbl->it_lock, flags);
 262 }
 263
 264 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 265         unsigned int npages)
 266 {
 267         unsigned long flags;
 268         unsigned long offset;
 269
 270         BUG_ON(npages == 0);
 271
 272         spin_lock_irqsave(&tbl->it_lock, flags);
 273
 274         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 275                                        tbl->it_size, npages);
 276         if (offset == ~0UL) {
 277                 tbl->chip_ops->tce_cache_blast(tbl);
 278                 offset = find_next_zero_string(tbl->it_map, 0,
 279                                                tbl->it_size, npages);
 280                 if (offset == ~0UL) {
 281                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 282                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 283                         if (panic_on_overflow)
 284                                 panic("Calgary: fix the allocator.\n");
 285                         else
 286                                 return bad_dma_address;
 287                 }
 288         }
 289
 290         set_bit_string(tbl->it_map, offset, npages);
 291         tbl->it_hint = offset + npages;
 292         BUG_ON(tbl->it_hint > tbl->it_size);
 293
 294         spin_unlock_irqrestore(&tbl->it_lock, flags);
 295
 296         return offset;
 297 }
 298
 299 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 300         unsigned int npages, int direction)
 301 {
 302         unsigned long entry;
 303         dma_addr_t ret = bad_dma_address;
 304
 305         entry = iommu_range_alloc(tbl, npages);
 306
 307         if (unlikely(entry == bad_dma_address))
 308                 goto error;
 309
 310         /* set the return dma address */
 311         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 312
 313         /* put the TCEs in the HW table */
 314         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 315                   direction);
 316
 317         return ret;
 318
 319 error:
 320         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 321                "iommu %p\n", npages, tbl);
 322         return bad_dma_address;
 323 }
 324
 325 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 326         unsigned int npages)
 327 {
 328         unsigned long entry;
 329         unsigned long badbit;
 330         unsigned long badend;
 331         unsigned long flags;
 332
 333         /* were we called with bad_dma_address? */
 334         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 335         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 336                 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
 337                        "address 0x%Lx\n", dma_addr);
 338                 WARN_ON(1);
 339                 return;
 340         }
 341
 342         entry = dma_addr >> PAGE_SHIFT;
 343
 344         BUG_ON(entry + npages > tbl->it_size);
 345
 346         tce_free(tbl, entry, npages);
 347
 348         spin_lock_irqsave(&tbl->it_lock, flags);
 349
 350         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 351         if (badbit != ~0UL) {
 352                 if (printk_ratelimit())
 353                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 354                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 355                                badbit, tbl, dma_addr, entry, npages);
 356         }
 357
 358         __clear_bit_string(tbl->it_map, entry, npages);
 359
 360         spin_unlock_irqrestore(&tbl->it_lock, flags);
 361 }
 362
 363 static inline struct iommu_table *find_iommu_table(struct device *dev)
 364 {
 365         struct pci_dev *pdev;
 366         struct pci_bus *pbus;
 367         struct iommu_table *tbl;
 368
 369         pdev = to_pci_dev(dev);
 370
 371         pbus = pdev->bus;
 372
 373         /* is the device behind a bridge? Look for the root bus */
 374         while (pbus->parent)
 375                 pbus = pbus->parent;
 376
 377         tbl = pci_iommu(pbus);
 378
 379         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 380
 381         return tbl;
 382 }
 383
 384 static void calgary_unmap_sg(struct device *dev,
 385         struct scatterlist *sglist, int nelems, int direction)
 386 {
 387         struct iommu_table *tbl = find_iommu_table(dev);
 388         struct scatterlist *s;
 389         int i;
 390
 391         if (!translate_phb(to_pci_dev(dev)))
 392                 return;
 393
 394         for_each_sg(sglist, s, nelems, i) {
 395                 unsigned int npages;
 396                 dma_addr_t dma = s->dma_address;
 397                 unsigned int dmalen = s->dma_length;
 398
 399                 if (dmalen == 0)
 400                         break;
 401
 402                 npages = num_dma_pages(dma, dmalen);
 403                 iommu_free(tbl, dma, npages);
 404         }
 405 }
 406
 407 static int calgary_nontranslate_map_sg(struct device* dev,
 408         struct scatterlist *sg, int nelems, int direction)
 409 {
 410         struct scatterlist *s;
 411         int i;
 412
 413         for_each_sg(sg, s, nelems, i) {
 414                 BUG_ON(!s->page);
 415                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 416                 s->dma_length = s->length;
 417         }
 418         return nelems;
 419 }
 420
 421 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 422         int nelems, int direction)
 423 {
 424         struct iommu_table *tbl = find_iommu_table(dev);
 425         struct scatterlist *s;
 426         unsigned long vaddr;
 427         unsigned int npages;
 428         unsigned long entry;
 429         int i;
 430
 431         if (!translate_phb(to_pci_dev(dev)))
 432                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 433
 434         for_each_sg(sg, s, nelems, i) {
 435                 BUG_ON(!s->page);
 436
 437                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 438                 npages = num_dma_pages(vaddr, s->length);
 439
 440                 entry = iommu_range_alloc(tbl, npages);
 441                 if (entry == bad_dma_address) {
 442                         /* makes sure unmap knows to stop */
 443                         s->dma_length = 0;
 444                         goto error;
 445                 }
 446
 447                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 448
 449                 /* insert into HW table */
 450                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 451                           direction);
 452
 453                 s->dma_length = s->length;
 454         }
 455
 456         return nelems;
 457 error:
 458         calgary_unmap_sg(dev, sg, nelems, direction);
 459         for_each_sg(sg, s, nelems, i) {
 460                 sg->dma_address = bad_dma_address;
 461                 sg->dma_length = 0;
 462         }
 463         return 0;
 464 }
 465
 466 static dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 467         size_t size, int direction)
 468 {
 469         dma_addr_t dma_handle = bad_dma_address;
 470         unsigned long uaddr;
 471         unsigned int npages;
 472         struct iommu_table *tbl = find_iommu_table(dev);
 473
 474         uaddr = (unsigned long)vaddr;
 475         npages = num_dma_pages(uaddr, size);
 476
 477         if (translate_phb(to_pci_dev(dev)))
 478                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 479         else
 480                 dma_handle = virt_to_bus(vaddr);
 481
 482         return dma_handle;
 483 }
 484
 485 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 486         size_t size, int direction)
 487 {
 488         struct iommu_table *tbl = find_iommu_table(dev);
 489         unsigned int npages;
 490
 491         if (!translate_phb(to_pci_dev(dev)))
 492                 return;
 493
 494         npages = num_dma_pages(dma_handle, size);
 495         iommu_free(tbl, dma_handle, npages);
 496 }
 497
 498 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 499         dma_addr_t *dma_handle, gfp_t flag)
 500 {
 501         void *ret = NULL;
 502         dma_addr_t mapping;
 503         unsigned int npages, order;
 504         struct iommu_table *tbl = find_iommu_table(dev);
 505
 506         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 507         npages = size >> PAGE_SHIFT;
 508         order = get_order(size);
 509
 510         /* alloc enough pages (and possibly more) */
 511         ret = (void *)__get_free_pages(flag, order);
 512         if (!ret)
 513                 goto error;
 514         memset(ret, 0, size);
 515
 516         if (translate_phb(to_pci_dev(dev))) {
 517                 /* set up tces to cover the allocated range */
 518                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 519                 if (mapping == bad_dma_address)
 520                         goto free;
 521
 522                 *dma_handle = mapping;
 523         } else /* non translated slot */
 524                 *dma_handle = virt_to_bus(ret);
 525
 526         return ret;
 527
 528 free:
 529         free_pages((unsigned long)ret, get_order(size));
 530         ret = NULL;
 531 error:
 532         return ret;
 533 }
 534
 535 static const struct dma_mapping_ops calgary_dma_ops = {
 536         .alloc_coherent = calgary_alloc_coherent,
 537         .map_single = calgary_map_single,
 538         .unmap_single = calgary_unmap_single,
 539         .map_sg = calgary_map_sg,
 540         .unmap_sg = calgary_unmap_sg,
 541 };
 542
 543 static inline void __iomem * busno_to_bbar(unsigned char num)
 544 {
 545         return bus_info[num].bbar;
 546 }
 547
 548 static inline int busno_to_phbid(unsigned char num)
 549 {
 550         return bus_info[num].phbid;
 551 }
 552
 553 static inline unsigned long split_queue_offset(unsigned char num)
 554 {
 555         size_t idx = busno_to_phbid(num);
 556
 557         return split_queue_offsets[idx];
 558 }
 559
 560 static inline unsigned long tar_offset(unsigned char num)
 561 {
 562         size_t idx = busno_to_phbid(num);
 563
 564         return tar_offsets[idx];
 565 }
 566
 567 static inline unsigned long phb_offset(unsigned char num)
 568 {
 569         size_t idx = busno_to_phbid(num);
 570
 571         return phb_offsets[idx];
 572 }
 573
 574 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 575 {
 576         unsigned long target = ((unsigned long)bar) | offset;
 577         return (void __iomem*)target;
 578 }
 579
 580 static inline int is_calioc2(unsigned short device)
 581 {
 582         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 583 }
 584
 585 static inline int is_calgary(unsigned short device)
 586 {
 587         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 588 }
 589
 590 static inline int is_cal_pci_dev(unsigned short device)
 591 {
 592         return (is_calgary(device) || is_calioc2(device));
 593 }
 594
 595 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 596 {
 597         u64 val;
 598         u32 aer;
 599         int i = 0;
 600         void __iomem *bbar = tbl->bbar;
 601         void __iomem *target;
 602
 603         /* disable arbitration on the bus */
 604         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 605         aer = readl(target);
 606         writel(0, target);
 607
 608         /* read plssr to ensure it got there */
 609         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 610         val = readl(target);
 611
 612         /* poll split queues until all DMA activity is done */
 613         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 614         do {
 615                 val = readq(target);
 616                 i++;
 617         } while ((val & 0xff) != 0xff && i < 100);
 618         if (i == 100)
 619                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 620                        "continuing anyway\n");
 621
 622         /* invalidate TCE cache */
 623         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 624         writeq(tbl->tar_val, target);
 625
 626         /* enable arbitration */
 627         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 628         writel(aer, target);
 629         (void)readl(target); /* flush */
 630 }
 631
 632 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 633 {
 634         void __iomem *bbar = tbl->bbar;
 635         void __iomem *target;
 636         u64 val64;
 637         u32 val;
 638         int i = 0;
 639         int count = 1;
 640         unsigned char bus = tbl->it_busno;
 641
 642 begin:
 643         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 644                "sequence - count %d\n", bus, count);
 645
 646         /* 1. using the Page Migration Control reg set SoftStop */
 647         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 648         val = be32_to_cpu(readl(target));
 649         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 650         val |= PMR_SOFTSTOP;
 651         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 652         writel(cpu_to_be32(val), target);
 653
 654         /* 2. poll split queues until all DMA activity is done */
 655         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 656         target = calgary_reg(bbar, split_queue_offset(bus));
 657         do {
 658                 val64 = readq(target);
 659                 i++;
 660         } while ((val64 & 0xff) != 0xff && i < 100);
 661         if (i == 100)
 662                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 663                        "continuing anyway\n");
 664
 665         /* 3. poll Page Migration DEBUG for SoftStopFault */
 666         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 667         val = be32_to_cpu(readl(target));
 668         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 669
 670         /* 4. if SoftStopFault - goto (1) */
 671         if (val & PMR_SOFTSTOPFAULT) {
 672                 if (++count < 100)
 673                         goto begin;
 674                 else {
 675                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 676                                "aborting TCE cache flush sequence!\n");
 677                         return; /* pray for the best */
 678                 }
 679         }
 680
 681         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 682         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 683         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 684         val = be32_to_cpu(readl(target));
 685         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 686         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 687         val = be32_to_cpu(readl(target));
 688         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 689
 690         /* 6. invalidate TCE cache */
 691         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 692         target = calgary_reg(bbar, tar_offset(bus));
 693         writeq(tbl->tar_val, target);
 694
 695         /* 7. Re-read PMCR */
 696         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 697         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 698         val = be32_to_cpu(readl(target));
 699         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 700
 701         /* 8. Remove HardStop */
 702         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 703         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 704         val = 0;
 705         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 706         writel(cpu_to_be32(val), target);
 707         val = be32_to_cpu(readl(target));
 708         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 709 }
 710
 711 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 712         u64 limit)
 713 {
 714         unsigned int numpages;
 715
 716         limit = limit | 0xfffff;
 717         limit++;
 718
 719         numpages = ((limit - start) >> PAGE_SHIFT);
 720         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 721 }
 722
 723 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 724 {
 725         void __iomem *target;
 726         u64 low, high, sizelow;
 727         u64 start, limit;
 728         struct iommu_table *tbl = pci_iommu(dev->bus);
 729         unsigned char busnum = dev->bus->number;
 730         void __iomem *bbar = tbl->bbar;
 731
 732         /* peripheral MEM_1 region */
 733         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 734         low = be32_to_cpu(readl(target));
 735         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 736         high = be32_to_cpu(readl(target));
 737         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 738         sizelow = be32_to_cpu(readl(target));
 739
 740         start = (high << 32) | low;
 741         limit = sizelow;
 742
 743         calgary_reserve_mem_region(dev, start, limit);
 744 }
 745
 746 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 747 {
 748         void __iomem *target;
 749         u32 val32;
 750         u64 low, high, sizelow, sizehigh;
 751         u64 start, limit;
 752         struct iommu_table *tbl = pci_iommu(dev->bus);
 753         unsigned char busnum = dev->bus->number;
 754         void __iomem *bbar = tbl->bbar;
 755
 756         /* is it enabled? */
 757         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 758         val32 = be32_to_cpu(readl(target));
 759         if (!(val32 & PHB_MEM2_ENABLE))
 760                 return;
 761
 762         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 763         low = be32_to_cpu(readl(target));
 764         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 765         high = be32_to_cpu(readl(target));
 766         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 767         sizelow = be32_to_cpu(readl(target));
 768         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 769         sizehigh = be32_to_cpu(readl(target));
 770
 771         start = (high << 32) | low;
 772         limit = (sizehigh << 32) | sizelow;
 773
 774         calgary_reserve_mem_region(dev, start, limit);
 775 }
 776
 777 /*
 778  * some regions of the IO address space do not get translated, so we
 779  * must not give devices IO addresses in those regions. The regions
 780  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 781  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 782  * later.
 783  */
 784 static void __init calgary_reserve_regions(struct pci_dev *dev)
 785 {
 786         unsigned int npages;
 787         u64 start;
 788         struct iommu_table *tbl = pci_iommu(dev->bus);
 789
 790         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 791         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 792
 793         /* avoid the BIOS/VGA first 640KB-1MB region */
 794         /* for CalIOC2 - avoid the entire first MB */
 795         if (is_calgary(dev->device)) {
 796                 start = (640 * 1024);
 797                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 798         } else { /* calioc2 */
 799                 start = 0;
 800                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 801         }
 802         iommu_range_reserve(tbl, start, npages);
 803
 804         /* reserve the two PCI peripheral memory regions in IO space */
 805         calgary_reserve_peripheral_mem_1(dev);
 806         calgary_reserve_peripheral_mem_2(dev);
 807 }
 808
 809 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 810 {
 811         u64 val64;
 812         u64 table_phys;
 813         void __iomem *target;
 814         int ret;
 815         struct iommu_table *tbl;
 816
 817         /* build TCE tables for each PHB */
 818         ret = build_tce_table(dev, bbar);
 819         if (ret)
 820                 return ret;
 821
 822         tbl = pci_iommu(dev->bus);
 823         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 824         tce_free(tbl, 0, tbl->it_size);
 825
 826         if (is_calgary(dev->device))
 827                 tbl->chip_ops = &calgary_chip_ops;
 828         else if (is_calioc2(dev->device))
 829                 tbl->chip_ops = &calioc2_chip_ops;
 830         else
 831                 BUG();
 832
 833         calgary_reserve_regions(dev);
 834
 835         /* set TARs for each PHB */
 836         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 837         val64 = be64_to_cpu(readq(target));
 838
 839         /* zero out all TAR bits under sw control */
 840         val64 &= ~TAR_SW_BITS;
 841         table_phys = (u64)__pa(tbl->it_base);
 842
 843         val64 |= table_phys;
 844
 845         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 846         val64 |= (u64) specified_table_size;
 847
 848         tbl->tar_val = cpu_to_be64(val64);
 849
 850         writeq(tbl->tar_val, target);
 851         readq(target); /* flush */
 852
 853         return 0;
 854 }
 855
 856 static void __init calgary_free_bus(struct pci_dev *dev)
 857 {
 858         u64 val64;
 859         struct iommu_table *tbl = pci_iommu(dev->bus);
 860         void __iomem *target;
 861         unsigned int bitmapsz;
 862
 863         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 864         val64 = be64_to_cpu(readq(target));
 865         val64 &= ~TAR_SW_BITS;
 866         writeq(cpu_to_be64(val64), target);
 867         readq(target); /* flush */
 868
 869         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 870         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 871         tbl->it_map = NULL;
 872
 873         kfree(tbl);
 874
 875         set_pci_iommu(dev->bus, NULL);
 876
 877         /* Can't free bootmem allocated memory after system is up :-( */
 878         bus_info[dev->bus->number].tce_space = NULL;
 879 }
 880
 881 static void calgary_dump_error_regs(struct iommu_table *tbl)
 882 {
 883         void __iomem *bbar = tbl->bbar;
 884         void __iomem *target;
 885         u32 csr, plssr;
 886
 887         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 888         csr = be32_to_cpu(readl(target));
 889
 890         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 891         plssr = be32_to_cpu(readl(target));
 892
 893         /* If no error, the agent ID in the CSR is not valid */
 894         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 895                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 896 }
 897
 898 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 899 {
 900         void __iomem *bbar = tbl->bbar;
 901         u32 csr, csmr, plssr, mck, rcstat;
 902         void __iomem *target;
 903         unsigned long phboff = phb_offset(tbl->it_busno);
 904         unsigned long erroff;
 905         u32 errregs[7];
 906         int i;
 907
 908         /* dump CSR */
 909         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 910         csr = be32_to_cpu(readl(target));
 911         /* dump PLSSR */
 912         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 913         plssr = be32_to_cpu(readl(target));
 914         /* dump CSMR */
 915         target = calgary_reg(bbar, phboff | 0x290);
 916         csmr = be32_to_cpu(readl(target));
 917         /* dump mck */
 918         target = calgary_reg(bbar, phboff | 0x800);
 919         mck = be32_to_cpu(readl(target));
 920
 921         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 922                tbl->it_busno);
 923
 924         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 925                csr, plssr, csmr, mck);
 926
 927         /* dump rest of error regs */
 928         printk(KERN_EMERG "Calgary: ");
 929         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 930                 /* err regs are at 0x810 - 0x870 */
 931                 erroff = (0x810 + (i * 0x10));
 932                 target = calgary_reg(bbar, phboff | erroff);
 933                 errregs[i] = be32_to_cpu(readl(target));
 934                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 935         }
 936         printk("\n");
 937
 938         /* root complex status */
 939         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 940         rcstat = be32_to_cpu(readl(target));
 941         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 942                PHB_ROOT_COMPLEX_STATUS);
 943 }
 944
 945 static void calgary_watchdog(unsigned long data)
 946 {
 947         struct pci_dev *dev = (struct pci_dev *)data;
 948         struct iommu_table *tbl = pci_iommu(dev->bus);
 949         void __iomem *bbar = tbl->bbar;
 950         u32 val32;
 951         void __iomem *target;
 952
 953         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 954         val32 = be32_to_cpu(readl(target));
 955
 956         /* If no error, the agent ID in the CSR is not valid */
 957         if (val32 & CSR_AGENT_MASK) {
 958                 tbl->chip_ops->dump_error_regs(tbl);
 959
 960                 /* reset error */
 961                 writel(0, target);
 962
 963                 /* Disable bus that caused the error */
 964                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 965                                      PHB_CONFIG_RW_OFFSET);
 966                 val32 = be32_to_cpu(readl(target));
 967                 val32 |= PHB_SLOT_DISABLE;
 968                 writel(cpu_to_be32(val32), target);
 969                 readl(target); /* flush */
 970         } else {
 971                 /* Reset the timer */
 972                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 973         }
 974 }
 975
 976 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 977         unsigned char busnum, unsigned long timeout)
 978 {
 979         u64 val64;
 980         void __iomem *target;
 981         unsigned int phb_shift = ~0; /* silence gcc */
 982         u64 mask;
 983
 984         switch (busno_to_phbid(busnum)) {
 985         case 0: phb_shift = (63 - 19);
 986                 break;
 987         case 1: phb_shift = (63 - 23);
 988                 break;
 989         case 2: phb_shift = (63 - 27);
 990                 break;
 991         case 3: phb_shift = (63 - 35);
 992                 break;
 993         default:
 994                 BUG_ON(busno_to_phbid(busnum));
 995         }
 996
 997         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 998         val64 = be64_to_cpu(readq(target));
 999
1000         /* zero out this PHB's timer bits */
1001         mask = ~(0xFUL << phb_shift);
1002         val64 &= mask;
1003         val64 |= (timeout << phb_shift);
1004         writeq(cpu_to_be64(val64), target);
1005         readq(target); /* flush */
1006 }
1007
1008 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1009 {
1010         unsigned char busnum = dev->bus->number;
1011         void __iomem *bbar = tbl->bbar;
1012         void __iomem *target;
1013         u32 val;
1014
1015         /*
1016          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1017          */
1018         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1019         val = cpu_to_be32(readl(target));
1020         val |= 0x00800000;
1021         writel(cpu_to_be32(val), target);
1022 }
1023
1024 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1025 {
1026         unsigned char busnum = dev->bus->number;
1027
1028         /*
1029          * Give split completion a longer timeout on bus 1 for aic94xx
1030          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1031          */
1032         if (is_calgary(dev->device) && (busnum == 1))
1033                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1034                                                      CCR_2SEC_TIMEOUT);
1035 }
1036
1037 static void __init calgary_enable_translation(struct pci_dev *dev)
1038 {
1039         u32 val32;
1040         unsigned char busnum;
1041         void __iomem *target;
1042         void __iomem *bbar;
1043         struct iommu_table *tbl;
1044
1045         busnum = dev->bus->number;
1046         tbl = pci_iommu(dev->bus);
1047         bbar = tbl->bbar;
1048
1049         /* enable TCE in PHB Config Register */
1050         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1051         val32 = be32_to_cpu(readl(target));
1052         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1053
1054         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1055                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1056                "Calgary" : "CalIOC2", busnum);
1057         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1058                "bus.\n");
1059
1060         writel(cpu_to_be32(val32), target);
1061         readl(target); /* flush */
1062
1063         init_timer(&tbl->watchdog_timer);
1064         tbl->watchdog_timer.function = &calgary_watchdog;
1065         tbl->watchdog_timer.data = (unsigned long)dev;
1066         mod_timer(&tbl->watchdog_timer, jiffies);
1067 }
1068
1069 static void __init calgary_disable_translation(struct pci_dev *dev)
1070 {
1071         u32 val32;
1072         unsigned char busnum;
1073         void __iomem *target;
1074         void __iomem *bbar;
1075         struct iommu_table *tbl;
1076
1077         busnum = dev->bus->number;
1078         tbl = pci_iommu(dev->bus);
1079         bbar = tbl->bbar;
1080
1081         /* disable TCE in PHB Config Register */
1082         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1083         val32 = be32_to_cpu(readl(target));
1084         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1085
1086         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1087         writel(cpu_to_be32(val32), target);
1088         readl(target); /* flush */
1089
1090         del_timer_sync(&tbl->watchdog_timer);
1091 }
1092
1093 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1094 {
1095         pci_dev_get(dev);
1096         set_pci_iommu(dev->bus, NULL);
1097
1098         /* is the device behind a bridge? */
1099         if (dev->bus->parent)
1100                 dev->bus->parent->self = dev;
1101         else
1102                 dev->bus->self = dev;
1103 }
1104
1105 static int __init calgary_init_one(struct pci_dev *dev)
1106 {
1107         void __iomem *bbar;
1108         struct iommu_table *tbl;
1109         int ret;
1110
1111         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1112
1113         bbar = busno_to_bbar(dev->bus->number);
1114         ret = calgary_setup_tar(dev, bbar);
1115         if (ret)
1116                 goto done;
1117
1118         pci_dev_get(dev);
1119
1120         if (dev->bus->parent) {
1121                 if (dev->bus->parent->self)
1122                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1123                                "bus->parent->self!\n", dev);
1124                 dev->bus->parent->self = dev;
1125         } else
1126                 dev->bus->self = dev;
1127
1128         tbl = pci_iommu(dev->bus);
1129         tbl->chip_ops->handle_quirks(tbl, dev);
1130
1131         calgary_enable_translation(dev);
1132
1133         return 0;
1134
1135 done:
1136         return ret;
1137 }
1138
1139 static int __init calgary_locate_bbars(void)
1140 {
1141         int ret;
1142         int rioidx, phb, bus;
1143         void __iomem *bbar;
1144         void __iomem *target;
1145         unsigned long offset;
1146         u8 start_bus, end_bus;
1147         u32 val;
1148
1149         ret = -ENODATA;
1150         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1151                 struct rio_detail *rio = rio_devs[rioidx];
1152
1153                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1154                         continue;
1155
1156                 /* map entire 1MB of Calgary config space */
1157                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1158                 if (!bbar)
1159                         goto error;
1160
1161                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1162                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1163                         target = calgary_reg(bbar, offset);
1164
1165                         val = be32_to_cpu(readl(target));
1166
1167                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1168                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1169
1170                         if (end_bus) {
1171                                 for (bus = start_bus; bus <= end_bus; bus++) {
1172                                         bus_info[bus].bbar = bbar;
1173                                         bus_info[bus].phbid = phb;
1174                                 }
1175                         } else {
1176                                 bus_info[start_bus].bbar = bbar;
1177                                 bus_info[start_bus].phbid = phb;
1178                         }
1179                 }
1180         }
1181
1182         return 0;
1183
1184 error:
1185         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1186         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1187                 if (bus_info[bus].bbar)
1188                         iounmap(bus_info[bus].bbar);
1189
1190         return ret;
1191 }
1192
1193 static int __init calgary_init(void)
1194 {
1195         int ret;
1196         struct pci_dev *dev = NULL;
1197         void *tce_space;
1198
1199         ret = calgary_locate_bbars();
1200         if (ret)
1201                 return ret;
1202
1203         do {
1204                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1205                 if (!dev)
1206                         break;
1207                 if (!is_cal_pci_dev(dev->device))
1208                         continue;
1209                 if (!translate_phb(dev)) {
1210                         calgary_init_one_nontraslated(dev);
1211                         continue;
1212                 }
1213                 tce_space = bus_info[dev->bus->number].tce_space;
1214                 if (!tce_space && !translate_empty_slots)
1215                         continue;
1216
1217                 ret = calgary_init_one(dev);
1218                 if (ret)
1219                         goto error;
1220         } while (1);
1221
1222         return ret;
1223
1224 error:
1225         do {
1226                 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
1227                                              PCI_ANY_ID, dev);
1228                 if (!dev)
1229                         break;
1230                 if (!is_cal_pci_dev(dev->device))
1231                         continue;
1232                 if (!translate_phb(dev)) {
1233                         pci_dev_put(dev);
1234                         continue;
1235                 }
1236                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
1237                         continue;
1238
1239                 calgary_disable_translation(dev);
1240                 calgary_free_bus(dev);
1241                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1242         } while (1);
1243
1244         return ret;
1245 }
1246
1247 static inline int __init determine_tce_table_size(u64 ram)
1248 {
1249         int ret;
1250
1251         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1252                 return specified_table_size;
1253
1254         /*
1255          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1256          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1257          * larger table size has twice as many entries, so shift the
1258          * max ram address by 13 to divide by 8K and then look at the
1259          * order of the result to choose between 0-7.
1260          */
1261         ret = get_order(ram >> 13);
1262         if (ret > TCE_TABLE_SIZE_8M)
1263                 ret = TCE_TABLE_SIZE_8M;
1264
1265         return ret;
1266 }
1267
1268 static int __init build_detail_arrays(void)
1269 {
1270         unsigned long ptr;
1271         int i, scal_detail_size, rio_detail_size;
1272
1273         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1274                 printk(KERN_WARNING
1275                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1276                         "but system has %d nodes.\n",
1277                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1278                 return -ENODEV;
1279         }
1280
1281         switch (rio_table_hdr->version){
1282         case 2:
1283                 scal_detail_size = 11;
1284                 rio_detail_size = 13;
1285                 break;
1286         case 3:
1287                 scal_detail_size = 12;
1288                 rio_detail_size = 15;
1289                 break;
1290         default:
1291                 printk(KERN_WARNING
1292                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1293                        rio_table_hdr->version);
1294                 return -EPROTO;
1295         }
1296
1297         ptr = ((unsigned long)rio_table_hdr) + 3;
1298         for (i = 0; i < rio_table_hdr->num_scal_dev;
1299                     i++, ptr += scal_detail_size)
1300                 scal_devs[i] = (struct scal_detail *)ptr;
1301
1302         for (i = 0; i < rio_table_hdr->num_rio_dev;
1303                     i++, ptr += rio_detail_size)
1304                 rio_devs[i] = (struct rio_detail *)ptr;
1305
1306         return 0;
1307 }
1308
1309 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1310 {
1311         int dev;
1312         u32 val;
1313
1314         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1315                 /*
1316                  * FIXME: properly scan for devices accross the
1317                  * PCI-to-PCI bridge on every CalIOC2 port.
1318                  */
1319                 return 1;
1320         }
1321
1322         for (dev = 1; dev < 8; dev++) {
1323                 val = read_pci_config(bus, dev, 0, 0);
1324                 if (val != 0xffffffff)
1325                         break;
1326         }
1327         return (val != 0xffffffff);
1328 }
1329
1330 void __init detect_calgary(void)
1331 {
1332         int bus;
1333         void *tbl;
1334         int calgary_found = 0;
1335         unsigned long ptr;
1336         unsigned int offset, prev_offset;
1337         int ret;
1338
1339         /*
1340          * if the user specified iommu=off or iommu=soft or we found
1341          * another HW IOMMU already, bail out.
1342          */
1343         if (swiotlb || no_iommu || iommu_detected)
1344                 return;
1345
1346         if (!use_calgary)
1347                 return;
1348
1349         if (!early_pci_allowed())
1350                 return;
1351
1352         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1353
1354         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1355
1356         rio_table_hdr = NULL;
1357         prev_offset = 0;
1358         offset = 0x180;
1359         /*
1360          * The next offset is stored in the 1st word.
1361          * Only parse up until the offset increases:
1362          */
1363         while (offset > prev_offset) {
1364                 /* The block id is stored in the 2nd word */
1365                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1366                         /* set the pointer past the offset & block id */
1367                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1368                         break;
1369                 }
1370                 prev_offset = offset;
1371                 offset = *((unsigned short *)(ptr + offset));
1372         }
1373         if (!rio_table_hdr) {
1374                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1375                        "in EBDA - bailing!\n");
1376                 return;
1377         }
1378
1379         ret = build_detail_arrays();
1380         if (ret) {
1381                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1382                 return;
1383         }
1384
1385         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1386
1387         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1388                 struct calgary_bus_info *info = &bus_info[bus];
1389                 unsigned short pci_device;
1390                 u32 val;
1391
1392                 val = read_pci_config(bus, 0, 0, 0);
1393                 pci_device = (val & 0xFFFF0000) >> 16;
1394
1395                 if (!is_cal_pci_dev(pci_device))
1396                         continue;
1397
1398                 if (info->translation_disabled)
1399                         continue;
1400
1401                 if (calgary_bus_has_devices(bus, pci_device) ||
1402                     translate_empty_slots) {
1403                         tbl = alloc_tce_table();
1404                         if (!tbl)
1405                                 goto cleanup;
1406                         info->tce_space = tbl;
1407                         calgary_found = 1;
1408                 }
1409         }
1410
1411         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1412                calgary_found ? "found" : "not found");
1413
1414         if (calgary_found) {
1415                 iommu_detected = 1;
1416                 calgary_detected = 1;
1417                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1418                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1419                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1420                        debugging ? "enabled" : "disabled");
1421         }
1422         return;
1423
1424 cleanup:
1425         for (--bus; bus >= 0; --bus) {
1426                 struct calgary_bus_info *info = &bus_info[bus];
1427
1428                 if (info->tce_space)
1429                         free_tce_table(info->tce_space);
1430         }
1431 }
1432
1433 int __init calgary_iommu_init(void)
1434 {
1435         int ret;
1436
1437         if (no_iommu || swiotlb)
1438                 return -ENODEV;
1439
1440         if (!calgary_detected)
1441                 return -ENODEV;
1442
1443         /* ok, we're trying to use Calgary - let's roll */
1444         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1445
1446         ret = calgary_init();
1447         if (ret) {
1448                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1449                        "falling back to no_iommu\n", ret);
1450                 if (end_pfn > MAX_DMA32_PFN)
1451                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1452                                         "32bit PCI may malfunction.\n");
1453                 return ret;
1454         }
1455
1456         force_iommu = 1;
1457         bad_dma_address = 0x0;
1458         dma_ops = &calgary_dma_ops;
1459
1460         return 0;
1461 }
1462
1463 static int __init calgary_parse_options(char *p)
1464 {
1465         unsigned int bridge;
1466         size_t len;
1467         char* endp;
1468
1469         while (*p) {
1470                 if (!strncmp(p, "64k", 3))
1471                         specified_table_size = TCE_TABLE_SIZE_64K;
1472                 else if (!strncmp(p, "128k", 4))
1473                         specified_table_size = TCE_TABLE_SIZE_128K;
1474                 else if (!strncmp(p, "256k", 4))
1475                         specified_table_size = TCE_TABLE_SIZE_256K;
1476                 else if (!strncmp(p, "512k", 4))
1477                         specified_table_size = TCE_TABLE_SIZE_512K;
1478                 else if (!strncmp(p, "1M", 2))
1479                         specified_table_size = TCE_TABLE_SIZE_1M;
1480                 else if (!strncmp(p, "2M", 2))
1481                         specified_table_size = TCE_TABLE_SIZE_2M;
1482                 else if (!strncmp(p, "4M", 2))
1483                         specified_table_size = TCE_TABLE_SIZE_4M;
1484                 else if (!strncmp(p, "8M", 2))
1485                         specified_table_size = TCE_TABLE_SIZE_8M;
1486
1487                 len = strlen("translate_empty_slots");
1488                 if (!strncmp(p, "translate_empty_slots", len))
1489                         translate_empty_slots = 1;
1490
1491                 len = strlen("disable");
1492                 if (!strncmp(p, "disable", len)) {
1493                         p += len;
1494                         if (*p == '=')
1495                                 ++p;
1496                         if (*p == '\0')
1497                                 break;
1498                         bridge = simple_strtol(p, &endp, 0);
1499                         if (p == endp)
1500                                 break;
1501
1502                         if (bridge < MAX_PHB_BUS_NUM) {
1503                                 printk(KERN_INFO "Calgary: disabling "
1504                                        "translation for PHB %#x\n", bridge);
1505                                 bus_info[bridge].translation_disabled = 1;
1506                         }
1507                 }
1508
1509                 p = strpbrk(p, ",");
1510                 if (!p)
1511                         break;
1512
1513                 p++; /* skip ',' */
1514         }
1515         return 1;
1516 }
1517 __setup("calgary=", calgary_parse_options);
1518
1519 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1520 {
1521         struct iommu_table *tbl;
1522         unsigned int npages;
1523         int i;
1524
1525         tbl = pci_iommu(dev->bus);
1526
1527         for (i = 0; i < 4; i++) {
1528                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1529
1530                 /* Don't give out TCEs that map MEM resources */
1531                 if (!(r->flags & IORESOURCE_MEM))
1532                         continue;
1533
1534                 /* 0-based? we reserve the whole 1st MB anyway */
1535                 if (!r->start)
1536                         continue;
1537
1538                 /* cover the whole region */
1539                 npages = (r->end - r->start) >> PAGE_SHIFT;
1540                 npages++;
1541
1542                 iommu_range_reserve(tbl, r->start, npages);
1543         }
1544 }
1545
1546 static int __init calgary_fixup_tce_spaces(void)
1547 {
1548         struct pci_dev *dev = NULL;
1549         void *tce_space;
1550
1551         if (no_iommu || swiotlb || !calgary_detected)
1552                 return -ENODEV;
1553
1554         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1555
1556         do {
1557                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1558                 if (!dev)
1559                         break;
1560                 if (!is_cal_pci_dev(dev->device))
1561                         continue;
1562                 if (!translate_phb(dev))
1563                         continue;
1564
1565                 tce_space = bus_info[dev->bus->number].tce_space;
1566                 if (!tce_space)
1567                         continue;
1568
1569                 calgary_fixup_one_tce_space(dev);
1570
1571         } while (1);
1572
1573         return 0;
1574 }
1575
1576 /*
1577  * We need to be call after pcibios_assign_resources (fs_initcall level)
1578  * and before device_initcall.
1579  */
1580 rootfs_initcall(calgary_fixup_tce_spaces);