arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/crash_dump.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <linux/scatterlist.h>
  39 #include <linux/iommu-helper.h>
  40
  41 #include <asm/iommu.h>
  42 #include <asm/calgary.h>
  43 #include <asm/tce.h>
  44 #include <asm/pci-direct.h>
  45 #include <asm/system.h>
  46 #include <asm/dma.h>
  47 #include <asm/rio.h>
  48 #include <asm/bios_ebda.h>
  49
  50 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  51 int use_calgary __read_mostly = 1;
  52 #else
  53 int use_calgary __read_mostly = 0;
  54 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  55
  56 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  57 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  58
  59 /* register offsets inside the host bridge space */
  60 #define CALGARY_CONFIG_REG      0x0108
  61 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  62 #define PHB_PLSSR_OFFSET        0x0120
  63 #define PHB_CONFIG_RW_OFFSET    0x0160
  64 #define PHB_IOBASE_BAR_LOW      0x0170
  65 #define PHB_IOBASE_BAR_HIGH     0x0180
  66 #define PHB_MEM_1_LOW           0x0190
  67 #define PHB_MEM_1_HIGH          0x01A0
  68 #define PHB_IO_ADDR_SIZE        0x01B0
  69 #define PHB_MEM_1_SIZE          0x01C0
  70 #define PHB_MEM_ST_OFFSET       0x01D0
  71 #define PHB_AER_OFFSET          0x0200
  72 #define PHB_CONFIG_0_HIGH       0x0220
  73 #define PHB_CONFIG_0_LOW        0x0230
  74 #define PHB_CONFIG_0_END        0x0240
  75 #define PHB_MEM_2_LOW           0x02B0
  76 #define PHB_MEM_2_HIGH          0x02C0
  77 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  78 #define PHB_MEM_2_SIZE_LOW      0x02E0
  79 #define PHB_DOSHOLE_OFFSET      0x08E0
  80
  81 /* CalIOC2 specific */
  82 #define PHB_SAVIOR_L2           0x0DB0
  83 #define PHB_PAGE_MIG_CTRL       0x0DA8
  84 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  85 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  86
  87 /* PHB_CONFIG_RW */
  88 #define PHB_TCE_ENABLE          0x20000000
  89 #define PHB_SLOT_DISABLE        0x1C000000
  90 #define PHB_DAC_DISABLE         0x01000000
  91 #define PHB_MEM2_ENABLE         0x00400000
  92 #define PHB_MCSR_ENABLE         0x00100000
  93 /* TAR (Table Address Register) */
  94 #define TAR_SW_BITS             0x0000ffffffff800fUL
  95 #define TAR_VALID               0x0000000000000008UL
  96 /* CSR (Channel/DMA Status Register) */
  97 #define CSR_AGENT_MASK          0xffe0ffff
  98 /* CCR (Calgary Configuration Register) */
  99 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
 100 /* PMCR/PMDR (Page Migration Control/Debug Registers */
 101 #define PMR_SOFTSTOP            0x80000000
 102 #define PMR_SOFTSTOPFAULT       0x40000000
 103 #define PMR_HARDSTOP            0x20000000
 104
 105 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 106 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 107 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 108 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 109 #define PHBS_PER_CALGARY        4
 110
 111 /* register offsets in Calgary's internal register space */
 112 static const unsigned long tar_offsets[] = {
 113         0x0580 /* TAR0 */,
 114         0x0588 /* TAR1 */,
 115         0x0590 /* TAR2 */,
 116         0x0598 /* TAR3 */
 117 };
 118
 119 static const unsigned long split_queue_offsets[] = {
 120         0x4870 /* SPLIT QUEUE 0 */,
 121         0x5870 /* SPLIT QUEUE 1 */,
 122         0x6870 /* SPLIT QUEUE 2 */,
 123         0x7870 /* SPLIT QUEUE 3 */
 124 };
 125
 126 static const unsigned long phb_offsets[] = {
 127         0x8000 /* PHB0 */,
 128         0x9000 /* PHB1 */,
 129         0xA000 /* PHB2 */,
 130         0xB000 /* PHB3 */
 131 };
 132
 133 /* PHB debug registers */
 134
 135 static const unsigned long phb_debug_offsets[] = {
 136         0x4000  /* PHB 0 DEBUG */,
 137         0x5000  /* PHB 1 DEBUG */,
 138         0x6000  /* PHB 2 DEBUG */,
 139         0x7000  /* PHB 3 DEBUG */
 140 };
 141
 142 /*
 143  * STUFF register for each debug PHB,
 144  * byte 1 = start bus number, byte 2 = end bus number
 145  */
 146
 147 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 148
 149 #define EMERGENCY_PAGES 32 /* = 128KB */
 150
 151 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 152 static int translate_empty_slots __read_mostly = 0;
 153 static int calgary_detected __read_mostly = 0;
 154
 155 static struct rio_table_hdr     *rio_table_hdr __initdata;
 156 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 157 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 158
 159 struct calgary_bus_info {
 160         void *tce_space;
 161         unsigned char translation_disabled;
 162         signed char phbid;
 163         void __iomem *bbar;
 164 };
 165
 166 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 167 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 168 static void calgary_dump_error_regs(struct iommu_table *tbl);
 169 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 170 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 171 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 172 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 173 static void get_tce_space_from_tar(void);
 174
 175 static struct cal_chipset_ops calgary_chip_ops = {
 176         .handle_quirks = calgary_handle_quirks,
 177         .tce_cache_blast = calgary_tce_cache_blast,
 178         .dump_error_regs = calgary_dump_error_regs
 179 };
 180
 181 static struct cal_chipset_ops calioc2_chip_ops = {
 182         .handle_quirks = calioc2_handle_quirks,
 183         .tce_cache_blast = calioc2_tce_cache_blast,
 184         .dump_error_regs = calioc2_dump_error_regs
 185 };
 186
 187 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 188
 189 /* enable this to stress test the chip's TCE cache */
 190 #ifdef CONFIG_IOMMU_DEBUG
 191 static int debugging = 1;
 192
 193 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 194         int expected, unsigned long start, unsigned long end)
 195 {
 196         unsigned long idx = start;
 197
 198         BUG_ON(start >= end);
 199
 200         while (idx < end) {
 201                 if (!!test_bit(idx, bitmap) != expected)
 202                         return idx;
 203                 ++idx;
 204         }
 205
 206         /* all bits have the expected value */
 207         return ~0UL;
 208 }
 209 #else /* debugging is disabled */
 210 static int debugging;
 211
 212 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 213         int expected, unsigned long start, unsigned long end)
 214 {
 215         return ~0UL;
 216 }
 217
 218 #endif /* CONFIG_IOMMU_DEBUG */
 219
 220 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 221 {
 222         unsigned int npages;
 223
 224         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 225         npages >>= PAGE_SHIFT;
 226
 227         return npages;
 228 }
 229
 230 static inline int translation_enabled(struct iommu_table *tbl)
 231 {
 232         /* only PHBs with translation enabled have an IOMMU table */
 233         return (tbl != NULL);
 234 }
 235
 236 static void iommu_range_reserve(struct iommu_table *tbl,
 237         unsigned long start_addr, unsigned int npages)
 238 {
 239         unsigned long index;
 240         unsigned long end;
 241         unsigned long badbit;
 242         unsigned long flags;
 243
 244         index = start_addr >> PAGE_SHIFT;
 245
 246         /* bail out if we're asked to reserve a region we don't cover */
 247         if (index >= tbl->it_size)
 248                 return;
 249
 250         end = index + npages;
 251         if (end > tbl->it_size) /* don't go off the table */
 252                 end = tbl->it_size;
 253
 254         spin_lock_irqsave(&tbl->it_lock, flags);
 255
 256         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 257         if (badbit != ~0UL) {
 258                 if (printk_ratelimit())
 259                         printk(KERN_ERR "Calgary: entry already allocated at "
 260                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 261                                badbit, tbl, start_addr, npages);
 262         }
 263
 264         set_bit_string(tbl->it_map, index, npages);
 265
 266         spin_unlock_irqrestore(&tbl->it_lock, flags);
 267 }
 268
 269 static unsigned long iommu_range_alloc(struct device *dev,
 270                                        struct iommu_table *tbl,
 271                                        unsigned int npages)
 272 {
 273         unsigned long flags;
 274         unsigned long offset;
 275         unsigned long boundary_size;
 276
 277         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 278                               PAGE_SIZE) >> PAGE_SHIFT;
 279
 280         BUG_ON(npages == 0);
 281
 282         spin_lock_irqsave(&tbl->it_lock, flags);
 283
 284         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 285                                   npages, 0, boundary_size, 0);
 286         if (offset == ~0UL) {
 287                 tbl->chip_ops->tce_cache_blast(tbl);
 288
 289                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 290                                           npages, 0, boundary_size, 0);
 291                 if (offset == ~0UL) {
 292                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 293                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 294                         if (panic_on_overflow)
 295                                 panic("Calgary: fix the allocator.\n");
 296                         else
 297                                 return bad_dma_address;
 298                 }
 299         }
 300
 301         tbl->it_hint = offset + npages;
 302         BUG_ON(tbl->it_hint > tbl->it_size);
 303
 304         spin_unlock_irqrestore(&tbl->it_lock, flags);
 305
 306         return offset;
 307 }
 308
 309 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 310                               void *vaddr, unsigned int npages, int direction)
 311 {
 312         unsigned long entry;
 313         dma_addr_t ret = bad_dma_address;
 314
 315         entry = iommu_range_alloc(dev, tbl, npages);
 316
 317         if (unlikely(entry == bad_dma_address))
 318                 goto error;
 319
 320         /* set the return dma address */
 321         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 322
 323         /* put the TCEs in the HW table */
 324         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 325                   direction);
 326
 327         return ret;
 328
 329 error:
 330         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 331                "iommu %p\n", npages, tbl);
 332         return bad_dma_address;
 333 }
 334
 335 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 336         unsigned int npages)
 337 {
 338         unsigned long entry;
 339         unsigned long badbit;
 340         unsigned long badend;
 341         unsigned long flags;
 342
 343         /* were we called with bad_dma_address? */
 344         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 345         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 346                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
 347                        "address 0x%Lx\n", dma_addr);
 348                 return;
 349         }
 350
 351         entry = dma_addr >> PAGE_SHIFT;
 352
 353         BUG_ON(entry + npages > tbl->it_size);
 354
 355         tce_free(tbl, entry, npages);
 356
 357         spin_lock_irqsave(&tbl->it_lock, flags);
 358
 359         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 360         if (badbit != ~0UL) {
 361                 if (printk_ratelimit())
 362                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 363                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 364                                badbit, tbl, dma_addr, entry, npages);
 365         }
 366
 367         iommu_area_free(tbl->it_map, entry, npages);
 368
 369         spin_unlock_irqrestore(&tbl->it_lock, flags);
 370 }
 371
 372 static inline struct iommu_table *find_iommu_table(struct device *dev)
 373 {
 374         struct pci_dev *pdev;
 375         struct pci_bus *pbus;
 376         struct iommu_table *tbl;
 377
 378         pdev = to_pci_dev(dev);
 379
 380         pbus = pdev->bus;
 381
 382         /* is the device behind a bridge? Look for the root bus */
 383         while (pbus->parent)
 384                 pbus = pbus->parent;
 385
 386         tbl = pci_iommu(pbus);
 387
 388         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 389
 390         return tbl;
 391 }
 392
 393 static void calgary_unmap_sg(struct device *dev,
 394         struct scatterlist *sglist, int nelems, int direction)
 395 {
 396         struct iommu_table *tbl = find_iommu_table(dev);
 397         struct scatterlist *s;
 398         int i;
 399
 400         if (!translation_enabled(tbl))
 401                 return;
 402
 403         for_each_sg(sglist, s, nelems, i) {
 404                 unsigned int npages;
 405                 dma_addr_t dma = s->dma_address;
 406                 unsigned int dmalen = s->dma_length;
 407
 408                 if (dmalen == 0)
 409                         break;
 410
 411                 npages = num_dma_pages(dma, dmalen);
 412                 iommu_free(tbl, dma, npages);
 413         }
 414 }
 415
 416 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 417         int nelems, int direction)
 418 {
 419         struct iommu_table *tbl = find_iommu_table(dev);
 420         struct scatterlist *s;
 421         unsigned long vaddr;
 422         unsigned int npages;
 423         unsigned long entry;
 424         int i;
 425
 426         for_each_sg(sg, s, nelems, i) {
 427                 BUG_ON(!sg_page(s));
 428
 429                 vaddr = (unsigned long) sg_virt(s);
 430                 npages = num_dma_pages(vaddr, s->length);
 431
 432                 entry = iommu_range_alloc(dev, tbl, npages);
 433                 if (entry == bad_dma_address) {
 434                         /* makes sure unmap knows to stop */
 435                         s->dma_length = 0;
 436                         goto error;
 437                 }
 438
 439                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 440
 441                 /* insert into HW table */
 442                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 443                           direction);
 444
 445                 s->dma_length = s->length;
 446         }
 447
 448         return nelems;
 449 error:
 450         calgary_unmap_sg(dev, sg, nelems, direction);
 451         for_each_sg(sg, s, nelems, i) {
 452                 sg->dma_address = bad_dma_address;
 453                 sg->dma_length = 0;
 454         }
 455         return 0;
 456 }
 457
 458 static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr,
 459         size_t size, int direction)
 460 {
 461         void *vaddr = phys_to_virt(paddr);
 462         unsigned long uaddr;
 463         unsigned int npages;
 464         struct iommu_table *tbl = find_iommu_table(dev);
 465
 466         uaddr = (unsigned long)vaddr;
 467         npages = num_dma_pages(uaddr, size);
 468
 469         return iommu_alloc(dev, tbl, vaddr, npages, direction);
 470 }
 471
 472 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 473         size_t size, int direction)
 474 {
 475         struct iommu_table *tbl = find_iommu_table(dev);
 476         unsigned int npages;
 477
 478         npages = num_dma_pages(dma_handle, size);
 479         iommu_free(tbl, dma_handle, npages);
 480 }
 481
 482 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 483         dma_addr_t *dma_handle, gfp_t flag)
 484 {
 485         void *ret = NULL;
 486         dma_addr_t mapping;
 487         unsigned int npages, order;
 488         struct iommu_table *tbl = find_iommu_table(dev);
 489
 490         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 491         npages = size >> PAGE_SHIFT;
 492         order = get_order(size);
 493
 494         /* alloc enough pages (and possibly more) */
 495         ret = (void *)__get_free_pages(flag, order);
 496         if (!ret)
 497                 goto error;
 498         memset(ret, 0, size);
 499
 500         /* set up tces to cover the allocated range */
 501         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 502         if (mapping == bad_dma_address)
 503                 goto free;
 504         *dma_handle = mapping;
 505         return ret;
 506 free:
 507         free_pages((unsigned long)ret, get_order(size));
 508         ret = NULL;
 509 error:
 510         return ret;
 511 }
 512
 513 static void calgary_free_coherent(struct device *dev, size_t size,
 514                                   void *vaddr, dma_addr_t dma_handle)
 515 {
 516         unsigned int npages;
 517         struct iommu_table *tbl = find_iommu_table(dev);
 518
 519         size = PAGE_ALIGN(size);
 520         npages = size >> PAGE_SHIFT;
 521
 522         iommu_free(tbl, dma_handle, npages);
 523         free_pages((unsigned long)vaddr, get_order(size));
 524 }
 525
 526 static struct dma_mapping_ops calgary_dma_ops = {
 527         .alloc_coherent = calgary_alloc_coherent,
 528         .free_coherent = calgary_free_coherent,
 529         .map_single = calgary_map_single,
 530         .unmap_single = calgary_unmap_single,
 531         .map_sg = calgary_map_sg,
 532         .unmap_sg = calgary_unmap_sg,
 533 };
 534
 535 static inline void __iomem * busno_to_bbar(unsigned char num)
 536 {
 537         return bus_info[num].bbar;
 538 }
 539
 540 static inline int busno_to_phbid(unsigned char num)
 541 {
 542         return bus_info[num].phbid;
 543 }
 544
 545 static inline unsigned long split_queue_offset(unsigned char num)
 546 {
 547         size_t idx = busno_to_phbid(num);
 548
 549         return split_queue_offsets[idx];
 550 }
 551
 552 static inline unsigned long tar_offset(unsigned char num)
 553 {
 554         size_t idx = busno_to_phbid(num);
 555
 556         return tar_offsets[idx];
 557 }
 558
 559 static inline unsigned long phb_offset(unsigned char num)
 560 {
 561         size_t idx = busno_to_phbid(num);
 562
 563         return phb_offsets[idx];
 564 }
 565
 566 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 567 {
 568         unsigned long target = ((unsigned long)bar) | offset;
 569         return (void __iomem*)target;
 570 }
 571
 572 static inline int is_calioc2(unsigned short device)
 573 {
 574         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 575 }
 576
 577 static inline int is_calgary(unsigned short device)
 578 {
 579         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 580 }
 581
 582 static inline int is_cal_pci_dev(unsigned short device)
 583 {
 584         return (is_calgary(device) || is_calioc2(device));
 585 }
 586
 587 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 588 {
 589         u64 val;
 590         u32 aer;
 591         int i = 0;
 592         void __iomem *bbar = tbl->bbar;
 593         void __iomem *target;
 594
 595         /* disable arbitration on the bus */
 596         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 597         aer = readl(target);
 598         writel(0, target);
 599
 600         /* read plssr to ensure it got there */
 601         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 602         val = readl(target);
 603
 604         /* poll split queues until all DMA activity is done */
 605         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 606         do {
 607                 val = readq(target);
 608                 i++;
 609         } while ((val & 0xff) != 0xff && i < 100);
 610         if (i == 100)
 611                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 612                        "continuing anyway\n");
 613
 614         /* invalidate TCE cache */
 615         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 616         writeq(tbl->tar_val, target);
 617
 618         /* enable arbitration */
 619         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 620         writel(aer, target);
 621         (void)readl(target); /* flush */
 622 }
 623
 624 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 625 {
 626         void __iomem *bbar = tbl->bbar;
 627         void __iomem *target;
 628         u64 val64;
 629         u32 val;
 630         int i = 0;
 631         int count = 1;
 632         unsigned char bus = tbl->it_busno;
 633
 634 begin:
 635         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 636                "sequence - count %d\n", bus, count);
 637
 638         /* 1. using the Page Migration Control reg set SoftStop */
 639         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 640         val = be32_to_cpu(readl(target));
 641         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 642         val |= PMR_SOFTSTOP;
 643         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 644         writel(cpu_to_be32(val), target);
 645
 646         /* 2. poll split queues until all DMA activity is done */
 647         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 648         target = calgary_reg(bbar, split_queue_offset(bus));
 649         do {
 650                 val64 = readq(target);
 651                 i++;
 652         } while ((val64 & 0xff) != 0xff && i < 100);
 653         if (i == 100)
 654                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 655                        "continuing anyway\n");
 656
 657         /* 3. poll Page Migration DEBUG for SoftStopFault */
 658         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 659         val = be32_to_cpu(readl(target));
 660         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 661
 662         /* 4. if SoftStopFault - goto (1) */
 663         if (val & PMR_SOFTSTOPFAULT) {
 664                 if (++count < 100)
 665                         goto begin;
 666                 else {
 667                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 668                                "aborting TCE cache flush sequence!\n");
 669                         return; /* pray for the best */
 670                 }
 671         }
 672
 673         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 674         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 675         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 676         val = be32_to_cpu(readl(target));
 677         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 678         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 679         val = be32_to_cpu(readl(target));
 680         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 681
 682         /* 6. invalidate TCE cache */
 683         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 684         target = calgary_reg(bbar, tar_offset(bus));
 685         writeq(tbl->tar_val, target);
 686
 687         /* 7. Re-read PMCR */
 688         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 689         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 690         val = be32_to_cpu(readl(target));
 691         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 692
 693         /* 8. Remove HardStop */
 694         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 695         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 696         val = 0;
 697         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 698         writel(cpu_to_be32(val), target);
 699         val = be32_to_cpu(readl(target));
 700         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 701 }
 702
 703 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 704         u64 limit)
 705 {
 706         unsigned int numpages;
 707
 708         limit = limit | 0xfffff;
 709         limit++;
 710
 711         numpages = ((limit - start) >> PAGE_SHIFT);
 712         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 713 }
 714
 715 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 716 {
 717         void __iomem *target;
 718         u64 low, high, sizelow;
 719         u64 start, limit;
 720         struct iommu_table *tbl = pci_iommu(dev->bus);
 721         unsigned char busnum = dev->bus->number;
 722         void __iomem *bbar = tbl->bbar;
 723
 724         /* peripheral MEM_1 region */
 725         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 726         low = be32_to_cpu(readl(target));
 727         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 728         high = be32_to_cpu(readl(target));
 729         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 730         sizelow = be32_to_cpu(readl(target));
 731
 732         start = (high << 32) | low;
 733         limit = sizelow;
 734
 735         calgary_reserve_mem_region(dev, start, limit);
 736 }
 737
 738 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 739 {
 740         void __iomem *target;
 741         u32 val32;
 742         u64 low, high, sizelow, sizehigh;
 743         u64 start, limit;
 744         struct iommu_table *tbl = pci_iommu(dev->bus);
 745         unsigned char busnum = dev->bus->number;
 746         void __iomem *bbar = tbl->bbar;
 747
 748         /* is it enabled? */
 749         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 750         val32 = be32_to_cpu(readl(target));
 751         if (!(val32 & PHB_MEM2_ENABLE))
 752                 return;
 753
 754         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 755         low = be32_to_cpu(readl(target));
 756         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 757         high = be32_to_cpu(readl(target));
 758         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 759         sizelow = be32_to_cpu(readl(target));
 760         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 761         sizehigh = be32_to_cpu(readl(target));
 762
 763         start = (high << 32) | low;
 764         limit = (sizehigh << 32) | sizelow;
 765
 766         calgary_reserve_mem_region(dev, start, limit);
 767 }
 768
 769 /*
 770  * some regions of the IO address space do not get translated, so we
 771  * must not give devices IO addresses in those regions. The regions
 772  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 773  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 774  * later.
 775  */
 776 static void __init calgary_reserve_regions(struct pci_dev *dev)
 777 {
 778         unsigned int npages;
 779         u64 start;
 780         struct iommu_table *tbl = pci_iommu(dev->bus);
 781
 782         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 783         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 784
 785         /* avoid the BIOS/VGA first 640KB-1MB region */
 786         /* for CalIOC2 - avoid the entire first MB */
 787         if (is_calgary(dev->device)) {
 788                 start = (640 * 1024);
 789                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 790         } else { /* calioc2 */
 791                 start = 0;
 792                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 793         }
 794         iommu_range_reserve(tbl, start, npages);
 795
 796         /* reserve the two PCI peripheral memory regions in IO space */
 797         calgary_reserve_peripheral_mem_1(dev);
 798         calgary_reserve_peripheral_mem_2(dev);
 799 }
 800
 801 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 802 {
 803         u64 val64;
 804         u64 table_phys;
 805         void __iomem *target;
 806         int ret;
 807         struct iommu_table *tbl;
 808
 809         /* build TCE tables for each PHB */
 810         ret = build_tce_table(dev, bbar);
 811         if (ret)
 812                 return ret;
 813
 814         tbl = pci_iommu(dev->bus);
 815         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 816
 817         if (is_kdump_kernel())
 818                 calgary_init_bitmap_from_tce_table(tbl);
 819         else
 820                 tce_free(tbl, 0, tbl->it_size);
 821
 822         if (is_calgary(dev->device))
 823                 tbl->chip_ops = &calgary_chip_ops;
 824         else if (is_calioc2(dev->device))
 825                 tbl->chip_ops = &calioc2_chip_ops;
 826         else
 827                 BUG();
 828
 829         calgary_reserve_regions(dev);
 830
 831         /* set TARs for each PHB */
 832         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 833         val64 = be64_to_cpu(readq(target));
 834
 835         /* zero out all TAR bits under sw control */
 836         val64 &= ~TAR_SW_BITS;
 837         table_phys = (u64)__pa(tbl->it_base);
 838
 839         val64 |= table_phys;
 840
 841         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 842         val64 |= (u64) specified_table_size;
 843
 844         tbl->tar_val = cpu_to_be64(val64);
 845
 846         writeq(tbl->tar_val, target);
 847         readq(target); /* flush */
 848
 849         return 0;
 850 }
 851
 852 static void __init calgary_free_bus(struct pci_dev *dev)
 853 {
 854         u64 val64;
 855         struct iommu_table *tbl = pci_iommu(dev->bus);
 856         void __iomem *target;
 857         unsigned int bitmapsz;
 858
 859         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 860         val64 = be64_to_cpu(readq(target));
 861         val64 &= ~TAR_SW_BITS;
 862         writeq(cpu_to_be64(val64), target);
 863         readq(target); /* flush */
 864
 865         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 866         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 867         tbl->it_map = NULL;
 868
 869         kfree(tbl);
 870
 871         set_pci_iommu(dev->bus, NULL);
 872
 873         /* Can't free bootmem allocated memory after system is up :-( */
 874         bus_info[dev->bus->number].tce_space = NULL;
 875 }
 876
 877 static void calgary_dump_error_regs(struct iommu_table *tbl)
 878 {
 879         void __iomem *bbar = tbl->bbar;
 880         void __iomem *target;
 881         u32 csr, plssr;
 882
 883         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 884         csr = be32_to_cpu(readl(target));
 885
 886         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 887         plssr = be32_to_cpu(readl(target));
 888
 889         /* If no error, the agent ID in the CSR is not valid */
 890         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 891                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 892 }
 893
 894 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 895 {
 896         void __iomem *bbar = tbl->bbar;
 897         u32 csr, csmr, plssr, mck, rcstat;
 898         void __iomem *target;
 899         unsigned long phboff = phb_offset(tbl->it_busno);
 900         unsigned long erroff;
 901         u32 errregs[7];
 902         int i;
 903
 904         /* dump CSR */
 905         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 906         csr = be32_to_cpu(readl(target));
 907         /* dump PLSSR */
 908         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 909         plssr = be32_to_cpu(readl(target));
 910         /* dump CSMR */
 911         target = calgary_reg(bbar, phboff | 0x290);
 912         csmr = be32_to_cpu(readl(target));
 913         /* dump mck */
 914         target = calgary_reg(bbar, phboff | 0x800);
 915         mck = be32_to_cpu(readl(target));
 916
 917         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 918                tbl->it_busno);
 919
 920         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 921                csr, plssr, csmr, mck);
 922
 923         /* dump rest of error regs */
 924         printk(KERN_EMERG "Calgary: ");
 925         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 926                 /* err regs are at 0x810 - 0x870 */
 927                 erroff = (0x810 + (i * 0x10));
 928                 target = calgary_reg(bbar, phboff | erroff);
 929                 errregs[i] = be32_to_cpu(readl(target));
 930                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 931         }
 932         printk("\n");
 933
 934         /* root complex status */
 935         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 936         rcstat = be32_to_cpu(readl(target));
 937         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 938                PHB_ROOT_COMPLEX_STATUS);
 939 }
 940
 941 static void calgary_watchdog(unsigned long data)
 942 {
 943         struct pci_dev *dev = (struct pci_dev *)data;
 944         struct iommu_table *tbl = pci_iommu(dev->bus);
 945         void __iomem *bbar = tbl->bbar;
 946         u32 val32;
 947         void __iomem *target;
 948
 949         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 950         val32 = be32_to_cpu(readl(target));
 951
 952         /* If no error, the agent ID in the CSR is not valid */
 953         if (val32 & CSR_AGENT_MASK) {
 954                 tbl->chip_ops->dump_error_regs(tbl);
 955
 956                 /* reset error */
 957                 writel(0, target);
 958
 959                 /* Disable bus that caused the error */
 960                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 961                                      PHB_CONFIG_RW_OFFSET);
 962                 val32 = be32_to_cpu(readl(target));
 963                 val32 |= PHB_SLOT_DISABLE;
 964                 writel(cpu_to_be32(val32), target);
 965                 readl(target); /* flush */
 966         } else {
 967                 /* Reset the timer */
 968                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 969         }
 970 }
 971
 972 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 973         unsigned char busnum, unsigned long timeout)
 974 {
 975         u64 val64;
 976         void __iomem *target;
 977         unsigned int phb_shift = ~0; /* silence gcc */
 978         u64 mask;
 979
 980         switch (busno_to_phbid(busnum)) {
 981         case 0: phb_shift = (63 - 19);
 982                 break;
 983         case 1: phb_shift = (63 - 23);
 984                 break;
 985         case 2: phb_shift = (63 - 27);
 986                 break;
 987         case 3: phb_shift = (63 - 35);
 988                 break;
 989         default:
 990                 BUG_ON(busno_to_phbid(busnum));
 991         }
 992
 993         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 994         val64 = be64_to_cpu(readq(target));
 995
 996         /* zero out this PHB's timer bits */
 997         mask = ~(0xFUL << phb_shift);
 998         val64 &= mask;
 999         val64 |= (timeout << phb_shift);
1000         writeq(cpu_to_be64(val64), target);
1001         readq(target); /* flush */
1002 }
1003
1004 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1005 {
1006         unsigned char busnum = dev->bus->number;
1007         void __iomem *bbar = tbl->bbar;
1008         void __iomem *target;
1009         u32 val;
1010
1011         /*
1012          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1013          */
1014         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1015         val = cpu_to_be32(readl(target));
1016         val |= 0x00800000;
1017         writel(cpu_to_be32(val), target);
1018 }
1019
1020 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1021 {
1022         unsigned char busnum = dev->bus->number;
1023
1024         /*
1025          * Give split completion a longer timeout on bus 1 for aic94xx
1026          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1027          */
1028         if (is_calgary(dev->device) && (busnum == 1))
1029                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1030                                                      CCR_2SEC_TIMEOUT);
1031 }
1032
1033 static void __init calgary_enable_translation(struct pci_dev *dev)
1034 {
1035         u32 val32;
1036         unsigned char busnum;
1037         void __iomem *target;
1038         void __iomem *bbar;
1039         struct iommu_table *tbl;
1040
1041         busnum = dev->bus->number;
1042         tbl = pci_iommu(dev->bus);
1043         bbar = tbl->bbar;
1044
1045         /* enable TCE in PHB Config Register */
1046         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1047         val32 = be32_to_cpu(readl(target));
1048         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1049
1050         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1051                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1052                "Calgary" : "CalIOC2", busnum);
1053         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1054                "bus.\n");
1055
1056         writel(cpu_to_be32(val32), target);
1057         readl(target); /* flush */
1058
1059         init_timer(&tbl->watchdog_timer);
1060         tbl->watchdog_timer.function = &calgary_watchdog;
1061         tbl->watchdog_timer.data = (unsigned long)dev;
1062         mod_timer(&tbl->watchdog_timer, jiffies);
1063 }
1064
1065 static void __init calgary_disable_translation(struct pci_dev *dev)
1066 {
1067         u32 val32;
1068         unsigned char busnum;
1069         void __iomem *target;
1070         void __iomem *bbar;
1071         struct iommu_table *tbl;
1072
1073         busnum = dev->bus->number;
1074         tbl = pci_iommu(dev->bus);
1075         bbar = tbl->bbar;
1076
1077         /* disable TCE in PHB Config Register */
1078         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1079         val32 = be32_to_cpu(readl(target));
1080         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1081
1082         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1083         writel(cpu_to_be32(val32), target);
1084         readl(target); /* flush */
1085
1086         del_timer_sync(&tbl->watchdog_timer);
1087 }
1088
1089 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1090 {
1091         pci_dev_get(dev);
1092         set_pci_iommu(dev->bus, NULL);
1093
1094         /* is the device behind a bridge? */
1095         if (dev->bus->parent)
1096                 dev->bus->parent->self = dev;
1097         else
1098                 dev->bus->self = dev;
1099 }
1100
1101 static int __init calgary_init_one(struct pci_dev *dev)
1102 {
1103         void __iomem *bbar;
1104         struct iommu_table *tbl;
1105         int ret;
1106
1107         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1108
1109         bbar = busno_to_bbar(dev->bus->number);
1110         ret = calgary_setup_tar(dev, bbar);
1111         if (ret)
1112                 goto done;
1113
1114         pci_dev_get(dev);
1115
1116         if (dev->bus->parent) {
1117                 if (dev->bus->parent->self)
1118                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1119                                "bus->parent->self!\n", dev);
1120                 dev->bus->parent->self = dev;
1121         } else
1122                 dev->bus->self = dev;
1123
1124         tbl = pci_iommu(dev->bus);
1125         tbl->chip_ops->handle_quirks(tbl, dev);
1126
1127         calgary_enable_translation(dev);
1128
1129         return 0;
1130
1131 done:
1132         return ret;
1133 }
1134
1135 static int __init calgary_locate_bbars(void)
1136 {
1137         int ret;
1138         int rioidx, phb, bus;
1139         void __iomem *bbar;
1140         void __iomem *target;
1141         unsigned long offset;
1142         u8 start_bus, end_bus;
1143         u32 val;
1144
1145         ret = -ENODATA;
1146         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1147                 struct rio_detail *rio = rio_devs[rioidx];
1148
1149                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1150                         continue;
1151
1152                 /* map entire 1MB of Calgary config space */
1153                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1154                 if (!bbar)
1155                         goto error;
1156
1157                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1158                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1159                         target = calgary_reg(bbar, offset);
1160
1161                         val = be32_to_cpu(readl(target));
1162
1163                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1164                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1165
1166                         if (end_bus) {
1167                                 for (bus = start_bus; bus <= end_bus; bus++) {
1168                                         bus_info[bus].bbar = bbar;
1169                                         bus_info[bus].phbid = phb;
1170                                 }
1171                         } else {
1172                                 bus_info[start_bus].bbar = bbar;
1173                                 bus_info[start_bus].phbid = phb;
1174                         }
1175                 }
1176         }
1177
1178         return 0;
1179
1180 error:
1181         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1182         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1183                 if (bus_info[bus].bbar)
1184                         iounmap(bus_info[bus].bbar);
1185
1186         return ret;
1187 }
1188
1189 static int __init calgary_init(void)
1190 {
1191         int ret;
1192         struct pci_dev *dev = NULL;
1193         struct calgary_bus_info *info;
1194
1195         ret = calgary_locate_bbars();
1196         if (ret)
1197                 return ret;
1198
1199         /* Purely for kdump kernel case */
1200         if (is_kdump_kernel())
1201                 get_tce_space_from_tar();
1202
1203         do {
1204                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1205                 if (!dev)
1206                         break;
1207                 if (!is_cal_pci_dev(dev->device))
1208                         continue;
1209
1210                 info = &bus_info[dev->bus->number];
1211                 if (info->translation_disabled) {
1212                         calgary_init_one_nontraslated(dev);
1213                         continue;
1214                 }
1215
1216                 if (!info->tce_space && !translate_empty_slots)
1217                         continue;
1218
1219                 ret = calgary_init_one(dev);
1220                 if (ret)
1221                         goto error;
1222         } while (1);
1223
1224         dev = NULL;
1225         for_each_pci_dev(dev) {
1226                 struct iommu_table *tbl;
1227
1228                 tbl = find_iommu_table(&dev->dev);
1229
1230                 if (translation_enabled(tbl))
1231                         dev->dev.archdata.dma_ops = &calgary_dma_ops;
1232         }
1233
1234         return ret;
1235
1236 error:
1237         do {
1238                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1239                 if (!dev)
1240                         break;
1241                 if (!is_cal_pci_dev(dev->device))
1242                         continue;
1243
1244                 info = &bus_info[dev->bus->number];
1245                 if (info->translation_disabled) {
1246                         pci_dev_put(dev);
1247                         continue;
1248                 }
1249                 if (!info->tce_space && !translate_empty_slots)
1250                         continue;
1251
1252                 calgary_disable_translation(dev);
1253                 calgary_free_bus(dev);
1254                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1255                 dev->dev.archdata.dma_ops = NULL;
1256         } while (1);
1257
1258         return ret;
1259 }
1260
1261 static inline int __init determine_tce_table_size(u64 ram)
1262 {
1263         int ret;
1264
1265         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1266                 return specified_table_size;
1267
1268         /*
1269          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1270          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1271          * larger table size has twice as many entries, so shift the
1272          * max ram address by 13 to divide by 8K and then look at the
1273          * order of the result to choose between 0-7.
1274          */
1275         ret = get_order(ram >> 13);
1276         if (ret > TCE_TABLE_SIZE_8M)
1277                 ret = TCE_TABLE_SIZE_8M;
1278
1279         return ret;
1280 }
1281
1282 static int __init build_detail_arrays(void)
1283 {
1284         unsigned long ptr;
1285         unsigned numnodes, i;
1286         int scal_detail_size, rio_detail_size;
1287
1288         numnodes = rio_table_hdr->num_scal_dev;
1289         if (numnodes > MAX_NUMNODES){
1290                 printk(KERN_WARNING
1291                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1292                         "but system has %d nodes.\n",
1293                         MAX_NUMNODES, numnodes);
1294                 return -ENODEV;
1295         }
1296
1297         switch (rio_table_hdr->version){
1298         case 2:
1299                 scal_detail_size = 11;
1300                 rio_detail_size = 13;
1301                 break;
1302         case 3:
1303                 scal_detail_size = 12;
1304                 rio_detail_size = 15;
1305                 break;
1306         default:
1307                 printk(KERN_WARNING
1308                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1309                        rio_table_hdr->version);
1310                 return -EPROTO;
1311         }
1312
1313         ptr = ((unsigned long)rio_table_hdr) + 3;
1314         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1315                 scal_devs[i] = (struct scal_detail *)ptr;
1316
1317         for (i = 0; i < rio_table_hdr->num_rio_dev;
1318                     i++, ptr += rio_detail_size)
1319                 rio_devs[i] = (struct rio_detail *)ptr;
1320
1321         return 0;
1322 }
1323
1324 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1325 {
1326         int dev;
1327         u32 val;
1328
1329         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1330                 /*
1331                  * FIXME: properly scan for devices accross the
1332                  * PCI-to-PCI bridge on every CalIOC2 port.
1333                  */
1334                 return 1;
1335         }
1336
1337         for (dev = 1; dev < 8; dev++) {
1338                 val = read_pci_config(bus, dev, 0, 0);
1339                 if (val != 0xffffffff)
1340                         break;
1341         }
1342         return (val != 0xffffffff);
1343 }
1344
1345 /*
1346  * calgary_init_bitmap_from_tce_table():
1347  * Funtion for kdump case. In the second/kdump kernel initialize
1348  * the bitmap based on the tce table entries obtained from first kernel
1349  */
1350 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1351 {
1352         u64 *tp;
1353         unsigned int index;
1354         tp = ((u64 *)tbl->it_base);
1355         for (index = 0 ; index < tbl->it_size; index++) {
1356                 if (*tp != 0x0)
1357                         set_bit(index, tbl->it_map);
1358                 tp++;
1359         }
1360 }
1361
1362 /*
1363  * get_tce_space_from_tar():
1364  * Function for kdump case. Get the tce tables from first kernel
1365  * by reading the contents of the base adress register of calgary iommu
1366  */
1367 static void __init get_tce_space_from_tar(void)
1368 {
1369         int bus;
1370         void __iomem *target;
1371         unsigned long tce_space;
1372
1373         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1374                 struct calgary_bus_info *info = &bus_info[bus];
1375                 unsigned short pci_device;
1376                 u32 val;
1377
1378                 val = read_pci_config(bus, 0, 0, 0);
1379                 pci_device = (val & 0xFFFF0000) >> 16;
1380
1381                 if (!is_cal_pci_dev(pci_device))
1382                         continue;
1383                 if (info->translation_disabled)
1384                         continue;
1385
1386                 if (calgary_bus_has_devices(bus, pci_device) ||
1387                                                 translate_empty_slots) {
1388                         target = calgary_reg(bus_info[bus].bbar,
1389                                                 tar_offset(bus));
1390                         tce_space = be64_to_cpu(readq(target));
1391                         tce_space = tce_space & TAR_SW_BITS;
1392
1393                         tce_space = tce_space & (~specified_table_size);
1394                         info->tce_space = (u64 *)__va(tce_space);
1395                 }
1396         }
1397         return;
1398 }
1399
1400 void __init detect_calgary(void)
1401 {
1402         int bus;
1403         void *tbl;
1404         int calgary_found = 0;
1405         unsigned long ptr;
1406         unsigned int offset, prev_offset;
1407         int ret;
1408
1409         /*
1410          * if the user specified iommu=off or iommu=soft or we found
1411          * another HW IOMMU already, bail out.
1412          */
1413         if (swiotlb || no_iommu || iommu_detected)
1414                 return;
1415
1416         if (!use_calgary)
1417                 return;
1418
1419         if (!early_pci_allowed())
1420                 return;
1421
1422         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1423
1424         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1425
1426         rio_table_hdr = NULL;
1427         prev_offset = 0;
1428         offset = 0x180;
1429         /*
1430          * The next offset is stored in the 1st word.
1431          * Only parse up until the offset increases:
1432          */
1433         while (offset > prev_offset) {
1434                 /* The block id is stored in the 2nd word */
1435                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1436                         /* set the pointer past the offset & block id */
1437                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1438                         break;
1439                 }
1440                 prev_offset = offset;
1441                 offset = *((unsigned short *)(ptr + offset));
1442         }
1443         if (!rio_table_hdr) {
1444                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1445                        "in EBDA - bailing!\n");
1446                 return;
1447         }
1448
1449         ret = build_detail_arrays();
1450         if (ret) {
1451                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1452                 return;
1453         }
1454
1455         specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1456                                         saved_max_pfn : max_pfn) * PAGE_SIZE);
1457
1458         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1459                 struct calgary_bus_info *info = &bus_info[bus];
1460                 unsigned short pci_device;
1461                 u32 val;
1462
1463                 val = read_pci_config(bus, 0, 0, 0);
1464                 pci_device = (val & 0xFFFF0000) >> 16;
1465
1466                 if (!is_cal_pci_dev(pci_device))
1467                         continue;
1468
1469                 if (info->translation_disabled)
1470                         continue;
1471
1472                 if (calgary_bus_has_devices(bus, pci_device) ||
1473                     translate_empty_slots) {
1474                         /*
1475                          * If it is kdump kernel, find and use tce tables
1476                          * from first kernel, else allocate tce tables here
1477                          */
1478                         if (!is_kdump_kernel()) {
1479                                 tbl = alloc_tce_table();
1480                                 if (!tbl)
1481                                         goto cleanup;
1482                                 info->tce_space = tbl;
1483                         }
1484                         calgary_found = 1;
1485                 }
1486         }
1487
1488         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1489                calgary_found ? "found" : "not found");
1490
1491         if (calgary_found) {
1492                 iommu_detected = 1;
1493                 calgary_detected = 1;
1494                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1495                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1496                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1497                        debugging ? "enabled" : "disabled");
1498
1499                 /* swiotlb for devices that aren't behind the Calgary. */
1500                 if (max_pfn > MAX_DMA32_PFN)
1501                         swiotlb = 1;
1502         }
1503         return;
1504
1505 cleanup:
1506         for (--bus; bus >= 0; --bus) {
1507                 struct calgary_bus_info *info = &bus_info[bus];
1508
1509                 if (info->tce_space)
1510                         free_tce_table(info->tce_space);
1511         }
1512 }
1513
1514 int __init calgary_iommu_init(void)
1515 {
1516         int ret;
1517
1518         if (no_iommu || (swiotlb && !calgary_detected))
1519                 return -ENODEV;
1520
1521         if (!calgary_detected)
1522                 return -ENODEV;
1523
1524         /* ok, we're trying to use Calgary - let's roll */
1525         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1526
1527         ret = calgary_init();
1528         if (ret) {
1529                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1530                        "falling back to no_iommu\n", ret);
1531                 return ret;
1532         }
1533
1534         force_iommu = 1;
1535         bad_dma_address = 0x0;
1536         /* dma_ops is set to swiotlb or nommu */
1537         if (!dma_ops)
1538                 dma_ops = &nommu_dma_ops;
1539
1540         return 0;
1541 }
1542
1543 static int __init calgary_parse_options(char *p)
1544 {
1545         unsigned int bridge;
1546         size_t len;
1547         char* endp;
1548
1549         while (*p) {
1550                 if (!strncmp(p, "64k", 3))
1551                         specified_table_size = TCE_TABLE_SIZE_64K;
1552                 else if (!strncmp(p, "128k", 4))
1553                         specified_table_size = TCE_TABLE_SIZE_128K;
1554                 else if (!strncmp(p, "256k", 4))
1555                         specified_table_size = TCE_TABLE_SIZE_256K;
1556                 else if (!strncmp(p, "512k", 4))
1557                         specified_table_size = TCE_TABLE_SIZE_512K;
1558                 else if (!strncmp(p, "1M", 2))
1559                         specified_table_size = TCE_TABLE_SIZE_1M;
1560                 else if (!strncmp(p, "2M", 2))
1561                         specified_table_size = TCE_TABLE_SIZE_2M;
1562                 else if (!strncmp(p, "4M", 2))
1563                         specified_table_size = TCE_TABLE_SIZE_4M;
1564                 else if (!strncmp(p, "8M", 2))
1565                         specified_table_size = TCE_TABLE_SIZE_8M;
1566
1567                 len = strlen("translate_empty_slots");
1568                 if (!strncmp(p, "translate_empty_slots", len))
1569                         translate_empty_slots = 1;
1570
1571                 len = strlen("disable");
1572                 if (!strncmp(p, "disable", len)) {
1573                         p += len;
1574                         if (*p == '=')
1575                                 ++p;
1576                         if (*p == '\0')
1577                                 break;
1578                         bridge = simple_strtol(p, &endp, 0);
1579                         if (p == endp)
1580                                 break;
1581
1582                         if (bridge < MAX_PHB_BUS_NUM) {
1583                                 printk(KERN_INFO "Calgary: disabling "
1584                                        "translation for PHB %#x\n", bridge);
1585                                 bus_info[bridge].translation_disabled = 1;
1586                         }
1587                 }
1588
1589                 p = strpbrk(p, ",");
1590                 if (!p)
1591                         break;
1592
1593                 p++; /* skip ',' */
1594         }
1595         return 1;
1596 }
1597 __setup("calgary=", calgary_parse_options);
1598
1599 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1600 {
1601         struct iommu_table *tbl;
1602         unsigned int npages;
1603         int i;
1604
1605         tbl = pci_iommu(dev->bus);
1606
1607         for (i = 0; i < 4; i++) {
1608                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1609
1610                 /* Don't give out TCEs that map MEM resources */
1611                 if (!(r->flags & IORESOURCE_MEM))
1612                         continue;
1613
1614                 /* 0-based? we reserve the whole 1st MB anyway */
1615                 if (!r->start)
1616                         continue;
1617
1618                 /* cover the whole region */
1619                 npages = (r->end - r->start) >> PAGE_SHIFT;
1620                 npages++;
1621
1622                 iommu_range_reserve(tbl, r->start, npages);
1623         }
1624 }
1625
1626 static int __init calgary_fixup_tce_spaces(void)
1627 {
1628         struct pci_dev *dev = NULL;
1629         struct calgary_bus_info *info;
1630
1631         if (no_iommu || swiotlb || !calgary_detected)
1632                 return -ENODEV;
1633
1634         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1635
1636         do {
1637                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1638                 if (!dev)
1639                         break;
1640                 if (!is_cal_pci_dev(dev->device))
1641                         continue;
1642
1643                 info = &bus_info[dev->bus->number];
1644                 if (info->translation_disabled)
1645                         continue;
1646
1647                 if (!info->tce_space)
1648                         continue;
1649
1650                 calgary_fixup_one_tce_space(dev);
1651
1652         } while (1);
1653
1654         return 0;
1655 }
1656
1657 /*
1658  * We need to be call after pcibios_assign_resources (fs_initcall level)
1659  * and before device_initcall.
1660  */
1661 rootfs_initcall(calgary_fixup_tce_spaces);