2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/kernel_stat.h>
21 #include <linux/mc146818rtc.h>
22 #include <linux/acpi.h>
23 #include <linux/module.h>
27 #include <asm/mpspec.h>
28 #include <asm/pgalloc.h>
29 #include <asm/io_apic.h>
30 #include <asm/proto.h>
32 #include <asm/bios_ebda.h>
34 #include <mach_apic.h>
36 /* Have we found an MP table */
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
45 int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 };
47 static int mp_current_pci_id = 0;
48 /* I/O APIC entries */
49 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
51 /* # of MP IRQ source entries */
52 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
54 /* MP IRQ source entries */
59 /* Processor that is doing the boot up */
60 unsigned int boot_cpu_physical_apicid = -1U;
61 EXPORT_SYMBOL(boot_cpu_physical_apicid);
64 u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata
65 = {[0 ... NR_CPUS - 1] = BAD_APICID };
66 void *x86_bios_cpu_apicid_early_ptr;
68 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
69 EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
72 * Intel MP BIOS table parsing routines:
76 * Checksum an MP configuration block.
79 static int __init mpf_checksum(unsigned char *mp, int len)
89 void __cpuinit generic_processor_info(int apicid, int version)
94 if (num_processors >= NR_CPUS) {
95 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
96 " Processor ignored.\n", NR_CPUS);
100 if (num_processors >= maxcpus) {
101 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
102 " Processor ignored.\n", maxcpus);
107 cpus_complement(tmp_map, cpu_present_map);
108 cpu = first_cpu(tmp_map);
110 physid_set(apicid, phys_cpu_present_map);
111 if (apicid == boot_cpu_physical_apicid) {
113 * x86_bios_cpu_apicid is required to have processors listed
114 * in same order as logical cpu numbers. Hence the first
115 * entry is BSP, and so on.
119 /* are we being called early in kernel startup? */
120 if (x86_cpu_to_apicid_early_ptr) {
121 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
122 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
124 cpu_to_apicid[cpu] = apicid;
125 bios_cpu_apicid[cpu] = apicid;
127 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
128 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
131 cpu_set(cpu, cpu_possible_map);
132 cpu_set(cpu, cpu_present_map);
135 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
137 char *bootup_cpu = "";
139 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
143 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
144 bootup_cpu = " (Bootup-CPU)";
145 boot_cpu_physical_apicid = m->mpc_apicid;
148 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
149 generic_processor_info(m->mpc_apicid, 0);
152 static void __init MP_bus_info(struct mpc_config_bus *m)
156 memcpy(str, m->mpc_bustype, 6);
158 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
160 if (strncmp(str, "ISA", 3) == 0) {
161 set_bit(m->mpc_busid, mp_bus_not_pci);
162 } else if (strncmp(str, "PCI", 3) == 0) {
163 clear_bit(m->mpc_busid, mp_bus_not_pci);
164 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
167 printk(KERN_ERR "Unknown bustype %s\n", str);
171 static int bad_ioapic(unsigned long address)
173 if (nr_ioapics >= MAX_IO_APICS) {
174 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
175 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
176 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
179 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
180 " found in table, skipping!\n");
186 static void __init MP_ioapic_info(struct mpc_config_ioapic *m)
188 if (!(m->mpc_flags & MPC_APIC_USABLE))
191 printk(KERN_INFO "I/O APIC #%d at 0x%X.\n", m->mpc_apicid,
194 if (bad_ioapic(m->mpc_apicaddr))
197 mp_ioapics[nr_ioapics] = *m;
201 static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
203 mp_irqs[mp_irq_entries] = *m;
204 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
205 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
206 m->mpc_irqtype, m->mpc_irqflag & 3,
207 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
208 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
209 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
210 panic("Max # of irq sources exceeded!!\n");
213 static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m)
215 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
216 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
217 m->mpc_irqtype, m->mpc_irqflag & 3,
218 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid,
219 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
225 static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
228 int count = sizeof(*mpc);
229 unsigned char *mpt = ((unsigned char *)mpc) + count;
231 if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) {
232 printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n",
233 mpc->mpc_signature[0],
234 mpc->mpc_signature[1],
235 mpc->mpc_signature[2], mpc->mpc_signature[3]);
238 if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) {
239 printk(KERN_ERR "MPTABLE: checksum error!\n");
242 if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) {
243 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
247 if (!mpc->mpc_lapic) {
248 printk(KERN_ERR "MPTABLE: null local APIC address!\n");
251 memcpy(str, mpc->mpc_oem, 8);
253 printk(KERN_INFO "MPTABLE: OEM ID: %s ", str);
255 memcpy(str, mpc->mpc_productid, 12);
257 printk(KERN_INFO "MPTABLE: Product ID: %s ", str);
259 printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic);
261 /* save the local APIC address, it might be non-default */
263 mp_lapic_addr = mpc->mpc_lapic;
269 * Now process the configuration blocks.
271 while (count < mpc->mpc_length) {
275 struct mpc_config_processor *m =
276 (struct mpc_config_processor *)mpt;
278 MP_processor_info(m);
285 struct mpc_config_bus *m =
286 (struct mpc_config_bus *)mpt;
294 struct mpc_config_ioapic *m =
295 (struct mpc_config_ioapic *)mpt;
303 struct mpc_config_intsrc *m =
304 (struct mpc_config_intsrc *)mpt;
313 struct mpc_config_lintsrc *m =
314 (struct mpc_config_lintsrc *)mpt;
322 setup_apic_routing();
324 printk(KERN_ERR "MPTABLE: no processors registered!\n");
325 return num_processors;
328 static int __init ELCR_trigger(unsigned int irq)
332 port = 0x4d0 + (irq >> 3);
333 return (inb(port) >> (irq & 7)) & 1;
336 static void __init construct_default_ioirq_mptable(int mpc_default_type)
338 struct mpc_config_intsrc intsrc;
340 int ELCR_fallback = 0;
342 intsrc.mpc_type = MP_INTSRC;
343 intsrc.mpc_irqflag = 0; /* conforming */
344 intsrc.mpc_srcbus = 0;
345 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
347 intsrc.mpc_irqtype = mp_INT;
350 * If true, we have an ISA/PCI system with no IRQ entries
351 * in the MP table. To prevent the PCI interrupts from being set up
352 * incorrectly, we try to use the ELCR. The sanity check to see if
353 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
354 * never be level sensitive, so we simply see if the ELCR agrees.
355 * If it does, we assume it's valid.
357 if (mpc_default_type == 5) {
358 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... "
359 "falling back to ELCR\n");
361 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) ||
363 printk(KERN_ERR "ELCR contains invalid data... "
367 "Using ELCR to identify PCI interrupts\n");
372 for (i = 0; i < 16; i++) {
373 switch (mpc_default_type) {
375 if (i == 0 || i == 13)
376 continue; /* IRQ0 & IRQ13 not connected */
380 continue; /* IRQ2 is never connected */
385 * If the ELCR indicates a level-sensitive interrupt, we
386 * copy that information over to the MP table in the
387 * irqflag field (level sensitive, active high polarity).
390 intsrc.mpc_irqflag = 13;
392 intsrc.mpc_irqflag = 0;
395 intsrc.mpc_srcbusirq = i;
396 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
397 MP_intsrc_info(&intsrc);
400 intsrc.mpc_irqtype = mp_ExtINT;
401 intsrc.mpc_srcbusirq = 0;
402 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
403 MP_intsrc_info(&intsrc);
406 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
408 struct mpc_config_processor processor;
409 struct mpc_config_bus bus;
410 struct mpc_config_ioapic ioapic;
411 struct mpc_config_lintsrc lintsrc;
412 int linttypes[2] = { mp_ExtINT, mp_NMI };
416 * local APIC has default address
418 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
421 * 2 CPUs, numbered 0 & 1.
423 processor.mpc_type = MP_PROCESSOR;
424 processor.mpc_apicver = 0;
425 processor.mpc_cpuflag = CPU_ENABLED;
426 processor.mpc_cpufeature = 0;
427 processor.mpc_featureflag = 0;
428 processor.mpc_reserved[0] = 0;
429 processor.mpc_reserved[1] = 0;
430 for (i = 0; i < 2; i++) {
431 processor.mpc_apicid = i;
432 MP_processor_info(&processor);
435 bus.mpc_type = MP_BUS;
437 switch (mpc_default_type) {
439 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
444 memcpy(bus.mpc_bustype, "ISA ", 6);
448 if (mpc_default_type > 4) {
450 memcpy(bus.mpc_bustype, "PCI ", 6);
454 ioapic.mpc_type = MP_IOAPIC;
455 ioapic.mpc_apicid = 2;
456 ioapic.mpc_apicver = 0;
457 ioapic.mpc_flags = MPC_APIC_USABLE;
458 ioapic.mpc_apicaddr = 0xFEC00000;
459 MP_ioapic_info(&ioapic);
462 * We set up most of the low 16 IO-APIC pins according to MPS rules.
464 construct_default_ioirq_mptable(mpc_default_type);
466 lintsrc.mpc_type = MP_LINTSRC;
467 lintsrc.mpc_irqflag = 0; /* conforming */
468 lintsrc.mpc_srcbusid = 0;
469 lintsrc.mpc_srcbusirq = 0;
470 lintsrc.mpc_destapic = MP_APIC_ALL;
471 for (i = 0; i < 2; i++) {
472 lintsrc.mpc_irqtype = linttypes[i];
473 lintsrc.mpc_destapiclint = i;
474 MP_lintsrc_info(&lintsrc);
478 static struct intel_mp_floating *mpf_found;
481 * Scan the memory blocks for an SMP configuration block.
483 static void __init __get_smp_config(unsigned early)
485 struct intel_mp_floating *mpf = mpf_found;
487 if (acpi_lapic && early)
490 * ACPI supports both logical (e.g. Hyper-Threading) and physical
491 * processors, where MPS only supports physical.
493 if (acpi_lapic && acpi_ioapic) {
494 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration "
497 } else if (acpi_lapic)
498 printk(KERN_INFO "Using ACPI for processor (LAPIC) "
499 "configuration information\n");
501 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n",
502 mpf->mpf_specification);
505 * Now see if we need to read further.
507 if (mpf->mpf_feature1 != 0) {
510 * local APIC has default address
512 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
516 printk(KERN_INFO "Default MP configuration #%d\n",
518 construct_default_ISA_mptable(mpf->mpf_feature1);
520 } else if (mpf->mpf_physptr) {
523 * Read the physical hardware table. Anything here will
524 * override the defaults.
526 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) {
527 smp_found_config = 0;
529 "BIOS bug, MP table errors detected!...\n");
530 printk(KERN_ERR "... disabling SMP support. "
531 "(tell your hw vendor)\n");
538 * If there are no explicit MP IRQ entries, then we are
539 * broken. We set up most of the low 16 IO-APIC pins to
540 * ISA defaults and hope it will work.
542 if (!mp_irq_entries) {
543 struct mpc_config_bus bus;
545 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, "
546 "using default mptable. "
547 "(tell your hw vendor)\n");
549 bus.mpc_type = MP_BUS;
551 memcpy(bus.mpc_bustype, "ISA ", 6);
554 construct_default_ioirq_mptable(0);
561 printk(KERN_INFO "Processors: %d\n", num_processors);
563 * Only use the first configuration found.
567 void __init early_get_smp_config(void)
572 void __init get_smp_config(void)
577 static int __init smp_scan_config(unsigned long base, unsigned long length,
580 extern void __bad_mpf_size(void);
581 unsigned int *bp = phys_to_virt(base);
582 struct intel_mp_floating *mpf;
584 Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length);
585 if (sizeof(*mpf) != 16)
589 mpf = (struct intel_mp_floating *)bp;
590 if ((*bp == SMP_MAGIC_IDENT) &&
591 (mpf->mpf_length == 1) &&
592 !mpf_checksum((unsigned char *)bp, 16) &&
593 ((mpf->mpf_specification == 1)
594 || (mpf->mpf_specification == 4))) {
596 smp_found_config = 1;
602 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
603 if (mpf->mpf_physptr)
604 reserve_bootmem_generic(mpf->mpf_physptr,
614 static void __init __find_smp_config(unsigned reserve)
616 unsigned int address;
619 * FIXME: Linux assumes you have 640K of base ram..
620 * this continues the error...
622 * 1) Scan the bottom 1K for a signature
623 * 2) Scan the top 1K of base RAM
624 * 3) Scan the 64K of bios
626 if (smp_scan_config(0x0, 0x400, reserve) ||
627 smp_scan_config(639 * 0x400, 0x400, reserve) ||
628 smp_scan_config(0xF0000, 0x10000, reserve))
631 * If it is an SMP machine we should know now.
633 * there is a real-mode segmented pointer pointing to the
634 * 4K EBDA area at 0x40E, calculate and scan it here.
636 * NOTE! There are Linux loaders that will corrupt the EBDA
637 * area, and as such this kind of SMP config may be less
638 * trustworthy, simply because the SMP table may have been
639 * stomped on during early boot. These loaders are buggy and
642 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
645 address = get_bios_ebda();
647 smp_scan_config(address, 0x400, reserve);
650 void __init early_find_smp_config(void)
652 __find_smp_config(0);
655 void __init find_smp_config(void)
657 __find_smp_config(1);
660 /* --------------------------------------------------------------------------
661 ACPI-based MP Configuration
662 -------------------------------------------------------------------------- */
666 void __init mp_register_lapic_address(u64 address)
668 mp_lapic_addr = (unsigned long)address;
669 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
670 if (boot_cpu_physical_apicid == -1U)
671 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
674 void __cpuinit mp_register_lapic(u8 id, u8 enabled)
681 generic_processor_info(id, 0);
685 #define MP_MAX_IOAPIC_PIN 127
687 static struct mp_ioapic_routing {
691 u32 pin_programmed[4];
692 } mp_ioapic_routing[MAX_IO_APICS];
694 static int mp_find_ioapic(int gsi)
698 /* Find the IOAPIC that manages this GSI. */
699 for (i = 0; i < nr_ioapics; i++) {
700 if ((gsi >= mp_ioapic_routing[i].gsi_base)
701 && (gsi <= mp_ioapic_routing[i].gsi_end))
705 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
709 static u8 uniq_ioapic_id(u8 id)
712 DECLARE_BITMAP(used, 256);
713 bitmap_zero(used, 256);
714 for (i = 0; i < nr_ioapics; i++) {
715 struct mpc_config_ioapic *ia = &mp_ioapics[i];
716 __set_bit(ia->mpc_apicid, used);
718 if (!test_bit(id, used))
720 return find_first_zero_bit(used, 256);
723 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
727 if (bad_ioapic(address))
732 mp_ioapics[idx].mpc_type = MP_IOAPIC;
733 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
734 mp_ioapics[idx].mpc_apicaddr = address;
736 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
737 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
738 mp_ioapics[idx].mpc_apicver = 0;
741 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
742 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
744 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
745 mp_ioapic_routing[idx].gsi_base = gsi_base;
746 mp_ioapic_routing[idx].gsi_end = gsi_base +
747 io_apic_get_redir_entries(idx);
749 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
750 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
751 mp_ioapics[idx].mpc_apicaddr,
752 mp_ioapic_routing[idx].gsi_base,
753 mp_ioapic_routing[idx].gsi_end);
758 void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
760 struct mpc_config_intsrc intsrc;
765 * Convert 'gsi' to 'ioapic.pin'.
767 ioapic = mp_find_ioapic(gsi);
770 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
773 * TBD: This check is for faulty timer entries, where the override
774 * erroneously sets the trigger to level, resulting in a HUGE
775 * increase of timer interrupts!
777 if ((bus_irq == 0) && (trigger == 3))
780 intsrc.mpc_type = MP_INTSRC;
781 intsrc.mpc_irqtype = mp_INT;
782 intsrc.mpc_irqflag = (trigger << 2) | polarity;
783 intsrc.mpc_srcbus = MP_ISA_BUS;
784 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
785 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
786 intsrc.mpc_dstirq = pin; /* INTIN# */
788 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
789 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
790 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
791 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
793 mp_irqs[mp_irq_entries] = intsrc;
794 if (++mp_irq_entries == MAX_IRQ_SOURCES)
795 panic("Max # of irq sources exceeded!\n");
798 void __init mp_config_acpi_legacy_irqs(void)
800 struct mpc_config_intsrc intsrc;
805 * Fabricate the legacy ISA bus (bus #31).
807 set_bit(MP_ISA_BUS, mp_bus_not_pci);
810 * Locate the IOAPIC that manages the ISA IRQs (0-15).
812 ioapic = mp_find_ioapic(0);
816 intsrc.mpc_type = MP_INTSRC;
817 intsrc.mpc_irqflag = 0; /* Conforming */
818 intsrc.mpc_srcbus = MP_ISA_BUS;
819 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
822 * Use the default configuration for the IRQs 0-15. Unless
823 * overridden by (MADT) interrupt source override entries.
825 for (i = 0; i < 16; i++) {
828 for (idx = 0; idx < mp_irq_entries; idx++) {
829 struct mpc_config_intsrc *irq = mp_irqs + idx;
831 /* Do we already have a mapping for this ISA IRQ? */
832 if (irq->mpc_srcbus == MP_ISA_BUS
833 && irq->mpc_srcbusirq == i)
836 /* Do we already have a mapping for this IOAPIC pin */
837 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
838 (irq->mpc_dstirq == i))
842 if (idx != mp_irq_entries) {
843 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
844 continue; /* IRQ already used */
847 intsrc.mpc_irqtype = mp_INT;
848 intsrc.mpc_srcbusirq = i; /* Identity mapped */
849 intsrc.mpc_dstirq = i;
851 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
852 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
853 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
854 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
857 mp_irqs[mp_irq_entries] = intsrc;
858 if (++mp_irq_entries == MAX_IRQ_SOURCES)
859 panic("Max # of irq sources exceeded!\n");
863 int mp_register_gsi(u32 gsi, int triggering, int polarity)
869 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
872 /* Don't set up the ACPI SCI because it's already set up */
873 if (acpi_gbl_FADT.sci_interrupt == gsi)
876 ioapic = mp_find_ioapic(gsi);
878 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
882 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
885 * Avoid pin reprogramming. PRTs typically include entries
886 * with redundant pin->gsi mappings (but unique PCI devices);
887 * we only program the IOAPIC on the first.
889 bit = ioapic_pin % 32;
890 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
892 printk(KERN_ERR "Invalid reference to IOAPIC pin "
893 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
897 if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
898 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
899 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
903 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit);
905 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
906 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
907 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
910 #endif /* CONFIG_ACPI */