2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
36 /* Have we found an MP table */
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 int apic_version [MAX_APICS];
45 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
46 int mp_bus_id_to_type [MAX_MP_BUSSES];
48 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
49 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
50 static int mp_current_pci_id;
52 /* I/O APIC entries */
53 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
55 /* # of MP IRQ source entries */
56 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
58 /* MP IRQ source entries */
64 unsigned long mp_lapic_addr;
66 unsigned int def_to_bigsmp = 0;
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid = -1U;
70 /* Internal processor count */
71 unsigned int num_processors;
73 unsigned disabled_cpus __cpuinitdata;
75 /* Bitmask of physically existing CPUs */
76 physid_mask_t phys_cpu_present_map;
79 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
83 * Intel MP BIOS table parsing routines:
88 * Checksum an MP configuration block.
91 static int __init mpf_checksum(unsigned char *mp, int len)
102 * Have to match translation table entries to main table entries by counter
103 * hence the mpc_record variable .... can't see a less disgusting way of
107 static int mpc_record;
108 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
110 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
112 int ver, apicid, cpu;
114 physid_mask_t phys_cpu;
116 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
121 #ifdef CONFIG_X86_NUMAQ
122 apicid = mpc_apic_id(m, translation_table[mpc_record]);
124 Dprintk("Processor #%d %u:%u APIC version %d\n",
126 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
127 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
129 apicid = m->mpc_apicid;
132 if (m->mpc_featureflag&(1<<0))
133 Dprintk(" Floating point unit present.\n");
134 if (m->mpc_featureflag&(1<<7))
135 Dprintk(" Machine Exception supported.\n");
136 if (m->mpc_featureflag&(1<<8))
137 Dprintk(" 64 bit compare & exchange supported.\n");
138 if (m->mpc_featureflag&(1<<9))
139 Dprintk(" Internal APIC present.\n");
140 if (m->mpc_featureflag&(1<<11))
141 Dprintk(" SEP present.\n");
142 if (m->mpc_featureflag&(1<<12))
143 Dprintk(" MTRR present.\n");
144 if (m->mpc_featureflag&(1<<13))
145 Dprintk(" PGE present.\n");
146 if (m->mpc_featureflag&(1<<14))
147 Dprintk(" MCA present.\n");
148 if (m->mpc_featureflag&(1<<15))
149 Dprintk(" CMOV present.\n");
150 if (m->mpc_featureflag&(1<<16))
151 Dprintk(" PAT present.\n");
152 if (m->mpc_featureflag&(1<<17))
153 Dprintk(" PSE present.\n");
154 if (m->mpc_featureflag&(1<<18))
155 Dprintk(" PSN present.\n");
156 if (m->mpc_featureflag&(1<<19))
157 Dprintk(" Cache Line Flush Instruction present.\n");
159 if (m->mpc_featureflag&(1<<21))
160 Dprintk(" Debug Trace and EMON Store present.\n");
161 if (m->mpc_featureflag&(1<<22))
162 Dprintk(" ACPI Thermal Throttle Registers present.\n");
163 if (m->mpc_featureflag&(1<<23))
164 Dprintk(" MMX present.\n");
165 if (m->mpc_featureflag&(1<<24))
166 Dprintk(" FXSR present.\n");
167 if (m->mpc_featureflag&(1<<25))
168 Dprintk(" XMM present.\n");
169 if (m->mpc_featureflag&(1<<26))
170 Dprintk(" Willamette New Instructions present.\n");
171 if (m->mpc_featureflag&(1<<27))
172 Dprintk(" Self Snoop present.\n");
173 if (m->mpc_featureflag&(1<<28))
174 Dprintk(" HT present.\n");
175 if (m->mpc_featureflag&(1<<29))
176 Dprintk(" Thermal Monitor present.\n");
177 /* 30, 31 Reserved */
180 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
181 Dprintk(" Bootup CPU\n");
182 boot_cpu_physical_apicid = m->mpc_apicid;
185 ver = m->mpc_apicver;
191 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
192 "fixing up to 0x10. (tell your hw vendor)\n",
196 apic_version[m->mpc_apicid] = ver;
198 phys_cpu = apicid_to_cpu_present(apicid);
199 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
201 if (num_processors >= NR_CPUS) {
202 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
203 " Processor ignored.\n", NR_CPUS);
207 if (num_processors >= maxcpus) {
208 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
209 " Processor ignored.\n", maxcpus);
213 cpu_set(num_processors, cpu_possible_map);
215 cpus_complement(tmp_map, cpu_present_map);
216 cpu = first_cpu(tmp_map);
218 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
220 * x86_bios_cpu_apicid is required to have processors listed
221 * in same order as logical cpu numbers. Hence the first
222 * entry is BSP, and so on.
227 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
228 * but we need to work other dependencies like SMP_SUSPEND etc
229 * before this can be done without some confusion.
230 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
231 * - Ashok Raj <ashok.raj@intel.com>
233 if (num_processors > 8) {
234 switch (boot_cpu_data.x86_vendor) {
235 case X86_VENDOR_INTEL:
236 if (!APIC_XAPIC(ver)) {
240 /* If P4 and above fall through */
246 /* are we being called early in kernel startup? */
247 if (x86_cpu_to_apicid_early_ptr) {
248 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
249 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
251 cpu_to_apicid[cpu] = m->mpc_apicid;
252 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
254 per_cpu(x86_cpu_to_apicid, cpu) = m->mpc_apicid;
255 per_cpu(x86_bios_cpu_apicid, cpu) = m->mpc_apicid;
258 cpu_set(cpu, cpu_present_map);
261 static void __init MP_bus_info (struct mpc_config_bus *m)
265 memcpy(str, m->mpc_bustype, 6);
268 #ifdef CONFIG_X86_NUMAQ
269 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
271 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
274 #if MAX_MP_BUSSES < 256
275 if (m->mpc_busid >= MAX_MP_BUSSES) {
276 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
277 " is too large, max. supported is %d\n",
278 m->mpc_busid, str, MAX_MP_BUSSES - 1);
283 set_bit(m->mpc_busid, mp_bus_not_pci);
284 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
285 #ifdef CONFIG_X86_NUMAQ
286 mpc_oem_pci_bus(m, translation_table[mpc_record]);
288 clear_bit(m->mpc_busid, mp_bus_not_pci);
289 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
291 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
292 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
293 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
294 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
295 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
296 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
297 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
298 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
300 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
305 static int bad_ioapic(unsigned long address)
307 if (nr_ioapics >= MAX_IO_APICS) {
308 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
309 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
310 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
313 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
314 " found in table, skipping!\n");
320 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
322 if (!(m->mpc_flags & MPC_APIC_USABLE))
325 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
326 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
328 if (bad_ioapic(m->mpc_apicaddr))
331 mp_ioapics[nr_ioapics] = *m;
335 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
337 mp_irqs [mp_irq_entries] = *m;
338 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
339 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
340 m->mpc_irqtype, m->mpc_irqflag & 3,
341 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
342 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
343 if (++mp_irq_entries == MAX_IRQ_SOURCES)
344 panic("Max # of irq sources exceeded!!\n");
347 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
349 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
350 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
351 m->mpc_irqtype, m->mpc_irqflag & 3,
352 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
353 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
356 #ifdef CONFIG_X86_NUMAQ
357 static void __init MP_translation_info (struct mpc_config_translation *m)
359 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
361 if (mpc_record >= MAX_MPC_ENTRY)
362 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
364 translation_table[mpc_record] = m; /* stash this for later */
365 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
366 node_set_online(m->trans_quad);
370 * Read/parse the MPC oem tables
373 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
374 unsigned short oemsize)
376 int count = sizeof (*oemtable); /* the header size */
377 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
380 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
381 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
383 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
384 oemtable->oem_signature[0],
385 oemtable->oem_signature[1],
386 oemtable->oem_signature[2],
387 oemtable->oem_signature[3]);
390 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
392 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
395 while (count < oemtable->oem_length) {
399 struct mpc_config_translation *m=
400 (struct mpc_config_translation *)oemptr;
401 MP_translation_info(m);
402 oemptr += sizeof(*m);
409 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
416 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
419 if (strncmp(oem, "IBM NUMA", 8))
420 printk("Warning! May not be a NUMA-Q system!\n");
422 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
425 #endif /* CONFIG_X86_NUMAQ */
431 static int __init smp_read_mpc(struct mp_config_table *mpc)
435 int count=sizeof(*mpc);
436 unsigned char *mpt=((unsigned char *)mpc)+count;
438 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
439 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
440 *(u32 *)mpc->mpc_signature);
443 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
444 printk(KERN_ERR "SMP mptable: checksum error!\n");
447 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
448 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
452 if (!mpc->mpc_lapic) {
453 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
456 memcpy(oem,mpc->mpc_oem,8);
458 printk(KERN_INFO "OEM ID: %s ",oem);
460 memcpy(str,mpc->mpc_productid,12);
462 printk("Product ID: %s ",str);
464 mps_oem_check(mpc, oem, str);
466 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
469 * Save the local APIC address (it might be non-default) -- but only
470 * if we're not using ACPI.
473 mp_lapic_addr = mpc->mpc_lapic;
476 * Now process the configuration blocks.
479 while (count < mpc->mpc_length) {
483 struct mpc_config_processor *m=
484 (struct mpc_config_processor *)mpt;
485 /* ACPI may have already provided this data */
487 MP_processor_info(m);
494 struct mpc_config_bus *m=
495 (struct mpc_config_bus *)mpt;
503 struct mpc_config_ioapic *m=
504 (struct mpc_config_ioapic *)mpt;
512 struct mpc_config_intsrc *m=
513 (struct mpc_config_intsrc *)mpt;
522 struct mpc_config_lintsrc *m=
523 (struct mpc_config_lintsrc *)mpt;
531 count = mpc->mpc_length;
537 setup_apic_routing();
539 printk(KERN_ERR "SMP mptable: no processors registered!\n");
540 return num_processors;
543 static int __init ELCR_trigger(unsigned int irq)
547 port = 0x4d0 + (irq >> 3);
548 return (inb(port) >> (irq & 7)) & 1;
551 static void __init construct_default_ioirq_mptable(int mpc_default_type)
553 struct mpc_config_intsrc intsrc;
555 int ELCR_fallback = 0;
557 intsrc.mpc_type = MP_INTSRC;
558 intsrc.mpc_irqflag = 0; /* conforming */
559 intsrc.mpc_srcbus = 0;
560 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
562 intsrc.mpc_irqtype = mp_INT;
565 * If true, we have an ISA/PCI system with no IRQ entries
566 * in the MP table. To prevent the PCI interrupts from being set up
567 * incorrectly, we try to use the ELCR. The sanity check to see if
568 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
569 * never be level sensitive, so we simply see if the ELCR agrees.
570 * If it does, we assume it's valid.
572 if (mpc_default_type == 5) {
573 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
575 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
576 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
578 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
583 for (i = 0; i < 16; i++) {
584 switch (mpc_default_type) {
586 if (i == 0 || i == 13)
587 continue; /* IRQ0 & IRQ13 not connected */
591 continue; /* IRQ2 is never connected */
596 * If the ELCR indicates a level-sensitive interrupt, we
597 * copy that information over to the MP table in the
598 * irqflag field (level sensitive, active high polarity).
601 intsrc.mpc_irqflag = 13;
603 intsrc.mpc_irqflag = 0;
606 intsrc.mpc_srcbusirq = i;
607 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
608 MP_intsrc_info(&intsrc);
611 intsrc.mpc_irqtype = mp_ExtINT;
612 intsrc.mpc_srcbusirq = 0;
613 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
614 MP_intsrc_info(&intsrc);
617 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
619 struct mpc_config_processor processor;
620 struct mpc_config_bus bus;
621 struct mpc_config_ioapic ioapic;
622 struct mpc_config_lintsrc lintsrc;
623 int linttypes[2] = { mp_ExtINT, mp_NMI };
627 * local APIC has default address
629 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
632 * 2 CPUs, numbered 0 & 1.
634 processor.mpc_type = MP_PROCESSOR;
635 /* Either an integrated APIC or a discrete 82489DX. */
636 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
637 processor.mpc_cpuflag = CPU_ENABLED;
638 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
639 (boot_cpu_data.x86_model << 4) |
640 boot_cpu_data.x86_mask;
641 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
642 processor.mpc_reserved[0] = 0;
643 processor.mpc_reserved[1] = 0;
644 for (i = 0; i < 2; i++) {
645 processor.mpc_apicid = i;
646 MP_processor_info(&processor);
649 bus.mpc_type = MP_BUS;
651 switch (mpc_default_type) {
654 printk(KERN_ERR "Unknown standard configuration %d\n",
659 memcpy(bus.mpc_bustype, "ISA ", 6);
664 memcpy(bus.mpc_bustype, "EISA ", 6);
668 memcpy(bus.mpc_bustype, "MCA ", 6);
671 if (mpc_default_type > 4) {
673 memcpy(bus.mpc_bustype, "PCI ", 6);
677 ioapic.mpc_type = MP_IOAPIC;
678 ioapic.mpc_apicid = 2;
679 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
680 ioapic.mpc_flags = MPC_APIC_USABLE;
681 ioapic.mpc_apicaddr = 0xFEC00000;
682 MP_ioapic_info(&ioapic);
685 * We set up most of the low 16 IO-APIC pins according to MPS rules.
687 construct_default_ioirq_mptable(mpc_default_type);
689 lintsrc.mpc_type = MP_LINTSRC;
690 lintsrc.mpc_irqflag = 0; /* conforming */
691 lintsrc.mpc_srcbusid = 0;
692 lintsrc.mpc_srcbusirq = 0;
693 lintsrc.mpc_destapic = MP_APIC_ALL;
694 for (i = 0; i < 2; i++) {
695 lintsrc.mpc_irqtype = linttypes[i];
696 lintsrc.mpc_destapiclint = i;
697 MP_lintsrc_info(&lintsrc);
701 static struct intel_mp_floating *mpf_found;
704 * Scan the memory blocks for an SMP configuration block.
706 void __init get_smp_config (void)
708 struct intel_mp_floating *mpf = mpf_found;
711 * ACPI supports both logical (e.g. Hyper-Threading) and physical
712 * processors, where MPS only supports physical.
714 if (acpi_lapic && acpi_ioapic) {
715 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
719 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
721 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
722 if (mpf->mpf_feature2 & (1<<7)) {
723 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
726 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
731 * Now see if we need to read further.
733 if (mpf->mpf_feature1 != 0) {
735 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
736 construct_default_ISA_mptable(mpf->mpf_feature1);
738 } else if (mpf->mpf_physptr) {
741 * Read the physical hardware table. Anything here will
742 * override the defaults.
744 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
745 smp_found_config = 0;
746 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
747 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
751 * If there are no explicit MP IRQ entries, then we are
752 * broken. We set up most of the low 16 IO-APIC pins to
753 * ISA defaults and hope it will work.
755 if (!mp_irq_entries) {
756 struct mpc_config_bus bus;
758 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
760 bus.mpc_type = MP_BUS;
762 memcpy(bus.mpc_bustype, "ISA ", 6);
765 construct_default_ioirq_mptable(0);
771 printk(KERN_INFO "Processors: %d\n", num_processors);
773 * Only use the first configuration found.
777 static int __init smp_scan_config (unsigned long base, unsigned long length)
779 unsigned long *bp = phys_to_virt(base);
780 struct intel_mp_floating *mpf;
782 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
783 if (sizeof(*mpf) != 16)
784 printk("Error: MPF size\n");
787 mpf = (struct intel_mp_floating *)bp;
788 if ((*bp == SMP_MAGIC_IDENT) &&
789 (mpf->mpf_length == 1) &&
790 !mpf_checksum((unsigned char *)bp, 16) &&
791 ((mpf->mpf_specification == 1)
792 || (mpf->mpf_specification == 4)) ) {
794 smp_found_config = 1;
795 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
796 mpf, virt_to_phys(mpf));
797 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
799 if (mpf->mpf_physptr) {
801 * We cannot access to MPC table to compute
802 * table size yet, as only few megabytes from
803 * the bottom is mapped now.
804 * PC-9800's MPC table places on the very last
805 * of physical memory; so that simply reserving
806 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
807 * in reserve_bootmem.
809 unsigned long size = PAGE_SIZE;
810 unsigned long end = max_low_pfn * PAGE_SIZE;
811 if (mpf->mpf_physptr + size > end)
812 size = end - mpf->mpf_physptr;
813 reserve_bootmem(mpf->mpf_physptr, size,
826 void __init find_smp_config (void)
828 unsigned int address;
831 * FIXME: Linux assumes you have 640K of base ram..
832 * this continues the error...
834 * 1) Scan the bottom 1K for a signature
835 * 2) Scan the top 1K of base RAM
836 * 3) Scan the 64K of bios
838 if (smp_scan_config(0x0,0x400) ||
839 smp_scan_config(639*0x400,0x400) ||
840 smp_scan_config(0xF0000,0x10000))
843 * If it is an SMP machine we should know now, unless the
844 * configuration is in an EISA/MCA bus machine with an
845 * extended bios data area.
847 * there is a real-mode segmented pointer pointing to the
848 * 4K EBDA area at 0x40E, calculate and scan it here.
850 * NOTE! There are Linux loaders that will corrupt the EBDA
851 * area, and as such this kind of SMP config may be less
852 * trustworthy, simply because the SMP table may have been
853 * stomped on during early boot. These loaders are buggy and
856 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
859 address = get_bios_ebda();
861 smp_scan_config(address, 0x400);
866 /* --------------------------------------------------------------------------
867 ACPI-based MP Configuration
868 -------------------------------------------------------------------------- */
872 void __init mp_register_lapic_address(u64 address)
874 mp_lapic_addr = (unsigned long) address;
876 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
878 if (boot_cpu_physical_apicid == -1U)
879 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
881 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
884 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
886 struct mpc_config_processor processor;
889 if (MAX_APICS - id <= 0) {
890 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
895 if (id == boot_cpu_physical_apicid)
898 processor.mpc_type = MP_PROCESSOR;
899 processor.mpc_apicid = id;
900 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
901 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
902 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
903 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
904 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
905 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
906 processor.mpc_reserved[0] = 0;
907 processor.mpc_reserved[1] = 0;
909 MP_processor_info(&processor);
912 #ifdef CONFIG_X86_IO_APIC
915 #define MP_MAX_IOAPIC_PIN 127
917 static struct mp_ioapic_routing {
921 u32 pin_programmed[4];
922 } mp_ioapic_routing[MAX_IO_APICS];
924 static int mp_find_ioapic (int gsi)
928 /* Find the IOAPIC that manages this GSI. */
929 for (i = 0; i < nr_ioapics; i++) {
930 if ((gsi >= mp_ioapic_routing[i].gsi_base)
931 && (gsi <= mp_ioapic_routing[i].gsi_end))
935 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
940 static u8 uniq_ioapic_id(u8 id)
942 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
943 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
944 return io_apic_get_unique_id(nr_ioapics, id);
949 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
953 if (bad_ioapic(address))
958 mp_ioapics[idx].mpc_type = MP_IOAPIC;
959 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
960 mp_ioapics[idx].mpc_apicaddr = address;
962 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
963 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
964 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
967 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
968 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
970 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
971 mp_ioapic_routing[idx].gsi_base = gsi_base;
972 mp_ioapic_routing[idx].gsi_end = gsi_base +
973 io_apic_get_redir_entries(idx);
975 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
976 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
977 mp_ioapics[idx].mpc_apicver,
978 mp_ioapics[idx].mpc_apicaddr,
979 mp_ioapic_routing[idx].gsi_base,
980 mp_ioapic_routing[idx].gsi_end);
986 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
988 struct mpc_config_intsrc intsrc;
993 * Convert 'gsi' to 'ioapic.pin'.
995 ioapic = mp_find_ioapic(gsi);
998 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1001 * TBD: This check is for faulty timer entries, where the override
1002 * erroneously sets the trigger to level, resulting in a HUGE
1003 * increase of timer interrupts!
1005 if ((bus_irq == 0) && (trigger == 3))
1008 intsrc.mpc_type = MP_INTSRC;
1009 intsrc.mpc_irqtype = mp_INT;
1010 intsrc.mpc_irqflag = (trigger << 2) | polarity;
1011 intsrc.mpc_srcbus = MP_ISA_BUS;
1012 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
1013 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
1014 intsrc.mpc_dstirq = pin; /* INTIN# */
1016 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
1017 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1018 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1019 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1021 mp_irqs[mp_irq_entries] = intsrc;
1022 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1023 panic("Max # of irq sources exceeded!\n");
1026 void __init mp_config_acpi_legacy_irqs (void)
1028 struct mpc_config_intsrc intsrc;
1032 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
1034 * Fabricate the legacy ISA bus (bus #31).
1036 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1038 set_bit(MP_ISA_BUS, mp_bus_not_pci);
1039 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1042 * Older generations of ES7000 have no legacy identity mappings
1044 if (es7000_plat == 1)
1048 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1050 ioapic = mp_find_ioapic(0);
1054 intsrc.mpc_type = MP_INTSRC;
1055 intsrc.mpc_irqflag = 0; /* Conforming */
1056 intsrc.mpc_srcbus = MP_ISA_BUS;
1057 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1060 * Use the default configuration for the IRQs 0-15. Unless
1061 * overridden by (MADT) interrupt source override entries.
1063 for (i = 0; i < 16; i++) {
1066 for (idx = 0; idx < mp_irq_entries; idx++) {
1067 struct mpc_config_intsrc *irq = mp_irqs + idx;
1069 /* Do we already have a mapping for this ISA IRQ? */
1070 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1073 /* Do we already have a mapping for this IOAPIC pin */
1074 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1075 (irq->mpc_dstirq == i))
1079 if (idx != mp_irq_entries) {
1080 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1081 continue; /* IRQ already used */
1084 intsrc.mpc_irqtype = mp_INT;
1085 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1086 intsrc.mpc_dstirq = i;
1088 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1089 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1090 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1091 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1094 mp_irqs[mp_irq_entries] = intsrc;
1095 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1096 panic("Max # of irq sources exceeded!\n");
1100 #define MAX_GSI_NUM 4096
1101 #define IRQ_COMPRESSION_START 64
1103 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1108 static int pci_irq = IRQ_COMPRESSION_START;
1110 * Mapping between Global System Interrupts, which
1111 * represent all possible interrupts, and IRQs
1112 * assigned to actual devices.
1114 static int gsi_to_irq[MAX_GSI_NUM];
1116 /* Don't set up the ACPI SCI because it's already set up */
1117 if (acpi_gbl_FADT.sci_interrupt == gsi)
1120 ioapic = mp_find_ioapic(gsi);
1122 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1126 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1128 if (ioapic_renumber_irq)
1129 gsi = ioapic_renumber_irq(ioapic, gsi);
1132 * Avoid pin reprogramming. PRTs typically include entries
1133 * with redundant pin->gsi mappings (but unique PCI devices);
1134 * we only program the IOAPIC on the first.
1136 bit = ioapic_pin % 32;
1137 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1139 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1140 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1144 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1145 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1146 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1147 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1150 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1153 * For GSI >= 64, use IRQ compression
1155 if ((gsi >= IRQ_COMPRESSION_START)
1156 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1158 * For PCI devices assign IRQs in order, avoiding gaps
1159 * due to unused I/O APIC pins.
1162 if (gsi < MAX_GSI_NUM) {
1164 * Retain the VIA chipset work-around (gsi > 15), but
1165 * avoid a problem where the 8254 timer (IRQ0) is setup
1166 * via an override (so it's not on pin 0 of the ioapic),
1167 * and at the same time, the pin 0 interrupt is a PCI
1168 * type. The gsi > 15 test could cause these two pins
1169 * to be shared as IRQ0, and they are not shareable.
1170 * So test for this condition, and if necessary, avoid
1171 * the pin collision.
1173 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
1176 * Don't assign IRQ used by ACPI SCI
1178 if (gsi == acpi_gbl_FADT.sci_interrupt)
1180 gsi_to_irq[irq] = gsi;
1182 printk(KERN_ERR "GSI %u is too high\n", gsi);
1187 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1188 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1189 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1193 #endif /* CONFIG_X86_IO_APIC */
1194 #endif /* CONFIG_ACPI */