2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
46 #include <asm/proto.h>
49 #include <asm/i8259.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
56 #include <mach_apic.h>
58 #define __apicdebuginit(type) static type __init
65 struct irq_pin_list *irq_2_pin;
68 unsigned move_cleanup_count;
70 u8 move_in_progress : 1;
73 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
74 static struct irq_cfg irq_cfg_legacy[] __initdata = {
75 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
76 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
77 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
78 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
79 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
80 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
81 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
82 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
83 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
84 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
85 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
86 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
87 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
88 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
89 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
90 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
93 static struct irq_cfg irq_cfg_init = { .irq = -1U, };
94 /* need to be biger than size of irq_cfg_legacy */
95 static int nr_irq_cfg = 32;
97 static int __init parse_nr_irq_cfg(char *arg)
100 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
107 early_param("nr_irq_cfg", parse_nr_irq_cfg);
109 static void init_one_irq_cfg(struct irq_cfg *cfg)
111 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
114 static struct irq_cfg *irq_cfgx;
115 static struct irq_cfg *irq_cfgx_free;
116 static void __init init_work(void *data)
118 struct dyn_array *da = data;
125 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
127 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
128 for (i = legacy_count; i < *da->nr; i++)
129 init_one_irq_cfg(&cfg[i]);
131 for (i = 1; i < *da->nr; i++)
132 cfg[i-1].next = &cfg[i];
134 irq_cfgx_free = &irq_cfgx[legacy_count];
135 irq_cfgx[legacy_count - 1].next = NULL;
138 #define for_each_irq_cfg(cfg) \
139 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
141 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
143 static struct irq_cfg *irq_cfg(unsigned int irq)
158 static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
160 struct irq_cfg *cfg, *cfg_pri;
164 cfg_pri = cfg = irq_cfgx;
174 if (!irq_cfgx_free) {
176 unsigned long total_bytes;
178 * we run out of pre-allocate ones, allocate more
180 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
182 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
184 cfg = kzalloc(total_bytes, GFP_ATOMIC);
186 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
189 panic("please boot with nr_irq_cfg= %d\n", count * 2);
192 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
194 for (i = 0; i < nr_irq_cfg; i++)
195 init_one_irq_cfg(&cfg[i]);
197 for (i = 1; i < nr_irq_cfg; i++)
198 cfg[i-1].next = &cfg[i];
204 irq_cfgx_free = irq_cfgx_free->next;
211 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
212 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
214 /* dump the results */
217 unsigned long bytes = sizeof(struct irq_cfg);
219 printk(KERN_DEBUG "=========================== %d\n", irq);
220 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
221 for_each_irq_cfg(cfg) {
223 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
225 printk(KERN_DEBUG "===========================\n");
231 static int assign_irq_vector(int irq, cpumask_t mask);
233 int first_system_vector = 0xfe;
235 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
237 int sis_apic_bug; /* not actually supported, dummy for compile */
239 static int no_timer_check;
241 static int disable_timer_pin_1 __initdata;
243 int timer_through_8259 __initdata;
245 /* Where if anywhere is the i8259 connect in external int mode */
246 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
248 static DEFINE_SPINLOCK(ioapic_lock);
249 static DEFINE_SPINLOCK(vector_lock);
252 * # of IRQ routing registers
254 int nr_ioapic_registers[MAX_IO_APICS];
256 /* I/O APIC RTE contents at the OS boot up */
257 struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
259 /* I/O APIC entries */
260 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
263 /* MP IRQ source entries */
264 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
266 /* # of MP IRQ source entries */
269 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
272 * Rough estimation of how many shared IRQs there are, can
273 * be changed anytime.
279 * This is performance-critical, we want to do it O(1)
281 * the indexing order of this array favors 1:1 mappings
282 * between pins and IRQs.
285 struct irq_pin_list {
287 struct irq_pin_list *next;
290 static struct irq_pin_list *irq_2_pin_head;
291 /* fill one page ? */
292 static int nr_irq_2_pin = 0x100;
293 static struct irq_pin_list *irq_2_pin_ptr;
294 static void __init irq_2_pin_init_work(void *data)
296 struct dyn_array *da = data;
297 struct irq_pin_list *pin;
302 for (i = 1; i < *da->nr; i++)
303 pin[i-1].next = &pin[i];
305 irq_2_pin_ptr = &pin[0];
307 DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
309 static struct irq_pin_list *get_one_free_irq_2_pin(void)
311 struct irq_pin_list *pin;
317 irq_2_pin_ptr = pin->next;
323 * we run out of pre-allocate ones, allocate more
325 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
328 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
331 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
332 nr_irq_2_pin, PAGE_SIZE, 0);
335 panic("can not get more irq_2_pin\n");
337 for (i = 1; i < nr_irq_2_pin; i++)
338 pin[i-1].next = &pin[i];
340 irq_2_pin_ptr = pin->next;
348 unsigned int unused[3];
352 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
354 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
355 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
358 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
360 struct io_apic __iomem *io_apic = io_apic_base(apic);
361 writel(reg, &io_apic->index);
362 return readl(&io_apic->data);
365 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
367 struct io_apic __iomem *io_apic = io_apic_base(apic);
368 writel(reg, &io_apic->index);
369 writel(value, &io_apic->data);
373 * Re-write a value: to be used for read-modify-write
374 * cycles where the read already set up the index register.
376 static inline void io_apic_modify(unsigned int apic, unsigned int value)
378 struct io_apic __iomem *io_apic = io_apic_base(apic);
379 writel(value, &io_apic->data);
382 static bool io_apic_level_ack_pending(unsigned int irq)
384 struct irq_pin_list *entry;
386 struct irq_cfg *cfg = irq_cfg(irq);
388 spin_lock_irqsave(&ioapic_lock, flags);
389 entry = cfg->irq_2_pin;
397 reg = io_apic_read(entry->apic, 0x10 + pin*2);
398 /* Is the remote IRR bit set? */
399 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
400 spin_unlock_irqrestore(&ioapic_lock, flags);
407 spin_unlock_irqrestore(&ioapic_lock, flags);
413 struct { u32 w1, w2; };
414 struct IO_APIC_route_entry entry;
417 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
419 union entry_union eu;
421 spin_lock_irqsave(&ioapic_lock, flags);
422 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
423 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
424 spin_unlock_irqrestore(&ioapic_lock, flags);
429 * When we write a new IO APIC routing entry, we need to write the high
430 * word first! If the mask bit in the low word is clear, we will enable
431 * the interrupt, and we need to make sure the entry is fully populated
432 * before that happens.
435 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
437 union entry_union eu;
439 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
440 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
443 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
446 spin_lock_irqsave(&ioapic_lock, flags);
447 __ioapic_write_entry(apic, pin, e);
448 spin_unlock_irqrestore(&ioapic_lock, flags);
452 * When we mask an IO APIC routing entry, we need to write the low
453 * word first, in order to set the mask bit before we change the
456 static void ioapic_mask_entry(int apic, int pin)
459 union entry_union eu = { .entry.mask = 1 };
461 spin_lock_irqsave(&ioapic_lock, flags);
462 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
463 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
464 spin_unlock_irqrestore(&ioapic_lock, flags);
468 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
472 struct irq_pin_list *entry;
475 entry = cfg->irq_2_pin;
485 * With interrupt-remapping, destination information comes
486 * from interrupt-remapping table entry.
488 if (!irq_remapped(irq))
489 io_apic_write(apic, 0x11 + pin*2, dest);
490 reg = io_apic_read(apic, 0x10 + pin*2);
491 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
493 io_apic_modify(apic, reg);
500 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
502 struct irq_cfg *cfg = irq_cfg(irq);
506 struct irq_desc *desc;
508 cpus_and(tmp, mask, cpu_online_map);
512 if (assign_irq_vector(irq, mask))
515 cpus_and(tmp, cfg->domain, mask);
516 dest = cpu_mask_to_apicid(tmp);
519 * Only the high 8 bits are valid.
521 dest = SET_APIC_LOGICAL_ID(dest);
523 desc = irq_to_desc(irq);
524 spin_lock_irqsave(&ioapic_lock, flags);
525 __target_IO_APIC_irq(irq, dest, cfg->vector);
526 desc->affinity = mask;
527 spin_unlock_irqrestore(&ioapic_lock, flags);
532 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
533 * shared ISA-space IRQs, so we have to support them. We are super
534 * fast in the common case, and fast for shared ISA-space IRQs.
536 int first_free_entry;
537 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
540 struct irq_pin_list *entry;
542 /* first time to refer irq_cfg, so with new */
543 cfg = irq_cfg_alloc(irq);
544 entry = cfg->irq_2_pin;
546 entry = get_one_free_irq_2_pin();
547 cfg->irq_2_pin = entry;
550 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
554 while (entry->next) {
555 /* not again, please */
556 if (entry->apic == apic && entry->pin == pin)
562 entry->next = get_one_free_irq_2_pin();
566 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
570 * Reroute an IRQ to a different pin.
572 static void __init replace_pin_at_irq(unsigned int irq,
573 int oldapic, int oldpin,
574 int newapic, int newpin)
576 struct irq_cfg *cfg = irq_cfg(irq);
577 struct irq_pin_list *entry = cfg->irq_2_pin;
581 if (entry->apic == oldapic && entry->pin == oldpin) {
582 entry->apic = newapic;
585 /* every one is different, right? */
591 /* why? call replace before add? */
593 add_pin_to_irq(irq, newapic, newpin);
597 * Synchronize the IO-APIC and the CPU by doing
598 * a dummy read from the IO-APIC
600 static inline void io_apic_sync(unsigned int apic)
602 struct io_apic __iomem *io_apic = io_apic_base(apic);
603 readl(&io_apic->data);
606 #define __DO_ACTION(R, ACTION, FINAL) \
610 struct irq_cfg *cfg; \
611 struct irq_pin_list *entry; \
613 cfg = irq_cfg(irq); \
614 entry = cfg->irq_2_pin; \
620 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
622 io_apic_modify(entry->apic, reg); \
626 entry = entry->next; \
630 #define DO_ACTION(name,R,ACTION, FINAL) \
632 static void name##_IO_APIC_irq (unsigned int irq) \
633 __DO_ACTION(R, ACTION, FINAL)
636 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
639 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
641 static void mask_IO_APIC_irq (unsigned int irq)
645 spin_lock_irqsave(&ioapic_lock, flags);
646 __mask_IO_APIC_irq(irq);
647 spin_unlock_irqrestore(&ioapic_lock, flags);
650 static void unmask_IO_APIC_irq (unsigned int irq)
654 spin_lock_irqsave(&ioapic_lock, flags);
655 __unmask_IO_APIC_irq(irq);
656 spin_unlock_irqrestore(&ioapic_lock, flags);
659 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
661 struct IO_APIC_route_entry entry;
663 /* Check delivery_mode to be sure we're not clearing an SMI pin */
664 entry = ioapic_read_entry(apic, pin);
665 if (entry.delivery_mode == dest_SMI)
668 * Disable it in the IO-APIC irq-routing table:
670 ioapic_mask_entry(apic, pin);
673 static void clear_IO_APIC (void)
677 for (apic = 0; apic < nr_ioapics; apic++)
678 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
679 clear_IO_APIC_pin(apic, pin);
683 * Saves and masks all the unmasked IO-APIC RTE's
685 int save_mask_IO_APIC_setup(void)
687 union IO_APIC_reg_01 reg_01;
692 * The number of IO-APIC IRQ registers (== #pins):
694 for (apic = 0; apic < nr_ioapics; apic++) {
695 spin_lock_irqsave(&ioapic_lock, flags);
696 reg_01.raw = io_apic_read(apic, 1);
697 spin_unlock_irqrestore(&ioapic_lock, flags);
698 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
701 for (apic = 0; apic < nr_ioapics; apic++) {
702 early_ioapic_entries[apic] =
703 kzalloc(sizeof(struct IO_APIC_route_entry) *
704 nr_ioapic_registers[apic], GFP_KERNEL);
705 if (!early_ioapic_entries[apic])
709 for (apic = 0; apic < nr_ioapics; apic++)
710 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
711 struct IO_APIC_route_entry entry;
713 entry = early_ioapic_entries[apic][pin] =
714 ioapic_read_entry(apic, pin);
717 ioapic_write_entry(apic, pin, entry);
723 void restore_IO_APIC_setup(void)
727 for (apic = 0; apic < nr_ioapics; apic++)
728 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
729 ioapic_write_entry(apic, pin,
730 early_ioapic_entries[apic][pin]);
733 void reinit_intr_remapped_IO_APIC(int intr_remapping)
736 * for now plain restore of previous settings.
737 * TBD: In the case of OS enabling interrupt-remapping,
738 * IO-APIC RTE's need to be setup to point to interrupt-remapping
739 * table entries. for now, do a plain restore, and wait for
740 * the setup_IO_APIC_irqs() to do proper initialization.
742 restore_IO_APIC_setup();
745 int skip_ioapic_setup;
748 static int __init parse_noapic(char *str)
750 disable_ioapic_setup();
753 early_param("noapic", parse_noapic);
755 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
756 static int __init disable_timer_pin_setup(char *arg)
758 disable_timer_pin_1 = 1;
761 __setup("disable_timer_pin_1", disable_timer_pin_setup);
765 * Find the IRQ entry number of a certain pin.
767 static int find_irq_entry(int apic, int pin, int type)
771 for (i = 0; i < mp_irq_entries; i++)
772 if (mp_irqs[i].mp_irqtype == type &&
773 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
774 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
775 mp_irqs[i].mp_dstirq == pin)
782 * Find the pin to which IRQ[irq] (ISA) is connected
784 static int __init find_isa_irq_pin(int irq, int type)
788 for (i = 0; i < mp_irq_entries; i++) {
789 int lbus = mp_irqs[i].mp_srcbus;
791 if (test_bit(lbus, mp_bus_not_pci) &&
792 (mp_irqs[i].mp_irqtype == type) &&
793 (mp_irqs[i].mp_srcbusirq == irq))
795 return mp_irqs[i].mp_dstirq;
800 static int __init find_isa_irq_apic(int irq, int type)
804 for (i = 0; i < mp_irq_entries; i++) {
805 int lbus = mp_irqs[i].mp_srcbus;
807 if (test_bit(lbus, mp_bus_not_pci) &&
808 (mp_irqs[i].mp_irqtype == type) &&
809 (mp_irqs[i].mp_srcbusirq == irq))
812 if (i < mp_irq_entries) {
814 for(apic = 0; apic < nr_ioapics; apic++) {
815 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
824 * Find a specific PCI IRQ entry.
825 * Not an __init, possibly needed by modules
827 static int pin_2_irq(int idx, int apic, int pin);
829 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
831 int apic, i, best_guess = -1;
833 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
835 if (test_bit(bus, mp_bus_not_pci)) {
836 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
839 for (i = 0; i < mp_irq_entries; i++) {
840 int lbus = mp_irqs[i].mp_srcbus;
842 for (apic = 0; apic < nr_ioapics; apic++)
843 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
844 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
847 if (!test_bit(lbus, mp_bus_not_pci) &&
848 !mp_irqs[i].mp_irqtype &&
850 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
851 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
853 if (!(apic || IO_APIC_IRQ(irq)))
856 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
859 * Use the first all-but-pin matching entry as a
860 * best-guess fuzzy result for broken mptables.
869 /* ISA interrupts are always polarity zero edge triggered,
870 * when listed as conforming in the MP table. */
872 #define default_ISA_trigger(idx) (0)
873 #define default_ISA_polarity(idx) (0)
875 /* PCI interrupts are always polarity one level triggered,
876 * when listed as conforming in the MP table. */
878 #define default_PCI_trigger(idx) (1)
879 #define default_PCI_polarity(idx) (1)
881 static int MPBIOS_polarity(int idx)
883 int bus = mp_irqs[idx].mp_srcbus;
887 * Determine IRQ line polarity (high active or low active):
889 switch (mp_irqs[idx].mp_irqflag & 3)
891 case 0: /* conforms, ie. bus-type dependent polarity */
892 if (test_bit(bus, mp_bus_not_pci))
893 polarity = default_ISA_polarity(idx);
895 polarity = default_PCI_polarity(idx);
897 case 1: /* high active */
902 case 2: /* reserved */
904 printk(KERN_WARNING "broken BIOS!!\n");
908 case 3: /* low active */
913 default: /* invalid */
915 printk(KERN_WARNING "broken BIOS!!\n");
923 static int MPBIOS_trigger(int idx)
925 int bus = mp_irqs[idx].mp_srcbus;
929 * Determine IRQ trigger mode (edge or level sensitive):
931 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
933 case 0: /* conforms, ie. bus-type dependent */
934 if (test_bit(bus, mp_bus_not_pci))
935 trigger = default_ISA_trigger(idx);
937 trigger = default_PCI_trigger(idx);
944 case 2: /* reserved */
946 printk(KERN_WARNING "broken BIOS!!\n");
955 default: /* invalid */
957 printk(KERN_WARNING "broken BIOS!!\n");
965 static inline int irq_polarity(int idx)
967 return MPBIOS_polarity(idx);
970 static inline int irq_trigger(int idx)
972 return MPBIOS_trigger(idx);
975 static int pin_2_irq(int idx, int apic, int pin)
978 int bus = mp_irqs[idx].mp_srcbus;
981 * Debugging check, we are in big trouble if this message pops up!
983 if (mp_irqs[idx].mp_dstirq != pin)
984 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
986 if (test_bit(bus, mp_bus_not_pci)) {
987 irq = mp_irqs[idx].mp_srcbusirq;
990 * PCI IRQs are mapped in order
994 irq += nr_ioapic_registers[i++];
1000 void lock_vector_lock(void)
1002 /* Used to the online set of cpus does not change
1003 * during assign_irq_vector.
1005 spin_lock(&vector_lock);
1008 void unlock_vector_lock(void)
1010 spin_unlock(&vector_lock);
1013 static int __assign_irq_vector(int irq, cpumask_t mask)
1016 * NOTE! The local APIC isn't very good at handling
1017 * multiple interrupts at the same interrupt level.
1018 * As the interrupt level is determined by taking the
1019 * vector number and shifting that right by 4, we
1020 * want to spread these out a bit so that they don't
1021 * all fall in the same interrupt level.
1023 * Also, we've got to be careful not to trash gate
1024 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1026 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1027 unsigned int old_vector;
1029 struct irq_cfg *cfg;
1033 /* Only try and allocate irqs on cpus that are present */
1034 cpus_and(mask, mask, cpu_online_map);
1036 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1039 old_vector = cfg->vector;
1042 cpus_and(tmp, cfg->domain, mask);
1043 if (!cpus_empty(tmp))
1047 for_each_cpu_mask_nr(cpu, mask) {
1048 cpumask_t domain, new_mask;
1052 domain = vector_allocation_domain(cpu);
1053 cpus_and(new_mask, domain, cpu_online_map);
1055 vector = current_vector;
1056 offset = current_offset;
1059 if (vector >= first_system_vector) {
1060 /* If we run out of vectors on large boxen, must share them. */
1061 offset = (offset + 1) % 8;
1062 vector = FIRST_DEVICE_VECTOR + offset;
1064 if (unlikely(current_vector == vector))
1066 if (vector == IA32_SYSCALL_VECTOR)
1068 for_each_cpu_mask_nr(new_cpu, new_mask)
1069 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1072 current_vector = vector;
1073 current_offset = offset;
1075 cfg->move_in_progress = 1;
1076 cfg->old_domain = cfg->domain;
1078 for_each_cpu_mask_nr(new_cpu, new_mask)
1079 per_cpu(vector_irq, new_cpu)[vector] = irq;
1080 cfg->vector = vector;
1081 cfg->domain = domain;
1087 static int assign_irq_vector(int irq, cpumask_t mask)
1090 unsigned long flags;
1092 spin_lock_irqsave(&vector_lock, flags);
1093 err = __assign_irq_vector(irq, mask);
1094 spin_unlock_irqrestore(&vector_lock, flags);
1098 static void __clear_irq_vector(int irq)
1100 struct irq_cfg *cfg;
1105 BUG_ON(!cfg->vector);
1107 vector = cfg->vector;
1108 cpus_and(mask, cfg->domain, cpu_online_map);
1109 for_each_cpu_mask_nr(cpu, mask)
1110 per_cpu(vector_irq, cpu)[vector] = -1;
1113 cpus_clear(cfg->domain);
1116 void __setup_vector_irq(int cpu)
1118 /* Initialize vector_irq on a new cpu */
1119 /* This function must be called with vector_lock held */
1121 struct irq_cfg *cfg;
1123 /* Mark the inuse vectors */
1124 for_each_irq_cfg(cfg) {
1125 if (!cpu_isset(cpu, cfg->domain))
1127 vector = cfg->vector;
1129 per_cpu(vector_irq, cpu)[vector] = irq;
1131 /* Mark the free vectors */
1132 for (vector = 0; vector < NR_VECTORS; ++vector) {
1133 irq = per_cpu(vector_irq, cpu)[vector];
1138 if (!cpu_isset(cpu, cfg->domain))
1139 per_cpu(vector_irq, cpu)[vector] = -1;
1143 static struct irq_chip ioapic_chip;
1144 #ifdef CONFIG_INTR_REMAP
1145 static struct irq_chip ir_ioapic_chip;
1148 static void ioapic_register_intr(int irq, unsigned long trigger)
1150 struct irq_desc *desc;
1152 /* first time to use this irq_desc */
1154 desc = irq_to_desc(irq);
1156 desc = irq_to_desc_alloc(irq);
1159 desc->status |= IRQ_LEVEL;
1161 desc->status &= ~IRQ_LEVEL;
1163 #ifdef CONFIG_INTR_REMAP
1164 if (irq_remapped(irq)) {
1165 desc->status |= IRQ_MOVE_PCNTXT;
1167 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1171 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1172 handle_edge_irq, "edge");
1177 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1181 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1182 handle_edge_irq, "edge");
1185 static int setup_ioapic_entry(int apic, int irq,
1186 struct IO_APIC_route_entry *entry,
1187 unsigned int destination, int trigger,
1188 int polarity, int vector)
1191 * add it to the IO-APIC irq-routing table:
1193 memset(entry,0,sizeof(*entry));
1195 #ifdef CONFIG_INTR_REMAP
1196 if (intr_remapping_enabled) {
1197 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1199 struct IR_IO_APIC_route_entry *ir_entry =
1200 (struct IR_IO_APIC_route_entry *) entry;
1204 panic("No mapping iommu for ioapic %d\n", apic);
1206 index = alloc_irte(iommu, irq, 1);
1208 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1210 memset(&irte, 0, sizeof(irte));
1213 irte.dst_mode = INT_DEST_MODE;
1214 irte.trigger_mode = trigger;
1215 irte.dlvry_mode = INT_DELIVERY_MODE;
1216 irte.vector = vector;
1217 irte.dest_id = IRTE_DEST(destination);
1219 modify_irte(irq, &irte);
1221 ir_entry->index2 = (index >> 15) & 0x1;
1223 ir_entry->format = 1;
1224 ir_entry->index = (index & 0x7fff);
1228 entry->delivery_mode = INT_DELIVERY_MODE;
1229 entry->dest_mode = INT_DEST_MODE;
1230 entry->dest = destination;
1233 entry->mask = 0; /* enable IRQ */
1234 entry->trigger = trigger;
1235 entry->polarity = polarity;
1236 entry->vector = vector;
1238 /* Mask level triggered irqs.
1239 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1246 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1247 int trigger, int polarity)
1249 struct irq_cfg *cfg;
1250 struct IO_APIC_route_entry entry;
1253 if (!IO_APIC_IRQ(irq))
1259 if (assign_irq_vector(irq, mask))
1262 cpus_and(mask, cfg->domain, mask);
1264 apic_printk(APIC_VERBOSE,KERN_DEBUG
1265 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1266 "IRQ %d Mode:%i Active:%i)\n",
1267 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1268 irq, trigger, polarity);
1271 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1272 cpu_mask_to_apicid(mask), trigger, polarity,
1274 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1275 mp_ioapics[apic].mp_apicid, pin);
1276 __clear_irq_vector(irq);
1280 ioapic_register_intr(irq, trigger);
1282 disable_8259A_irq(irq);
1284 ioapic_write_entry(apic, pin, entry);
1287 static void __init setup_IO_APIC_irqs(void)
1289 int apic, pin, idx, irq, first_notcon = 1;
1291 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1293 for (apic = 0; apic < nr_ioapics; apic++) {
1294 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1296 idx = find_irq_entry(apic,pin,mp_INT);
1299 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1302 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1305 if (!first_notcon) {
1306 apic_printk(APIC_VERBOSE, " not connected.\n");
1310 irq = pin_2_irq(idx, apic, pin);
1311 add_pin_to_irq(irq, apic, pin);
1313 setup_IO_APIC_irq(apic, pin, irq,
1314 irq_trigger(idx), irq_polarity(idx));
1319 apic_printk(APIC_VERBOSE, " not connected.\n");
1323 * Set up the timer pin, possibly with the 8259A-master behind.
1325 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1328 struct IO_APIC_route_entry entry;
1330 if (intr_remapping_enabled)
1333 memset(&entry, 0, sizeof(entry));
1336 * We use logical delivery to get the timer IRQ
1339 entry.dest_mode = INT_DEST_MODE;
1340 entry.mask = 1; /* mask IRQ now */
1341 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1342 entry.delivery_mode = INT_DELIVERY_MODE;
1345 entry.vector = vector;
1348 * The timer IRQ doesn't have to know that behind the
1349 * scene we may have a 8259A-master in AEOI mode ...
1351 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1354 * Add it to the IO-APIC irq-routing table:
1356 ioapic_write_entry(apic, pin, entry);
1360 __apicdebuginit(void) print_IO_APIC(void)
1363 union IO_APIC_reg_00 reg_00;
1364 union IO_APIC_reg_01 reg_01;
1365 union IO_APIC_reg_02 reg_02;
1366 unsigned long flags;
1367 struct irq_cfg *cfg;
1369 if (apic_verbosity == APIC_QUIET)
1372 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1373 for (i = 0; i < nr_ioapics; i++)
1374 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1375 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1378 * We are a bit conservative about what we expect. We have to
1379 * know about every hardware change ASAP.
1381 printk(KERN_INFO "testing the IO APIC.......................\n");
1383 for (apic = 0; apic < nr_ioapics; apic++) {
1385 spin_lock_irqsave(&ioapic_lock, flags);
1386 reg_00.raw = io_apic_read(apic, 0);
1387 reg_01.raw = io_apic_read(apic, 1);
1388 if (reg_01.bits.version >= 0x10)
1389 reg_02.raw = io_apic_read(apic, 2);
1390 spin_unlock_irqrestore(&ioapic_lock, flags);
1393 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1394 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1395 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1396 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1397 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1399 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1400 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1402 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1403 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1405 if (reg_01.bits.version >= 0x10) {
1406 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1407 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1410 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1412 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1413 " Stat Dmod Deli Vect: \n");
1415 for (i = 0; i <= reg_01.bits.entries; i++) {
1416 struct IO_APIC_route_entry entry;
1418 entry = ioapic_read_entry(apic, i);
1420 printk(KERN_DEBUG " %02x %03X ",
1425 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1430 entry.delivery_status,
1432 entry.delivery_mode,
1437 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1438 for_each_irq_cfg(cfg) {
1439 struct irq_pin_list *entry = cfg->irq_2_pin;
1442 printk(KERN_DEBUG "IRQ%d ", cfg->irq);
1444 printk("-> %d:%d", entry->apic, entry->pin);
1447 entry = entry->next;
1452 printk(KERN_INFO ".................................... done.\n");
1457 __apicdebuginit(void) print_APIC_bitfield(int base)
1462 if (apic_verbosity == APIC_QUIET)
1465 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1466 for (i = 0; i < 8; i++) {
1467 v = apic_read(base + i*0x10);
1468 for (j = 0; j < 32; j++) {
1478 __apicdebuginit(void) print_local_APIC(void *dummy)
1480 unsigned int v, ver, maxlvt;
1483 if (apic_verbosity == APIC_QUIET)
1486 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1487 smp_processor_id(), hard_smp_processor_id());
1488 v = apic_read(APIC_ID);
1489 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1490 v = apic_read(APIC_LVR);
1491 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1492 ver = GET_APIC_VERSION(v);
1493 maxlvt = lapic_get_maxlvt();
1495 v = apic_read(APIC_TASKPRI);
1496 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1498 v = apic_read(APIC_ARBPRI);
1499 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1500 v & APIC_ARBPRI_MASK);
1501 v = apic_read(APIC_PROCPRI);
1502 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1504 v = apic_read(APIC_EOI);
1505 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1506 v = apic_read(APIC_RRR);
1507 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1508 v = apic_read(APIC_LDR);
1509 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1510 v = apic_read(APIC_DFR);
1511 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1512 v = apic_read(APIC_SPIV);
1513 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1515 printk(KERN_DEBUG "... APIC ISR field:\n");
1516 print_APIC_bitfield(APIC_ISR);
1517 printk(KERN_DEBUG "... APIC TMR field:\n");
1518 print_APIC_bitfield(APIC_TMR);
1519 printk(KERN_DEBUG "... APIC IRR field:\n");
1520 print_APIC_bitfield(APIC_IRR);
1522 v = apic_read(APIC_ESR);
1523 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1525 icr = apic_icr_read();
1526 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1527 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1529 v = apic_read(APIC_LVTT);
1530 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1532 if (maxlvt > 3) { /* PC is LVT#4. */
1533 v = apic_read(APIC_LVTPC);
1534 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1536 v = apic_read(APIC_LVT0);
1537 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1538 v = apic_read(APIC_LVT1);
1539 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1541 if (maxlvt > 2) { /* ERR is LVT#3. */
1542 v = apic_read(APIC_LVTERR);
1543 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1546 v = apic_read(APIC_TMICT);
1547 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1548 v = apic_read(APIC_TMCCT);
1549 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1550 v = apic_read(APIC_TDCR);
1551 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1555 __apicdebuginit(void) print_all_local_APICs(void)
1557 on_each_cpu(print_local_APIC, NULL, 1);
1560 __apicdebuginit(void) print_PIC(void)
1563 unsigned long flags;
1565 if (apic_verbosity == APIC_QUIET)
1568 printk(KERN_DEBUG "\nprinting PIC contents\n");
1570 spin_lock_irqsave(&i8259A_lock, flags);
1572 v = inb(0xa1) << 8 | inb(0x21);
1573 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1575 v = inb(0xa0) << 8 | inb(0x20);
1576 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1580 v = inb(0xa0) << 8 | inb(0x20);
1584 spin_unlock_irqrestore(&i8259A_lock, flags);
1586 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1588 v = inb(0x4d1) << 8 | inb(0x4d0);
1589 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1592 __apicdebuginit(int) print_all_ICs(void)
1595 print_all_local_APICs();
1601 fs_initcall(print_all_ICs);
1604 void __init enable_IO_APIC(void)
1606 union IO_APIC_reg_01 reg_01;
1607 int i8259_apic, i8259_pin;
1609 unsigned long flags;
1612 * The number of IO-APIC IRQ registers (== #pins):
1614 for (apic = 0; apic < nr_ioapics; apic++) {
1615 spin_lock_irqsave(&ioapic_lock, flags);
1616 reg_01.raw = io_apic_read(apic, 1);
1617 spin_unlock_irqrestore(&ioapic_lock, flags);
1618 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1620 for(apic = 0; apic < nr_ioapics; apic++) {
1622 /* See if any of the pins is in ExtINT mode */
1623 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1624 struct IO_APIC_route_entry entry;
1625 entry = ioapic_read_entry(apic, pin);
1627 /* If the interrupt line is enabled and in ExtInt mode
1628 * I have found the pin where the i8259 is connected.
1630 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1631 ioapic_i8259.apic = apic;
1632 ioapic_i8259.pin = pin;
1638 /* Look to see what if the MP table has reported the ExtINT */
1639 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1640 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1641 /* Trust the MP table if nothing is setup in the hardware */
1642 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1643 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1644 ioapic_i8259.pin = i8259_pin;
1645 ioapic_i8259.apic = i8259_apic;
1647 /* Complain if the MP table and the hardware disagree */
1648 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1649 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1651 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1655 * Do not trust the IO-APIC being empty at bootup
1661 * Not an __init, needed by the reboot code
1663 void disable_IO_APIC(void)
1666 * Clear the IO-APIC before rebooting:
1671 * If the i8259 is routed through an IOAPIC
1672 * Put that IOAPIC in virtual wire mode
1673 * so legacy interrupts can be delivered.
1675 if (ioapic_i8259.pin != -1) {
1676 struct IO_APIC_route_entry entry;
1678 memset(&entry, 0, sizeof(entry));
1679 entry.mask = 0; /* Enabled */
1680 entry.trigger = 0; /* Edge */
1682 entry.polarity = 0; /* High */
1683 entry.delivery_status = 0;
1684 entry.dest_mode = 0; /* Physical */
1685 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1687 entry.dest = read_apic_id();
1690 * Add it to the IO-APIC irq-routing table:
1692 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1695 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1699 * There is a nasty bug in some older SMP boards, their mptable lies
1700 * about the timer IRQ. We do the following to work around the situation:
1702 * - timer IRQ defaults to IO-APIC IRQ
1703 * - if this function detects that timer IRQs are defunct, then we fall
1704 * back to ISA timer IRQs
1706 static int __init timer_irq_works(void)
1708 unsigned long t1 = jiffies;
1709 unsigned long flags;
1711 local_save_flags(flags);
1713 /* Let ten ticks pass... */
1714 mdelay((10 * 1000) / HZ);
1715 local_irq_restore(flags);
1718 * Expect a few ticks at least, to be sure some possible
1719 * glue logic does not lock up after one or two first
1720 * ticks in a non-ExtINT mode. Also the local APIC
1721 * might have cached one ExtINT interrupt. Finally, at
1722 * least one tick may be lost due to delays.
1726 if (time_after(jiffies, t1 + 4))
1732 * In the SMP+IOAPIC case it might happen that there are an unspecified
1733 * number of pending IRQ events unhandled. These cases are very rare,
1734 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1735 * better to do it this way as thus we do not have to be aware of
1736 * 'pending' interrupts in the IRQ path, except at this point.
1739 * Edge triggered needs to resend any interrupt
1740 * that was delayed but this is now handled in the device
1745 * Starting up a edge-triggered IO-APIC interrupt is
1746 * nasty - we need to make sure that we get the edge.
1747 * If it is already asserted for some reason, we need
1748 * return 1 to indicate that is was pending.
1750 * This is not complete - we should be able to fake
1751 * an edge even if it isn't on the 8259A...
1754 static unsigned int startup_ioapic_irq(unsigned int irq)
1756 int was_pending = 0;
1757 unsigned long flags;
1759 spin_lock_irqsave(&ioapic_lock, flags);
1761 disable_8259A_irq(irq);
1762 if (i8259A_irq_pending(irq))
1765 __unmask_IO_APIC_irq(irq);
1766 spin_unlock_irqrestore(&ioapic_lock, flags);
1771 static int ioapic_retrigger_irq(unsigned int irq)
1773 struct irq_cfg *cfg = irq_cfg(irq);
1774 unsigned long flags;
1776 spin_lock_irqsave(&vector_lock, flags);
1777 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
1778 spin_unlock_irqrestore(&vector_lock, flags);
1784 * Level and edge triggered IO-APIC interrupts need different handling,
1785 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1786 * handled with the level-triggered descriptor, but that one has slightly
1787 * more overhead. Level-triggered interrupts cannot be handled with the
1788 * edge-triggered handler, without risking IRQ storms and other ugly
1794 #ifdef CONFIG_INTR_REMAP
1795 static void ir_irq_migration(struct work_struct *work);
1797 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
1800 * Migrate the IO-APIC irq in the presence of intr-remapping.
1802 * For edge triggered, irq migration is a simple atomic update(of vector
1803 * and cpu destination) of IRTE and flush the hardware cache.
1805 * For level triggered, we need to modify the io-apic RTE aswell with the update
1806 * vector information, along with modifying IRTE with vector and destination.
1807 * So irq migration for level triggered is little bit more complex compared to
1808 * edge triggered migration. But the good news is, we use the same algorithm
1809 * for level triggered migration as we have today, only difference being,
1810 * we now initiate the irq migration from process context instead of the
1811 * interrupt context.
1813 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1814 * suppression) to the IO-APIC, level triggered irq migration will also be
1815 * as simple as edge triggered migration and we can do the irq migration
1816 * with a simple atomic update to IO-APIC RTE.
1818 static void migrate_ioapic_irq(int irq, cpumask_t mask)
1820 struct irq_cfg *cfg;
1821 struct irq_desc *desc;
1822 cpumask_t tmp, cleanup_mask;
1824 int modify_ioapic_rte;
1826 unsigned long flags;
1828 cpus_and(tmp, mask, cpu_online_map);
1829 if (cpus_empty(tmp))
1832 if (get_irte(irq, &irte))
1835 if (assign_irq_vector(irq, mask))
1839 cpus_and(tmp, cfg->domain, mask);
1840 dest = cpu_mask_to_apicid(tmp);
1842 desc = irq_to_desc(irq);
1843 modify_ioapic_rte = desc->status & IRQ_LEVEL;
1844 if (modify_ioapic_rte) {
1845 spin_lock_irqsave(&ioapic_lock, flags);
1846 __target_IO_APIC_irq(irq, dest, cfg->vector);
1847 spin_unlock_irqrestore(&ioapic_lock, flags);
1850 irte.vector = cfg->vector;
1851 irte.dest_id = IRTE_DEST(dest);
1854 * Modified the IRTE and flushes the Interrupt entry cache.
1856 modify_irte(irq, &irte);
1858 if (cfg->move_in_progress) {
1859 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1860 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1861 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1862 cfg->move_in_progress = 0;
1865 desc->affinity = mask;
1868 static int migrate_irq_remapped_level(int irq)
1871 struct irq_desc *desc = irq_to_desc(irq);
1873 mask_IO_APIC_irq(irq);
1875 if (io_apic_level_ack_pending(irq)) {
1877 * Interrupt in progress. Migrating irq now will change the
1878 * vector information in the IO-APIC RTE and that will confuse
1879 * the EOI broadcast performed by cpu.
1880 * So, delay the irq migration to the next instance.
1882 schedule_delayed_work(&ir_migration_work, 1);
1886 /* everthing is clear. we have right of way */
1887 migrate_ioapic_irq(irq, desc->pending_mask);
1890 desc->status &= ~IRQ_MOVE_PENDING;
1891 cpus_clear(desc->pending_mask);
1894 unmask_IO_APIC_irq(irq);
1898 static void ir_irq_migration(struct work_struct *work)
1901 struct irq_desc *desc;
1903 for_each_irq_desc(irq, desc) {
1904 if (desc->status & IRQ_MOVE_PENDING) {
1905 unsigned long flags;
1907 spin_lock_irqsave(&desc->lock, flags);
1908 if (!desc->chip->set_affinity ||
1909 !(desc->status & IRQ_MOVE_PENDING)) {
1910 desc->status &= ~IRQ_MOVE_PENDING;
1911 spin_unlock_irqrestore(&desc->lock, flags);
1915 desc->chip->set_affinity(irq, desc->pending_mask);
1916 spin_unlock_irqrestore(&desc->lock, flags);
1922 * Migrates the IRQ destination in the process context.
1924 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1926 struct irq_desc *desc = irq_to_desc(irq);
1928 if (desc->status & IRQ_LEVEL) {
1929 desc->status |= IRQ_MOVE_PENDING;
1930 desc->pending_mask = mask;
1931 migrate_irq_remapped_level(irq);
1935 migrate_ioapic_irq(irq, mask);
1939 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1941 unsigned vector, me;
1946 me = smp_processor_id();
1947 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1949 struct irq_desc *desc;
1950 struct irq_cfg *cfg;
1951 irq = __get_cpu_var(vector_irq)[vector];
1953 desc = irq_to_desc(irq);
1958 spin_lock(&desc->lock);
1959 if (!cfg->move_cleanup_count)
1962 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1965 __get_cpu_var(vector_irq)[vector] = -1;
1966 cfg->move_cleanup_count--;
1968 spin_unlock(&desc->lock);
1974 static void irq_complete_move(unsigned int irq)
1976 struct irq_cfg *cfg = irq_cfg(irq);
1977 unsigned vector, me;
1979 if (likely(!cfg->move_in_progress))
1982 vector = ~get_irq_regs()->orig_ax;
1983 me = smp_processor_id();
1984 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1985 cpumask_t cleanup_mask;
1987 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1988 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1989 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1990 cfg->move_in_progress = 0;
1994 static inline void irq_complete_move(unsigned int irq) {}
1996 #ifdef CONFIG_INTR_REMAP
1997 static void ack_x2apic_level(unsigned int irq)
2002 static void ack_x2apic_edge(unsigned int irq)
2008 static void ack_apic_edge(unsigned int irq)
2010 irq_complete_move(irq);
2011 move_native_irq(irq);
2015 static void ack_apic_level(unsigned int irq)
2017 int do_unmask_irq = 0;
2019 irq_complete_move(irq);
2020 #ifdef CONFIG_GENERIC_PENDING_IRQ
2021 /* If we are moving the irq we need to mask it */
2022 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2024 mask_IO_APIC_irq(irq);
2029 * We must acknowledge the irq before we move it or the acknowledge will
2030 * not propagate properly.
2034 /* Now we can move and renable the irq */
2035 if (unlikely(do_unmask_irq)) {
2036 /* Only migrate the irq if the ack has been received.
2038 * On rare occasions the broadcast level triggered ack gets
2039 * delayed going to ioapics, and if we reprogram the
2040 * vector while Remote IRR is still set the irq will never
2043 * To prevent this scenario we read the Remote IRR bit
2044 * of the ioapic. This has two effects.
2045 * - On any sane system the read of the ioapic will
2046 * flush writes (and acks) going to the ioapic from
2048 * - We get to see if the ACK has actually been delivered.
2050 * Based on failed experiments of reprogramming the
2051 * ioapic entry from outside of irq context starting
2052 * with masking the ioapic entry and then polling until
2053 * Remote IRR was clear before reprogramming the
2054 * ioapic I don't trust the Remote IRR bit to be
2055 * completey accurate.
2057 * However there appears to be no other way to plug
2058 * this race, so if the Remote IRR bit is not
2059 * accurate and is causing problems then it is a hardware bug
2060 * and you can go talk to the chipset vendor about it.
2062 if (!io_apic_level_ack_pending(irq))
2063 move_masked_irq(irq);
2064 unmask_IO_APIC_irq(irq);
2068 static struct irq_chip ioapic_chip __read_mostly = {
2070 .startup = startup_ioapic_irq,
2071 .mask = mask_IO_APIC_irq,
2072 .unmask = unmask_IO_APIC_irq,
2073 .ack = ack_apic_edge,
2074 .eoi = ack_apic_level,
2076 .set_affinity = set_ioapic_affinity_irq,
2078 .retrigger = ioapic_retrigger_irq,
2081 #ifdef CONFIG_INTR_REMAP
2082 static struct irq_chip ir_ioapic_chip __read_mostly = {
2083 .name = "IR-IO-APIC",
2084 .startup = startup_ioapic_irq,
2085 .mask = mask_IO_APIC_irq,
2086 .unmask = unmask_IO_APIC_irq,
2087 .ack = ack_x2apic_edge,
2088 .eoi = ack_x2apic_level,
2090 .set_affinity = set_ir_ioapic_affinity_irq,
2092 .retrigger = ioapic_retrigger_irq,
2096 static inline void init_IO_APIC_traps(void)
2099 struct irq_desc *desc;
2100 struct irq_cfg *cfg;
2103 * NOTE! The local APIC isn't very good at handling
2104 * multiple interrupts at the same interrupt level.
2105 * As the interrupt level is determined by taking the
2106 * vector number and shifting that right by 4, we
2107 * want to spread these out a bit so that they don't
2108 * all fall in the same interrupt level.
2110 * Also, we've got to be careful not to trash gate
2111 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2113 for_each_irq_cfg(cfg) {
2115 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2117 * Hmm.. We don't have an entry for this,
2118 * so default to an old-fashioned 8259
2119 * interrupt if we can..
2122 make_8259A_irq(irq);
2124 desc = irq_to_desc(irq);
2125 /* Strange. Oh, well.. */
2126 desc->chip = &no_irq_chip;
2132 static void unmask_lapic_irq(unsigned int irq)
2136 v = apic_read(APIC_LVT0);
2137 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2140 static void mask_lapic_irq(unsigned int irq)
2144 v = apic_read(APIC_LVT0);
2145 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2148 static void ack_lapic_irq (unsigned int irq)
2153 static struct irq_chip lapic_chip __read_mostly = {
2154 .name = "local-APIC",
2155 .mask = mask_lapic_irq,
2156 .unmask = unmask_lapic_irq,
2157 .ack = ack_lapic_irq,
2160 static void lapic_register_intr(int irq)
2162 struct irq_desc *desc;
2164 desc = irq_to_desc(irq);
2165 desc->status &= ~IRQ_LEVEL;
2166 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2170 static void __init setup_nmi(void)
2173 * Dirty trick to enable the NMI watchdog ...
2174 * We put the 8259A master into AEOI mode and
2175 * unmask on all local APICs LVT0 as NMI.
2177 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2178 * is from Maciej W. Rozycki - so we do not have to EOI from
2179 * the NMI handler or the timer interrupt.
2181 printk(KERN_INFO "activating NMI Watchdog ...");
2183 enable_NMI_through_LVT0();
2189 * This looks a bit hackish but it's about the only one way of sending
2190 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2191 * not support the ExtINT mode, unfortunately. We need to send these
2192 * cycles as some i82489DX-based boards have glue logic that keeps the
2193 * 8259A interrupt line asserted until INTA. --macro
2195 static inline void __init unlock_ExtINT_logic(void)
2198 struct IO_APIC_route_entry entry0, entry1;
2199 unsigned char save_control, save_freq_select;
2201 pin = find_isa_irq_pin(8, mp_INT);
2202 apic = find_isa_irq_apic(8, mp_INT);
2206 entry0 = ioapic_read_entry(apic, pin);
2208 clear_IO_APIC_pin(apic, pin);
2210 memset(&entry1, 0, sizeof(entry1));
2212 entry1.dest_mode = 0; /* physical delivery */
2213 entry1.mask = 0; /* unmask IRQ now */
2214 entry1.dest = hard_smp_processor_id();
2215 entry1.delivery_mode = dest_ExtINT;
2216 entry1.polarity = entry0.polarity;
2220 ioapic_write_entry(apic, pin, entry1);
2222 save_control = CMOS_READ(RTC_CONTROL);
2223 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2224 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2226 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2231 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2235 CMOS_WRITE(save_control, RTC_CONTROL);
2236 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2237 clear_IO_APIC_pin(apic, pin);
2239 ioapic_write_entry(apic, pin, entry0);
2243 * This code may look a bit paranoid, but it's supposed to cooperate with
2244 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2245 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2246 * fanatically on his truly buggy board.
2248 * FIXME: really need to revamp this for modern platforms only.
2250 static inline void __init check_timer(void)
2252 struct irq_cfg *cfg = irq_cfg(0);
2253 int apic1, pin1, apic2, pin2;
2254 unsigned long flags;
2257 local_irq_save(flags);
2260 * get/set the timer IRQ vector:
2262 disable_8259A_irq(0);
2263 assign_irq_vector(0, TARGET_CPUS);
2266 * As IRQ0 is to be enabled in the 8259A, the virtual
2267 * wire has to be disabled in the local APIC.
2269 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2272 pin1 = find_isa_irq_pin(0, mp_INT);
2273 apic1 = find_isa_irq_apic(0, mp_INT);
2274 pin2 = ioapic_i8259.pin;
2275 apic2 = ioapic_i8259.apic;
2277 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2278 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2279 cfg->vector, apic1, pin1, apic2, pin2);
2282 * Some BIOS writers are clueless and report the ExtINTA
2283 * I/O APIC input from the cascaded 8259A as the timer
2284 * interrupt input. So just in case, if only one pin
2285 * was found above, try it both directly and through the
2289 if (intr_remapping_enabled)
2290 panic("BIOS bug: timer not connected to IO-APIC");
2294 } else if (pin2 == -1) {
2301 * Ok, does IRQ0 through the IOAPIC work?
2304 add_pin_to_irq(0, apic1, pin1);
2305 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2307 unmask_IO_APIC_irq(0);
2308 if (!no_timer_check && timer_irq_works()) {
2309 if (nmi_watchdog == NMI_IO_APIC) {
2311 enable_8259A_irq(0);
2313 if (disable_timer_pin_1 > 0)
2314 clear_IO_APIC_pin(0, pin1);
2317 if (intr_remapping_enabled)
2318 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2319 clear_IO_APIC_pin(apic1, pin1);
2321 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2322 "8254 timer not connected to IO-APIC\n");
2324 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2325 "(IRQ0) through the 8259A ...\n");
2326 apic_printk(APIC_QUIET, KERN_INFO
2327 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2329 * legacy devices should be connected to IO APIC #0
2331 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2332 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2333 unmask_IO_APIC_irq(0);
2334 enable_8259A_irq(0);
2335 if (timer_irq_works()) {
2336 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2337 timer_through_8259 = 1;
2338 if (nmi_watchdog == NMI_IO_APIC) {
2339 disable_8259A_irq(0);
2341 enable_8259A_irq(0);
2346 * Cleanup, just in case ...
2348 disable_8259A_irq(0);
2349 clear_IO_APIC_pin(apic2, pin2);
2350 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2353 if (nmi_watchdog == NMI_IO_APIC) {
2354 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2355 "through the IO-APIC - disabling NMI Watchdog!\n");
2356 nmi_watchdog = NMI_NONE;
2359 apic_printk(APIC_QUIET, KERN_INFO
2360 "...trying to set up timer as Virtual Wire IRQ...\n");
2362 lapic_register_intr(0);
2363 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2364 enable_8259A_irq(0);
2366 if (timer_irq_works()) {
2367 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2370 disable_8259A_irq(0);
2371 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2372 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2374 apic_printk(APIC_QUIET, KERN_INFO
2375 "...trying to set up timer as ExtINT IRQ...\n");
2379 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2381 unlock_ExtINT_logic();
2383 if (timer_irq_works()) {
2384 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2387 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2388 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2389 "report. Then try booting with the 'noapic' option.\n");
2391 local_irq_restore(flags);
2394 static int __init notimercheck(char *s)
2399 __setup("no_timer_check", notimercheck);
2402 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2403 * to devices. However there may be an I/O APIC pin available for
2404 * this interrupt regardless. The pin may be left unconnected, but
2405 * typically it will be reused as an ExtINT cascade interrupt for
2406 * the master 8259A. In the MPS case such a pin will normally be
2407 * reported as an ExtINT interrupt in the MP table. With ACPI
2408 * there is no provision for ExtINT interrupts, and in the absence
2409 * of an override it would be treated as an ordinary ISA I/O APIC
2410 * interrupt, that is edge-triggered and unmasked by default. We
2411 * used to do this, but it caused problems on some systems because
2412 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2413 * the same ExtINT cascade interrupt to drive the local APIC of the
2414 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2415 * the I/O APIC in all cases now. No actual device should request
2416 * it anyway. --macro
2418 #define PIC_IRQS (1<<2)
2420 void __init setup_IO_APIC(void)
2424 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2427 io_apic_irqs = ~PIC_IRQS;
2429 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2432 setup_IO_APIC_irqs();
2433 init_IO_APIC_traps();
2437 struct sysfs_ioapic_data {
2438 struct sys_device dev;
2439 struct IO_APIC_route_entry entry[0];
2441 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2443 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2445 struct IO_APIC_route_entry *entry;
2446 struct sysfs_ioapic_data *data;
2449 data = container_of(dev, struct sysfs_ioapic_data, dev);
2450 entry = data->entry;
2451 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2452 *entry = ioapic_read_entry(dev->id, i);
2457 static int ioapic_resume(struct sys_device *dev)
2459 struct IO_APIC_route_entry *entry;
2460 struct sysfs_ioapic_data *data;
2461 unsigned long flags;
2462 union IO_APIC_reg_00 reg_00;
2465 data = container_of(dev, struct sysfs_ioapic_data, dev);
2466 entry = data->entry;
2468 spin_lock_irqsave(&ioapic_lock, flags);
2469 reg_00.raw = io_apic_read(dev->id, 0);
2470 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2471 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2472 io_apic_write(dev->id, 0, reg_00.raw);
2474 spin_unlock_irqrestore(&ioapic_lock, flags);
2475 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2476 ioapic_write_entry(dev->id, i, entry[i]);
2481 static struct sysdev_class ioapic_sysdev_class = {
2483 .suspend = ioapic_suspend,
2484 .resume = ioapic_resume,
2487 static int __init ioapic_init_sysfs(void)
2489 struct sys_device * dev;
2492 error = sysdev_class_register(&ioapic_sysdev_class);
2496 for (i = 0; i < nr_ioapics; i++ ) {
2497 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2498 * sizeof(struct IO_APIC_route_entry);
2499 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2500 if (!mp_ioapic_data[i]) {
2501 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2504 dev = &mp_ioapic_data[i]->dev;
2506 dev->cls = &ioapic_sysdev_class;
2507 error = sysdev_register(dev);
2509 kfree(mp_ioapic_data[i]);
2510 mp_ioapic_data[i] = NULL;
2511 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2519 device_initcall(ioapic_init_sysfs);
2522 * Dynamic irq allocate and deallocation
2524 unsigned int create_irq_nr(unsigned int irq_want)
2526 /* Allocate an unused irq */
2529 unsigned long flags;
2530 struct irq_cfg *cfg_new;
2532 #ifndef CONFIG_HAVE_SPARSE_IRQ
2533 irq_want = nr_irqs - 1;
2537 spin_lock_irqsave(&vector_lock, flags);
2538 for (new = irq_want; new > 0; new--) {
2539 if (platform_legacy_irq(new))
2541 cfg_new = irq_cfg(new);
2542 if (cfg_new && cfg_new->vector != 0)
2544 /* check if need to create one */
2546 cfg_new = irq_cfg_alloc(new);
2547 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2551 spin_unlock_irqrestore(&vector_lock, flags);
2554 dynamic_irq_init(irq);
2559 int create_irq(void)
2563 irq = create_irq_nr(nr_irqs - 1);
2571 void destroy_irq(unsigned int irq)
2573 unsigned long flags;
2575 dynamic_irq_cleanup(irq);
2577 #ifdef CONFIG_INTR_REMAP
2580 spin_lock_irqsave(&vector_lock, flags);
2581 __clear_irq_vector(irq);
2582 spin_unlock_irqrestore(&vector_lock, flags);
2586 * MSI message composition
2588 #ifdef CONFIG_PCI_MSI
2589 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2591 struct irq_cfg *cfg;
2597 err = assign_irq_vector(irq, tmp);
2602 cpus_and(tmp, cfg->domain, tmp);
2603 dest = cpu_mask_to_apicid(tmp);
2605 #ifdef CONFIG_INTR_REMAP
2606 if (irq_remapped(irq)) {
2611 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2612 BUG_ON(ir_index == -1);
2614 memset (&irte, 0, sizeof(irte));
2617 irte.dst_mode = INT_DEST_MODE;
2618 irte.trigger_mode = 0; /* edge */
2619 irte.dlvry_mode = INT_DELIVERY_MODE;
2620 irte.vector = cfg->vector;
2621 irte.dest_id = IRTE_DEST(dest);
2623 modify_irte(irq, &irte);
2625 msg->address_hi = MSI_ADDR_BASE_HI;
2626 msg->data = sub_handle;
2627 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
2629 MSI_ADDR_IR_INDEX1(ir_index) |
2630 MSI_ADDR_IR_INDEX2(ir_index);
2634 msg->address_hi = MSI_ADDR_BASE_HI;
2637 ((INT_DEST_MODE == 0) ?
2638 MSI_ADDR_DEST_MODE_PHYSICAL:
2639 MSI_ADDR_DEST_MODE_LOGICAL) |
2640 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2641 MSI_ADDR_REDIRECTION_CPU:
2642 MSI_ADDR_REDIRECTION_LOWPRI) |
2643 MSI_ADDR_DEST_ID(dest);
2646 MSI_DATA_TRIGGER_EDGE |
2647 MSI_DATA_LEVEL_ASSERT |
2648 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2649 MSI_DATA_DELIVERY_FIXED:
2650 MSI_DATA_DELIVERY_LOWPRI) |
2651 MSI_DATA_VECTOR(cfg->vector);
2657 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2659 struct irq_cfg *cfg;
2663 struct irq_desc *desc;
2665 cpus_and(tmp, mask, cpu_online_map);
2666 if (cpus_empty(tmp))
2669 if (assign_irq_vector(irq, mask))
2673 cpus_and(tmp, cfg->domain, mask);
2674 dest = cpu_mask_to_apicid(tmp);
2676 read_msi_msg(irq, &msg);
2678 msg.data &= ~MSI_DATA_VECTOR_MASK;
2679 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2680 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2681 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2683 write_msi_msg(irq, &msg);
2684 desc = irq_to_desc(irq);
2685 desc->affinity = mask;
2688 #ifdef CONFIG_INTR_REMAP
2690 * Migrate the MSI irq to another cpumask. This migration is
2691 * done in the process context using interrupt-remapping hardware.
2693 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2695 struct irq_cfg *cfg;
2697 cpumask_t tmp, cleanup_mask;
2699 struct irq_desc *desc;
2701 cpus_and(tmp, mask, cpu_online_map);
2702 if (cpus_empty(tmp))
2705 if (get_irte(irq, &irte))
2708 if (assign_irq_vector(irq, mask))
2712 cpus_and(tmp, cfg->domain, mask);
2713 dest = cpu_mask_to_apicid(tmp);
2715 irte.vector = cfg->vector;
2716 irte.dest_id = IRTE_DEST(dest);
2719 * atomically update the IRTE with the new destination and vector.
2721 modify_irte(irq, &irte);
2724 * After this point, all the interrupts will start arriving
2725 * at the new destination. So, time to cleanup the previous
2726 * vector allocation.
2728 if (cfg->move_in_progress) {
2729 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2730 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2731 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2732 cfg->move_in_progress = 0;
2735 desc = irq_to_desc(irq);
2736 desc->affinity = mask;
2739 #endif /* CONFIG_SMP */
2742 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2743 * which implement the MSI or MSI-X Capability Structure.
2745 static struct irq_chip msi_chip = {
2747 .unmask = unmask_msi_irq,
2748 .mask = mask_msi_irq,
2749 .ack = ack_apic_edge,
2751 .set_affinity = set_msi_irq_affinity,
2753 .retrigger = ioapic_retrigger_irq,
2756 #ifdef CONFIG_INTR_REMAP
2757 static struct irq_chip msi_ir_chip = {
2758 .name = "IR-PCI-MSI",
2759 .unmask = unmask_msi_irq,
2760 .mask = mask_msi_irq,
2761 .ack = ack_x2apic_edge,
2763 .set_affinity = ir_set_msi_irq_affinity,
2765 .retrigger = ioapic_retrigger_irq,
2769 * Map the PCI dev to the corresponding remapping hardware unit
2770 * and allocate 'nvec' consecutive interrupt-remapping table entries
2773 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
2775 struct intel_iommu *iommu;
2778 iommu = map_dev_to_ir(dev);
2781 "Unable to map PCI %s to iommu\n", pci_name(dev));
2785 index = alloc_irte(iommu, irq, nvec);
2788 "Unable to allocate %d IRTE for PCI %s\n", nvec,
2796 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2801 ret = msi_compose_msg(dev, irq, &msg);
2805 set_irq_msi(irq, desc);
2806 write_msi_msg(irq, &msg);
2808 #ifdef CONFIG_INTR_REMAP
2809 if (irq_remapped(irq)) {
2810 struct irq_desc *desc = irq_to_desc(irq);
2812 * irq migration in process context
2814 desc->status |= IRQ_MOVE_PCNTXT;
2815 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
2818 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2823 static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
2827 irq = dev->bus->number;
2835 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2839 unsigned int irq_want;
2841 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2843 irq = create_irq_nr(irq_want);
2847 #ifdef CONFIG_INTR_REMAP
2848 if (!intr_remapping_enabled)
2851 ret = msi_alloc_irte(dev, irq, 1);
2856 ret = setup_msi_irq(dev, desc, irq);
2863 #ifdef CONFIG_INTR_REMAP
2870 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2873 int ret, sub_handle;
2874 struct msi_desc *desc;
2875 unsigned int irq_want;
2877 #ifdef CONFIG_INTR_REMAP
2878 struct intel_iommu *iommu = 0;
2882 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2884 list_for_each_entry(desc, &dev->msi_list, list) {
2885 irq = create_irq_nr(irq_want--);
2888 #ifdef CONFIG_INTR_REMAP
2889 if (!intr_remapping_enabled)
2894 * allocate the consecutive block of IRTE's
2897 index = msi_alloc_irte(dev, irq, nvec);
2903 iommu = map_dev_to_ir(dev);
2909 * setup the mapping between the irq and the IRTE
2910 * base index, the sub_handle pointing to the
2911 * appropriate interrupt remap table entry.
2913 set_irte_irq(irq, iommu, index, sub_handle);
2917 ret = setup_msi_irq(dev, desc, irq);
2929 void arch_teardown_msi_irq(unsigned int irq)
2936 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2938 struct irq_cfg *cfg;
2942 struct irq_desc *desc;
2944 cpus_and(tmp, mask, cpu_online_map);
2945 if (cpus_empty(tmp))
2948 if (assign_irq_vector(irq, mask))
2952 cpus_and(tmp, cfg->domain, mask);
2953 dest = cpu_mask_to_apicid(tmp);
2955 dmar_msi_read(irq, &msg);
2957 msg.data &= ~MSI_DATA_VECTOR_MASK;
2958 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2959 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2960 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2962 dmar_msi_write(irq, &msg);
2963 desc = irq_to_desc(irq);
2964 desc->affinity = mask;
2966 #endif /* CONFIG_SMP */
2968 struct irq_chip dmar_msi_type = {
2970 .unmask = dmar_msi_unmask,
2971 .mask = dmar_msi_mask,
2972 .ack = ack_apic_edge,
2974 .set_affinity = dmar_msi_set_affinity,
2976 .retrigger = ioapic_retrigger_irq,
2979 int arch_setup_dmar_msi(unsigned int irq)
2984 ret = msi_compose_msg(NULL, irq, &msg);
2987 dmar_msi_write(irq, &msg);
2988 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2994 #endif /* CONFIG_PCI_MSI */
2996 * Hypertransport interrupt support
2998 #ifdef CONFIG_HT_IRQ
3002 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3004 struct ht_irq_msg msg;
3005 fetch_ht_irq_msg(irq, &msg);
3007 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3008 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3010 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3011 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3013 write_ht_irq_msg(irq, &msg);
3016 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3018 struct irq_cfg *cfg;
3021 struct irq_desc *desc;
3023 cpus_and(tmp, mask, cpu_online_map);
3024 if (cpus_empty(tmp))
3027 if (assign_irq_vector(irq, mask))
3031 cpus_and(tmp, cfg->domain, mask);
3032 dest = cpu_mask_to_apicid(tmp);
3034 target_ht_irq(irq, dest, cfg->vector);
3035 desc = irq_to_desc(irq);
3036 desc->affinity = mask;
3040 static struct irq_chip ht_irq_chip = {
3042 .mask = mask_ht_irq,
3043 .unmask = unmask_ht_irq,
3044 .ack = ack_apic_edge,
3046 .set_affinity = set_ht_irq_affinity,
3048 .retrigger = ioapic_retrigger_irq,
3051 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3053 struct irq_cfg *cfg;
3058 err = assign_irq_vector(irq, tmp);
3060 struct ht_irq_msg msg;
3064 cpus_and(tmp, cfg->domain, tmp);
3065 dest = cpu_mask_to_apicid(tmp);
3067 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3071 HT_IRQ_LOW_DEST_ID(dest) |
3072 HT_IRQ_LOW_VECTOR(cfg->vector) |
3073 ((INT_DEST_MODE == 0) ?
3074 HT_IRQ_LOW_DM_PHYSICAL :
3075 HT_IRQ_LOW_DM_LOGICAL) |
3076 HT_IRQ_LOW_RQEOI_EDGE |
3077 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3078 HT_IRQ_LOW_MT_FIXED :
3079 HT_IRQ_LOW_MT_ARBITRATED) |
3080 HT_IRQ_LOW_IRQ_MASKED;
3082 write_ht_irq_msg(irq, &msg);
3084 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3085 handle_edge_irq, "edge");
3089 #endif /* CONFIG_HT_IRQ */
3091 /* --------------------------------------------------------------------------
3092 ACPI-based IOAPIC Configuration
3093 -------------------------------------------------------------------------- */
3097 #define IO_APIC_MAX_ID 0xFE
3099 int __init io_apic_get_redir_entries (int ioapic)
3101 union IO_APIC_reg_01 reg_01;
3102 unsigned long flags;
3104 spin_lock_irqsave(&ioapic_lock, flags);
3105 reg_01.raw = io_apic_read(ioapic, 1);
3106 spin_unlock_irqrestore(&ioapic_lock, flags);
3108 return reg_01.bits.entries;
3112 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3114 if (!IO_APIC_IRQ(irq)) {
3115 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3121 * IRQs < 16 are already in the irq_2_pin[] map
3124 add_pin_to_irq(irq, ioapic, pin);
3126 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
3132 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3136 if (skip_ioapic_setup)
3139 for (i = 0; i < mp_irq_entries; i++)
3140 if (mp_irqs[i].mp_irqtype == mp_INT &&
3141 mp_irqs[i].mp_srcbusirq == bus_irq)
3143 if (i >= mp_irq_entries)
3146 *trigger = irq_trigger(i);
3147 *polarity = irq_polarity(i);
3151 #endif /* CONFIG_ACPI */
3154 * This function currently is only a helper for the i386 smp boot process where
3155 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3156 * so mask in all cases should simply be TARGET_CPUS
3159 void __init setup_ioapic_dest(void)
3161 int pin, ioapic, irq, irq_entry;
3162 struct irq_cfg *cfg;
3164 if (skip_ioapic_setup == 1)
3167 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3168 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3169 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3170 if (irq_entry == -1)
3172 irq = pin_2_irq(irq_entry, ioapic, pin);
3174 /* setup_IO_APIC_irqs could fail to get vector for some device
3175 * when you have too many devices, because at that time only boot
3180 setup_IO_APIC_irq(ioapic, pin, irq,
3181 irq_trigger(irq_entry),
3182 irq_polarity(irq_entry));
3183 #ifdef CONFIG_INTR_REMAP
3184 else if (intr_remapping_enabled)
3185 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3188 set_ioapic_affinity_irq(irq, TARGET_CPUS);
3195 #define IOAPIC_RESOURCE_NAME_SIZE 11
3197 static struct resource *ioapic_resources;
3199 static struct resource * __init ioapic_setup_resources(void)
3202 struct resource *res;
3206 if (nr_ioapics <= 0)
3209 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3212 mem = alloc_bootmem(n);
3216 mem += sizeof(struct resource) * nr_ioapics;
3218 for (i = 0; i < nr_ioapics; i++) {
3220 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3221 sprintf(mem, "IOAPIC %u", i);
3222 mem += IOAPIC_RESOURCE_NAME_SIZE;
3226 ioapic_resources = res;
3231 void __init ioapic_init_mappings(void)
3233 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3234 struct resource *ioapic_res;
3237 ioapic_res = ioapic_setup_resources();
3238 for (i = 0; i < nr_ioapics; i++) {
3239 if (smp_found_config) {
3240 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3242 ioapic_phys = (unsigned long)
3243 alloc_bootmem_pages(PAGE_SIZE);
3244 ioapic_phys = __pa(ioapic_phys);
3246 set_fixmap_nocache(idx, ioapic_phys);
3247 apic_printk(APIC_VERBOSE,
3248 "mapped IOAPIC to %016lx (%016lx)\n",
3249 __fix_to_virt(idx), ioapic_phys);
3252 if (ioapic_res != NULL) {
3253 ioapic_res->start = ioapic_phys;
3254 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3260 static int __init ioapic_insert_resources(void)
3263 struct resource *r = ioapic_resources;
3267 "IO APIC resources could be not be allocated.\n");
3271 for (i = 0; i < nr_ioapics; i++) {
3272 insert_resource(&iomem_resource, r);
3279 /* Insert the IO APIC resources after PCI initialization has occured to handle
3280 * IO APICS that are mapped in on a BAR in PCI space. */
3281 late_initcall(ioapic_insert_resources);