arch/x86/kernel/io_apic_32.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/mc146818rtc.h>
  29 #include <linux/compiler.h>
  30 #include <linux/acpi.h>
  31 #include <linux/module.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/pci.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39
  40 #include <asm/io.h>
  41 #include <asm/smp.h>
  42 #include <asm/desc.h>
  43 #include <asm/timer.h>
  44 #include <asm/i8259.h>
  45 #include <asm/nmi.h>
  46 #include <asm/msidef.h>
  47 #include <asm/hypertransport.h>
  48
  49 #include <mach_apic.h>
  50 #include <mach_apicdef.h>
  51
  52 int (*ioapic_renumber_irq)(int ioapic, int irq);
  53 atomic_t irq_mis_count;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 int timer_through_8259 __initdata;
  62
  63 /*
  64  *      Is the SiS APIC rmw bug present ?
  65  *      -1 = don't know, 0 = no, 1 = yes
  66  */
  67 int sis_apic_bug = -1;
  68
  69 /*
  70  * # of IRQ routing registers
  71  */
  72 int nr_ioapic_registers[MAX_IO_APICS];
  73
  74 /* I/O APIC entries */
  75 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
  76 int nr_ioapics;
  77
  78 /* MP IRQ source entries */
  79 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
  80
  81 /* # of MP IRQ source entries */
  82 int mp_irq_entries;
  83
  84 static int disable_timer_pin_1 __initdata;
  85
  86 /*
  87  * Rough estimation of how many shared IRQs there are, can
  88  * be changed anytime.
  89  */
  90 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  91 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  92
  93 /*
  94  * This is performance-critical, we want to do it O(1)
  95  *
  96  * the indexing order of this array favors 1:1 mappings
  97  * between pins and IRQs.
  98  */
  99
 100 static struct irq_pin_list {
 101         int apic, pin, next;
 102 } irq_2_pin[PIN_MAP_SIZE];
 103
 104 struct io_apic {
 105         unsigned int index;
 106         unsigned int unused[3];
 107         unsigned int data;
 108 };
 109
 110 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 111 {
 112         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 113                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 114 }
 115
 116 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 117 {
 118         struct io_apic __iomem *io_apic = io_apic_base(apic);
 119         writel(reg, &io_apic->index);
 120         return readl(&io_apic->data);
 121 }
 122
 123 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 124 {
 125         struct io_apic __iomem *io_apic = io_apic_base(apic);
 126         writel(reg, &io_apic->index);
 127         writel(value, &io_apic->data);
 128 }
 129
 130 /*
 131  * Re-write a value: to be used for read-modify-write
 132  * cycles where the read already set up the index register.
 133  *
 134  * Older SiS APIC requires we rewrite the index register
 135  */
 136 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 137 {
 138         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
 139         if (sis_apic_bug)
 140                 writel(reg, &io_apic->index);
 141         writel(value, &io_apic->data);
 142 }
 143
 144 union entry_union {
 145         struct { u32 w1, w2; };
 146         struct IO_APIC_route_entry entry;
 147 };
 148
 149 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 150 {
 151         union entry_union eu;
 152         unsigned long flags;
 153         spin_lock_irqsave(&ioapic_lock, flags);
 154         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 155         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 156         spin_unlock_irqrestore(&ioapic_lock, flags);
 157         return eu.entry;
 158 }
 159
 160 /*
 161  * When we write a new IO APIC routing entry, we need to write the high
 162  * word first! If the mask bit in the low word is clear, we will enable
 163  * the interrupt, and we need to make sure the entry is fully populated
 164  * before that happens.
 165  */
 166 static void
 167 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 168 {
 169         union entry_union eu;
 170         eu.entry = e;
 171         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 172         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 173 }
 174
 175 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 176 {
 177         unsigned long flags;
 178         spin_lock_irqsave(&ioapic_lock, flags);
 179         __ioapic_write_entry(apic, pin, e);
 180         spin_unlock_irqrestore(&ioapic_lock, flags);
 181 }
 182
 183 /*
 184  * When we mask an IO APIC routing entry, we need to write the low
 185  * word first, in order to set the mask bit before we change the
 186  * high bits!
 187  */
 188 static void ioapic_mask_entry(int apic, int pin)
 189 {
 190         unsigned long flags;
 191         union entry_union eu = { .entry.mask = 1 };
 192
 193         spin_lock_irqsave(&ioapic_lock, flags);
 194         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 195         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 196         spin_unlock_irqrestore(&ioapic_lock, flags);
 197 }
 198
 199 /*
 200  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 201  * shared ISA-space IRQs, so we have to support them. We are super
 202  * fast in the common case, and fast for shared ISA-space IRQs.
 203  */
 204 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 205 {
 206         static int first_free_entry = NR_IRQS;
 207         struct irq_pin_list *entry = irq_2_pin + irq;
 208
 209         while (entry->next)
 210                 entry = irq_2_pin + entry->next;
 211
 212         if (entry->pin != -1) {
 213                 entry->next = first_free_entry;
 214                 entry = irq_2_pin + entry->next;
 215                 if (++first_free_entry >= PIN_MAP_SIZE)
 216                         panic("io_apic.c: whoops");
 217         }
 218         entry->apic = apic;
 219         entry->pin = pin;
 220 }
 221
 222 /*
 223  * Reroute an IRQ to a different pin.
 224  */
 225 static void __init replace_pin_at_irq(unsigned int irq,
 226                                       int oldapic, int oldpin,
 227                                       int newapic, int newpin)
 228 {
 229         struct irq_pin_list *entry = irq_2_pin + irq;
 230
 231         while (1) {
 232                 if (entry->apic == oldapic && entry->pin == oldpin) {
 233                         entry->apic = newapic;
 234                         entry->pin = newpin;
 235                 }
 236                 if (!entry->next)
 237                         break;
 238                 entry = irq_2_pin + entry->next;
 239         }
 240 }
 241
 242 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 243 {
 244         struct irq_pin_list *entry = irq_2_pin + irq;
 245         unsigned int pin, reg;
 246
 247         for (;;) {
 248                 pin = entry->pin;
 249                 if (pin == -1)
 250                         break;
 251                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 252                 reg &= ~disable;
 253                 reg |= enable;
 254                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 255                 if (!entry->next)
 256                         break;
 257                 entry = irq_2_pin + entry->next;
 258         }
 259 }
 260
 261 /* mask = 1 */
 262 static void __mask_IO_APIC_irq (unsigned int irq)
 263 {
 264         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
 265 }
 266
 267 /* mask = 0 */
 268 static void __unmask_IO_APIC_irq (unsigned int irq)
 269 {
 270         __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
 271 }
 272
 273 /* mask = 1, trigger = 0 */
 274 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 275 {
 276         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
 277                                 IO_APIC_REDIR_LEVEL_TRIGGER);
 278 }
 279
 280 /* mask = 0, trigger = 1 */
 281 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 282 {
 283         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
 284                                 IO_APIC_REDIR_MASKED);
 285 }
 286
 287 static void mask_IO_APIC_irq (unsigned int irq)
 288 {
 289         unsigned long flags;
 290
 291         spin_lock_irqsave(&ioapic_lock, flags);
 292         __mask_IO_APIC_irq(irq);
 293         spin_unlock_irqrestore(&ioapic_lock, flags);
 294 }
 295
 296 static void unmask_IO_APIC_irq (unsigned int irq)
 297 {
 298         unsigned long flags;
 299
 300         spin_lock_irqsave(&ioapic_lock, flags);
 301         __unmask_IO_APIC_irq(irq);
 302         spin_unlock_irqrestore(&ioapic_lock, flags);
 303 }
 304
 305 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 306 {
 307         struct IO_APIC_route_entry entry;
 308
 309         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 310         entry = ioapic_read_entry(apic, pin);
 311         if (entry.delivery_mode == dest_SMI)
 312                 return;
 313
 314         /*
 315          * Disable it in the IO-APIC irq-routing table:
 316          */
 317         ioapic_mask_entry(apic, pin);
 318 }
 319
 320 static void clear_IO_APIC (void)
 321 {
 322         int apic, pin;
 323
 324         for (apic = 0; apic < nr_ioapics; apic++)
 325                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 326                         clear_IO_APIC_pin(apic, pin);
 327 }
 328
 329 #ifdef CONFIG_SMP
 330 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 331 {
 332         unsigned long flags;
 333         int pin;
 334         struct irq_pin_list *entry = irq_2_pin + irq;
 335         unsigned int apicid_value;
 336         cpumask_t tmp;
 337
 338         cpus_and(tmp, cpumask, cpu_online_map);
 339         if (cpus_empty(tmp))
 340                 tmp = TARGET_CPUS;
 341
 342         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 343
 344         apicid_value = cpu_mask_to_apicid(cpumask);
 345         /* Prepare to do the io_apic_write */
 346         apicid_value = apicid_value << 24;
 347         spin_lock_irqsave(&ioapic_lock, flags);
 348         for (;;) {
 349                 pin = entry->pin;
 350                 if (pin == -1)
 351                         break;
 352                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 353                 if (!entry->next)
 354                         break;
 355                 entry = irq_2_pin + entry->next;
 356         }
 357         irq_desc[irq].affinity = cpumask;
 358         spin_unlock_irqrestore(&ioapic_lock, flags);
 359 }
 360
 361 #if defined(CONFIG_IRQBALANCE)
 362 # include <asm/processor.h>     /* kernel_thread() */
 363 # include <linux/kernel_stat.h> /* kstat */
 364 # include <linux/slab.h>                /* kmalloc() */
 365 # include <linux/timer.h>
 366
 367 #define IRQBALANCE_CHECK_ARCH -999
 368 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 369 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 370 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 371 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 372
 373 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 374 static int physical_balance __read_mostly;
 375 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 376
 377 static struct irq_cpu_info {
 378         unsigned long * last_irq;
 379         unsigned long * irq_delta;
 380         unsigned long irq;
 381 } irq_cpu_data[NR_CPUS];
 382
 383 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 384 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 385 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 386
 387 #define IDLE_ENOUGH(cpu,now) \
 388         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 389
 390 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 391
 392 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
 393
 394 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 395         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 396 };
 397
 398 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 399 {
 400         balance_irq_affinity[irq] = mask;
 401 }
 402
 403 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 404                         unsigned long now, int direction)
 405 {
 406         int search_idle = 1;
 407         int cpu = curr_cpu;
 408
 409         goto inside;
 410
 411         do {
 412                 if (unlikely(cpu == curr_cpu))
 413                         search_idle = 0;
 414 inside:
 415                 if (direction == 1) {
 416                         cpu++;
 417                         if (cpu >= NR_CPUS)
 418                                 cpu = 0;
 419                 } else {
 420                         cpu--;
 421                         if (cpu == -1)
 422                                 cpu = NR_CPUS-1;
 423                 }
 424         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 425                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 426
 427         return cpu;
 428 }
 429
 430 static inline void balance_irq(int cpu, int irq)
 431 {
 432         unsigned long now = jiffies;
 433         cpumask_t allowed_mask;
 434         unsigned int new_cpu;
 435
 436         if (irqbalance_disabled)
 437                 return;
 438
 439         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 440         new_cpu = move(cpu, allowed_mask, now, 1);
 441         if (cpu != new_cpu) {
 442                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 443         }
 444 }
 445
 446 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 447 {
 448         int i, j;
 449
 450         for_each_online_cpu(i) {
 451                 for (j = 0; j < NR_IRQS; j++) {
 452                         if (!irq_desc[j].action)
 453                                 continue;
 454                         /* Is it a significant load ?  */
 455                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 456                                                 useful_load_threshold)
 457                                 continue;
 458                         balance_irq(i, j);
 459                 }
 460         }
 461         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 462                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 463         return;
 464 }
 465
 466 static void do_irq_balance(void)
 467 {
 468         int i, j;
 469         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 470         unsigned long move_this_load = 0;
 471         int max_loaded = 0, min_loaded = 0;
 472         int load;
 473         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 474         int selected_irq;
 475         int tmp_loaded, first_attempt = 1;
 476         unsigned long tmp_cpu_irq;
 477         unsigned long imbalance = 0;
 478         cpumask_t allowed_mask, target_cpu_mask, tmp;
 479
 480         for_each_possible_cpu(i) {
 481                 int package_index;
 482                 CPU_IRQ(i) = 0;
 483                 if (!cpu_online(i))
 484                         continue;
 485                 package_index = CPU_TO_PACKAGEINDEX(i);
 486                 for (j = 0; j < NR_IRQS; j++) {
 487                         unsigned long value_now, delta;
 488                         /* Is this an active IRQ or balancing disabled ? */
 489                         if (!irq_desc[j].action || irq_balancing_disabled(j))
 490                                 continue;
 491                         if ( package_index == i )
 492                                 IRQ_DELTA(package_index,j) = 0;
 493                         /* Determine the total count per processor per IRQ */
 494                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 495
 496                         /* Determine the activity per processor per IRQ */
 497                         delta = value_now - LAST_CPU_IRQ(i,j);
 498
 499                         /* Update last_cpu_irq[][] for the next time */
 500                         LAST_CPU_IRQ(i,j) = value_now;
 501
 502                         /* Ignore IRQs whose rate is less than the clock */
 503                         if (delta < useful_load_threshold)
 504                                 continue;
 505                         /* update the load for the processor or package total */
 506                         IRQ_DELTA(package_index,j) += delta;
 507
 508                         /* Keep track of the higher numbered sibling as well */
 509                         if (i != package_index)
 510                                 CPU_IRQ(i) += delta;
 511                         /*
 512                          * We have sibling A and sibling B in the package
 513                          *
 514                          * cpu_irq[A] = load for cpu A + load for cpu B
 515                          * cpu_irq[B] = load for cpu B
 516                          */
 517                         CPU_IRQ(package_index) += delta;
 518                 }
 519         }
 520         /* Find the least loaded processor package */
 521         for_each_online_cpu(i) {
 522                 if (i != CPU_TO_PACKAGEINDEX(i))
 523                         continue;
 524                 if (min_cpu_irq > CPU_IRQ(i)) {
 525                         min_cpu_irq = CPU_IRQ(i);
 526                         min_loaded = i;
 527                 }
 528         }
 529         max_cpu_irq = ULONG_MAX;
 530
 531 tryanothercpu:
 532         /* Look for heaviest loaded processor.
 533          * We may come back to get the next heaviest loaded processor.
 534          * Skip processors with trivial loads.
 535          */
 536         tmp_cpu_irq = 0;
 537         tmp_loaded = -1;
 538         for_each_online_cpu(i) {
 539                 if (i != CPU_TO_PACKAGEINDEX(i))
 540                         continue;
 541                 if (max_cpu_irq <= CPU_IRQ(i))
 542                         continue;
 543                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 544                         tmp_cpu_irq = CPU_IRQ(i);
 545                         tmp_loaded = i;
 546                 }
 547         }
 548
 549         if (tmp_loaded == -1) {
 550          /* In the case of small number of heavy interrupt sources,
 551           * loading some of the cpus too much. We use Ingo's original
 552           * approach to rotate them around.
 553           */
 554                 if (!first_attempt && imbalance >= useful_load_threshold) {
 555                         rotate_irqs_among_cpus(useful_load_threshold);
 556                         return;
 557                 }
 558                 goto not_worth_the_effort;
 559         }
 560
 561         first_attempt = 0;              /* heaviest search */
 562         max_cpu_irq = tmp_cpu_irq;      /* load */
 563         max_loaded = tmp_loaded;        /* processor */
 564         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 565
 566         /* if imbalance is less than approx 10% of max load, then
 567          * observe diminishing returns action. - quit
 568          */
 569         if (imbalance < (max_cpu_irq >> 3))
 570                 goto not_worth_the_effort;
 571
 572 tryanotherirq:
 573         /* if we select an IRQ to move that can't go where we want, then
 574          * see if there is another one to try.
 575          */
 576         move_this_load = 0;
 577         selected_irq = -1;
 578         for (j = 0; j < NR_IRQS; j++) {
 579                 /* Is this an active IRQ? */
 580                 if (!irq_desc[j].action)
 581                         continue;
 582                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 583                         continue;
 584                 /* Try to find the IRQ that is closest to the imbalance
 585                  * without going over.
 586                  */
 587                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 588                         move_this_load = IRQ_DELTA(max_loaded,j);
 589                         selected_irq = j;
 590                 }
 591         }
 592         if (selected_irq == -1) {
 593                 goto tryanothercpu;
 594         }
 595
 596         imbalance = move_this_load;
 597
 598         /* For physical_balance case, we accumulated both load
 599          * values in the one of the siblings cpu_irq[],
 600          * to use the same code for physical and logical processors
 601          * as much as possible.
 602          *
 603          * NOTE: the cpu_irq[] array holds the sum of the load for
 604          * sibling A and sibling B in the slot for the lowest numbered
 605          * sibling (A), _AND_ the load for sibling B in the slot for
 606          * the higher numbered sibling.
 607          *
 608          * We seek the least loaded sibling by making the comparison
 609          * (A+B)/2 vs B
 610          */
 611         load = CPU_IRQ(min_loaded) >> 1;
 612         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
 613                 if (load > CPU_IRQ(j)) {
 614                         /* This won't change cpu_sibling_map[min_loaded] */
 615                         load = CPU_IRQ(j);
 616                         min_loaded = j;
 617                 }
 618         }
 619
 620         cpus_and(allowed_mask,
 621                 cpu_online_map,
 622                 balance_irq_affinity[selected_irq]);
 623         target_cpu_mask = cpumask_of_cpu(min_loaded);
 624         cpus_and(tmp, target_cpu_mask, allowed_mask);
 625
 626         if (!cpus_empty(tmp)) {
 627                 /* mark for change destination */
 628                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 629
 630                 /* Since we made a change, come back sooner to
 631                  * check for more variation.
 632                  */
 633                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 634                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 635                 return;
 636         }
 637         goto tryanotherirq;
 638
 639 not_worth_the_effort:
 640         /*
 641          * if we did not find an IRQ to move, then adjust the time interval
 642          * upward
 643          */
 644         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 645                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 646         return;
 647 }
 648
 649 static int balanced_irq(void *unused)
 650 {
 651         int i;
 652         unsigned long prev_balance_time = jiffies;
 653         long time_remaining = balanced_irq_interval;
 654
 655         /* push everything to CPU 0 to give us a starting point.  */
 656         for (i = 0 ; i < NR_IRQS ; i++) {
 657                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 658                 set_pending_irq(i, cpumask_of_cpu(0));
 659         }
 660
 661         set_freezable();
 662         for ( ; ; ) {
 663                 time_remaining = schedule_timeout_interruptible(time_remaining);
 664                 try_to_freeze();
 665                 if (time_after(jiffies,
 666                                 prev_balance_time+balanced_irq_interval)) {
 667                         preempt_disable();
 668                         do_irq_balance();
 669                         prev_balance_time = jiffies;
 670                         time_remaining = balanced_irq_interval;
 671                         preempt_enable();
 672                 }
 673         }
 674         return 0;
 675 }
 676
 677 static int __init balanced_irq_init(void)
 678 {
 679         int i;
 680         struct cpuinfo_x86 *c;
 681         cpumask_t tmp;
 682
 683         cpus_shift_right(tmp, cpu_online_map, 2);
 684         c = &boot_cpu_data;
 685         /* When not overwritten by the command line ask subarchitecture. */
 686         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 687                 irqbalance_disabled = NO_BALANCE_IRQ;
 688         if (irqbalance_disabled)
 689                 return 0;
 690
 691          /* disable irqbalance completely if there is only one processor online */
 692         if (num_online_cpus() < 2) {
 693                 irqbalance_disabled = 1;
 694                 return 0;
 695         }
 696         /*
 697          * Enable physical balance only if more than 1 physical processor
 698          * is present
 699          */
 700         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 701                 physical_balance = 1;
 702
 703         for_each_online_cpu(i) {
 704                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 705                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 706                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 707                         printk(KERN_ERR "balanced_irq_init: out of memory");
 708                         goto failed;
 709                 }
 710                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 711                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 712         }
 713
 714         printk(KERN_INFO "Starting balanced_irq\n");
 715         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
 716                 return 0;
 717         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 718 failed:
 719         for_each_possible_cpu(i) {
 720                 kfree(irq_cpu_data[i].irq_delta);
 721                 irq_cpu_data[i].irq_delta = NULL;
 722                 kfree(irq_cpu_data[i].last_irq);
 723                 irq_cpu_data[i].last_irq = NULL;
 724         }
 725         return 0;
 726 }
 727
 728 int __devinit irqbalance_disable(char *str)
 729 {
 730         irqbalance_disabled = 1;
 731         return 1;
 732 }
 733
 734 __setup("noirqbalance", irqbalance_disable);
 735
 736 late_initcall(balanced_irq_init);
 737 #endif /* CONFIG_IRQBALANCE */
 738 #endif /* CONFIG_SMP */
 739
 740 #ifndef CONFIG_SMP
 741 void send_IPI_self(int vector)
 742 {
 743         unsigned int cfg;
 744
 745         /*
 746          * Wait for idle.
 747          */
 748         apic_wait_icr_idle();
 749         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 750         /*
 751          * Send the IPI. The write to APIC_ICR fires this off.
 752          */
 753         apic_write_around(APIC_ICR, cfg);
 754 }
 755 #endif /* !CONFIG_SMP */
 756
 757
 758 /*
 759  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 760  * specific CPU-side IRQs.
 761  */
 762
 763 #define MAX_PIRQS 8
 764 static int pirq_entries [MAX_PIRQS];
 765 static int pirqs_enabled;
 766 int skip_ioapic_setup;
 767
 768 static int __init ioapic_pirq_setup(char *str)
 769 {
 770         int i, max;
 771         int ints[MAX_PIRQS+1];
 772
 773         get_options(str, ARRAY_SIZE(ints), ints);
 774
 775         for (i = 0; i < MAX_PIRQS; i++)
 776                 pirq_entries[i] = -1;
 777
 778         pirqs_enabled = 1;
 779         apic_printk(APIC_VERBOSE, KERN_INFO
 780                         "PIRQ redirection, working around broken MP-BIOS.\n");
 781         max = MAX_PIRQS;
 782         if (ints[0] < MAX_PIRQS)
 783                 max = ints[0];
 784
 785         for (i = 0; i < max; i++) {
 786                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 787                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 788                 /*
 789                  * PIRQs are mapped upside down, usually.
 790                  */
 791                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 792         }
 793         return 1;
 794 }
 795
 796 __setup("pirq=", ioapic_pirq_setup);
 797
 798 /*
 799  * Find the IRQ entry number of a certain pin.
 800  */
 801 static int find_irq_entry(int apic, int pin, int type)
 802 {
 803         int i;
 804
 805         for (i = 0; i < mp_irq_entries; i++)
 806                 if (mp_irqs[i].mpc_irqtype == type &&
 807                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 808                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 809                     mp_irqs[i].mpc_dstirq == pin)
 810                         return i;
 811
 812         return -1;
 813 }
 814
 815 /*
 816  * Find the pin to which IRQ[irq] (ISA) is connected
 817  */
 818 static int __init find_isa_irq_pin(int irq, int type)
 819 {
 820         int i;
 821
 822         for (i = 0; i < mp_irq_entries; i++) {
 823                 int lbus = mp_irqs[i].mpc_srcbus;
 824
 825                 if (test_bit(lbus, mp_bus_not_pci) &&
 826                     (mp_irqs[i].mpc_irqtype == type) &&
 827                     (mp_irqs[i].mpc_srcbusirq == irq))
 828
 829                         return mp_irqs[i].mpc_dstirq;
 830         }
 831         return -1;
 832 }
 833
 834 static int __init find_isa_irq_apic(int irq, int type)
 835 {
 836         int i;
 837
 838         for (i = 0; i < mp_irq_entries; i++) {
 839                 int lbus = mp_irqs[i].mpc_srcbus;
 840
 841                 if (test_bit(lbus, mp_bus_not_pci) &&
 842                     (mp_irqs[i].mpc_irqtype == type) &&
 843                     (mp_irqs[i].mpc_srcbusirq == irq))
 844                         break;
 845         }
 846         if (i < mp_irq_entries) {
 847                 int apic;
 848                 for(apic = 0; apic < nr_ioapics; apic++) {
 849                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 850                                 return apic;
 851                 }
 852         }
 853
 854         return -1;
 855 }
 856
 857 /*
 858  * Find a specific PCI IRQ entry.
 859  * Not an __init, possibly needed by modules
 860  */
 861 static int pin_2_irq(int idx, int apic, int pin);
 862
 863 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 864 {
 865         int apic, i, best_guess = -1;
 866
 867         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 868                 "slot:%d, pin:%d.\n", bus, slot, pin);
 869         if (mp_bus_id_to_pci_bus[bus] == -1) {
 870                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 871                 return -1;
 872         }
 873         for (i = 0; i < mp_irq_entries; i++) {
 874                 int lbus = mp_irqs[i].mpc_srcbus;
 875
 876                 for (apic = 0; apic < nr_ioapics; apic++)
 877                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 878                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 879                                 break;
 880
 881                 if (!test_bit(lbus, mp_bus_not_pci) &&
 882                     !mp_irqs[i].mpc_irqtype &&
 883                     (bus == lbus) &&
 884                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 885                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 886
 887                         if (!(apic || IO_APIC_IRQ(irq)))
 888                                 continue;
 889
 890                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 891                                 return irq;
 892                         /*
 893                          * Use the first all-but-pin matching entry as a
 894                          * best-guess fuzzy result for broken mptables.
 895                          */
 896                         if (best_guess < 0)
 897                                 best_guess = irq;
 898                 }
 899         }
 900         return best_guess;
 901 }
 902 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 903
 904 /*
 905  * This function currently is only a helper for the i386 smp boot process where
 906  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 907  * so mask in all cases should simply be TARGET_CPUS
 908  */
 909 #ifdef CONFIG_SMP
 910 void __init setup_ioapic_dest(void)
 911 {
 912         int pin, ioapic, irq, irq_entry;
 913
 914         if (skip_ioapic_setup == 1)
 915                 return;
 916
 917         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 918                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 919                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 920                         if (irq_entry == -1)
 921                                 continue;
 922                         irq = pin_2_irq(irq_entry, ioapic, pin);
 923                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 924                 }
 925
 926         }
 927 }
 928 #endif
 929
 930 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
 931 /*
 932  * EISA Edge/Level control register, ELCR
 933  */
 934 static int EISA_ELCR(unsigned int irq)
 935 {
 936         if (irq < 16) {
 937                 unsigned int port = 0x4d0 + (irq >> 3);
 938                 return (inb(port) >> (irq & 7)) & 1;
 939         }
 940         apic_printk(APIC_VERBOSE, KERN_INFO
 941                         "Broken MPtable reports ISA irq %d\n", irq);
 942         return 0;
 943 }
 944 #endif
 945
 946 /* ISA interrupts are always polarity zero edge triggered,
 947  * when listed as conforming in the MP table. */
 948
 949 #define default_ISA_trigger(idx)        (0)
 950 #define default_ISA_polarity(idx)       (0)
 951
 952 /* EISA interrupts are always polarity zero and can be edge or level
 953  * trigger depending on the ELCR value.  If an interrupt is listed as
 954  * EISA conforming in the MP table, that means its trigger type must
 955  * be read in from the ELCR */
 956
 957 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 958 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
 959
 960 /* PCI interrupts are always polarity one level triggered,
 961  * when listed as conforming in the MP table. */
 962
 963 #define default_PCI_trigger(idx)        (1)
 964 #define default_PCI_polarity(idx)       (1)
 965
 966 /* MCA interrupts are always polarity zero level triggered,
 967  * when listed as conforming in the MP table. */
 968
 969 #define default_MCA_trigger(idx)        (1)
 970 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
 971
 972 static int MPBIOS_polarity(int idx)
 973 {
 974         int bus = mp_irqs[idx].mpc_srcbus;
 975         int polarity;
 976
 977         /*
 978          * Determine IRQ line polarity (high active or low active):
 979          */
 980         switch (mp_irqs[idx].mpc_irqflag & 3)
 981         {
 982                 case 0: /* conforms, ie. bus-type dependent polarity */
 983                 {
 984                         polarity = test_bit(bus, mp_bus_not_pci)?
 985                                 default_ISA_polarity(idx):
 986                                 default_PCI_polarity(idx);
 987                         break;
 988                 }
 989                 case 1: /* high active */
 990                 {
 991                         polarity = 0;
 992                         break;
 993                 }
 994                 case 2: /* reserved */
 995                 {
 996                         printk(KERN_WARNING "broken BIOS!!\n");
 997                         polarity = 1;
 998                         break;
 999                 }
1000                 case 3: /* low active */
1001                 {
1002                         polarity = 1;
1003                         break;
1004                 }
1005                 default: /* invalid */
1006                 {
1007                         printk(KERN_WARNING "broken BIOS!!\n");
1008                         polarity = 1;
1009                         break;
1010                 }
1011         }
1012         return polarity;
1013 }
1014
1015 static int MPBIOS_trigger(int idx)
1016 {
1017         int bus = mp_irqs[idx].mpc_srcbus;
1018         int trigger;
1019
1020         /*
1021          * Determine IRQ trigger mode (edge or level sensitive):
1022          */
1023         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1024         {
1025                 case 0: /* conforms, ie. bus-type dependent */
1026                 {
1027                         trigger = test_bit(bus, mp_bus_not_pci)?
1028                                         default_ISA_trigger(idx):
1029                                         default_PCI_trigger(idx);
1030 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1031                         switch (mp_bus_id_to_type[bus])
1032                         {
1033                                 case MP_BUS_ISA: /* ISA pin */
1034                                 {
1035                                         /* set before the switch */
1036                                         break;
1037                                 }
1038                                 case MP_BUS_EISA: /* EISA pin */
1039                                 {
1040                                         trigger = default_EISA_trigger(idx);
1041                                         break;
1042                                 }
1043                                 case MP_BUS_PCI: /* PCI pin */
1044                                 {
1045                                         /* set before the switch */
1046                                         break;
1047                                 }
1048                                 case MP_BUS_MCA: /* MCA pin */
1049                                 {
1050                                         trigger = default_MCA_trigger(idx);
1051                                         break;
1052                                 }
1053                                 default:
1054                                 {
1055                                         printk(KERN_WARNING "broken BIOS!!\n");
1056                                         trigger = 1;
1057                                         break;
1058                                 }
1059                         }
1060 #endif
1061                         break;
1062                 }
1063                 case 1: /* edge */
1064                 {
1065                         trigger = 0;
1066                         break;
1067                 }
1068                 case 2: /* reserved */
1069                 {
1070                         printk(KERN_WARNING "broken BIOS!!\n");
1071                         trigger = 1;
1072                         break;
1073                 }
1074                 case 3: /* level */
1075                 {
1076                         trigger = 1;
1077                         break;
1078                 }
1079                 default: /* invalid */
1080                 {
1081                         printk(KERN_WARNING "broken BIOS!!\n");
1082                         trigger = 0;
1083                         break;
1084                 }
1085         }
1086         return trigger;
1087 }
1088
1089 static inline int irq_polarity(int idx)
1090 {
1091         return MPBIOS_polarity(idx);
1092 }
1093
1094 static inline int irq_trigger(int idx)
1095 {
1096         return MPBIOS_trigger(idx);
1097 }
1098
1099 static int pin_2_irq(int idx, int apic, int pin)
1100 {
1101         int irq, i;
1102         int bus = mp_irqs[idx].mpc_srcbus;
1103
1104         /*
1105          * Debugging check, we are in big trouble if this message pops up!
1106          */
1107         if (mp_irqs[idx].mpc_dstirq != pin)
1108                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1109
1110         if (test_bit(bus, mp_bus_not_pci))
1111                 irq = mp_irqs[idx].mpc_srcbusirq;
1112         else {
1113                 /*
1114                  * PCI IRQs are mapped in order
1115                  */
1116                 i = irq = 0;
1117                 while (i < apic)
1118                         irq += nr_ioapic_registers[i++];
1119                 irq += pin;
1120
1121                 /*
1122                  * For MPS mode, so far only needed by ES7000 platform
1123                  */
1124                 if (ioapic_renumber_irq)
1125                         irq = ioapic_renumber_irq(apic, irq);
1126         }
1127
1128         /*
1129          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1130          */
1131         if ((pin >= 16) && (pin <= 23)) {
1132                 if (pirq_entries[pin-16] != -1) {
1133                         if (!pirq_entries[pin-16]) {
1134                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1135                                                 "disabling PIRQ%d\n", pin-16);
1136                         } else {
1137                                 irq = pirq_entries[pin-16];
1138                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1139                                                 "using PIRQ%d -> IRQ %d\n",
1140                                                 pin-16, irq);
1141                         }
1142                 }
1143         }
1144         return irq;
1145 }
1146
1147 static inline int IO_APIC_irq_trigger(int irq)
1148 {
1149         int apic, idx, pin;
1150
1151         for (apic = 0; apic < nr_ioapics; apic++) {
1152                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1153                         idx = find_irq_entry(apic,pin,mp_INT);
1154                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1155                                 return irq_trigger(idx);
1156                 }
1157         }
1158         /*
1159          * nonexistent IRQs are edge default
1160          */
1161         return 0;
1162 }
1163
1164 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1165 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1166
1167 static int __assign_irq_vector(int irq)
1168 {
1169         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1170         int vector, offset;
1171
1172         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1173
1174         if (irq_vector[irq] > 0)
1175                 return irq_vector[irq];
1176
1177         vector = current_vector;
1178         offset = current_offset;
1179 next:
1180         vector += 8;
1181         if (vector >= FIRST_SYSTEM_VECTOR) {
1182                 offset = (offset + 1) % 8;
1183                 vector = FIRST_DEVICE_VECTOR + offset;
1184         }
1185         if (vector == current_vector)
1186                 return -ENOSPC;
1187         if (test_and_set_bit(vector, used_vectors))
1188                 goto next;
1189
1190         current_vector = vector;
1191         current_offset = offset;
1192         irq_vector[irq] = vector;
1193
1194         return vector;
1195 }
1196
1197 static int assign_irq_vector(int irq)
1198 {
1199         unsigned long flags;
1200         int vector;
1201
1202         spin_lock_irqsave(&vector_lock, flags);
1203         vector = __assign_irq_vector(irq);
1204         spin_unlock_irqrestore(&vector_lock, flags);
1205
1206         return vector;
1207 }
1208 static struct irq_chip ioapic_chip;
1209
1210 #define IOAPIC_AUTO     -1
1211 #define IOAPIC_EDGE     0
1212 #define IOAPIC_LEVEL    1
1213
1214 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1215 {
1216         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1217             trigger == IOAPIC_LEVEL) {
1218                 irq_desc[irq].status |= IRQ_LEVEL;
1219                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1220                                          handle_fasteoi_irq, "fasteoi");
1221         } else {
1222                 irq_desc[irq].status &= ~IRQ_LEVEL;
1223                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1224                                          handle_edge_irq, "edge");
1225         }
1226         set_intr_gate(vector, interrupt[irq]);
1227 }
1228
1229 static void __init setup_IO_APIC_irqs(void)
1230 {
1231         struct IO_APIC_route_entry entry;
1232         int apic, pin, idx, irq, first_notcon = 1, vector;
1233
1234         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1235
1236         for (apic = 0; apic < nr_ioapics; apic++) {
1237         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1238
1239                 /*
1240                  * add it to the IO-APIC irq-routing table:
1241                  */
1242                 memset(&entry,0,sizeof(entry));
1243
1244                 entry.delivery_mode = INT_DELIVERY_MODE;
1245                 entry.dest_mode = INT_DEST_MODE;
1246                 entry.mask = 0;                         /* enable IRQ */
1247                 entry.dest.logical.logical_dest =
1248                                         cpu_mask_to_apicid(TARGET_CPUS);
1249
1250                 idx = find_irq_entry(apic,pin,mp_INT);
1251                 if (idx == -1) {
1252                         if (first_notcon) {
1253                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1254                                                 " IO-APIC (apicid-pin) %d-%d",
1255                                                 mp_ioapics[apic].mpc_apicid,
1256                                                 pin);
1257                                 first_notcon = 0;
1258                         } else
1259                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1260                                         mp_ioapics[apic].mpc_apicid, pin);
1261                         continue;
1262                 }
1263
1264                 if (!first_notcon) {
1265                         apic_printk(APIC_VERBOSE, " not connected.\n");
1266                         first_notcon = 1;
1267                 }
1268
1269                 entry.trigger = irq_trigger(idx);
1270                 entry.polarity = irq_polarity(idx);
1271
1272                 if (irq_trigger(idx)) {
1273                         entry.trigger = 1;
1274                         entry.mask = 1;
1275                 }
1276
1277                 irq = pin_2_irq(idx, apic, pin);
1278                 /*
1279                  * skip adding the timer int on secondary nodes, which causes
1280                  * a small but painful rift in the time-space continuum
1281                  */
1282                 if (multi_timer_check(apic, irq))
1283                         continue;
1284                 else
1285                         add_pin_to_irq(irq, apic, pin);
1286
1287                 if (!apic && !IO_APIC_IRQ(irq))
1288                         continue;
1289
1290                 if (IO_APIC_IRQ(irq)) {
1291                         vector = assign_irq_vector(irq);
1292                         entry.vector = vector;
1293                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1294
1295                         if (!apic && (irq < 16))
1296                                 disable_8259A_irq(irq);
1297                 }
1298                 ioapic_write_entry(apic, pin, entry);
1299         }
1300         }
1301
1302         if (!first_notcon)
1303                 apic_printk(APIC_VERBOSE, " not connected.\n");
1304 }
1305
1306 /*
1307  * Set up the timer pin, possibly with the 8259A-master behind.
1308  */
1309 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1310                                         int vector)
1311 {
1312         struct IO_APIC_route_entry entry;
1313
1314         memset(&entry,0,sizeof(entry));
1315
1316         /*
1317          * We use logical delivery to get the timer IRQ
1318          * to the first CPU.
1319          */
1320         entry.dest_mode = INT_DEST_MODE;
1321         entry.mask = 1;                                 /* mask IRQ now */
1322         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1323         entry.delivery_mode = INT_DELIVERY_MODE;
1324         entry.polarity = 0;
1325         entry.trigger = 0;
1326         entry.vector = vector;
1327
1328         /*
1329          * The timer IRQ doesn't have to know that behind the
1330          * scene we may have a 8259A-master in AEOI mode ...
1331          */
1332         ioapic_register_intr(0, vector, IOAPIC_EDGE);
1333
1334         /*
1335          * Add it to the IO-APIC irq-routing table:
1336          */
1337         ioapic_write_entry(apic, pin, entry);
1338 }
1339
1340 void __init print_IO_APIC(void)
1341 {
1342         int apic, i;
1343         union IO_APIC_reg_00 reg_00;
1344         union IO_APIC_reg_01 reg_01;
1345         union IO_APIC_reg_02 reg_02;
1346         union IO_APIC_reg_03 reg_03;
1347         unsigned long flags;
1348
1349         if (apic_verbosity == APIC_QUIET)
1350                 return;
1351
1352         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1353         for (i = 0; i < nr_ioapics; i++)
1354                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1355                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1356
1357         /*
1358          * We are a bit conservative about what we expect.  We have to
1359          * know about every hardware change ASAP.
1360          */
1361         printk(KERN_INFO "testing the IO APIC.......................\n");
1362
1363         for (apic = 0; apic < nr_ioapics; apic++) {
1364
1365         spin_lock_irqsave(&ioapic_lock, flags);
1366         reg_00.raw = io_apic_read(apic, 0);
1367         reg_01.raw = io_apic_read(apic, 1);
1368         if (reg_01.bits.version >= 0x10)
1369                 reg_02.raw = io_apic_read(apic, 2);
1370         if (reg_01.bits.version >= 0x20)
1371                 reg_03.raw = io_apic_read(apic, 3);
1372         spin_unlock_irqrestore(&ioapic_lock, flags);
1373
1374         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1375         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1376         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1377         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1378         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1379
1380         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1381         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1382
1383         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1384         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1385
1386         /*
1387          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1388          * but the value of reg_02 is read as the previous read register
1389          * value, so ignore it if reg_02 == reg_01.
1390          */
1391         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1392                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1393                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1394         }
1395
1396         /*
1397          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1398          * or reg_03, but the value of reg_0[23] is read as the previous read
1399          * register value, so ignore it if reg_03 == reg_0[12].
1400          */
1401         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1402             reg_03.raw != reg_01.raw) {
1403                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1404                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1405         }
1406
1407         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1408
1409         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1410                           " Stat Dest Deli Vect:   \n");
1411
1412         for (i = 0; i <= reg_01.bits.entries; i++) {
1413                 struct IO_APIC_route_entry entry;
1414
1415                 entry = ioapic_read_entry(apic, i);
1416
1417                 printk(KERN_DEBUG " %02x %03X %02X  ",
1418                         i,
1419                         entry.dest.logical.logical_dest,
1420                         entry.dest.physical.physical_dest
1421                 );
1422
1423                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1424                         entry.mask,
1425                         entry.trigger,
1426                         entry.irr,
1427                         entry.polarity,
1428                         entry.delivery_status,
1429                         entry.dest_mode,
1430                         entry.delivery_mode,
1431                         entry.vector
1432                 );
1433         }
1434         }
1435         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1436         for (i = 0; i < NR_IRQS; i++) {
1437                 struct irq_pin_list *entry = irq_2_pin + i;
1438                 if (entry->pin < 0)
1439                         continue;
1440                 printk(KERN_DEBUG "IRQ%d ", i);
1441                 for (;;) {
1442                         printk("-> %d:%d", entry->apic, entry->pin);
1443                         if (!entry->next)
1444                                 break;
1445                         entry = irq_2_pin + entry->next;
1446                 }
1447                 printk("\n");
1448         }
1449
1450         printk(KERN_INFO ".................................... done.\n");
1451
1452         return;
1453 }
1454
1455 #if 0
1456
1457 static void print_APIC_bitfield (int base)
1458 {
1459         unsigned int v;
1460         int i, j;
1461
1462         if (apic_verbosity == APIC_QUIET)
1463                 return;
1464
1465         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1466         for (i = 0; i < 8; i++) {
1467                 v = apic_read(base + i*0x10);
1468                 for (j = 0; j < 32; j++) {
1469                         if (v & (1<<j))
1470                                 printk("1");
1471                         else
1472                                 printk("0");
1473                 }
1474                 printk("\n");
1475         }
1476 }
1477
1478 void /*__init*/ print_local_APIC(void * dummy)
1479 {
1480         unsigned int v, ver, maxlvt;
1481
1482         if (apic_verbosity == APIC_QUIET)
1483                 return;
1484
1485         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1486                 smp_processor_id(), hard_smp_processor_id());
1487         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v,
1488                         GET_APIC_ID(read_apic_id()));
1489         v = apic_read(APIC_LVR);
1490         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1491         ver = GET_APIC_VERSION(v);
1492         maxlvt = lapic_get_maxlvt();
1493
1494         v = apic_read(APIC_TASKPRI);
1495         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1496
1497         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1498                 v = apic_read(APIC_ARBPRI);
1499                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1500                         v & APIC_ARBPRI_MASK);
1501                 v = apic_read(APIC_PROCPRI);
1502                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1503         }
1504
1505         v = apic_read(APIC_EOI);
1506         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1507         v = apic_read(APIC_RRR);
1508         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1509         v = apic_read(APIC_LDR);
1510         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1511         v = apic_read(APIC_DFR);
1512         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1513         v = apic_read(APIC_SPIV);
1514         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1515
1516         printk(KERN_DEBUG "... APIC ISR field:\n");
1517         print_APIC_bitfield(APIC_ISR);
1518         printk(KERN_DEBUG "... APIC TMR field:\n");
1519         print_APIC_bitfield(APIC_TMR);
1520         printk(KERN_DEBUG "... APIC IRR field:\n");
1521         print_APIC_bitfield(APIC_IRR);
1522
1523         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1524                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1525                         apic_write(APIC_ESR, 0);
1526                 v = apic_read(APIC_ESR);
1527                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1528         }
1529
1530         v = apic_read(APIC_ICR);
1531         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1532         v = apic_read(APIC_ICR2);
1533         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1534
1535         v = apic_read(APIC_LVTT);
1536         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1537
1538         if (maxlvt > 3) {                       /* PC is LVT#4. */
1539                 v = apic_read(APIC_LVTPC);
1540                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1541         }
1542         v = apic_read(APIC_LVT0);
1543         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1544         v = apic_read(APIC_LVT1);
1545         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1546
1547         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1548                 v = apic_read(APIC_LVTERR);
1549                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1550         }
1551
1552         v = apic_read(APIC_TMICT);
1553         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1554         v = apic_read(APIC_TMCCT);
1555         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1556         v = apic_read(APIC_TDCR);
1557         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1558         printk("\n");
1559 }
1560
1561 void print_all_local_APICs (void)
1562 {
1563         on_each_cpu(print_local_APIC, NULL, 1, 1);
1564 }
1565
1566 void /*__init*/ print_PIC(void)
1567 {
1568         unsigned int v;
1569         unsigned long flags;
1570
1571         if (apic_verbosity == APIC_QUIET)
1572                 return;
1573
1574         printk(KERN_DEBUG "\nprinting PIC contents\n");
1575
1576         spin_lock_irqsave(&i8259A_lock, flags);
1577
1578         v = inb(0xa1) << 8 | inb(0x21);
1579         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1580
1581         v = inb(0xa0) << 8 | inb(0x20);
1582         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1583
1584         outb(0x0b,0xa0);
1585         outb(0x0b,0x20);
1586         v = inb(0xa0) << 8 | inb(0x20);
1587         outb(0x0a,0xa0);
1588         outb(0x0a,0x20);
1589
1590         spin_unlock_irqrestore(&i8259A_lock, flags);
1591
1592         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1593
1594         v = inb(0x4d1) << 8 | inb(0x4d0);
1595         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1596 }
1597
1598 #endif  /*  0  */
1599
1600 static void __init enable_IO_APIC(void)
1601 {
1602         union IO_APIC_reg_01 reg_01;
1603         int i8259_apic, i8259_pin;
1604         int i, apic;
1605         unsigned long flags;
1606
1607         for (i = 0; i < PIN_MAP_SIZE; i++) {
1608                 irq_2_pin[i].pin = -1;
1609                 irq_2_pin[i].next = 0;
1610         }
1611         if (!pirqs_enabled)
1612                 for (i = 0; i < MAX_PIRQS; i++)
1613                         pirq_entries[i] = -1;
1614
1615         /*
1616          * The number of IO-APIC IRQ registers (== #pins):
1617          */
1618         for (apic = 0; apic < nr_ioapics; apic++) {
1619                 spin_lock_irqsave(&ioapic_lock, flags);
1620                 reg_01.raw = io_apic_read(apic, 1);
1621                 spin_unlock_irqrestore(&ioapic_lock, flags);
1622                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1623         }
1624         for(apic = 0; apic < nr_ioapics; apic++) {
1625                 int pin;
1626                 /* See if any of the pins is in ExtINT mode */
1627                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1628                         struct IO_APIC_route_entry entry;
1629                         entry = ioapic_read_entry(apic, pin);
1630
1631
1632                         /* If the interrupt line is enabled and in ExtInt mode
1633                          * I have found the pin where the i8259 is connected.
1634                          */
1635                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1636                                 ioapic_i8259.apic = apic;
1637                                 ioapic_i8259.pin  = pin;
1638                                 goto found_i8259;
1639                         }
1640                 }
1641         }
1642  found_i8259:
1643         /* Look to see what if the MP table has reported the ExtINT */
1644         /* If we could not find the appropriate pin by looking at the ioapic
1645          * the i8259 probably is not connected the ioapic but give the
1646          * mptable a chance anyway.
1647          */
1648         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1649         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1650         /* Trust the MP table if nothing is setup in the hardware */
1651         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1652                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1653                 ioapic_i8259.pin  = i8259_pin;
1654                 ioapic_i8259.apic = i8259_apic;
1655         }
1656         /* Complain if the MP table and the hardware disagree */
1657         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1658                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1659         {
1660                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1661         }
1662
1663         /*
1664          * Do not trust the IO-APIC being empty at bootup
1665          */
1666         clear_IO_APIC();
1667 }
1668
1669 /*
1670  * Not an __init, needed by the reboot code
1671  */
1672 void disable_IO_APIC(void)
1673 {
1674         /*
1675          * Clear the IO-APIC before rebooting:
1676          */
1677         clear_IO_APIC();
1678
1679         /*
1680          * If the i8259 is routed through an IOAPIC
1681          * Put that IOAPIC in virtual wire mode
1682          * so legacy interrupts can be delivered.
1683          */
1684         if (ioapic_i8259.pin != -1) {
1685                 struct IO_APIC_route_entry entry;
1686
1687                 memset(&entry, 0, sizeof(entry));
1688                 entry.mask            = 0; /* Enabled */
1689                 entry.trigger         = 0; /* Edge */
1690                 entry.irr             = 0;
1691                 entry.polarity        = 0; /* High */
1692                 entry.delivery_status = 0;
1693                 entry.dest_mode       = 0; /* Physical */
1694                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1695                 entry.vector          = 0;
1696                 entry.dest.physical.physical_dest =
1697                                         GET_APIC_ID(read_apic_id());
1698
1699                 /*
1700                  * Add it to the IO-APIC irq-routing table:
1701                  */
1702                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1703         }
1704         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1705 }
1706
1707 /*
1708  * function to set the IO-APIC physical IDs based on the
1709  * values stored in the MPC table.
1710  *
1711  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1712  */
1713
1714 #ifndef CONFIG_X86_NUMAQ
1715 static void __init setup_ioapic_ids_from_mpc(void)
1716 {
1717         union IO_APIC_reg_00 reg_00;
1718         physid_mask_t phys_id_present_map;
1719         int apic;
1720         int i;
1721         unsigned char old_id;
1722         unsigned long flags;
1723
1724         /*
1725          * Don't check I/O APIC IDs for xAPIC systems.  They have
1726          * no meaning without the serial APIC bus.
1727          */
1728         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1729                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1730                 return;
1731         /*
1732          * This is broken; anything with a real cpu count has to
1733          * circumvent this idiocy regardless.
1734          */
1735         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1736
1737         /*
1738          * Set the IOAPIC ID to the value stored in the MPC table.
1739          */
1740         for (apic = 0; apic < nr_ioapics; apic++) {
1741
1742                 /* Read the register 0 value */
1743                 spin_lock_irqsave(&ioapic_lock, flags);
1744                 reg_00.raw = io_apic_read(apic, 0);
1745                 spin_unlock_irqrestore(&ioapic_lock, flags);
1746
1747                 old_id = mp_ioapics[apic].mpc_apicid;
1748
1749                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1750                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1751                                 apic, mp_ioapics[apic].mpc_apicid);
1752                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1753                                 reg_00.bits.ID);
1754                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1755                 }
1756
1757                 /*
1758                  * Sanity check, is the ID really free? Every APIC in a
1759                  * system must have a unique ID or we get lots of nice
1760                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1761                  */
1762                 if (check_apicid_used(phys_id_present_map,
1763                                         mp_ioapics[apic].mpc_apicid)) {
1764                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1765                                 apic, mp_ioapics[apic].mpc_apicid);
1766                         for (i = 0; i < get_physical_broadcast(); i++)
1767                                 if (!physid_isset(i, phys_id_present_map))
1768                                         break;
1769                         if (i >= get_physical_broadcast())
1770                                 panic("Max APIC ID exceeded!\n");
1771                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1772                                 i);
1773                         physid_set(i, phys_id_present_map);
1774                         mp_ioapics[apic].mpc_apicid = i;
1775                 } else {
1776                         physid_mask_t tmp;
1777                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1778                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1779                                         "phys_id_present_map\n",
1780                                         mp_ioapics[apic].mpc_apicid);
1781                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1782                 }
1783
1784
1785                 /*
1786                  * We need to adjust the IRQ routing table
1787                  * if the ID changed.
1788                  */
1789                 if (old_id != mp_ioapics[apic].mpc_apicid)
1790                         for (i = 0; i < mp_irq_entries; i++)
1791                                 if (mp_irqs[i].mpc_dstapic == old_id)
1792                                         mp_irqs[i].mpc_dstapic
1793                                                 = mp_ioapics[apic].mpc_apicid;
1794
1795                 /*
1796                  * Read the right value from the MPC table and
1797                  * write it into the ID register.
1798                  */
1799                 apic_printk(APIC_VERBOSE, KERN_INFO
1800                         "...changing IO-APIC physical APIC ID to %d ...",
1801                         mp_ioapics[apic].mpc_apicid);
1802
1803                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1804                 spin_lock_irqsave(&ioapic_lock, flags);
1805                 io_apic_write(apic, 0, reg_00.raw);
1806                 spin_unlock_irqrestore(&ioapic_lock, flags);
1807
1808                 /*
1809                  * Sanity check
1810                  */
1811                 spin_lock_irqsave(&ioapic_lock, flags);
1812                 reg_00.raw = io_apic_read(apic, 0);
1813                 spin_unlock_irqrestore(&ioapic_lock, flags);
1814                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1815                         printk("could not set ID!\n");
1816                 else
1817                         apic_printk(APIC_VERBOSE, " ok.\n");
1818         }
1819 }
1820 #else
1821 static void __init setup_ioapic_ids_from_mpc(void) { }
1822 #endif
1823
1824 int no_timer_check __initdata;
1825
1826 static int __init notimercheck(char *s)
1827 {
1828         no_timer_check = 1;
1829         return 1;
1830 }
1831 __setup("no_timer_check", notimercheck);
1832
1833 /*
1834  * There is a nasty bug in some older SMP boards, their mptable lies
1835  * about the timer IRQ. We do the following to work around the situation:
1836  *
1837  *      - timer IRQ defaults to IO-APIC IRQ
1838  *      - if this function detects that timer IRQs are defunct, then we fall
1839  *        back to ISA timer IRQs
1840  */
1841 static int __init timer_irq_works(void)
1842 {
1843         unsigned long t1 = jiffies;
1844         unsigned long flags;
1845
1846         if (no_timer_check)
1847                 return 1;
1848
1849         local_save_flags(flags);
1850         local_irq_enable();
1851         /* Let ten ticks pass... */
1852         mdelay((10 * 1000) / HZ);
1853         local_irq_restore(flags);
1854
1855         /*
1856          * Expect a few ticks at least, to be sure some possible
1857          * glue logic does not lock up after one or two first
1858          * ticks in a non-ExtINT mode.  Also the local APIC
1859          * might have cached one ExtINT interrupt.  Finally, at
1860          * least one tick may be lost due to delays.
1861          */
1862         if (time_after(jiffies, t1 + 4))
1863                 return 1;
1864
1865         return 0;
1866 }
1867
1868 /*
1869  * In the SMP+IOAPIC case it might happen that there are an unspecified
1870  * number of pending IRQ events unhandled. These cases are very rare,
1871  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1872  * better to do it this way as thus we do not have to be aware of
1873  * 'pending' interrupts in the IRQ path, except at this point.
1874  */
1875 /*
1876  * Edge triggered needs to resend any interrupt
1877  * that was delayed but this is now handled in the device
1878  * independent code.
1879  */
1880
1881 /*
1882  * Startup quirk:
1883  *
1884  * Starting up a edge-triggered IO-APIC interrupt is
1885  * nasty - we need to make sure that we get the edge.
1886  * If it is already asserted for some reason, we need
1887  * return 1 to indicate that is was pending.
1888  *
1889  * This is not complete - we should be able to fake
1890  * an edge even if it isn't on the 8259A...
1891  *
1892  * (We do this for level-triggered IRQs too - it cannot hurt.)
1893  */
1894 static unsigned int startup_ioapic_irq(unsigned int irq)
1895 {
1896         int was_pending = 0;
1897         unsigned long flags;
1898
1899         spin_lock_irqsave(&ioapic_lock, flags);
1900         if (irq < 16) {
1901                 disable_8259A_irq(irq);
1902                 if (i8259A_irq_pending(irq))
1903                         was_pending = 1;
1904         }
1905         __unmask_IO_APIC_irq(irq);
1906         spin_unlock_irqrestore(&ioapic_lock, flags);
1907
1908         return was_pending;
1909 }
1910
1911 static void ack_ioapic_irq(unsigned int irq)
1912 {
1913         move_native_irq(irq);
1914         ack_APIC_irq();
1915 }
1916
1917 static void ack_ioapic_quirk_irq(unsigned int irq)
1918 {
1919         unsigned long v;
1920         int i;
1921
1922         move_native_irq(irq);
1923 /*
1924  * It appears there is an erratum which affects at least version 0x11
1925  * of I/O APIC (that's the 82093AA and cores integrated into various
1926  * chipsets).  Under certain conditions a level-triggered interrupt is
1927  * erroneously delivered as edge-triggered one but the respective IRR
1928  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1929  * message but it will never arrive and further interrupts are blocked
1930  * from the source.  The exact reason is so far unknown, but the
1931  * phenomenon was observed when two consecutive interrupt requests
1932  * from a given source get delivered to the same CPU and the source is
1933  * temporarily disabled in between.
1934  *
1935  * A workaround is to simulate an EOI message manually.  We achieve it
1936  * by setting the trigger mode to edge and then to level when the edge
1937  * trigger mode gets detected in the TMR of a local APIC for a
1938  * level-triggered interrupt.  We mask the source for the time of the
1939  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1940  * The idea is from Manfred Spraul.  --macro
1941  */
1942         i = irq_vector[irq];
1943
1944         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1945
1946         ack_APIC_irq();
1947
1948         if (!(v & (1 << (i & 0x1f)))) {
1949                 atomic_inc(&irq_mis_count);
1950                 spin_lock(&ioapic_lock);
1951                 __mask_and_edge_IO_APIC_irq(irq);
1952                 __unmask_and_level_IO_APIC_irq(irq);
1953                 spin_unlock(&ioapic_lock);
1954         }
1955 }
1956
1957 static int ioapic_retrigger_irq(unsigned int irq)
1958 {
1959         send_IPI_self(irq_vector[irq]);
1960
1961         return 1;
1962 }
1963
1964 static struct irq_chip ioapic_chip __read_mostly = {
1965         .name           = "IO-APIC",
1966         .startup        = startup_ioapic_irq,
1967         .mask           = mask_IO_APIC_irq,
1968         .unmask         = unmask_IO_APIC_irq,
1969         .ack            = ack_ioapic_irq,
1970         .eoi            = ack_ioapic_quirk_irq,
1971 #ifdef CONFIG_SMP
1972         .set_affinity   = set_ioapic_affinity_irq,
1973 #endif
1974         .retrigger      = ioapic_retrigger_irq,
1975 };
1976
1977
1978 static inline void init_IO_APIC_traps(void)
1979 {
1980         int irq;
1981
1982         /*
1983          * NOTE! The local APIC isn't very good at handling
1984          * multiple interrupts at the same interrupt level.
1985          * As the interrupt level is determined by taking the
1986          * vector number and shifting that right by 4, we
1987          * want to spread these out a bit so that they don't
1988          * all fall in the same interrupt level.
1989          *
1990          * Also, we've got to be careful not to trash gate
1991          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1992          */
1993         for (irq = 0; irq < NR_IRQS ; irq++) {
1994                 if (IO_APIC_IRQ(irq) && !irq_vector[irq]) {
1995                         /*
1996                          * Hmm.. We don't have an entry for this,
1997                          * so default to an old-fashioned 8259
1998                          * interrupt if we can..
1999                          */
2000                         if (irq < 16)
2001                                 make_8259A_irq(irq);
2002                         else
2003                                 /* Strange. Oh, well.. */
2004                                 irq_desc[irq].chip = &no_irq_chip;
2005                 }
2006         }
2007 }
2008
2009 /*
2010  * The local APIC irq-chip implementation:
2011  */
2012
2013 static void ack_apic(unsigned int irq)
2014 {
2015         ack_APIC_irq();
2016 }
2017
2018 static void mask_lapic_irq (unsigned int irq)
2019 {
2020         unsigned long v;
2021
2022         v = apic_read(APIC_LVT0);
2023         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2024 }
2025
2026 static void unmask_lapic_irq (unsigned int irq)
2027 {
2028         unsigned long v;
2029
2030         v = apic_read(APIC_LVT0);
2031         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2032 }
2033
2034 static struct irq_chip lapic_chip __read_mostly = {
2035         .name           = "local-APIC",
2036         .mask           = mask_lapic_irq,
2037         .unmask         = unmask_lapic_irq,
2038         .eoi            = ack_apic,
2039 };
2040
2041 static void __init setup_nmi(void)
2042 {
2043         /*
2044          * Dirty trick to enable the NMI watchdog ...
2045          * We put the 8259A master into AEOI mode and
2046          * unmask on all local APICs LVT0 as NMI.
2047          *
2048          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2049          * is from Maciej W. Rozycki - so we do not have to EOI from
2050          * the NMI handler or the timer interrupt.
2051          */
2052         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2053
2054         enable_NMI_through_LVT0();
2055
2056         apic_printk(APIC_VERBOSE, " done.\n");
2057 }
2058
2059 /*
2060  * This looks a bit hackish but it's about the only one way of sending
2061  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2062  * not support the ExtINT mode, unfortunately.  We need to send these
2063  * cycles as some i82489DX-based boards have glue logic that keeps the
2064  * 8259A interrupt line asserted until INTA.  --macro
2065  */
2066 static inline void __init unlock_ExtINT_logic(void)
2067 {
2068         int apic, pin, i;
2069         struct IO_APIC_route_entry entry0, entry1;
2070         unsigned char save_control, save_freq_select;
2071
2072         pin  = find_isa_irq_pin(8, mp_INT);
2073         if (pin == -1) {
2074                 WARN_ON_ONCE(1);
2075                 return;
2076         }
2077         apic = find_isa_irq_apic(8, mp_INT);
2078         if (apic == -1) {
2079                 WARN_ON_ONCE(1);
2080                 return;
2081         }
2082
2083         entry0 = ioapic_read_entry(apic, pin);
2084         clear_IO_APIC_pin(apic, pin);
2085
2086         memset(&entry1, 0, sizeof(entry1));
2087
2088         entry1.dest_mode = 0;                   /* physical delivery */
2089         entry1.mask = 0;                        /* unmask IRQ now */
2090         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2091         entry1.delivery_mode = dest_ExtINT;
2092         entry1.polarity = entry0.polarity;
2093         entry1.trigger = 0;
2094         entry1.vector = 0;
2095
2096         ioapic_write_entry(apic, pin, entry1);
2097
2098         save_control = CMOS_READ(RTC_CONTROL);
2099         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2100         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2101                    RTC_FREQ_SELECT);
2102         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2103
2104         i = 100;
2105         while (i-- > 0) {
2106                 mdelay(10);
2107                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2108                         i -= 10;
2109         }
2110
2111         CMOS_WRITE(save_control, RTC_CONTROL);
2112         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2113         clear_IO_APIC_pin(apic, pin);
2114
2115         ioapic_write_entry(apic, pin, entry0);
2116 }
2117
2118 /*
2119  * This code may look a bit paranoid, but it's supposed to cooperate with
2120  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2121  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2122  * fanatically on his truly buggy board.
2123  */
2124 static inline void __init check_timer(void)
2125 {
2126         int apic1, pin1, apic2, pin2;
2127         int no_pin1 = 0;
2128         int vector;
2129         unsigned int ver;
2130         unsigned long flags;
2131
2132         local_irq_save(flags);
2133
2134         ver = apic_read(APIC_LVR);
2135         ver = GET_APIC_VERSION(ver);
2136
2137         /*
2138          * get/set the timer IRQ vector:
2139          */
2140         disable_8259A_irq(0);
2141         vector = assign_irq_vector(0);
2142         set_intr_gate(vector, interrupt[0]);
2143
2144         /*
2145          * As IRQ0 is to be enabled in the 8259A, the virtual
2146          * wire has to be disabled in the local APIC.  Also
2147          * timer interrupts need to be acknowledged manually in
2148          * the 8259A for the i82489DX when using the NMI
2149          * watchdog as that APIC treats NMIs as level-triggered.
2150          * The AEOI mode will finish them in the 8259A
2151          * automatically.
2152          */
2153         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2154         init_8259A(1);
2155         timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2156
2157         pin1  = find_isa_irq_pin(0, mp_INT);
2158         apic1 = find_isa_irq_apic(0, mp_INT);
2159         pin2  = ioapic_i8259.pin;
2160         apic2 = ioapic_i8259.apic;
2161
2162         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2163                 vector, apic1, pin1, apic2, pin2);
2164
2165         /*
2166          * Some BIOS writers are clueless and report the ExtINTA
2167          * I/O APIC input from the cascaded 8259A as the timer
2168          * interrupt input.  So just in case, if only one pin
2169          * was found above, try it both directly and through the
2170          * 8259A.
2171          */
2172         if (pin1 == -1) {
2173                 pin1 = pin2;
2174                 apic1 = apic2;
2175                 no_pin1 = 1;
2176         } else if (pin2 == -1) {
2177                 pin2 = pin1;
2178                 apic2 = apic1;
2179         }
2180
2181         if (pin1 != -1) {
2182                 /*
2183                  * Ok, does IRQ0 through the IOAPIC work?
2184                  */
2185                 if (no_pin1) {
2186                         add_pin_to_irq(0, apic1, pin1);
2187                         setup_timer_IRQ0_pin(apic1, pin1, vector);
2188                 }
2189                 unmask_IO_APIC_irq(0);
2190                 if (timer_irq_works()) {
2191                         if (nmi_watchdog == NMI_IO_APIC) {
2192                                 setup_nmi();
2193                                 enable_8259A_irq(0);
2194                         }
2195                         if (disable_timer_pin_1 > 0)
2196                                 clear_IO_APIC_pin(0, pin1);
2197                         goto out;
2198                 }
2199                 clear_IO_APIC_pin(apic1, pin1);
2200                 if (!no_pin1)
2201                         printk(KERN_ERR "..MP-BIOS bug: "
2202                                "8254 timer not connected to IO-APIC\n");
2203
2204                 printk(KERN_INFO "...trying to set up timer (IRQ0) "
2205                        "through the 8259A ... ");
2206                 printk("\n..... (found pin %d) ...", pin2);
2207                 /*
2208                  * legacy devices should be connected to IO APIC #0
2209                  */
2210                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2211                 setup_timer_IRQ0_pin(apic2, pin2, vector);
2212                 unmask_IO_APIC_irq(0);
2213                 enable_8259A_irq(0);
2214                 if (timer_irq_works()) {
2215                         printk("works.\n");
2216                         timer_through_8259 = 1;
2217                         if (nmi_watchdog == NMI_IO_APIC) {
2218                                 disable_8259A_irq(0);
2219                                 setup_nmi();
2220                                 enable_8259A_irq(0);
2221                         }
2222                         goto out;
2223                 }
2224                 /*
2225                  * Cleanup, just in case ...
2226                  */
2227                 disable_8259A_irq(0);
2228                 clear_IO_APIC_pin(apic2, pin2);
2229                 printk(" failed.\n");
2230         }
2231
2232         if (nmi_watchdog == NMI_IO_APIC) {
2233                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2234                 nmi_watchdog = NMI_NONE;
2235         }
2236         timer_ack = 0;
2237
2238         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2239
2240         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2241                                       "fasteoi");
2242         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2243         enable_8259A_irq(0);
2244
2245         if (timer_irq_works()) {
2246                 printk(" works.\n");
2247                 goto out;
2248         }
2249         disable_8259A_irq(0);
2250         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2251         printk(" failed.\n");
2252
2253         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2254
2255         init_8259A(0);
2256         make_8259A_irq(0);
2257         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2258
2259         unlock_ExtINT_logic();
2260
2261         if (timer_irq_works()) {
2262                 printk(" works.\n");
2263                 goto out;
2264         }
2265         printk(" failed :(.\n");
2266         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2267                 "report.  Then try booting with the 'noapic' option");
2268 out:
2269         local_irq_restore(flags);
2270 }
2271
2272 /*
2273  *
2274  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2275  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2276  *   Linux doesn't really care, as it's not actually used
2277  *   for any interrupt handling anyway.
2278  */
2279 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2280
2281 void __init setup_IO_APIC(void)
2282 {
2283         int i;
2284
2285         /* Reserve all the system vectors. */
2286         for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2287                 set_bit(i, used_vectors);
2288
2289         enable_IO_APIC();
2290
2291         if (acpi_ioapic)
2292                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2293         else
2294                 io_apic_irqs = ~PIC_IRQS;
2295
2296         printk("ENABLING IO-APIC IRQs\n");
2297
2298         /*
2299          * Set up IO-APIC IRQ routing.
2300          */
2301         if (!acpi_ioapic)
2302                 setup_ioapic_ids_from_mpc();
2303         sync_Arb_IDs();
2304         setup_IO_APIC_irqs();
2305         init_IO_APIC_traps();
2306         check_timer();
2307         if (!acpi_ioapic)
2308                 print_IO_APIC();
2309 }
2310
2311 /*
2312  *      Called after all the initialization is done. If we didnt find any
2313  *      APIC bugs then we can allow the modify fast path
2314  */
2315
2316 static int __init io_apic_bug_finalize(void)
2317 {
2318         if(sis_apic_bug == -1)
2319                 sis_apic_bug = 0;
2320         return 0;
2321 }
2322
2323 late_initcall(io_apic_bug_finalize);
2324
2325 struct sysfs_ioapic_data {
2326         struct sys_device dev;
2327         struct IO_APIC_route_entry entry[0];
2328 };
2329 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2330
2331 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2332 {
2333         struct IO_APIC_route_entry *entry;
2334         struct sysfs_ioapic_data *data;
2335         int i;
2336
2337         data = container_of(dev, struct sysfs_ioapic_data, dev);
2338         entry = data->entry;
2339         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2340                 entry[i] = ioapic_read_entry(dev->id, i);
2341
2342         return 0;
2343 }
2344
2345 static int ioapic_resume(struct sys_device *dev)
2346 {
2347         struct IO_APIC_route_entry *entry;
2348         struct sysfs_ioapic_data *data;
2349         unsigned long flags;
2350         union IO_APIC_reg_00 reg_00;
2351         int i;
2352
2353         data = container_of(dev, struct sysfs_ioapic_data, dev);
2354         entry = data->entry;
2355
2356         spin_lock_irqsave(&ioapic_lock, flags);
2357         reg_00.raw = io_apic_read(dev->id, 0);
2358         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2359                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2360                 io_apic_write(dev->id, 0, reg_00.raw);
2361         }
2362         spin_unlock_irqrestore(&ioapic_lock, flags);
2363         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2364                 ioapic_write_entry(dev->id, i, entry[i]);
2365
2366         return 0;
2367 }
2368
2369 static struct sysdev_class ioapic_sysdev_class = {
2370         .name = "ioapic",
2371         .suspend = ioapic_suspend,
2372         .resume = ioapic_resume,
2373 };
2374
2375 static int __init ioapic_init_sysfs(void)
2376 {
2377         struct sys_device * dev;
2378         int i, size, error = 0;
2379
2380         error = sysdev_class_register(&ioapic_sysdev_class);
2381         if (error)
2382                 return error;
2383
2384         for (i = 0; i < nr_ioapics; i++ ) {
2385                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2386                         * sizeof(struct IO_APIC_route_entry);
2387                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2388                 if (!mp_ioapic_data[i]) {
2389                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2390                         continue;
2391                 }
2392                 memset(mp_ioapic_data[i], 0, size);
2393                 dev = &mp_ioapic_data[i]->dev;
2394                 dev->id = i;
2395                 dev->cls = &ioapic_sysdev_class;
2396                 error = sysdev_register(dev);
2397                 if (error) {
2398                         kfree(mp_ioapic_data[i]);
2399                         mp_ioapic_data[i] = NULL;
2400                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2401                         continue;
2402                 }
2403         }
2404
2405         return 0;
2406 }
2407
2408 device_initcall(ioapic_init_sysfs);
2409
2410 /*
2411  * Dynamic irq allocate and deallocation
2412  */
2413 int create_irq(void)
2414 {
2415         /* Allocate an unused irq */
2416         int irq, new, vector = 0;
2417         unsigned long flags;
2418
2419         irq = -ENOSPC;
2420         spin_lock_irqsave(&vector_lock, flags);
2421         for (new = (NR_IRQS - 1); new >= 0; new--) {
2422                 if (platform_legacy_irq(new))
2423                         continue;
2424                 if (irq_vector[new] != 0)
2425                         continue;
2426                 vector = __assign_irq_vector(new);
2427                 if (likely(vector > 0))
2428                         irq = new;
2429                 break;
2430         }
2431         spin_unlock_irqrestore(&vector_lock, flags);
2432
2433         if (irq >= 0) {
2434                 set_intr_gate(vector, interrupt[irq]);
2435                 dynamic_irq_init(irq);
2436         }
2437         return irq;
2438 }
2439
2440 void destroy_irq(unsigned int irq)
2441 {
2442         unsigned long flags;
2443
2444         dynamic_irq_cleanup(irq);
2445
2446         spin_lock_irqsave(&vector_lock, flags);
2447         clear_bit(irq_vector[irq], used_vectors);
2448         irq_vector[irq] = 0;
2449         spin_unlock_irqrestore(&vector_lock, flags);
2450 }
2451
2452 /*
2453  * MSI message composition
2454  */
2455 #ifdef CONFIG_PCI_MSI
2456 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2457 {
2458         int vector;
2459         unsigned dest;
2460
2461         vector = assign_irq_vector(irq);
2462         if (vector >= 0) {
2463                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2464
2465                 msg->address_hi = MSI_ADDR_BASE_HI;
2466                 msg->address_lo =
2467                         MSI_ADDR_BASE_LO |
2468                         ((INT_DEST_MODE == 0) ?
2469                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2470                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2471                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2472                                 MSI_ADDR_REDIRECTION_CPU:
2473                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2474                         MSI_ADDR_DEST_ID(dest);
2475
2476                 msg->data =
2477                         MSI_DATA_TRIGGER_EDGE |
2478                         MSI_DATA_LEVEL_ASSERT |
2479                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2480                                 MSI_DATA_DELIVERY_FIXED:
2481                                 MSI_DATA_DELIVERY_LOWPRI) |
2482                         MSI_DATA_VECTOR(vector);
2483         }
2484         return vector;
2485 }
2486
2487 #ifdef CONFIG_SMP
2488 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2489 {
2490         struct msi_msg msg;
2491         unsigned int dest;
2492         cpumask_t tmp;
2493         int vector;
2494
2495         cpus_and(tmp, mask, cpu_online_map);
2496         if (cpus_empty(tmp))
2497                 tmp = TARGET_CPUS;
2498
2499         vector = assign_irq_vector(irq);
2500         if (vector < 0)
2501                 return;
2502
2503         dest = cpu_mask_to_apicid(mask);
2504
2505         read_msi_msg(irq, &msg);
2506
2507         msg.data &= ~MSI_DATA_VECTOR_MASK;
2508         msg.data |= MSI_DATA_VECTOR(vector);
2509         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2510         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2511
2512         write_msi_msg(irq, &msg);
2513         irq_desc[irq].affinity = mask;
2514 }
2515 #endif /* CONFIG_SMP */
2516
2517 /*
2518  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2519  * which implement the MSI or MSI-X Capability Structure.
2520  */
2521 static struct irq_chip msi_chip = {
2522         .name           = "PCI-MSI",
2523         .unmask         = unmask_msi_irq,
2524         .mask           = mask_msi_irq,
2525         .ack            = ack_ioapic_irq,
2526 #ifdef CONFIG_SMP
2527         .set_affinity   = set_msi_irq_affinity,
2528 #endif
2529         .retrigger      = ioapic_retrigger_irq,
2530 };
2531
2532 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2533 {
2534         struct msi_msg msg;
2535         int irq, ret;
2536         irq = create_irq();
2537         if (irq < 0)
2538                 return irq;
2539
2540         ret = msi_compose_msg(dev, irq, &msg);
2541         if (ret < 0) {
2542                 destroy_irq(irq);
2543                 return ret;
2544         }
2545
2546         set_irq_msi(irq, desc);
2547         write_msi_msg(irq, &msg);
2548
2549         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2550                                       "edge");
2551
2552         return 0;
2553 }
2554
2555 void arch_teardown_msi_irq(unsigned int irq)
2556 {
2557         destroy_irq(irq);
2558 }
2559
2560 #endif /* CONFIG_PCI_MSI */
2561
2562 /*
2563  * Hypertransport interrupt support
2564  */
2565 #ifdef CONFIG_HT_IRQ
2566
2567 #ifdef CONFIG_SMP
2568
2569 static void target_ht_irq(unsigned int irq, unsigned int dest)
2570 {
2571         struct ht_irq_msg msg;
2572         fetch_ht_irq_msg(irq, &msg);
2573
2574         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2575         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2576
2577         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2578         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2579
2580         write_ht_irq_msg(irq, &msg);
2581 }
2582
2583 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2584 {
2585         unsigned int dest;
2586         cpumask_t tmp;
2587
2588         cpus_and(tmp, mask, cpu_online_map);
2589         if (cpus_empty(tmp))
2590                 tmp = TARGET_CPUS;
2591
2592         cpus_and(mask, tmp, CPU_MASK_ALL);
2593
2594         dest = cpu_mask_to_apicid(mask);
2595
2596         target_ht_irq(irq, dest);
2597         irq_desc[irq].affinity = mask;
2598 }
2599 #endif
2600
2601 static struct irq_chip ht_irq_chip = {
2602         .name           = "PCI-HT",
2603         .mask           = mask_ht_irq,
2604         .unmask         = unmask_ht_irq,
2605         .ack            = ack_ioapic_irq,
2606 #ifdef CONFIG_SMP
2607         .set_affinity   = set_ht_irq_affinity,
2608 #endif
2609         .retrigger      = ioapic_retrigger_irq,
2610 };
2611
2612 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2613 {
2614         int vector;
2615
2616         vector = assign_irq_vector(irq);
2617         if (vector >= 0) {
2618                 struct ht_irq_msg msg;
2619                 unsigned dest;
2620                 cpumask_t tmp;
2621
2622                 cpus_clear(tmp);
2623                 cpu_set(vector >> 8, tmp);
2624                 dest = cpu_mask_to_apicid(tmp);
2625
2626                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2627
2628                 msg.address_lo =
2629                         HT_IRQ_LOW_BASE |
2630                         HT_IRQ_LOW_DEST_ID(dest) |
2631                         HT_IRQ_LOW_VECTOR(vector) |
2632                         ((INT_DEST_MODE == 0) ?
2633                                 HT_IRQ_LOW_DM_PHYSICAL :
2634                                 HT_IRQ_LOW_DM_LOGICAL) |
2635                         HT_IRQ_LOW_RQEOI_EDGE |
2636                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2637                                 HT_IRQ_LOW_MT_FIXED :
2638                                 HT_IRQ_LOW_MT_ARBITRATED) |
2639                         HT_IRQ_LOW_IRQ_MASKED;
2640
2641                 write_ht_irq_msg(irq, &msg);
2642
2643                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2644                                               handle_edge_irq, "edge");
2645         }
2646         return vector;
2647 }
2648 #endif /* CONFIG_HT_IRQ */
2649
2650 /* --------------------------------------------------------------------------
2651                           ACPI-based IOAPIC Configuration
2652    -------------------------------------------------------------------------- */
2653
2654 #ifdef CONFIG_ACPI
2655
2656 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2657 {
2658         union IO_APIC_reg_00 reg_00;
2659         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2660         physid_mask_t tmp;
2661         unsigned long flags;
2662         int i = 0;
2663
2664         /*
2665          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2666          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2667          * supports up to 16 on one shared APIC bus.
2668          *
2669          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2670          *      advantage of new APIC bus architecture.
2671          */
2672
2673         if (physids_empty(apic_id_map))
2674                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2675
2676         spin_lock_irqsave(&ioapic_lock, flags);
2677         reg_00.raw = io_apic_read(ioapic, 0);
2678         spin_unlock_irqrestore(&ioapic_lock, flags);
2679
2680         if (apic_id >= get_physical_broadcast()) {
2681                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2682                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2683                 apic_id = reg_00.bits.ID;
2684         }
2685
2686         /*
2687          * Every APIC in a system must have a unique ID or we get lots of nice
2688          * 'stuck on smp_invalidate_needed IPI wait' messages.
2689          */
2690         if (check_apicid_used(apic_id_map, apic_id)) {
2691
2692                 for (i = 0; i < get_physical_broadcast(); i++) {
2693                         if (!check_apicid_used(apic_id_map, i))
2694                                 break;
2695                 }
2696
2697                 if (i == get_physical_broadcast())
2698                         panic("Max apic_id exceeded!\n");
2699
2700                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2701                         "trying %d\n", ioapic, apic_id, i);
2702
2703                 apic_id = i;
2704         }
2705
2706         tmp = apicid_to_cpu_present(apic_id);
2707         physids_or(apic_id_map, apic_id_map, tmp);
2708
2709         if (reg_00.bits.ID != apic_id) {
2710                 reg_00.bits.ID = apic_id;
2711
2712                 spin_lock_irqsave(&ioapic_lock, flags);
2713                 io_apic_write(ioapic, 0, reg_00.raw);
2714                 reg_00.raw = io_apic_read(ioapic, 0);
2715                 spin_unlock_irqrestore(&ioapic_lock, flags);
2716
2717                 /* Sanity check */
2718                 if (reg_00.bits.ID != apic_id) {
2719                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2720                         return -1;
2721                 }
2722         }
2723
2724         apic_printk(APIC_VERBOSE, KERN_INFO
2725                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2726
2727         return apic_id;
2728 }
2729
2730
2731 int __init io_apic_get_version (int ioapic)
2732 {
2733         union IO_APIC_reg_01    reg_01;
2734         unsigned long flags;
2735
2736         spin_lock_irqsave(&ioapic_lock, flags);
2737         reg_01.raw = io_apic_read(ioapic, 1);
2738         spin_unlock_irqrestore(&ioapic_lock, flags);
2739
2740         return reg_01.bits.version;
2741 }
2742
2743
2744 int __init io_apic_get_redir_entries (int ioapic)
2745 {
2746         union IO_APIC_reg_01    reg_01;
2747         unsigned long flags;
2748
2749         spin_lock_irqsave(&ioapic_lock, flags);
2750         reg_01.raw = io_apic_read(ioapic, 1);
2751         spin_unlock_irqrestore(&ioapic_lock, flags);
2752
2753         return reg_01.bits.entries;
2754 }
2755
2756
2757 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2758 {
2759         struct IO_APIC_route_entry entry;
2760
2761         if (!IO_APIC_IRQ(irq)) {
2762                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2763                         ioapic);
2764                 return -EINVAL;
2765         }
2766
2767         /*
2768          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2769          * Note that we mask (disable) IRQs now -- these get enabled when the
2770          * corresponding device driver registers for this IRQ.
2771          */
2772
2773         memset(&entry,0,sizeof(entry));
2774
2775         entry.delivery_mode = INT_DELIVERY_MODE;
2776         entry.dest_mode = INT_DEST_MODE;
2777         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2778         entry.trigger = edge_level;
2779         entry.polarity = active_high_low;
2780         entry.mask  = 1;
2781
2782         /*
2783          * IRQs < 16 are already in the irq_2_pin[] map
2784          */
2785         if (irq >= 16)
2786                 add_pin_to_irq(irq, ioapic, pin);
2787
2788         entry.vector = assign_irq_vector(irq);
2789
2790         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2791                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2792                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2793                 edge_level, active_high_low);
2794
2795         ioapic_register_intr(irq, entry.vector, edge_level);
2796
2797         if (!ioapic && (irq < 16))
2798                 disable_8259A_irq(irq);
2799
2800         ioapic_write_entry(ioapic, pin, entry);
2801
2802         return 0;
2803 }
2804
2805 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2806 {
2807         int i;
2808
2809         if (skip_ioapic_setup)
2810                 return -1;
2811
2812         for (i = 0; i < mp_irq_entries; i++)
2813                 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2814                     mp_irqs[i].mpc_srcbusirq == bus_irq)
2815                         break;
2816         if (i >= mp_irq_entries)
2817                 return -1;
2818
2819         *trigger = irq_trigger(i);
2820         *polarity = irq_polarity(i);
2821         return 0;
2822 }
2823
2824 #endif /* CONFIG_ACPI */
2825
2826 static int __init parse_disable_timer_pin_1(char *arg)
2827 {
2828         disable_timer_pin_1 = 1;
2829         return 0;
2830 }
2831 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2832
2833 static int __init parse_enable_timer_pin_1(char *arg)
2834 {
2835         disable_timer_pin_1 = -1;
2836         return 0;
2837 }
2838 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2839
2840 static int __init parse_noapic(char *arg)
2841 {
2842         /* disable IO-APIC */
2843         disable_ioapic_setup();
2844         return 0;
2845 }
2846 early_param("noapic", parse_noapic);