2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
52 #include <mach_apic.h>
53 #include <mach_apicdef.h>
55 #define __apicdebuginit(type) static type __init
57 int (*ioapic_renumber_irq)(int ioapic, int irq);
58 atomic_t irq_mis_count;
60 /* Where if anywhere is the i8259 connect in external int mode */
61 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
63 static DEFINE_SPINLOCK(ioapic_lock);
64 static DEFINE_SPINLOCK(vector_lock);
66 int timer_through_8259 __initdata;
69 * Is the SiS APIC rmw bug present ?
70 * -1 = don't know, 0 = no, 1 = yes
72 int sis_apic_bug = -1;
76 * # of IRQ routing registers
78 int nr_ioapic_registers[MAX_IO_APICS];
80 /* I/O APIC entries */
81 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
84 /* MP IRQ source entries */
85 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
87 /* # of MP IRQ source entries */
90 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
91 int mp_bus_id_to_type[MAX_MP_BUSSES];
94 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
96 static int disable_timer_pin_1 __initdata;
102 struct irq_cfg *next;
103 struct irq_pin_list *irq_2_pin;
105 cpumask_t old_domain;
106 unsigned move_cleanup_count;
108 u8 move_in_progress : 1;
112 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
113 static struct irq_cfg irq_cfg_legacy[] __initdata = {
114 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
115 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
116 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
117 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
118 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
119 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
120 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
121 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
122 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
123 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
124 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
125 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
126 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
127 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
128 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
129 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
132 static struct irq_cfg irq_cfg_init = { .irq = -1U, };
133 /* need to be biger than size of irq_cfg_legacy */
134 static int nr_irq_cfg = 32;
136 static int __init parse_nr_irq_cfg(char *arg)
139 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
146 early_param("nr_irq_cfg", parse_nr_irq_cfg);
148 static void init_one_irq_cfg(struct irq_cfg *cfg)
150 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
153 static struct irq_cfg *irq_cfgx;
154 static struct irq_cfg *irq_cfgx_free;
155 static void __init init_work(void *data)
157 struct dyn_array *da = data;
164 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
166 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
167 for (i = legacy_count; i < *da->nr; i++)
168 init_one_irq_cfg(&cfg[i]);
170 for (i = 1; i < *da->nr; i++)
171 cfg[i-1].next = &cfg[i];
173 irq_cfgx_free = &irq_cfgx[legacy_count];
174 irq_cfgx[legacy_count - 1].next = NULL;
177 #define for_each_irq_cfg(cfg) \
178 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
180 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
182 static struct irq_cfg *irq_cfg(unsigned int irq)
197 static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
199 struct irq_cfg *cfg, *cfg_pri;
203 cfg_pri = cfg = irq_cfgx;
213 if (!irq_cfgx_free) {
215 unsigned long total_bytes;
217 * we run out of pre-allocate ones, allocate more
219 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
221 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
223 cfg = kzalloc(total_bytes, GFP_ATOMIC);
225 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
228 panic("please boot with nr_irq_cfg= %d\n", count * 2);
231 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
233 for (i = 0; i < nr_irq_cfg; i++)
234 init_one_irq_cfg(&cfg[i]);
236 for (i = 1; i < nr_irq_cfg; i++)
237 cfg[i-1].next = &cfg[i];
243 irq_cfgx_free = irq_cfgx_free->next;
250 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
252 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
254 /* dump the results */
257 unsigned long bytes = sizeof(struct irq_cfg);
259 printk(KERN_DEBUG "=========================== %d\n", irq);
260 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
261 for_each_irq_cfg(cfg) {
263 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
265 printk(KERN_DEBUG "===========================\n");
271 static int assign_irq_vector(int irq, cpumask_t mask);
273 * Rough estimation of how many shared IRQs there are, can
274 * be changed anytime.
279 * This is performance-critical, we want to do it O(1)
281 * the indexing order of this array favors 1:1 mappings
282 * between pins and IRQs.
285 struct irq_pin_list {
287 struct irq_pin_list *next;
290 static struct irq_pin_list *irq_2_pin_head;
291 /* fill one page ? */
292 static int nr_irq_2_pin = 0x100;
293 static struct irq_pin_list *irq_2_pin_ptr;
294 static void __init irq_2_pin_init_work(void *data)
296 struct dyn_array *da = data;
297 struct irq_pin_list *pin;
302 for (i = 1; i < *da->nr; i++)
303 pin[i-1].next = &pin[i];
305 irq_2_pin_ptr = &pin[0];
307 DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
309 static struct irq_pin_list *get_one_free_irq_2_pin(void)
311 struct irq_pin_list *pin;
317 irq_2_pin_ptr = pin->next;
323 * we run out of pre-allocate ones, allocate more
325 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
328 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
331 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
332 nr_irq_2_pin, PAGE_SIZE, 0);
335 panic("can not get more irq_2_pin\n");
337 for (i = 1; i < nr_irq_2_pin; i++)
338 pin[i-1].next = &pin[i];
340 irq_2_pin_ptr = pin->next;
348 unsigned int unused[3];
352 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
354 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
355 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
358 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
360 struct io_apic __iomem *io_apic = io_apic_base(apic);
361 writel(reg, &io_apic->index);
362 return readl(&io_apic->data);
365 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
367 struct io_apic __iomem *io_apic = io_apic_base(apic);
368 writel(reg, &io_apic->index);
369 writel(value, &io_apic->data);
373 * Re-write a value: to be used for read-modify-write
374 * cycles where the read already set up the index register.
376 * Older SiS APIC requires we rewrite the index register
378 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
380 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
382 writel(reg, &io_apic->index);
383 writel(value, &io_apic->data);
387 struct { u32 w1, w2; };
388 struct IO_APIC_route_entry entry;
391 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
393 union entry_union eu;
395 spin_lock_irqsave(&ioapic_lock, flags);
396 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
397 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
398 spin_unlock_irqrestore(&ioapic_lock, flags);
403 * When we write a new IO APIC routing entry, we need to write the high
404 * word first! If the mask bit in the low word is clear, we will enable
405 * the interrupt, and we need to make sure the entry is fully populated
406 * before that happens.
409 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
411 union entry_union eu;
413 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
414 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
417 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
420 spin_lock_irqsave(&ioapic_lock, flags);
421 __ioapic_write_entry(apic, pin, e);
422 spin_unlock_irqrestore(&ioapic_lock, flags);
426 * When we mask an IO APIC routing entry, we need to write the low
427 * word first, in order to set the mask bit before we change the
430 static void ioapic_mask_entry(int apic, int pin)
433 union entry_union eu = { .entry.mask = 1 };
435 spin_lock_irqsave(&ioapic_lock, flags);
436 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
437 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
438 spin_unlock_irqrestore(&ioapic_lock, flags);
442 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
446 struct irq_pin_list *entry;
449 entry = cfg->irq_2_pin;
458 io_apic_write(apic, 0x11 + pin*2, dest);
459 reg = io_apic_read(apic, 0x10 + pin*2);
460 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
462 io_apic_modify(apic, 0x10 + pin *2, reg);
468 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
477 cpus_and(tmp, mask, cpu_online_map);
481 if (assign_irq_vector(irq, mask))
484 cpus_and(tmp, cfg->domain, mask);
486 dest = cpu_mask_to_apicid(tmp);
488 * Only the high 8 bits are valid.
490 dest = SET_APIC_LOGICAL_ID(dest);
492 spin_lock_irqsave(&ioapic_lock, flags);
493 __target_IO_APIC_irq(irq, dest, cfg->vector);
494 irq_to_desc(irq)->affinity = mask;
495 spin_unlock_irqrestore(&ioapic_lock, flags);
498 #endif /* CONFIG_SMP */
501 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
502 * shared ISA-space IRQs, so we have to support them. We are super
503 * fast in the common case, and fast for shared ISA-space IRQs.
505 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
508 struct irq_pin_list *entry;
510 /* first time to refer irq_cfg, so with new */
511 cfg = irq_cfg_alloc(irq);
512 entry = cfg->irq_2_pin;
514 entry = get_one_free_irq_2_pin();
515 cfg->irq_2_pin = entry;
518 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
522 while (entry->next) {
523 /* not again, please */
524 if (entry->apic == apic && entry->pin == pin)
530 entry->next = get_one_free_irq_2_pin();
534 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
538 * Reroute an IRQ to a different pin.
540 static void __init replace_pin_at_irq(unsigned int irq,
541 int oldapic, int oldpin,
542 int newapic, int newpin)
544 struct irq_cfg *cfg = irq_cfg(irq);
545 struct irq_pin_list *entry = cfg->irq_2_pin;
549 if (entry->apic == oldapic && entry->pin == oldpin) {
550 entry->apic = newapic;
553 /* every one is different, right? */
559 /* why? call replace before add? */
561 add_pin_to_irq(irq, newapic, newpin);
564 static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
567 struct irq_pin_list *entry;
568 unsigned int pin, reg;
571 entry = cfg->irq_2_pin;
576 reg = io_apic_read(entry->apic, 0x10 + pin*2);
579 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
587 static void __mask_IO_APIC_irq(unsigned int irq)
589 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
593 static void __unmask_IO_APIC_irq(unsigned int irq)
595 __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
598 /* mask = 1, trigger = 0 */
599 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
601 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
602 IO_APIC_REDIR_LEVEL_TRIGGER);
605 /* mask = 0, trigger = 1 */
606 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
608 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
609 IO_APIC_REDIR_MASKED);
612 static void mask_IO_APIC_irq(unsigned int irq)
616 spin_lock_irqsave(&ioapic_lock, flags);
617 __mask_IO_APIC_irq(irq);
618 spin_unlock_irqrestore(&ioapic_lock, flags);
621 static void unmask_IO_APIC_irq(unsigned int irq)
625 spin_lock_irqsave(&ioapic_lock, flags);
626 __unmask_IO_APIC_irq(irq);
627 spin_unlock_irqrestore(&ioapic_lock, flags);
630 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
632 struct IO_APIC_route_entry entry;
634 /* Check delivery_mode to be sure we're not clearing an SMI pin */
635 entry = ioapic_read_entry(apic, pin);
636 if (entry.delivery_mode == dest_SMI)
640 * Disable it in the IO-APIC irq-routing table:
642 ioapic_mask_entry(apic, pin);
645 static void clear_IO_APIC(void)
649 for (apic = 0; apic < nr_ioapics; apic++)
650 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
651 clear_IO_APIC_pin(apic, pin);
655 void send_IPI_self(int vector)
662 apic_wait_icr_idle();
663 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
665 * Send the IPI. The write to APIC_ICR fires this off.
667 apic_write(APIC_ICR, cfg);
669 #endif /* !CONFIG_SMP */
673 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
674 * specific CPU-side IRQs.
678 static int pirq_entries [MAX_PIRQS];
679 static int pirqs_enabled;
680 int skip_ioapic_setup;
682 static int __init ioapic_pirq_setup(char *str)
685 int ints[MAX_PIRQS+1];
687 get_options(str, ARRAY_SIZE(ints), ints);
689 for (i = 0; i < MAX_PIRQS; i++)
690 pirq_entries[i] = -1;
693 apic_printk(APIC_VERBOSE, KERN_INFO
694 "PIRQ redirection, working around broken MP-BIOS.\n");
696 if (ints[0] < MAX_PIRQS)
699 for (i = 0; i < max; i++) {
700 apic_printk(APIC_VERBOSE, KERN_DEBUG
701 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
703 * PIRQs are mapped upside down, usually.
705 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
710 __setup("pirq=", ioapic_pirq_setup);
713 * Find the IRQ entry number of a certain pin.
715 static int find_irq_entry(int apic, int pin, int type)
719 for (i = 0; i < mp_irq_entries; i++)
720 if (mp_irqs[i].mp_irqtype == type &&
721 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
722 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
723 mp_irqs[i].mp_dstirq == pin)
730 * Find the pin to which IRQ[irq] (ISA) is connected
732 static int __init find_isa_irq_pin(int irq, int type)
736 for (i = 0; i < mp_irq_entries; i++) {
737 int lbus = mp_irqs[i].mp_srcbus;
739 if (test_bit(lbus, mp_bus_not_pci) &&
740 (mp_irqs[i].mp_irqtype == type) &&
741 (mp_irqs[i].mp_srcbusirq == irq))
743 return mp_irqs[i].mp_dstirq;
748 static int __init find_isa_irq_apic(int irq, int type)
752 for (i = 0; i < mp_irq_entries; i++) {
753 int lbus = mp_irqs[i].mp_srcbus;
755 if (test_bit(lbus, mp_bus_not_pci) &&
756 (mp_irqs[i].mp_irqtype == type) &&
757 (mp_irqs[i].mp_srcbusirq == irq))
760 if (i < mp_irq_entries) {
762 for (apic = 0; apic < nr_ioapics; apic++) {
763 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
772 * Find a specific PCI IRQ entry.
773 * Not an __init, possibly needed by modules
775 static int pin_2_irq(int idx, int apic, int pin);
777 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
779 int apic, i, best_guess = -1;
781 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
782 "slot:%d, pin:%d.\n", bus, slot, pin);
783 if (test_bit(bus, mp_bus_not_pci)) {
784 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
787 for (i = 0; i < mp_irq_entries; i++) {
788 int lbus = mp_irqs[i].mp_srcbus;
790 for (apic = 0; apic < nr_ioapics; apic++)
791 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
792 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
795 if (!test_bit(lbus, mp_bus_not_pci) &&
796 !mp_irqs[i].mp_irqtype &&
798 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
799 int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
801 if (!(apic || IO_APIC_IRQ(irq)))
804 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
807 * Use the first all-but-pin matching entry as a
808 * best-guess fuzzy result for broken mptables.
816 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
818 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
820 * EISA Edge/Level control register, ELCR
822 static int EISA_ELCR(unsigned int irq)
825 unsigned int port = 0x4d0 + (irq >> 3);
826 return (inb(port) >> (irq & 7)) & 1;
828 apic_printk(APIC_VERBOSE, KERN_INFO
829 "Broken MPtable reports ISA irq %d\n", irq);
834 /* ISA interrupts are always polarity zero edge triggered,
835 * when listed as conforming in the MP table. */
837 #define default_ISA_trigger(idx) (0)
838 #define default_ISA_polarity(idx) (0)
840 /* EISA interrupts are always polarity zero and can be edge or level
841 * trigger depending on the ELCR value. If an interrupt is listed as
842 * EISA conforming in the MP table, that means its trigger type must
843 * be read in from the ELCR */
845 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
846 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
848 /* PCI interrupts are always polarity one level triggered,
849 * when listed as conforming in the MP table. */
851 #define default_PCI_trigger(idx) (1)
852 #define default_PCI_polarity(idx) (1)
854 /* MCA interrupts are always polarity zero level triggered,
855 * when listed as conforming in the MP table. */
857 #define default_MCA_trigger(idx) (1)
858 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
860 static int MPBIOS_polarity(int idx)
862 int bus = mp_irqs[idx].mp_srcbus;
866 * Determine IRQ line polarity (high active or low active):
868 switch (mp_irqs[idx].mp_irqflag & 3) {
869 case 0: /* conforms, ie. bus-type dependent polarity */
871 polarity = test_bit(bus, mp_bus_not_pci)?
872 default_ISA_polarity(idx):
873 default_PCI_polarity(idx);
876 case 1: /* high active */
881 case 2: /* reserved */
883 printk(KERN_WARNING "broken BIOS!!\n");
887 case 3: /* low active */
892 default: /* invalid */
894 printk(KERN_WARNING "broken BIOS!!\n");
902 static int MPBIOS_trigger(int idx)
904 int bus = mp_irqs[idx].mp_srcbus;
908 * Determine IRQ trigger mode (edge or level sensitive):
910 switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
911 case 0: /* conforms, ie. bus-type dependent */
913 trigger = test_bit(bus, mp_bus_not_pci)?
914 default_ISA_trigger(idx):
915 default_PCI_trigger(idx);
916 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
917 switch (mp_bus_id_to_type[bus]) {
918 case MP_BUS_ISA: /* ISA pin */
920 /* set before the switch */
923 case MP_BUS_EISA: /* EISA pin */
925 trigger = default_EISA_trigger(idx);
928 case MP_BUS_PCI: /* PCI pin */
930 /* set before the switch */
933 case MP_BUS_MCA: /* MCA pin */
935 trigger = default_MCA_trigger(idx);
940 printk(KERN_WARNING "broken BIOS!!\n");
953 case 2: /* reserved */
955 printk(KERN_WARNING "broken BIOS!!\n");
964 default: /* invalid */
966 printk(KERN_WARNING "broken BIOS!!\n");
974 static inline int irq_polarity(int idx)
976 return MPBIOS_polarity(idx);
979 static inline int irq_trigger(int idx)
981 return MPBIOS_trigger(idx);
984 static int pin_2_irq(int idx, int apic, int pin)
987 int bus = mp_irqs[idx].mp_srcbus;
990 * Debugging check, we are in big trouble if this message pops up!
992 if (mp_irqs[idx].mp_dstirq != pin)
993 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
995 if (test_bit(bus, mp_bus_not_pci))
996 irq = mp_irqs[idx].mp_srcbusirq;
999 * PCI IRQs are mapped in order
1003 irq += nr_ioapic_registers[i++];
1007 * For MPS mode, so far only needed by ES7000 platform
1009 if (ioapic_renumber_irq)
1010 irq = ioapic_renumber_irq(apic, irq);
1014 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1016 if ((pin >= 16) && (pin <= 23)) {
1017 if (pirq_entries[pin-16] != -1) {
1018 if (!pirq_entries[pin-16]) {
1019 apic_printk(APIC_VERBOSE, KERN_DEBUG
1020 "disabling PIRQ%d\n", pin-16);
1022 irq = pirq_entries[pin-16];
1023 apic_printk(APIC_VERBOSE, KERN_DEBUG
1024 "using PIRQ%d -> IRQ %d\n",
1032 void lock_vector_lock(void)
1034 /* Used to the online set of cpus does not change
1035 * during assign_irq_vector.
1037 spin_lock(&vector_lock);
1040 void unlock_vector_lock(void)
1042 spin_unlock(&vector_lock);
1045 static int __assign_irq_vector(int irq, cpumask_t mask)
1047 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1048 unsigned int old_vector;
1050 struct irq_cfg *cfg;
1054 /* Only try and allocate irqs on cpus that are present */
1055 cpus_and(mask, mask, cpu_online_map);
1057 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1060 old_vector = cfg->vector;
1063 cpus_and(tmp, cfg->domain, mask);
1064 if (!cpus_empty(tmp))
1068 for_each_cpu_mask_nr(cpu, mask) {
1069 cpumask_t domain, new_mask;
1073 domain = vector_allocation_domain(cpu);
1074 cpus_and(new_mask, domain, cpu_online_map);
1076 vector = current_vector;
1077 offset = current_offset;
1080 if (vector >= first_system_vector) {
1081 /* If we run out of vectors on large boxen, must share them. */
1082 offset = (offset + 1) % 8;
1083 vector = FIRST_DEVICE_VECTOR + offset;
1085 if (unlikely(current_vector == vector))
1087 if (vector == SYSCALL_VECTOR)
1090 for_each_cpu_mask_nr(new_cpu, new_mask)
1091 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1094 current_vector = vector;
1095 current_offset = offset;
1097 cfg->move_in_progress = 1;
1098 cfg->old_domain = cfg->domain;
1100 printk(KERN_DEBUG "assign_irq_vector: irq %d vector %#x cpu ", irq, vector);
1101 for_each_cpu_mask_nr(new_cpu, new_mask) {
1102 per_cpu(vector_irq, new_cpu)[vector] = irq;
1103 printk(KERN_CONT " %d ", new_cpu);
1105 printk(KERN_CONT "\n");
1106 cfg->vector = vector;
1107 cfg->domain = domain;
1113 static int assign_irq_vector(int irq, cpumask_t mask)
1116 unsigned long flags;
1118 spin_lock_irqsave(&vector_lock, flags);
1119 err = __assign_irq_vector(irq, mask);
1120 spin_unlock_irqrestore(&vector_lock, flags);
1125 static void __clear_irq_vector(int irq)
1127 struct irq_cfg *cfg;
1132 BUG_ON(!cfg->vector);
1134 vector = cfg->vector;
1135 cpus_and(mask, cfg->domain, cpu_online_map);
1136 for_each_cpu_mask_nr(cpu, mask)
1137 per_cpu(vector_irq, cpu)[vector] = -1;
1140 cpus_clear(cfg->domain);
1143 void __setup_vector_irq(int cpu)
1145 /* Initialize vector_irq on a new cpu */
1146 /* This function must be called with vector_lock held */
1148 struct irq_cfg *cfg;
1150 /* Mark the inuse vectors */
1151 for_each_irq_cfg(cfg) {
1152 if (!cpu_isset(cpu, cfg->domain))
1154 vector = cfg->vector;
1156 per_cpu(vector_irq, cpu)[vector] = irq;
1158 /* Mark the free vectors */
1159 for (vector = 0; vector < NR_VECTORS; ++vector) {
1160 irq = per_cpu(vector_irq, cpu)[vector];
1165 if (!cpu_isset(cpu, cfg->domain))
1166 per_cpu(vector_irq, cpu)[vector] = -1;
1170 static struct irq_chip ioapic_chip;
1172 #define IOAPIC_AUTO -1
1173 #define IOAPIC_EDGE 0
1174 #define IOAPIC_LEVEL 1
1176 static inline int IO_APIC_irq_trigger(int irq)
1180 for (apic = 0; apic < nr_ioapics; apic++) {
1181 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1182 idx = find_irq_entry(apic, pin, mp_INT);
1183 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1184 return irq_trigger(idx);
1188 * nonexistent IRQs are edge default
1193 static void ioapic_register_intr(int irq, unsigned long trigger)
1195 struct irq_desc *desc;
1197 /* first time to use this irq_desc */
1199 desc = irq_to_desc(irq);
1201 desc = irq_to_desc_alloc(irq);
1203 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1204 trigger == IOAPIC_LEVEL) {
1205 desc->status |= IRQ_LEVEL;
1206 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1207 handle_fasteoi_irq, "fasteoi");
1209 desc->status &= ~IRQ_LEVEL;
1210 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1211 handle_edge_irq, "edge");
1215 static int setup_ioapic_entry(int apic, int irq,
1216 struct IO_APIC_route_entry *entry,
1217 unsigned int destination, int trigger,
1218 int polarity, int vector)
1221 * add it to the IO-APIC irq-routing table:
1223 memset(entry,0,sizeof(*entry));
1225 entry->delivery_mode = INT_DELIVERY_MODE;
1226 entry->dest_mode = INT_DEST_MODE;
1227 entry->dest = destination;
1229 entry->mask = 0; /* enable IRQ */
1230 entry->trigger = trigger;
1231 entry->polarity = polarity;
1232 entry->vector = vector;
1234 /* Mask level triggered irqs.
1235 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1243 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1244 int trigger, int polarity)
1246 struct irq_cfg *cfg;
1247 struct IO_APIC_route_entry entry;
1250 if (!IO_APIC_IRQ(irq))
1256 if (assign_irq_vector(irq, mask))
1259 cpus_and(mask, cfg->domain, mask);
1261 apic_printk(APIC_VERBOSE,KERN_DEBUG
1262 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1263 "IRQ %d Mode:%i Active:%i)\n",
1264 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1265 irq, trigger, polarity);
1268 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1269 cpu_mask_to_apicid(mask), trigger, polarity,
1271 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1272 mp_ioapics[apic].mp_apicid, pin);
1273 __clear_irq_vector(irq);
1277 ioapic_register_intr(irq, trigger);
1279 disable_8259A_irq(irq);
1281 ioapic_write_entry(apic, pin, entry);
1284 static void __init setup_IO_APIC_irqs(void)
1286 int apic, pin, idx, irq, first_notcon = 1;
1288 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1290 for (apic = 0; apic < nr_ioapics; apic++) {
1291 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1293 idx = find_irq_entry(apic,pin,mp_INT);
1296 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1299 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1302 if (!first_notcon) {
1303 apic_printk(APIC_VERBOSE, " not connected.\n");
1307 irq = pin_2_irq(idx, apic, pin);
1309 if (multi_timer_check(apic, irq))
1312 add_pin_to_irq(irq, apic, pin);
1314 setup_IO_APIC_irq(apic, pin, irq,
1315 irq_trigger(idx), irq_polarity(idx));
1320 apic_printk(APIC_VERBOSE, " not connected.\n");
1324 * Set up the timer pin, possibly with the 8259A-master behind.
1326 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1329 struct IO_APIC_route_entry entry;
1331 memset(&entry, 0, sizeof(entry));
1334 * We use logical delivery to get the timer IRQ
1337 entry.dest_mode = INT_DEST_MODE;
1338 entry.mask = 1; /* mask IRQ now */
1339 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1340 entry.delivery_mode = INT_DELIVERY_MODE;
1343 entry.vector = vector;
1346 * The timer IRQ doesn't have to know that behind the
1347 * scene we may have a 8259A-master in AEOI mode ...
1349 ioapic_register_intr(0, IOAPIC_EDGE);
1352 * Add it to the IO-APIC irq-routing table:
1354 ioapic_write_entry(apic, pin, entry);
1358 __apicdebuginit(void) print_IO_APIC(void)
1361 union IO_APIC_reg_00 reg_00;
1362 union IO_APIC_reg_01 reg_01;
1363 union IO_APIC_reg_02 reg_02;
1364 union IO_APIC_reg_03 reg_03;
1365 unsigned long flags;
1366 struct irq_cfg *cfg;
1368 if (apic_verbosity == APIC_QUIET)
1371 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1372 for (i = 0; i < nr_ioapics; i++)
1373 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1374 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1377 * We are a bit conservative about what we expect. We have to
1378 * know about every hardware change ASAP.
1380 printk(KERN_INFO "testing the IO APIC.......................\n");
1382 for (apic = 0; apic < nr_ioapics; apic++) {
1384 spin_lock_irqsave(&ioapic_lock, flags);
1385 reg_00.raw = io_apic_read(apic, 0);
1386 reg_01.raw = io_apic_read(apic, 1);
1387 if (reg_01.bits.version >= 0x10)
1388 reg_02.raw = io_apic_read(apic, 2);
1389 if (reg_01.bits.version >= 0x20)
1390 reg_03.raw = io_apic_read(apic, 3);
1391 spin_unlock_irqrestore(&ioapic_lock, flags);
1393 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1394 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1395 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1396 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1397 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1399 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1400 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1402 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1403 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1406 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1407 * but the value of reg_02 is read as the previous read register
1408 * value, so ignore it if reg_02 == reg_01.
1410 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1411 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1412 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1416 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1417 * or reg_03, but the value of reg_0[23] is read as the previous read
1418 * register value, so ignore it if reg_03 == reg_0[12].
1420 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1421 reg_03.raw != reg_01.raw) {
1422 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1423 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1426 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1428 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1429 " Stat Dmod Deli Vect: \n");
1431 for (i = 0; i <= reg_01.bits.entries; i++) {
1432 struct IO_APIC_route_entry entry;
1434 entry = ioapic_read_entry(apic, i);
1436 printk(KERN_DEBUG " %02x %02X ", i, entry.dest);
1438 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1443 entry.delivery_status,
1445 entry.delivery_mode,
1450 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1451 for_each_irq_cfg(cfg) {
1452 struct irq_pin_list *entry = cfg->irq_2_pin;
1455 printk(KERN_DEBUG "IRQ%d ", i);
1457 printk("-> %d:%d", entry->apic, entry->pin);
1460 entry = entry->next;
1465 printk(KERN_INFO ".................................... done.\n");
1470 __apicdebuginit(void) print_APIC_bitfield(int base)
1475 if (apic_verbosity == APIC_QUIET)
1478 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1479 for (i = 0; i < 8; i++) {
1480 v = apic_read(base + i*0x10);
1481 for (j = 0; j < 32; j++) {
1491 __apicdebuginit(void) print_local_APIC(void *dummy)
1493 unsigned int v, ver, maxlvt;
1496 if (apic_verbosity == APIC_QUIET)
1499 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1500 smp_processor_id(), hard_smp_processor_id());
1501 v = apic_read(APIC_ID);
1502 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
1504 v = apic_read(APIC_LVR);
1505 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1506 ver = GET_APIC_VERSION(v);
1507 maxlvt = lapic_get_maxlvt();
1509 v = apic_read(APIC_TASKPRI);
1510 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1512 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1513 v = apic_read(APIC_ARBPRI);
1514 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1515 v & APIC_ARBPRI_MASK);
1516 v = apic_read(APIC_PROCPRI);
1517 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1520 v = apic_read(APIC_EOI);
1521 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1522 v = apic_read(APIC_RRR);
1523 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1524 v = apic_read(APIC_LDR);
1525 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1526 v = apic_read(APIC_DFR);
1527 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1528 v = apic_read(APIC_SPIV);
1529 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1531 printk(KERN_DEBUG "... APIC ISR field:\n");
1532 print_APIC_bitfield(APIC_ISR);
1533 printk(KERN_DEBUG "... APIC TMR field:\n");
1534 print_APIC_bitfield(APIC_TMR);
1535 printk(KERN_DEBUG "... APIC IRR field:\n");
1536 print_APIC_bitfield(APIC_IRR);
1538 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1539 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1540 apic_write(APIC_ESR, 0);
1541 v = apic_read(APIC_ESR);
1542 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1545 icr = apic_icr_read();
1546 printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
1547 printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
1549 v = apic_read(APIC_LVTT);
1550 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1552 if (maxlvt > 3) { /* PC is LVT#4. */
1553 v = apic_read(APIC_LVTPC);
1554 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1556 v = apic_read(APIC_LVT0);
1557 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1558 v = apic_read(APIC_LVT1);
1559 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1561 if (maxlvt > 2) { /* ERR is LVT#3. */
1562 v = apic_read(APIC_LVTERR);
1563 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1566 v = apic_read(APIC_TMICT);
1567 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1568 v = apic_read(APIC_TMCCT);
1569 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1570 v = apic_read(APIC_TDCR);
1571 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1575 __apicdebuginit(void) print_all_local_APICs(void)
1577 on_each_cpu(print_local_APIC, NULL, 1);
1580 __apicdebuginit(void) print_PIC(void)
1583 unsigned long flags;
1585 if (apic_verbosity == APIC_QUIET)
1588 printk(KERN_DEBUG "\nprinting PIC contents\n");
1590 spin_lock_irqsave(&i8259A_lock, flags);
1592 v = inb(0xa1) << 8 | inb(0x21);
1593 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1595 v = inb(0xa0) << 8 | inb(0x20);
1596 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1600 v = inb(0xa0) << 8 | inb(0x20);
1604 spin_unlock_irqrestore(&i8259A_lock, flags);
1606 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1608 v = inb(0x4d1) << 8 | inb(0x4d0);
1609 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1612 __apicdebuginit(int) print_all_ICs(void)
1615 print_all_local_APICs();
1621 fs_initcall(print_all_ICs);
1624 static void __init enable_IO_APIC(void)
1626 union IO_APIC_reg_01 reg_01;
1627 int i8259_apic, i8259_pin;
1629 unsigned long flags;
1632 for (i = 0; i < MAX_PIRQS; i++)
1633 pirq_entries[i] = -1;
1636 * The number of IO-APIC IRQ registers (== #pins):
1638 for (apic = 0; apic < nr_ioapics; apic++) {
1639 spin_lock_irqsave(&ioapic_lock, flags);
1640 reg_01.raw = io_apic_read(apic, 1);
1641 spin_unlock_irqrestore(&ioapic_lock, flags);
1642 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1644 for (apic = 0; apic < nr_ioapics; apic++) {
1646 /* See if any of the pins is in ExtINT mode */
1647 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1648 struct IO_APIC_route_entry entry;
1649 entry = ioapic_read_entry(apic, pin);
1652 /* If the interrupt line is enabled and in ExtInt mode
1653 * I have found the pin where the i8259 is connected.
1655 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1656 ioapic_i8259.apic = apic;
1657 ioapic_i8259.pin = pin;
1663 /* Look to see what if the MP table has reported the ExtINT */
1664 /* If we could not find the appropriate pin by looking at the ioapic
1665 * the i8259 probably is not connected the ioapic but give the
1666 * mptable a chance anyway.
1668 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1669 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1670 /* Trust the MP table if nothing is setup in the hardware */
1671 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1672 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1673 ioapic_i8259.pin = i8259_pin;
1674 ioapic_i8259.apic = i8259_apic;
1676 /* Complain if the MP table and the hardware disagree */
1677 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1678 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1680 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1684 * Do not trust the IO-APIC being empty at bootup
1690 * Not an __init, needed by the reboot code
1692 void disable_IO_APIC(void)
1695 * Clear the IO-APIC before rebooting:
1700 * If the i8259 is routed through an IOAPIC
1701 * Put that IOAPIC in virtual wire mode
1702 * so legacy interrupts can be delivered.
1704 if (ioapic_i8259.pin != -1) {
1705 struct IO_APIC_route_entry entry;
1707 memset(&entry, 0, sizeof(entry));
1708 entry.mask = 0; /* Enabled */
1709 entry.trigger = 0; /* Edge */
1711 entry.polarity = 0; /* High */
1712 entry.delivery_status = 0;
1713 entry.dest_mode = 0; /* Physical */
1714 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1716 entry.dest = read_apic_id();
1719 * Add it to the IO-APIC irq-routing table:
1721 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1723 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1727 * function to set the IO-APIC physical IDs based on the
1728 * values stored in the MPC table.
1730 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1733 static void __init setup_ioapic_ids_from_mpc(void)
1735 union IO_APIC_reg_00 reg_00;
1736 physid_mask_t phys_id_present_map;
1739 unsigned char old_id;
1740 unsigned long flags;
1742 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1746 * Don't check I/O APIC IDs for xAPIC systems. They have
1747 * no meaning without the serial APIC bus.
1749 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1750 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1753 * This is broken; anything with a real cpu count has to
1754 * circumvent this idiocy regardless.
1756 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1759 * Set the IOAPIC ID to the value stored in the MPC table.
1761 for (apic = 0; apic < nr_ioapics; apic++) {
1763 /* Read the register 0 value */
1764 spin_lock_irqsave(&ioapic_lock, flags);
1765 reg_00.raw = io_apic_read(apic, 0);
1766 spin_unlock_irqrestore(&ioapic_lock, flags);
1768 old_id = mp_ioapics[apic].mp_apicid;
1770 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1771 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1772 apic, mp_ioapics[apic].mp_apicid);
1773 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1775 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1779 * Sanity check, is the ID really free? Every APIC in a
1780 * system must have a unique ID or we get lots of nice
1781 * 'stuck on smp_invalidate_needed IPI wait' messages.
1783 if (check_apicid_used(phys_id_present_map,
1784 mp_ioapics[apic].mp_apicid)) {
1785 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1786 apic, mp_ioapics[apic].mp_apicid);
1787 for (i = 0; i < get_physical_broadcast(); i++)
1788 if (!physid_isset(i, phys_id_present_map))
1790 if (i >= get_physical_broadcast())
1791 panic("Max APIC ID exceeded!\n");
1792 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1794 physid_set(i, phys_id_present_map);
1795 mp_ioapics[apic].mp_apicid = i;
1798 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1799 apic_printk(APIC_VERBOSE, "Setting %d in the "
1800 "phys_id_present_map\n",
1801 mp_ioapics[apic].mp_apicid);
1802 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1807 * We need to adjust the IRQ routing table
1808 * if the ID changed.
1810 if (old_id != mp_ioapics[apic].mp_apicid)
1811 for (i = 0; i < mp_irq_entries; i++)
1812 if (mp_irqs[i].mp_dstapic == old_id)
1813 mp_irqs[i].mp_dstapic
1814 = mp_ioapics[apic].mp_apicid;
1817 * Read the right value from the MPC table and
1818 * write it into the ID register.
1820 apic_printk(APIC_VERBOSE, KERN_INFO
1821 "...changing IO-APIC physical APIC ID to %d ...",
1822 mp_ioapics[apic].mp_apicid);
1824 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1825 spin_lock_irqsave(&ioapic_lock, flags);
1826 io_apic_write(apic, 0, reg_00.raw);
1827 spin_unlock_irqrestore(&ioapic_lock, flags);
1832 spin_lock_irqsave(&ioapic_lock, flags);
1833 reg_00.raw = io_apic_read(apic, 0);
1834 spin_unlock_irqrestore(&ioapic_lock, flags);
1835 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1836 printk("could not set ID!\n");
1838 apic_printk(APIC_VERBOSE, " ok.\n");
1842 int no_timer_check __initdata;
1844 static int __init notimercheck(char *s)
1849 __setup("no_timer_check", notimercheck);
1852 * There is a nasty bug in some older SMP boards, their mptable lies
1853 * about the timer IRQ. We do the following to work around the situation:
1855 * - timer IRQ defaults to IO-APIC IRQ
1856 * - if this function detects that timer IRQs are defunct, then we fall
1857 * back to ISA timer IRQs
1859 static int __init timer_irq_works(void)
1861 unsigned long t1 = jiffies;
1862 unsigned long flags;
1867 local_save_flags(flags);
1869 /* Let ten ticks pass... */
1870 mdelay((10 * 1000) / HZ);
1871 local_irq_restore(flags);
1874 * Expect a few ticks at least, to be sure some possible
1875 * glue logic does not lock up after one or two first
1876 * ticks in a non-ExtINT mode. Also the local APIC
1877 * might have cached one ExtINT interrupt. Finally, at
1878 * least one tick may be lost due to delays.
1880 if (time_after(jiffies, t1 + 4))
1887 * In the SMP+IOAPIC case it might happen that there are an unspecified
1888 * number of pending IRQ events unhandled. These cases are very rare,
1889 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1890 * better to do it this way as thus we do not have to be aware of
1891 * 'pending' interrupts in the IRQ path, except at this point.
1894 * Edge triggered needs to resend any interrupt
1895 * that was delayed but this is now handled in the device
1902 * Starting up a edge-triggered IO-APIC interrupt is
1903 * nasty - we need to make sure that we get the edge.
1904 * If it is already asserted for some reason, we need
1905 * return 1 to indicate that is was pending.
1907 * This is not complete - we should be able to fake
1908 * an edge even if it isn't on the 8259A...
1910 * (We do this for level-triggered IRQs too - it cannot hurt.)
1912 static unsigned int startup_ioapic_irq(unsigned int irq)
1914 int was_pending = 0;
1915 unsigned long flags;
1917 spin_lock_irqsave(&ioapic_lock, flags);
1919 disable_8259A_irq(irq);
1920 if (i8259A_irq_pending(irq))
1923 __unmask_IO_APIC_irq(irq);
1924 spin_unlock_irqrestore(&ioapic_lock, flags);
1929 static int ioapic_retrigger_irq(unsigned int irq)
1931 send_IPI_self(irq_cfg(irq)->vector);
1937 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1939 unsigned vector, me;
1943 me = smp_processor_id();
1944 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1946 struct irq_desc *desc;
1947 struct irq_cfg *cfg;
1948 irq = __get_cpu_var(vector_irq)[vector];
1950 desc = irq_to_desc(irq);
1955 spin_lock(&desc->lock);
1956 if (!cfg->move_cleanup_count)
1959 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1962 __get_cpu_var(vector_irq)[vector] = -1;
1963 cfg->move_cleanup_count--;
1965 spin_unlock(&desc->lock);
1971 static void irq_complete_move(unsigned int irq)
1973 struct irq_cfg *cfg = irq_cfg(irq);
1974 unsigned vector, me;
1976 if (likely(!cfg->move_in_progress))
1979 vector = ~get_irq_regs()->orig_ax;
1980 me = smp_processor_id();
1981 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1982 cpumask_t cleanup_mask;
1984 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1985 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1986 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1987 cfg->move_in_progress = 0;
1991 static inline void irq_complete_move(unsigned int irq) {}
1994 static void ack_apic_edge(unsigned int irq)
1996 irq_complete_move(irq);
1997 move_native_irq(irq);
2001 static void ack_apic_level(unsigned int irq)
2006 irq_complete_move(irq);
2007 move_native_irq(irq);
2009 * It appears there is an erratum which affects at least version 0x11
2010 * of I/O APIC (that's the 82093AA and cores integrated into various
2011 * chipsets). Under certain conditions a level-triggered interrupt is
2012 * erroneously delivered as edge-triggered one but the respective IRR
2013 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2014 * message but it will never arrive and further interrupts are blocked
2015 * from the source. The exact reason is so far unknown, but the
2016 * phenomenon was observed when two consecutive interrupt requests
2017 * from a given source get delivered to the same CPU and the source is
2018 * temporarily disabled in between.
2020 * A workaround is to simulate an EOI message manually. We achieve it
2021 * by setting the trigger mode to edge and then to level when the edge
2022 * trigger mode gets detected in the TMR of a local APIC for a
2023 * level-triggered interrupt. We mask the source for the time of the
2024 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2025 * The idea is from Manfred Spraul. --macro
2027 i = irq_cfg(irq)->vector;
2029 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2033 if (!(v & (1 << (i & 0x1f)))) {
2034 atomic_inc(&irq_mis_count);
2035 spin_lock(&ioapic_lock);
2036 __mask_and_edge_IO_APIC_irq(irq);
2037 __unmask_and_level_IO_APIC_irq(irq);
2038 spin_unlock(&ioapic_lock);
2042 static struct irq_chip ioapic_chip __read_mostly = {
2044 .startup = startup_ioapic_irq,
2045 .mask = mask_IO_APIC_irq,
2046 .unmask = unmask_IO_APIC_irq,
2047 .ack = ack_apic_edge,
2048 .eoi = ack_apic_level,
2050 .set_affinity = set_ioapic_affinity_irq,
2052 .retrigger = ioapic_retrigger_irq,
2056 static inline void init_IO_APIC_traps(void)
2059 struct irq_desc *desc;
2060 struct irq_cfg *cfg;
2063 * NOTE! The local APIC isn't very good at handling
2064 * multiple interrupts at the same interrupt level.
2065 * As the interrupt level is determined by taking the
2066 * vector number and shifting that right by 4, we
2067 * want to spread these out a bit so that they don't
2068 * all fall in the same interrupt level.
2070 * Also, we've got to be careful not to trash gate
2071 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2073 for_each_irq_cfg(cfg) {
2075 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2077 * Hmm.. We don't have an entry for this,
2078 * so default to an old-fashioned 8259
2079 * interrupt if we can..
2082 make_8259A_irq(irq);
2084 desc = irq_to_desc(irq);
2085 /* Strange. Oh, well.. */
2086 desc->chip = &no_irq_chip;
2093 * The local APIC irq-chip implementation:
2096 static void mask_lapic_irq(unsigned int irq)
2100 v = apic_read(APIC_LVT0);
2101 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2104 static void unmask_lapic_irq(unsigned int irq)
2108 v = apic_read(APIC_LVT0);
2109 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2112 static void ack_lapic_irq(unsigned int irq)
2117 static struct irq_chip lapic_chip __read_mostly = {
2118 .name = "local-APIC",
2119 .mask = mask_lapic_irq,
2120 .unmask = unmask_lapic_irq,
2121 .ack = ack_lapic_irq,
2124 static void lapic_register_intr(int irq)
2126 struct irq_desc *desc;
2128 desc = irq_to_desc(irq);
2129 desc->status &= ~IRQ_LEVEL;
2130 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2134 static void __init setup_nmi(void)
2137 * Dirty trick to enable the NMI watchdog ...
2138 * We put the 8259A master into AEOI mode and
2139 * unmask on all local APICs LVT0 as NMI.
2141 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2142 * is from Maciej W. Rozycki - so we do not have to EOI from
2143 * the NMI handler or the timer interrupt.
2145 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2147 enable_NMI_through_LVT0();
2149 apic_printk(APIC_VERBOSE, " done.\n");
2153 * This looks a bit hackish but it's about the only one way of sending
2154 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2155 * not support the ExtINT mode, unfortunately. We need to send these
2156 * cycles as some i82489DX-based boards have glue logic that keeps the
2157 * 8259A interrupt line asserted until INTA. --macro
2159 static inline void __init unlock_ExtINT_logic(void)
2162 struct IO_APIC_route_entry entry0, entry1;
2163 unsigned char save_control, save_freq_select;
2165 pin = find_isa_irq_pin(8, mp_INT);
2170 apic = find_isa_irq_apic(8, mp_INT);
2176 entry0 = ioapic_read_entry(apic, pin);
2177 clear_IO_APIC_pin(apic, pin);
2179 memset(&entry1, 0, sizeof(entry1));
2181 entry1.dest_mode = 0; /* physical delivery */
2182 entry1.mask = 0; /* unmask IRQ now */
2183 entry1.dest = hard_smp_processor_id();
2184 entry1.delivery_mode = dest_ExtINT;
2185 entry1.polarity = entry0.polarity;
2189 ioapic_write_entry(apic, pin, entry1);
2191 save_control = CMOS_READ(RTC_CONTROL);
2192 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2193 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2195 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2200 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2204 CMOS_WRITE(save_control, RTC_CONTROL);
2205 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2206 clear_IO_APIC_pin(apic, pin);
2208 ioapic_write_entry(apic, pin, entry0);
2212 * This code may look a bit paranoid, but it's supposed to cooperate with
2213 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2214 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2215 * fanatically on his truly buggy board.
2217 static inline void __init check_timer(void)
2219 struct irq_cfg *cfg = irq_cfg(0);
2220 int apic1, pin1, apic2, pin2;
2223 unsigned long flags;
2225 local_irq_save(flags);
2227 ver = apic_read(APIC_LVR);
2228 ver = GET_APIC_VERSION(ver);
2231 * get/set the timer IRQ vector:
2233 disable_8259A_irq(0);
2234 assign_irq_vector(0, TARGET_CPUS);
2237 * As IRQ0 is to be enabled in the 8259A, the virtual
2238 * wire has to be disabled in the local APIC. Also
2239 * timer interrupts need to be acknowledged manually in
2240 * the 8259A for the i82489DX when using the NMI
2241 * watchdog as that APIC treats NMIs as level-triggered.
2242 * The AEOI mode will finish them in the 8259A
2245 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2247 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2249 pin1 = find_isa_irq_pin(0, mp_INT);
2250 apic1 = find_isa_irq_apic(0, mp_INT);
2251 pin2 = ioapic_i8259.pin;
2252 apic2 = ioapic_i8259.apic;
2254 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2255 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2256 cfg->vector, apic1, pin1, apic2, pin2);
2259 * Some BIOS writers are clueless and report the ExtINTA
2260 * I/O APIC input from the cascaded 8259A as the timer
2261 * interrupt input. So just in case, if only one pin
2262 * was found above, try it both directly and through the
2269 } else if (pin2 == -1) {
2276 * Ok, does IRQ0 through the IOAPIC work?
2279 add_pin_to_irq(0, apic1, pin1);
2280 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2282 unmask_IO_APIC_irq(0);
2283 if (timer_irq_works()) {
2284 if (nmi_watchdog == NMI_IO_APIC) {
2286 enable_8259A_irq(0);
2288 if (disable_timer_pin_1 > 0)
2289 clear_IO_APIC_pin(0, pin1);
2292 clear_IO_APIC_pin(apic1, pin1);
2294 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2295 "8254 timer not connected to IO-APIC\n");
2297 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2298 "(IRQ0) through the 8259A ...\n");
2299 apic_printk(APIC_QUIET, KERN_INFO
2300 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2302 * legacy devices should be connected to IO APIC #0
2304 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2305 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2306 unmask_IO_APIC_irq(0);
2307 enable_8259A_irq(0);
2308 if (timer_irq_works()) {
2309 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2310 timer_through_8259 = 1;
2311 if (nmi_watchdog == NMI_IO_APIC) {
2312 disable_8259A_irq(0);
2314 enable_8259A_irq(0);
2319 * Cleanup, just in case ...
2321 disable_8259A_irq(0);
2322 clear_IO_APIC_pin(apic2, pin2);
2323 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2326 if (nmi_watchdog == NMI_IO_APIC) {
2327 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2328 "through the IO-APIC - disabling NMI Watchdog!\n");
2329 nmi_watchdog = NMI_NONE;
2333 apic_printk(APIC_QUIET, KERN_INFO
2334 "...trying to set up timer as Virtual Wire IRQ...\n");
2336 lapic_register_intr(0);
2337 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2338 enable_8259A_irq(0);
2340 if (timer_irq_works()) {
2341 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2344 disable_8259A_irq(0);
2345 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2346 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2348 apic_printk(APIC_QUIET, KERN_INFO
2349 "...trying to set up timer as ExtINT IRQ...\n");
2353 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2355 unlock_ExtINT_logic();
2357 if (timer_irq_works()) {
2358 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2361 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2362 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2363 "report. Then try booting with the 'noapic' option.\n");
2365 local_irq_restore(flags);
2369 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2370 * to devices. However there may be an I/O APIC pin available for
2371 * this interrupt regardless. The pin may be left unconnected, but
2372 * typically it will be reused as an ExtINT cascade interrupt for
2373 * the master 8259A. In the MPS case such a pin will normally be
2374 * reported as an ExtINT interrupt in the MP table. With ACPI
2375 * there is no provision for ExtINT interrupts, and in the absence
2376 * of an override it would be treated as an ordinary ISA I/O APIC
2377 * interrupt, that is edge-triggered and unmasked by default. We
2378 * used to do this, but it caused problems on some systems because
2379 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2380 * the same ExtINT cascade interrupt to drive the local APIC of the
2381 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2382 * the I/O APIC in all cases now. No actual device should request
2383 * it anyway. --macro
2385 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2387 void __init setup_IO_APIC(void)
2391 io_apic_irqs = ~PIC_IRQS;
2393 printk("ENABLING IO-APIC IRQs\n");
2396 * Set up IO-APIC IRQ routing.
2399 setup_ioapic_ids_from_mpc();
2401 setup_IO_APIC_irqs();
2402 init_IO_APIC_traps();
2407 * Called after all the initialization is done. If we didnt find any
2408 * APIC bugs then we can allow the modify fast path
2411 static int __init io_apic_bug_finalize(void)
2413 if (sis_apic_bug == -1)
2418 late_initcall(io_apic_bug_finalize);
2420 struct sysfs_ioapic_data {
2421 struct sys_device dev;
2422 struct IO_APIC_route_entry entry[0];
2424 static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2426 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2428 struct IO_APIC_route_entry *entry;
2429 struct sysfs_ioapic_data *data;
2432 data = container_of(dev, struct sysfs_ioapic_data, dev);
2433 entry = data->entry;
2434 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2435 entry[i] = ioapic_read_entry(dev->id, i);
2440 static int ioapic_resume(struct sys_device *dev)
2442 struct IO_APIC_route_entry *entry;
2443 struct sysfs_ioapic_data *data;
2444 unsigned long flags;
2445 union IO_APIC_reg_00 reg_00;
2448 data = container_of(dev, struct sysfs_ioapic_data, dev);
2449 entry = data->entry;
2451 spin_lock_irqsave(&ioapic_lock, flags);
2452 reg_00.raw = io_apic_read(dev->id, 0);
2453 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2454 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2455 io_apic_write(dev->id, 0, reg_00.raw);
2457 spin_unlock_irqrestore(&ioapic_lock, flags);
2458 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2459 ioapic_write_entry(dev->id, i, entry[i]);
2464 static struct sysdev_class ioapic_sysdev_class = {
2466 .suspend = ioapic_suspend,
2467 .resume = ioapic_resume,
2470 static int __init ioapic_init_sysfs(void)
2472 struct sys_device *dev;
2473 int i, size, error = 0;
2475 error = sysdev_class_register(&ioapic_sysdev_class);
2479 for (i = 0; i < nr_ioapics; i++) {
2480 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2481 * sizeof(struct IO_APIC_route_entry);
2482 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2483 if (!mp_ioapic_data[i]) {
2484 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2487 dev = &mp_ioapic_data[i]->dev;
2489 dev->cls = &ioapic_sysdev_class;
2490 error = sysdev_register(dev);
2492 kfree(mp_ioapic_data[i]);
2493 mp_ioapic_data[i] = NULL;
2494 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2502 device_initcall(ioapic_init_sysfs);
2505 * Dynamic irq allocate and deallocation
2507 unsigned int create_irq_nr(unsigned int irq_want)
2509 /* Allocate an unused irq */
2510 unsigned int irq, new;
2511 unsigned long flags;
2512 struct irq_cfg *cfg_new;
2514 #ifndef CONFIG_HAVE_SPARSE_IRQ
2515 /* only can use bus/dev/fn.. when per_cpu vector is used */
2516 irq_want = nr_irqs - 1;
2520 spin_lock_irqsave(&vector_lock, flags);
2521 for (new = (nr_irqs - 1); new > 0; new--) {
2522 if (platform_legacy_irq(new))
2524 cfg_new = irq_cfg(new);
2525 if (cfg_new && cfg_new->vector != 0)
2528 cfg_new = irq_cfg_alloc(new);
2529 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2533 spin_unlock_irqrestore(&vector_lock, flags);
2536 dynamic_irq_init(irq);
2541 int create_irq(void)
2543 return create_irq_nr(nr_irqs - 1);
2546 void destroy_irq(unsigned int irq)
2548 unsigned long flags;
2550 dynamic_irq_cleanup(irq);
2552 spin_lock_irqsave(&vector_lock, flags);
2553 __clear_irq_vector(irq);
2554 spin_unlock_irqrestore(&vector_lock, flags);
2558 * MSI message composition
2560 #ifdef CONFIG_PCI_MSI
2561 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2563 struct irq_cfg *cfg;
2569 err = assign_irq_vector(irq, tmp);
2574 cpus_and(tmp, cfg->domain, tmp);
2575 dest = cpu_mask_to_apicid(tmp);
2577 msg->address_hi = MSI_ADDR_BASE_HI;
2580 ((INT_DEST_MODE == 0) ?
2581 MSI_ADDR_DEST_MODE_PHYSICAL:
2582 MSI_ADDR_DEST_MODE_LOGICAL) |
2583 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2584 MSI_ADDR_REDIRECTION_CPU:
2585 MSI_ADDR_REDIRECTION_LOWPRI) |
2586 MSI_ADDR_DEST_ID(dest);
2589 MSI_DATA_TRIGGER_EDGE |
2590 MSI_DATA_LEVEL_ASSERT |
2591 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2592 MSI_DATA_DELIVERY_FIXED:
2593 MSI_DATA_DELIVERY_LOWPRI) |
2594 MSI_DATA_VECTOR(cfg->vector);
2600 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2602 struct irq_cfg *cfg;
2607 cpus_and(tmp, mask, cpu_online_map);
2608 if (cpus_empty(tmp))
2611 if (assign_irq_vector(irq, mask))
2615 cpus_and(tmp, cfg->domain, mask);
2616 dest = cpu_mask_to_apicid(tmp);
2618 read_msi_msg(irq, &msg);
2620 msg.data &= ~MSI_DATA_VECTOR_MASK;
2621 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2622 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2623 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2625 write_msi_msg(irq, &msg);
2626 irq_to_desc(irq)->affinity = mask;
2628 #endif /* CONFIG_SMP */
2631 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2632 * which implement the MSI or MSI-X Capability Structure.
2634 static struct irq_chip msi_chip = {
2636 .unmask = unmask_msi_irq,
2637 .mask = mask_msi_irq,
2638 .ack = ack_apic_edge,
2640 .set_affinity = set_msi_irq_affinity,
2642 .retrigger = ioapic_retrigger_irq,
2646 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2651 ret = msi_compose_msg(dev, irq, &msg);
2655 set_irq_msi(irq, desc);
2656 write_msi_msg(irq, &msg);
2658 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2663 static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
2667 irq = dev->bus->number;
2675 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2679 unsigned int irq_want;
2681 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2683 irq = create_irq_nr(irq_want);
2688 ret = setup_msi_irq(dev, desc, irq);
2697 void arch_teardown_msi_irq(unsigned int irq)
2702 #endif /* CONFIG_PCI_MSI */
2705 * Hypertransport interrupt support
2707 #ifdef CONFIG_HT_IRQ
2711 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2713 struct ht_irq_msg msg;
2714 fetch_ht_irq_msg(irq, &msg);
2716 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2717 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2719 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2720 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2722 write_ht_irq_msg(irq, &msg);
2725 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2727 struct irq_cfg *cfg;
2731 cpus_and(tmp, mask, cpu_online_map);
2732 if (cpus_empty(tmp))
2735 if (assign_irq_vector(irq, mask))
2739 cpus_and(tmp, cfg->domain, mask);
2740 dest = cpu_mask_to_apicid(tmp);
2742 target_ht_irq(irq, dest, cfg->vector);
2743 irq_to_desc(irq)->affinity = mask;
2747 static struct irq_chip ht_irq_chip = {
2749 .mask = mask_ht_irq,
2750 .unmask = unmask_ht_irq,
2751 .ack = ack_apic_edge,
2753 .set_affinity = set_ht_irq_affinity,
2755 .retrigger = ioapic_retrigger_irq,
2758 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2760 struct irq_cfg *cfg;
2765 err = assign_irq_vector(irq, tmp);
2767 struct ht_irq_msg msg;
2771 cpus_and(tmp, cfg->domain, tmp);
2772 dest = cpu_mask_to_apicid(tmp);
2774 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2778 HT_IRQ_LOW_DEST_ID(dest) |
2779 HT_IRQ_LOW_VECTOR(cfg->vector) |
2780 ((INT_DEST_MODE == 0) ?
2781 HT_IRQ_LOW_DM_PHYSICAL :
2782 HT_IRQ_LOW_DM_LOGICAL) |
2783 HT_IRQ_LOW_RQEOI_EDGE |
2784 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2785 HT_IRQ_LOW_MT_FIXED :
2786 HT_IRQ_LOW_MT_ARBITRATED) |
2787 HT_IRQ_LOW_IRQ_MASKED;
2789 write_ht_irq_msg(irq, &msg);
2791 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2792 handle_edge_irq, "edge");
2796 #endif /* CONFIG_HT_IRQ */
2798 /* --------------------------------------------------------------------------
2799 ACPI-based IOAPIC Configuration
2800 -------------------------------------------------------------------------- */
2804 int __init io_apic_get_unique_id(int ioapic, int apic_id)
2806 union IO_APIC_reg_00 reg_00;
2807 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2809 unsigned long flags;
2813 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2814 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2815 * supports up to 16 on one shared APIC bus.
2817 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2818 * advantage of new APIC bus architecture.
2821 if (physids_empty(apic_id_map))
2822 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2824 spin_lock_irqsave(&ioapic_lock, flags);
2825 reg_00.raw = io_apic_read(ioapic, 0);
2826 spin_unlock_irqrestore(&ioapic_lock, flags);
2828 if (apic_id >= get_physical_broadcast()) {
2829 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2830 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2831 apic_id = reg_00.bits.ID;
2835 * Every APIC in a system must have a unique ID or we get lots of nice
2836 * 'stuck on smp_invalidate_needed IPI wait' messages.
2838 if (check_apicid_used(apic_id_map, apic_id)) {
2840 for (i = 0; i < get_physical_broadcast(); i++) {
2841 if (!check_apicid_used(apic_id_map, i))
2845 if (i == get_physical_broadcast())
2846 panic("Max apic_id exceeded!\n");
2848 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2849 "trying %d\n", ioapic, apic_id, i);
2854 tmp = apicid_to_cpu_present(apic_id);
2855 physids_or(apic_id_map, apic_id_map, tmp);
2857 if (reg_00.bits.ID != apic_id) {
2858 reg_00.bits.ID = apic_id;
2860 spin_lock_irqsave(&ioapic_lock, flags);
2861 io_apic_write(ioapic, 0, reg_00.raw);
2862 reg_00.raw = io_apic_read(ioapic, 0);
2863 spin_unlock_irqrestore(&ioapic_lock, flags);
2866 if (reg_00.bits.ID != apic_id) {
2867 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2872 apic_printk(APIC_VERBOSE, KERN_INFO
2873 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2879 int __init io_apic_get_version(int ioapic)
2881 union IO_APIC_reg_01 reg_01;
2882 unsigned long flags;
2884 spin_lock_irqsave(&ioapic_lock, flags);
2885 reg_01.raw = io_apic_read(ioapic, 1);
2886 spin_unlock_irqrestore(&ioapic_lock, flags);
2888 return reg_01.bits.version;
2892 int __init io_apic_get_redir_entries(int ioapic)
2894 union IO_APIC_reg_01 reg_01;
2895 unsigned long flags;
2897 spin_lock_irqsave(&ioapic_lock, flags);
2898 reg_01.raw = io_apic_read(ioapic, 1);
2899 spin_unlock_irqrestore(&ioapic_lock, flags);
2901 return reg_01.bits.entries;
2905 int io_apic_set_pci_routing(int ioapic, int pin, int irq, int triggering, int polarity)
2907 if (!IO_APIC_IRQ(irq)) {
2908 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2914 * IRQs < 16 are already in the irq_2_pin[] map
2917 add_pin_to_irq(irq, ioapic, pin);
2919 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2924 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2928 if (skip_ioapic_setup)
2931 for (i = 0; i < mp_irq_entries; i++)
2932 if (mp_irqs[i].mp_irqtype == mp_INT &&
2933 mp_irqs[i].mp_srcbusirq == bus_irq)
2935 if (i >= mp_irq_entries)
2938 *trigger = irq_trigger(i);
2939 *polarity = irq_polarity(i);
2943 #endif /* CONFIG_ACPI */
2946 * This function currently is only a helper for the i386 smp boot process where
2947 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2948 * so mask in all cases should simply be TARGET_CPUS
2951 void __init setup_ioapic_dest(void)
2953 int pin, ioapic, irq, irq_entry;
2954 struct irq_cfg *cfg;
2955 struct irq_desc *desc;
2957 if (skip_ioapic_setup == 1)
2960 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2961 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2962 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2963 if (irq_entry == -1)
2965 irq = pin_2_irq(irq_entry, ioapic, pin);
2967 /* setup_IO_APIC_irqs could fail to get vector for some device
2968 * when you have too many devices, because at that time only boot
2973 setup_IO_APIC_irq(ioapic, pin, irq,
2974 irq_trigger(irq_entry),
2975 irq_polarity(irq_entry));
2977 desc = irq_to_desc(irq);
2978 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2986 static int __init parse_disable_timer_pin_1(char *arg)
2988 disable_timer_pin_1 = 1;
2991 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2993 static int __init parse_enable_timer_pin_1(char *arg)
2995 disable_timer_pin_1 = -1;
2998 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
3000 static int __init parse_noapic(char *arg)
3002 /* disable IO-APIC */
3003 disable_ioapic_setup();
3006 early_param("noapic", parse_noapic);
3008 void __init ioapic_init_mappings(void)
3010 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3013 for (i = 0; i < nr_ioapics; i++) {
3014 if (smp_found_config) {
3015 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3018 "WARNING: bogus zero IO-APIC "
3019 "address found in MPTABLE, "
3020 "disabling IO/APIC support!\n");
3021 smp_found_config = 0;
3022 skip_ioapic_setup = 1;
3023 goto fake_ioapic_page;
3027 ioapic_phys = (unsigned long)
3028 alloc_bootmem_pages(PAGE_SIZE);
3029 ioapic_phys = __pa(ioapic_phys);
3031 set_fixmap_nocache(idx, ioapic_phys);
3032 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
3033 __fix_to_virt(idx), ioapic_phys);