2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
54 #define __apicdebuginit(type) static type __init
56 int (*ioapic_renumber_irq)(int ioapic, int irq);
57 atomic_t irq_mis_count;
59 /* Where if anywhere is the i8259 connect in external int mode */
60 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
62 static DEFINE_SPINLOCK(ioapic_lock);
63 DEFINE_SPINLOCK(vector_lock);
65 int timer_through_8259 __initdata;
68 * Is the SiS APIC rmw bug present ?
69 * -1 = don't know, 0 = no, 1 = yes
71 int sis_apic_bug = -1;
75 * # of IRQ routing registers
77 int nr_ioapic_registers[MAX_IO_APICS];
79 /* I/O APIC entries */
80 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
83 /* MP IRQ source entries */
84 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
86 /* # of MP IRQ source entries */
89 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
90 int mp_bus_id_to_type[MAX_MP_BUSSES];
93 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
95 static int disable_timer_pin_1 __initdata;
101 struct irq_cfg *next;
102 struct irq_pin_list *irq_2_pin;
107 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
108 static struct irq_cfg irq_cfg_legacy[] __initdata = {
109 [0] = { .irq = 0, .vector = IRQ0_VECTOR, },
110 [1] = { .irq = 1, .vector = IRQ1_VECTOR, },
111 [2] = { .irq = 2, .vector = IRQ2_VECTOR, },
112 [3] = { .irq = 3, .vector = IRQ3_VECTOR, },
113 [4] = { .irq = 4, .vector = IRQ4_VECTOR, },
114 [5] = { .irq = 5, .vector = IRQ5_VECTOR, },
115 [6] = { .irq = 6, .vector = IRQ6_VECTOR, },
116 [7] = { .irq = 7, .vector = IRQ7_VECTOR, },
117 [8] = { .irq = 8, .vector = IRQ8_VECTOR, },
118 [9] = { .irq = 9, .vector = IRQ9_VECTOR, },
119 [10] = { .irq = 10, .vector = IRQ10_VECTOR, },
120 [11] = { .irq = 11, .vector = IRQ11_VECTOR, },
121 [12] = { .irq = 12, .vector = IRQ12_VECTOR, },
122 [13] = { .irq = 13, .vector = IRQ13_VECTOR, },
123 [14] = { .irq = 14, .vector = IRQ14_VECTOR, },
124 [15] = { .irq = 15, .vector = IRQ15_VECTOR, },
127 static struct irq_cfg irq_cfg_init = { .irq = -1U, };
128 /* need to be biger than size of irq_cfg_legacy */
129 static int nr_irq_cfg = 32;
131 static int __init parse_nr_irq_cfg(char *arg)
134 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
141 early_param("nr_irq_cfg", parse_nr_irq_cfg);
143 static void init_one_irq_cfg(struct irq_cfg *cfg)
145 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
148 static struct irq_cfg *irq_cfgx;
149 static struct irq_cfg *irq_cfgx_free;
150 static void __init init_work(void *data)
152 struct dyn_array *da = data;
159 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
161 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
162 for (i = legacy_count; i < *da->nr; i++)
163 init_one_irq_cfg(&cfg[i]);
165 for (i = 1; i < *da->nr; i++)
166 cfg[i-1].next = &cfg[i];
168 irq_cfgx_free = &irq_cfgx[legacy_count];
169 irq_cfgx[legacy_count - 1].next = NULL;
172 #define for_each_irq_cfg(cfg) \
173 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
175 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
177 static struct irq_cfg *irq_cfg(unsigned int irq)
192 static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
194 struct irq_cfg *cfg, *cfg_pri;
198 cfg_pri = cfg = irq_cfgx;
208 if (!irq_cfgx_free) {
210 unsigned long total_bytes;
212 * we run out of pre-allocate ones, allocate more
214 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
216 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
218 cfg = kzalloc(total_bytes, GFP_ATOMIC);
220 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
223 panic("please boot with nr_irq_cfg= %d\n", count * 2);
226 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
228 for (i = 0; i < nr_irq_cfg; i++)
229 init_one_irq_cfg(&cfg[i]);
231 for (i = 1; i < nr_irq_cfg; i++)
232 cfg[i-1].next = &cfg[i];
238 irq_cfgx_free = irq_cfgx_free->next;
245 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
247 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
249 /* dump the results */
252 unsigned long bytes = sizeof(struct irq_cfg);
254 printk(KERN_DEBUG "=========================== %d\n", irq);
255 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
256 for_each_irq_cfg(cfg) {
258 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
260 printk(KERN_DEBUG "===========================\n");
267 * Rough estimation of how many shared IRQs there are, can
268 * be changed anytime.
273 * This is performance-critical, we want to do it O(1)
275 * the indexing order of this array favors 1:1 mappings
276 * between pins and IRQs.
279 struct irq_pin_list {
281 struct irq_pin_list *next;
284 static struct irq_pin_list *irq_2_pin_head;
285 /* fill one page ? */
286 static int nr_irq_2_pin = 0x100;
287 static struct irq_pin_list *irq_2_pin_ptr;
288 static void __init irq_2_pin_init_work(void *data)
290 struct dyn_array *da = data;
291 struct irq_pin_list *pin;
296 for (i = 1; i < *da->nr; i++)
297 pin[i-1].next = &pin[i];
299 irq_2_pin_ptr = &pin[0];
301 DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
303 static struct irq_pin_list *get_one_free_irq_2_pin(void)
305 struct irq_pin_list *pin;
311 irq_2_pin_ptr = pin->next;
317 * we run out of pre-allocate ones, allocate more
319 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
322 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
325 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
326 nr_irq_2_pin, PAGE_SIZE, 0);
329 panic("can not get more irq_2_pin\n");
331 for (i = 1; i < nr_irq_2_pin; i++)
332 pin[i-1].next = &pin[i];
334 irq_2_pin_ptr = pin->next;
342 unsigned int unused[3];
346 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
348 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
349 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
352 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
354 struct io_apic __iomem *io_apic = io_apic_base(apic);
355 writel(reg, &io_apic->index);
356 return readl(&io_apic->data);
359 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
361 struct io_apic __iomem *io_apic = io_apic_base(apic);
362 writel(reg, &io_apic->index);
363 writel(value, &io_apic->data);
367 * Re-write a value: to be used for read-modify-write
368 * cycles where the read already set up the index register.
370 * Older SiS APIC requires we rewrite the index register
372 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
374 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
376 writel(reg, &io_apic->index);
377 writel(value, &io_apic->data);
381 struct { u32 w1, w2; };
382 struct IO_APIC_route_entry entry;
385 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
387 union entry_union eu;
389 spin_lock_irqsave(&ioapic_lock, flags);
390 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
391 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
392 spin_unlock_irqrestore(&ioapic_lock, flags);
397 * When we write a new IO APIC routing entry, we need to write the high
398 * word first! If the mask bit in the low word is clear, we will enable
399 * the interrupt, and we need to make sure the entry is fully populated
400 * before that happens.
403 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
405 union entry_union eu;
407 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
408 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
411 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
414 spin_lock_irqsave(&ioapic_lock, flags);
415 __ioapic_write_entry(apic, pin, e);
416 spin_unlock_irqrestore(&ioapic_lock, flags);
420 * When we mask an IO APIC routing entry, we need to write the low
421 * word first, in order to set the mask bit before we change the
424 static void ioapic_mask_entry(int apic, int pin)
427 union entry_union eu = { .entry.mask = 1 };
429 spin_lock_irqsave(&ioapic_lock, flags);
430 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
431 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
432 spin_unlock_irqrestore(&ioapic_lock, flags);
436 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
437 * shared ISA-space IRQs, so we have to support them. We are super
438 * fast in the common case, and fast for shared ISA-space IRQs.
440 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
443 struct irq_pin_list *entry;
445 /* first time to refer irq_cfg, so with new */
446 cfg = irq_cfg_alloc(irq);
447 entry = cfg->irq_2_pin;
449 entry = get_one_free_irq_2_pin();
450 cfg->irq_2_pin = entry;
453 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
457 while (entry->next) {
458 /* not again, please */
459 if (entry->apic == apic && entry->pin == pin)
465 entry->next = get_one_free_irq_2_pin();
469 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
473 * Reroute an IRQ to a different pin.
475 static void __init replace_pin_at_irq(unsigned int irq,
476 int oldapic, int oldpin,
477 int newapic, int newpin)
479 struct irq_cfg *cfg = irq_cfg(irq);
480 struct irq_pin_list *entry = cfg->irq_2_pin;
484 if (entry->apic == oldapic && entry->pin == oldpin) {
485 entry->apic = newapic;
488 /* every one is different, right? */
494 /* why? call replace before add? */
496 add_pin_to_irq(irq, newapic, newpin);
499 static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
502 struct irq_pin_list *entry;
503 unsigned int pin, reg;
506 entry = cfg->irq_2_pin;
511 reg = io_apic_read(entry->apic, 0x10 + pin*2);
514 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
522 static void __mask_IO_APIC_irq(unsigned int irq)
524 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
528 static void __unmask_IO_APIC_irq(unsigned int irq)
530 __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
533 /* mask = 1, trigger = 0 */
534 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
536 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
537 IO_APIC_REDIR_LEVEL_TRIGGER);
540 /* mask = 0, trigger = 1 */
541 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
543 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
544 IO_APIC_REDIR_MASKED);
547 static void mask_IO_APIC_irq(unsigned int irq)
551 spin_lock_irqsave(&ioapic_lock, flags);
552 __mask_IO_APIC_irq(irq);
553 spin_unlock_irqrestore(&ioapic_lock, flags);
556 static void unmask_IO_APIC_irq(unsigned int irq)
560 spin_lock_irqsave(&ioapic_lock, flags);
561 __unmask_IO_APIC_irq(irq);
562 spin_unlock_irqrestore(&ioapic_lock, flags);
565 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
567 struct IO_APIC_route_entry entry;
569 /* Check delivery_mode to be sure we're not clearing an SMI pin */
570 entry = ioapic_read_entry(apic, pin);
571 if (entry.delivery_mode == dest_SMI)
575 * Disable it in the IO-APIC irq-routing table:
577 ioapic_mask_entry(apic, pin);
580 static void clear_IO_APIC(void)
584 for (apic = 0; apic < nr_ioapics; apic++)
585 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
586 clear_IO_APIC_pin(apic, pin);
590 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
595 struct irq_pin_list *entry;
596 unsigned int apicid_value;
598 struct irq_desc *desc;
602 entry = cfg->irq_2_pin;
604 cpus_and(tmp, cpumask, cpu_online_map);
608 cpus_and(cpumask, tmp, CPU_MASK_ALL);
610 apicid_value = cpu_mask_to_apicid(cpumask);
611 /* Prepare to do the io_apic_write */
612 apicid_value = apicid_value << 24;
613 spin_lock_irqsave(&ioapic_lock, flags);
618 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
623 desc = irq_to_desc(irq);
624 desc->affinity = cpumask;
625 spin_unlock_irqrestore(&ioapic_lock, flags);
628 #endif /* CONFIG_SMP */
631 void send_IPI_self(int vector)
638 apic_wait_icr_idle();
639 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
641 * Send the IPI. The write to APIC_ICR fires this off.
643 apic_write(APIC_ICR, cfg);
645 #endif /* !CONFIG_SMP */
649 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
650 * specific CPU-side IRQs.
654 static int pirq_entries [MAX_PIRQS];
655 static int pirqs_enabled;
656 int skip_ioapic_setup;
658 static int __init ioapic_pirq_setup(char *str)
661 int ints[MAX_PIRQS+1];
663 get_options(str, ARRAY_SIZE(ints), ints);
665 for (i = 0; i < MAX_PIRQS; i++)
666 pirq_entries[i] = -1;
669 apic_printk(APIC_VERBOSE, KERN_INFO
670 "PIRQ redirection, working around broken MP-BIOS.\n");
672 if (ints[0] < MAX_PIRQS)
675 for (i = 0; i < max; i++) {
676 apic_printk(APIC_VERBOSE, KERN_DEBUG
677 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
679 * PIRQs are mapped upside down, usually.
681 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
686 __setup("pirq=", ioapic_pirq_setup);
689 * Find the IRQ entry number of a certain pin.
691 static int find_irq_entry(int apic, int pin, int type)
695 for (i = 0; i < mp_irq_entries; i++)
696 if (mp_irqs[i].mp_irqtype == type &&
697 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
698 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
699 mp_irqs[i].mp_dstirq == pin)
706 * Find the pin to which IRQ[irq] (ISA) is connected
708 static int __init find_isa_irq_pin(int irq, int type)
712 for (i = 0; i < mp_irq_entries; i++) {
713 int lbus = mp_irqs[i].mp_srcbus;
715 if (test_bit(lbus, mp_bus_not_pci) &&
716 (mp_irqs[i].mp_irqtype == type) &&
717 (mp_irqs[i].mp_srcbusirq == irq))
719 return mp_irqs[i].mp_dstirq;
724 static int __init find_isa_irq_apic(int irq, int type)
728 for (i = 0; i < mp_irq_entries; i++) {
729 int lbus = mp_irqs[i].mp_srcbus;
731 if (test_bit(lbus, mp_bus_not_pci) &&
732 (mp_irqs[i].mp_irqtype == type) &&
733 (mp_irqs[i].mp_srcbusirq == irq))
736 if (i < mp_irq_entries) {
738 for (apic = 0; apic < nr_ioapics; apic++) {
739 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
748 * Find a specific PCI IRQ entry.
749 * Not an __init, possibly needed by modules
751 static int pin_2_irq(int idx, int apic, int pin);
753 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
755 int apic, i, best_guess = -1;
757 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
758 "slot:%d, pin:%d.\n", bus, slot, pin);
759 if (test_bit(bus, mp_bus_not_pci)) {
760 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
763 for (i = 0; i < mp_irq_entries; i++) {
764 int lbus = mp_irqs[i].mp_srcbus;
766 for (apic = 0; apic < nr_ioapics; apic++)
767 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
768 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
771 if (!test_bit(lbus, mp_bus_not_pci) &&
772 !mp_irqs[i].mp_irqtype &&
774 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
775 int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
777 if (!(apic || IO_APIC_IRQ(irq)))
780 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
783 * Use the first all-but-pin matching entry as a
784 * best-guess fuzzy result for broken mptables.
792 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
795 * This function currently is only a helper for the i386 smp boot process where
796 * we need to reprogram the ioredtbls to cater for the cpus which have come online
797 * so mask in all cases should simply be TARGET_CPUS
800 void __init setup_ioapic_dest(void)
802 int pin, ioapic, irq, irq_entry;
804 if (skip_ioapic_setup == 1)
807 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
808 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
809 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
812 irq = pin_2_irq(irq_entry, ioapic, pin);
813 set_ioapic_affinity_irq(irq, TARGET_CPUS);
820 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
822 * EISA Edge/Level control register, ELCR
824 static int EISA_ELCR(unsigned int irq)
827 unsigned int port = 0x4d0 + (irq >> 3);
828 return (inb(port) >> (irq & 7)) & 1;
830 apic_printk(APIC_VERBOSE, KERN_INFO
831 "Broken MPtable reports ISA irq %d\n", irq);
836 /* ISA interrupts are always polarity zero edge triggered,
837 * when listed as conforming in the MP table. */
839 #define default_ISA_trigger(idx) (0)
840 #define default_ISA_polarity(idx) (0)
842 /* EISA interrupts are always polarity zero and can be edge or level
843 * trigger depending on the ELCR value. If an interrupt is listed as
844 * EISA conforming in the MP table, that means its trigger type must
845 * be read in from the ELCR */
847 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
848 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
850 /* PCI interrupts are always polarity one level triggered,
851 * when listed as conforming in the MP table. */
853 #define default_PCI_trigger(idx) (1)
854 #define default_PCI_polarity(idx) (1)
856 /* MCA interrupts are always polarity zero level triggered,
857 * when listed as conforming in the MP table. */
859 #define default_MCA_trigger(idx) (1)
860 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
862 static int MPBIOS_polarity(int idx)
864 int bus = mp_irqs[idx].mp_srcbus;
868 * Determine IRQ line polarity (high active or low active):
870 switch (mp_irqs[idx].mp_irqflag & 3) {
871 case 0: /* conforms, ie. bus-type dependent polarity */
873 polarity = test_bit(bus, mp_bus_not_pci)?
874 default_ISA_polarity(idx):
875 default_PCI_polarity(idx);
878 case 1: /* high active */
883 case 2: /* reserved */
885 printk(KERN_WARNING "broken BIOS!!\n");
889 case 3: /* low active */
894 default: /* invalid */
896 printk(KERN_WARNING "broken BIOS!!\n");
904 static int MPBIOS_trigger(int idx)
906 int bus = mp_irqs[idx].mp_srcbus;
910 * Determine IRQ trigger mode (edge or level sensitive):
912 switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
913 case 0: /* conforms, ie. bus-type dependent */
915 trigger = test_bit(bus, mp_bus_not_pci)?
916 default_ISA_trigger(idx):
917 default_PCI_trigger(idx);
918 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
919 switch (mp_bus_id_to_type[bus]) {
920 case MP_BUS_ISA: /* ISA pin */
922 /* set before the switch */
925 case MP_BUS_EISA: /* EISA pin */
927 trigger = default_EISA_trigger(idx);
930 case MP_BUS_PCI: /* PCI pin */
932 /* set before the switch */
935 case MP_BUS_MCA: /* MCA pin */
937 trigger = default_MCA_trigger(idx);
942 printk(KERN_WARNING "broken BIOS!!\n");
955 case 2: /* reserved */
957 printk(KERN_WARNING "broken BIOS!!\n");
966 default: /* invalid */
968 printk(KERN_WARNING "broken BIOS!!\n");
976 static inline int irq_polarity(int idx)
978 return MPBIOS_polarity(idx);
981 static inline int irq_trigger(int idx)
983 return MPBIOS_trigger(idx);
986 static int pin_2_irq(int idx, int apic, int pin)
989 int bus = mp_irqs[idx].mp_srcbus;
992 * Debugging check, we are in big trouble if this message pops up!
994 if (mp_irqs[idx].mp_dstirq != pin)
995 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
997 if (test_bit(bus, mp_bus_not_pci))
998 irq = mp_irqs[idx].mp_srcbusirq;
1001 * PCI IRQs are mapped in order
1005 irq += nr_ioapic_registers[i++];
1009 * For MPS mode, so far only needed by ES7000 platform
1011 if (ioapic_renumber_irq)
1012 irq = ioapic_renumber_irq(apic, irq);
1016 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1018 if ((pin >= 16) && (pin <= 23)) {
1019 if (pirq_entries[pin-16] != -1) {
1020 if (!pirq_entries[pin-16]) {
1021 apic_printk(APIC_VERBOSE, KERN_DEBUG
1022 "disabling PIRQ%d\n", pin-16);
1024 irq = pirq_entries[pin-16];
1025 apic_printk(APIC_VERBOSE, KERN_DEBUG
1026 "using PIRQ%d -> IRQ %d\n",
1034 static inline int IO_APIC_irq_trigger(int irq)
1038 for (apic = 0; apic < nr_ioapics; apic++) {
1039 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1040 idx = find_irq_entry(apic, pin, mp_INT);
1041 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1042 return irq_trigger(idx);
1046 * nonexistent IRQs are edge default
1052 static int __assign_irq_vector(int irq)
1054 static int current_vector = FIRST_DEVICE_VECTOR, current_offset;
1056 struct irq_cfg *cfg;
1058 BUG_ON((unsigned)irq >= nr_irqs);
1061 if (cfg->vector > 0)
1064 vector = current_vector;
1065 offset = current_offset;
1068 if (vector >= first_system_vector) {
1069 offset = (offset + 1) % 8;
1070 vector = FIRST_DEVICE_VECTOR + offset;
1072 if (vector == current_vector)
1074 if (test_and_set_bit(vector, used_vectors))
1077 current_vector = vector;
1078 current_offset = offset;
1079 cfg->vector = vector;
1084 static int assign_irq_vector(int irq)
1086 unsigned long flags;
1089 spin_lock_irqsave(&vector_lock, flags);
1090 vector = __assign_irq_vector(irq);
1091 spin_unlock_irqrestore(&vector_lock, flags);
1096 static struct irq_chip ioapic_chip;
1098 #define IOAPIC_AUTO -1
1099 #define IOAPIC_EDGE 0
1100 #define IOAPIC_LEVEL 1
1102 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1104 struct irq_desc *desc;
1106 desc = irq_to_desc(irq);
1107 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1108 trigger == IOAPIC_LEVEL) {
1109 desc->status |= IRQ_LEVEL;
1110 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1111 handle_fasteoi_irq, "fasteoi");
1113 desc->status &= ~IRQ_LEVEL;
1114 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1115 handle_edge_irq, "edge");
1117 set_intr_gate(vector, interrupt[irq]);
1120 static void __init setup_IO_APIC_irqs(void)
1122 struct IO_APIC_route_entry entry;
1123 int apic, pin, idx, irq, first_notcon = 1, vector;
1125 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1127 for (apic = 0; apic < nr_ioapics; apic++) {
1128 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1131 * add it to the IO-APIC irq-routing table:
1133 memset(&entry, 0, sizeof(entry));
1135 entry.delivery_mode = INT_DELIVERY_MODE;
1136 entry.dest_mode = INT_DEST_MODE;
1137 entry.mask = 0; /* enable IRQ */
1138 entry.dest.logical.logical_dest =
1139 cpu_mask_to_apicid(TARGET_CPUS);
1141 idx = find_irq_entry(apic, pin, mp_INT);
1144 apic_printk(APIC_VERBOSE, KERN_DEBUG
1145 " IO-APIC (apicid-pin) %d-%d",
1146 mp_ioapics[apic].mp_apicid,
1150 apic_printk(APIC_VERBOSE, ", %d-%d",
1151 mp_ioapics[apic].mp_apicid, pin);
1155 if (!first_notcon) {
1156 apic_printk(APIC_VERBOSE, " not connected.\n");
1160 entry.trigger = irq_trigger(idx);
1161 entry.polarity = irq_polarity(idx);
1163 if (irq_trigger(idx)) {
1168 irq = pin_2_irq(idx, apic, pin);
1170 * skip adding the timer int on secondary nodes, which causes
1171 * a small but painful rift in the time-space continuum
1173 if (multi_timer_check(apic, irq))
1176 add_pin_to_irq(irq, apic, pin);
1178 if (!apic && !IO_APIC_IRQ(irq))
1181 if (IO_APIC_IRQ(irq)) {
1182 vector = assign_irq_vector(irq);
1183 entry.vector = vector;
1184 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1186 if (!apic && (irq < 16))
1187 disable_8259A_irq(irq);
1189 ioapic_write_entry(apic, pin, entry);
1194 apic_printk(APIC_VERBOSE, " not connected.\n");
1198 * Set up the timer pin, possibly with the 8259A-master behind.
1200 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1203 struct IO_APIC_route_entry entry;
1205 memset(&entry, 0, sizeof(entry));
1208 * We use logical delivery to get the timer IRQ
1211 entry.dest_mode = INT_DEST_MODE;
1212 entry.mask = 1; /* mask IRQ now */
1213 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1214 entry.delivery_mode = INT_DELIVERY_MODE;
1217 entry.vector = vector;
1220 * The timer IRQ doesn't have to know that behind the
1221 * scene we may have a 8259A-master in AEOI mode ...
1223 ioapic_register_intr(0, vector, IOAPIC_EDGE);
1226 * Add it to the IO-APIC irq-routing table:
1228 ioapic_write_entry(apic, pin, entry);
1232 __apicdebuginit(void) print_IO_APIC(void)
1235 union IO_APIC_reg_00 reg_00;
1236 union IO_APIC_reg_01 reg_01;
1237 union IO_APIC_reg_02 reg_02;
1238 union IO_APIC_reg_03 reg_03;
1239 unsigned long flags;
1240 struct irq_cfg *cfg;
1242 if (apic_verbosity == APIC_QUIET)
1245 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1246 for (i = 0; i < nr_ioapics; i++)
1247 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1248 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1251 * We are a bit conservative about what we expect. We have to
1252 * know about every hardware change ASAP.
1254 printk(KERN_INFO "testing the IO APIC.......................\n");
1256 for (apic = 0; apic < nr_ioapics; apic++) {
1258 spin_lock_irqsave(&ioapic_lock, flags);
1259 reg_00.raw = io_apic_read(apic, 0);
1260 reg_01.raw = io_apic_read(apic, 1);
1261 if (reg_01.bits.version >= 0x10)
1262 reg_02.raw = io_apic_read(apic, 2);
1263 if (reg_01.bits.version >= 0x20)
1264 reg_03.raw = io_apic_read(apic, 3);
1265 spin_unlock_irqrestore(&ioapic_lock, flags);
1267 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1268 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1269 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1270 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1271 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1273 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1274 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1276 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1277 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1280 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1281 * but the value of reg_02 is read as the previous read register
1282 * value, so ignore it if reg_02 == reg_01.
1284 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1285 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1286 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1290 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1291 * or reg_03, but the value of reg_0[23] is read as the previous read
1292 * register value, so ignore it if reg_03 == reg_0[12].
1294 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1295 reg_03.raw != reg_01.raw) {
1296 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1297 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1300 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1302 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1303 " Stat Dest Deli Vect: \n");
1305 for (i = 0; i <= reg_01.bits.entries; i++) {
1306 struct IO_APIC_route_entry entry;
1308 entry = ioapic_read_entry(apic, i);
1310 printk(KERN_DEBUG " %02x %03X %02X ",
1312 entry.dest.logical.logical_dest,
1313 entry.dest.physical.physical_dest
1316 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1321 entry.delivery_status,
1323 entry.delivery_mode,
1328 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1329 for_each_irq_cfg(cfg) {
1330 struct irq_pin_list *entry = cfg->irq_2_pin;
1333 printk(KERN_DEBUG "IRQ%d ", i);
1335 printk("-> %d:%d", entry->apic, entry->pin);
1338 entry = entry->next;
1343 printk(KERN_INFO ".................................... done.\n");
1348 __apicdebuginit(void) print_APIC_bitfield(int base)
1353 if (apic_verbosity == APIC_QUIET)
1356 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1357 for (i = 0; i < 8; i++) {
1358 v = apic_read(base + i*0x10);
1359 for (j = 0; j < 32; j++) {
1369 __apicdebuginit(void) print_local_APIC(void *dummy)
1371 unsigned int v, ver, maxlvt;
1374 if (apic_verbosity == APIC_QUIET)
1377 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1378 smp_processor_id(), hard_smp_processor_id());
1379 v = apic_read(APIC_ID);
1380 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
1382 v = apic_read(APIC_LVR);
1383 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1384 ver = GET_APIC_VERSION(v);
1385 maxlvt = lapic_get_maxlvt();
1387 v = apic_read(APIC_TASKPRI);
1388 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1390 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1391 v = apic_read(APIC_ARBPRI);
1392 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1393 v & APIC_ARBPRI_MASK);
1394 v = apic_read(APIC_PROCPRI);
1395 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1398 v = apic_read(APIC_EOI);
1399 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1400 v = apic_read(APIC_RRR);
1401 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1402 v = apic_read(APIC_LDR);
1403 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1404 v = apic_read(APIC_DFR);
1405 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1406 v = apic_read(APIC_SPIV);
1407 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1409 printk(KERN_DEBUG "... APIC ISR field:\n");
1410 print_APIC_bitfield(APIC_ISR);
1411 printk(KERN_DEBUG "... APIC TMR field:\n");
1412 print_APIC_bitfield(APIC_TMR);
1413 printk(KERN_DEBUG "... APIC IRR field:\n");
1414 print_APIC_bitfield(APIC_IRR);
1416 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1417 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1418 apic_write(APIC_ESR, 0);
1419 v = apic_read(APIC_ESR);
1420 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1423 icr = apic_icr_read();
1424 printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
1425 printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
1427 v = apic_read(APIC_LVTT);
1428 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1430 if (maxlvt > 3) { /* PC is LVT#4. */
1431 v = apic_read(APIC_LVTPC);
1432 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1434 v = apic_read(APIC_LVT0);
1435 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1436 v = apic_read(APIC_LVT1);
1437 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1439 if (maxlvt > 2) { /* ERR is LVT#3. */
1440 v = apic_read(APIC_LVTERR);
1441 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1444 v = apic_read(APIC_TMICT);
1445 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1446 v = apic_read(APIC_TMCCT);
1447 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1448 v = apic_read(APIC_TDCR);
1449 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1453 __apicdebuginit(void) print_all_local_APICs(void)
1455 on_each_cpu(print_local_APIC, NULL, 1);
1458 __apicdebuginit(void) print_PIC(void)
1461 unsigned long flags;
1463 if (apic_verbosity == APIC_QUIET)
1466 printk(KERN_DEBUG "\nprinting PIC contents\n");
1468 spin_lock_irqsave(&i8259A_lock, flags);
1470 v = inb(0xa1) << 8 | inb(0x21);
1471 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1473 v = inb(0xa0) << 8 | inb(0x20);
1474 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1478 v = inb(0xa0) << 8 | inb(0x20);
1482 spin_unlock_irqrestore(&i8259A_lock, flags);
1484 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1486 v = inb(0x4d1) << 8 | inb(0x4d0);
1487 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1490 __apicdebuginit(int) print_all_ICs(void)
1493 print_all_local_APICs();
1499 fs_initcall(print_all_ICs);
1502 static void __init enable_IO_APIC(void)
1504 union IO_APIC_reg_01 reg_01;
1505 int i8259_apic, i8259_pin;
1507 unsigned long flags;
1510 for (i = 0; i < MAX_PIRQS; i++)
1511 pirq_entries[i] = -1;
1514 * The number of IO-APIC IRQ registers (== #pins):
1516 for (apic = 0; apic < nr_ioapics; apic++) {
1517 spin_lock_irqsave(&ioapic_lock, flags);
1518 reg_01.raw = io_apic_read(apic, 1);
1519 spin_unlock_irqrestore(&ioapic_lock, flags);
1520 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1522 for (apic = 0; apic < nr_ioapics; apic++) {
1524 /* See if any of the pins is in ExtINT mode */
1525 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1526 struct IO_APIC_route_entry entry;
1527 entry = ioapic_read_entry(apic, pin);
1530 /* If the interrupt line is enabled and in ExtInt mode
1531 * I have found the pin where the i8259 is connected.
1533 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1534 ioapic_i8259.apic = apic;
1535 ioapic_i8259.pin = pin;
1541 /* Look to see what if the MP table has reported the ExtINT */
1542 /* If we could not find the appropriate pin by looking at the ioapic
1543 * the i8259 probably is not connected the ioapic but give the
1544 * mptable a chance anyway.
1546 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1547 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1548 /* Trust the MP table if nothing is setup in the hardware */
1549 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1550 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1551 ioapic_i8259.pin = i8259_pin;
1552 ioapic_i8259.apic = i8259_apic;
1554 /* Complain if the MP table and the hardware disagree */
1555 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1556 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1558 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1562 * Do not trust the IO-APIC being empty at bootup
1568 * Not an __init, needed by the reboot code
1570 void disable_IO_APIC(void)
1573 * Clear the IO-APIC before rebooting:
1578 * If the i8259 is routed through an IOAPIC
1579 * Put that IOAPIC in virtual wire mode
1580 * so legacy interrupts can be delivered.
1582 if (ioapic_i8259.pin != -1) {
1583 struct IO_APIC_route_entry entry;
1585 memset(&entry, 0, sizeof(entry));
1586 entry.mask = 0; /* Enabled */
1587 entry.trigger = 0; /* Edge */
1589 entry.polarity = 0; /* High */
1590 entry.delivery_status = 0;
1591 entry.dest_mode = 0; /* Physical */
1592 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1594 entry.dest.physical.physical_dest = read_apic_id();
1597 * Add it to the IO-APIC irq-routing table:
1599 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1601 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1605 * function to set the IO-APIC physical IDs based on the
1606 * values stored in the MPC table.
1608 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1611 static void __init setup_ioapic_ids_from_mpc(void)
1613 union IO_APIC_reg_00 reg_00;
1614 physid_mask_t phys_id_present_map;
1617 unsigned char old_id;
1618 unsigned long flags;
1620 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1624 * Don't check I/O APIC IDs for xAPIC systems. They have
1625 * no meaning without the serial APIC bus.
1627 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1628 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1631 * This is broken; anything with a real cpu count has to
1632 * circumvent this idiocy regardless.
1634 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1637 * Set the IOAPIC ID to the value stored in the MPC table.
1639 for (apic = 0; apic < nr_ioapics; apic++) {
1641 /* Read the register 0 value */
1642 spin_lock_irqsave(&ioapic_lock, flags);
1643 reg_00.raw = io_apic_read(apic, 0);
1644 spin_unlock_irqrestore(&ioapic_lock, flags);
1646 old_id = mp_ioapics[apic].mp_apicid;
1648 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1649 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1650 apic, mp_ioapics[apic].mp_apicid);
1651 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1653 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1657 * Sanity check, is the ID really free? Every APIC in a
1658 * system must have a unique ID or we get lots of nice
1659 * 'stuck on smp_invalidate_needed IPI wait' messages.
1661 if (check_apicid_used(phys_id_present_map,
1662 mp_ioapics[apic].mp_apicid)) {
1663 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1664 apic, mp_ioapics[apic].mp_apicid);
1665 for (i = 0; i < get_physical_broadcast(); i++)
1666 if (!physid_isset(i, phys_id_present_map))
1668 if (i >= get_physical_broadcast())
1669 panic("Max APIC ID exceeded!\n");
1670 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1672 physid_set(i, phys_id_present_map);
1673 mp_ioapics[apic].mp_apicid = i;
1676 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1677 apic_printk(APIC_VERBOSE, "Setting %d in the "
1678 "phys_id_present_map\n",
1679 mp_ioapics[apic].mp_apicid);
1680 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1685 * We need to adjust the IRQ routing table
1686 * if the ID changed.
1688 if (old_id != mp_ioapics[apic].mp_apicid)
1689 for (i = 0; i < mp_irq_entries; i++)
1690 if (mp_irqs[i].mp_dstapic == old_id)
1691 mp_irqs[i].mp_dstapic
1692 = mp_ioapics[apic].mp_apicid;
1695 * Read the right value from the MPC table and
1696 * write it into the ID register.
1698 apic_printk(APIC_VERBOSE, KERN_INFO
1699 "...changing IO-APIC physical APIC ID to %d ...",
1700 mp_ioapics[apic].mp_apicid);
1702 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1703 spin_lock_irqsave(&ioapic_lock, flags);
1704 io_apic_write(apic, 0, reg_00.raw);
1705 spin_unlock_irqrestore(&ioapic_lock, flags);
1710 spin_lock_irqsave(&ioapic_lock, flags);
1711 reg_00.raw = io_apic_read(apic, 0);
1712 spin_unlock_irqrestore(&ioapic_lock, flags);
1713 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1714 printk("could not set ID!\n");
1716 apic_printk(APIC_VERBOSE, " ok.\n");
1720 int no_timer_check __initdata;
1722 static int __init notimercheck(char *s)
1727 __setup("no_timer_check", notimercheck);
1730 * There is a nasty bug in some older SMP boards, their mptable lies
1731 * about the timer IRQ. We do the following to work around the situation:
1733 * - timer IRQ defaults to IO-APIC IRQ
1734 * - if this function detects that timer IRQs are defunct, then we fall
1735 * back to ISA timer IRQs
1737 static int __init timer_irq_works(void)
1739 unsigned long t1 = jiffies;
1740 unsigned long flags;
1745 local_save_flags(flags);
1747 /* Let ten ticks pass... */
1748 mdelay((10 * 1000) / HZ);
1749 local_irq_restore(flags);
1752 * Expect a few ticks at least, to be sure some possible
1753 * glue logic does not lock up after one or two first
1754 * ticks in a non-ExtINT mode. Also the local APIC
1755 * might have cached one ExtINT interrupt. Finally, at
1756 * least one tick may be lost due to delays.
1758 if (time_after(jiffies, t1 + 4))
1765 * In the SMP+IOAPIC case it might happen that there are an unspecified
1766 * number of pending IRQ events unhandled. These cases are very rare,
1767 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1768 * better to do it this way as thus we do not have to be aware of
1769 * 'pending' interrupts in the IRQ path, except at this point.
1772 * Edge triggered needs to resend any interrupt
1773 * that was delayed but this is now handled in the device
1780 * Starting up a edge-triggered IO-APIC interrupt is
1781 * nasty - we need to make sure that we get the edge.
1782 * If it is already asserted for some reason, we need
1783 * return 1 to indicate that is was pending.
1785 * This is not complete - we should be able to fake
1786 * an edge even if it isn't on the 8259A...
1788 * (We do this for level-triggered IRQs too - it cannot hurt.)
1790 static unsigned int startup_ioapic_irq(unsigned int irq)
1792 int was_pending = 0;
1793 unsigned long flags;
1795 spin_lock_irqsave(&ioapic_lock, flags);
1797 disable_8259A_irq(irq);
1798 if (i8259A_irq_pending(irq))
1801 __unmask_IO_APIC_irq(irq);
1802 spin_unlock_irqrestore(&ioapic_lock, flags);
1807 static void ack_ioapic_irq(unsigned int irq)
1809 move_native_irq(irq);
1813 static void ack_ioapic_quirk_irq(unsigned int irq)
1818 move_native_irq(irq);
1820 * It appears there is an erratum which affects at least version 0x11
1821 * of I/O APIC (that's the 82093AA and cores integrated into various
1822 * chipsets). Under certain conditions a level-triggered interrupt is
1823 * erroneously delivered as edge-triggered one but the respective IRR
1824 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1825 * message but it will never arrive and further interrupts are blocked
1826 * from the source. The exact reason is so far unknown, but the
1827 * phenomenon was observed when two consecutive interrupt requests
1828 * from a given source get delivered to the same CPU and the source is
1829 * temporarily disabled in between.
1831 * A workaround is to simulate an EOI message manually. We achieve it
1832 * by setting the trigger mode to edge and then to level when the edge
1833 * trigger mode gets detected in the TMR of a local APIC for a
1834 * level-triggered interrupt. We mask the source for the time of the
1835 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1836 * The idea is from Manfred Spraul. --macro
1838 i = irq_cfg(irq)->vector;
1840 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1844 if (!(v & (1 << (i & 0x1f)))) {
1845 atomic_inc(&irq_mis_count);
1846 spin_lock(&ioapic_lock);
1847 __mask_and_edge_IO_APIC_irq(irq);
1848 __unmask_and_level_IO_APIC_irq(irq);
1849 spin_unlock(&ioapic_lock);
1853 static int ioapic_retrigger_irq(unsigned int irq)
1855 send_IPI_self(irq_cfg(irq)->vector);
1860 static struct irq_chip ioapic_chip __read_mostly = {
1862 .startup = startup_ioapic_irq,
1863 .mask = mask_IO_APIC_irq,
1864 .unmask = unmask_IO_APIC_irq,
1865 .ack = ack_ioapic_irq,
1866 .eoi = ack_ioapic_quirk_irq,
1868 .set_affinity = set_ioapic_affinity_irq,
1870 .retrigger = ioapic_retrigger_irq,
1874 static inline void init_IO_APIC_traps(void)
1877 struct irq_desc *desc;
1878 struct irq_cfg *cfg;
1881 * NOTE! The local APIC isn't very good at handling
1882 * multiple interrupts at the same interrupt level.
1883 * As the interrupt level is determined by taking the
1884 * vector number and shifting that right by 4, we
1885 * want to spread these out a bit so that they don't
1886 * all fall in the same interrupt level.
1888 * Also, we've got to be careful not to trash gate
1889 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1891 for_each_irq_cfg(cfg) {
1893 if (IO_APIC_IRQ(irq) && !cfg->vector) {
1895 * Hmm.. We don't have an entry for this,
1896 * so default to an old-fashioned 8259
1897 * interrupt if we can..
1900 make_8259A_irq(irq);
1902 desc = irq_to_desc(irq);
1903 /* Strange. Oh, well.. */
1904 desc->chip = &no_irq_chip;
1911 * The local APIC irq-chip implementation:
1914 static void ack_lapic_irq(unsigned int irq)
1919 static void mask_lapic_irq(unsigned int irq)
1923 v = apic_read(APIC_LVT0);
1924 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1927 static void unmask_lapic_irq(unsigned int irq)
1931 v = apic_read(APIC_LVT0);
1932 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1935 static struct irq_chip lapic_chip __read_mostly = {
1936 .name = "local-APIC",
1937 .mask = mask_lapic_irq,
1938 .unmask = unmask_lapic_irq,
1939 .ack = ack_lapic_irq,
1942 static void lapic_register_intr(int irq, int vector)
1944 struct irq_desc *desc;
1946 desc = irq_to_desc(irq);
1947 desc->status &= ~IRQ_LEVEL;
1948 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1950 set_intr_gate(vector, interrupt[irq]);
1953 static void __init setup_nmi(void)
1956 * Dirty trick to enable the NMI watchdog ...
1957 * We put the 8259A master into AEOI mode and
1958 * unmask on all local APICs LVT0 as NMI.
1960 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1961 * is from Maciej W. Rozycki - so we do not have to EOI from
1962 * the NMI handler or the timer interrupt.
1964 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
1966 enable_NMI_through_LVT0();
1968 apic_printk(APIC_VERBOSE, " done.\n");
1972 * This looks a bit hackish but it's about the only one way of sending
1973 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1974 * not support the ExtINT mode, unfortunately. We need to send these
1975 * cycles as some i82489DX-based boards have glue logic that keeps the
1976 * 8259A interrupt line asserted until INTA. --macro
1978 static inline void __init unlock_ExtINT_logic(void)
1981 struct IO_APIC_route_entry entry0, entry1;
1982 unsigned char save_control, save_freq_select;
1984 pin = find_isa_irq_pin(8, mp_INT);
1989 apic = find_isa_irq_apic(8, mp_INT);
1995 entry0 = ioapic_read_entry(apic, pin);
1996 clear_IO_APIC_pin(apic, pin);
1998 memset(&entry1, 0, sizeof(entry1));
2000 entry1.dest_mode = 0; /* physical delivery */
2001 entry1.mask = 0; /* unmask IRQ now */
2002 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2003 entry1.delivery_mode = dest_ExtINT;
2004 entry1.polarity = entry0.polarity;
2008 ioapic_write_entry(apic, pin, entry1);
2010 save_control = CMOS_READ(RTC_CONTROL);
2011 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2012 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2014 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2019 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2023 CMOS_WRITE(save_control, RTC_CONTROL);
2024 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2025 clear_IO_APIC_pin(apic, pin);
2027 ioapic_write_entry(apic, pin, entry0);
2031 * This code may look a bit paranoid, but it's supposed to cooperate with
2032 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2033 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2034 * fanatically on his truly buggy board.
2036 static inline void __init check_timer(void)
2038 int apic1, pin1, apic2, pin2;
2042 unsigned long flags;
2044 local_irq_save(flags);
2046 ver = apic_read(APIC_LVR);
2047 ver = GET_APIC_VERSION(ver);
2050 * get/set the timer IRQ vector:
2052 disable_8259A_irq(0);
2053 vector = assign_irq_vector(0);
2054 set_intr_gate(vector, interrupt[0]);
2057 * As IRQ0 is to be enabled in the 8259A, the virtual
2058 * wire has to be disabled in the local APIC. Also
2059 * timer interrupts need to be acknowledged manually in
2060 * the 8259A for the i82489DX when using the NMI
2061 * watchdog as that APIC treats NMIs as level-triggered.
2062 * The AEOI mode will finish them in the 8259A
2065 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2067 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2069 pin1 = find_isa_irq_pin(0, mp_INT);
2070 apic1 = find_isa_irq_apic(0, mp_INT);
2071 pin2 = ioapic_i8259.pin;
2072 apic2 = ioapic_i8259.apic;
2074 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2075 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2076 vector, apic1, pin1, apic2, pin2);
2079 * Some BIOS writers are clueless and report the ExtINTA
2080 * I/O APIC input from the cascaded 8259A as the timer
2081 * interrupt input. So just in case, if only one pin
2082 * was found above, try it both directly and through the
2089 } else if (pin2 == -1) {
2096 * Ok, does IRQ0 through the IOAPIC work?
2099 add_pin_to_irq(0, apic1, pin1);
2100 setup_timer_IRQ0_pin(apic1, pin1, vector);
2102 unmask_IO_APIC_irq(0);
2103 if (timer_irq_works()) {
2104 if (nmi_watchdog == NMI_IO_APIC) {
2106 enable_8259A_irq(0);
2108 if (disable_timer_pin_1 > 0)
2109 clear_IO_APIC_pin(0, pin1);
2112 clear_IO_APIC_pin(apic1, pin1);
2114 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2115 "8254 timer not connected to IO-APIC\n");
2117 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2118 "(IRQ0) through the 8259A ...\n");
2119 apic_printk(APIC_QUIET, KERN_INFO
2120 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2122 * legacy devices should be connected to IO APIC #0
2124 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2125 setup_timer_IRQ0_pin(apic2, pin2, vector);
2126 unmask_IO_APIC_irq(0);
2127 enable_8259A_irq(0);
2128 if (timer_irq_works()) {
2129 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2130 timer_through_8259 = 1;
2131 if (nmi_watchdog == NMI_IO_APIC) {
2132 disable_8259A_irq(0);
2134 enable_8259A_irq(0);
2139 * Cleanup, just in case ...
2141 disable_8259A_irq(0);
2142 clear_IO_APIC_pin(apic2, pin2);
2143 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2146 if (nmi_watchdog == NMI_IO_APIC) {
2147 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2148 "through the IO-APIC - disabling NMI Watchdog!\n");
2149 nmi_watchdog = NMI_NONE;
2153 apic_printk(APIC_QUIET, KERN_INFO
2154 "...trying to set up timer as Virtual Wire IRQ...\n");
2156 lapic_register_intr(0, vector);
2157 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2158 enable_8259A_irq(0);
2160 if (timer_irq_works()) {
2161 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2164 disable_8259A_irq(0);
2165 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2166 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2168 apic_printk(APIC_QUIET, KERN_INFO
2169 "...trying to set up timer as ExtINT IRQ...\n");
2173 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2175 unlock_ExtINT_logic();
2177 if (timer_irq_works()) {
2178 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2181 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2182 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2183 "report. Then try booting with the 'noapic' option.\n");
2185 local_irq_restore(flags);
2189 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2190 * to devices. However there may be an I/O APIC pin available for
2191 * this interrupt regardless. The pin may be left unconnected, but
2192 * typically it will be reused as an ExtINT cascade interrupt for
2193 * the master 8259A. In the MPS case such a pin will normally be
2194 * reported as an ExtINT interrupt in the MP table. With ACPI
2195 * there is no provision for ExtINT interrupts, and in the absence
2196 * of an override it would be treated as an ordinary ISA I/O APIC
2197 * interrupt, that is edge-triggered and unmasked by default. We
2198 * used to do this, but it caused problems on some systems because
2199 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2200 * the same ExtINT cascade interrupt to drive the local APIC of the
2201 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2202 * the I/O APIC in all cases now. No actual device should request
2203 * it anyway. --macro
2205 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2207 void __init setup_IO_APIC(void)
2211 /* Reserve all the system vectors. */
2212 for (i = first_system_vector; i < NR_VECTORS; i++)
2213 set_bit(i, used_vectors);
2217 io_apic_irqs = ~PIC_IRQS;
2219 printk("ENABLING IO-APIC IRQs\n");
2222 * Set up IO-APIC IRQ routing.
2225 setup_ioapic_ids_from_mpc();
2227 setup_IO_APIC_irqs();
2228 init_IO_APIC_traps();
2233 * Called after all the initialization is done. If we didnt find any
2234 * APIC bugs then we can allow the modify fast path
2237 static int __init io_apic_bug_finalize(void)
2239 if (sis_apic_bug == -1)
2244 late_initcall(io_apic_bug_finalize);
2246 struct sysfs_ioapic_data {
2247 struct sys_device dev;
2248 struct IO_APIC_route_entry entry[0];
2250 static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2252 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2254 struct IO_APIC_route_entry *entry;
2255 struct sysfs_ioapic_data *data;
2258 data = container_of(dev, struct sysfs_ioapic_data, dev);
2259 entry = data->entry;
2260 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2261 entry[i] = ioapic_read_entry(dev->id, i);
2266 static int ioapic_resume(struct sys_device *dev)
2268 struct IO_APIC_route_entry *entry;
2269 struct sysfs_ioapic_data *data;
2270 unsigned long flags;
2271 union IO_APIC_reg_00 reg_00;
2274 data = container_of(dev, struct sysfs_ioapic_data, dev);
2275 entry = data->entry;
2277 spin_lock_irqsave(&ioapic_lock, flags);
2278 reg_00.raw = io_apic_read(dev->id, 0);
2279 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2280 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2281 io_apic_write(dev->id, 0, reg_00.raw);
2283 spin_unlock_irqrestore(&ioapic_lock, flags);
2284 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2285 ioapic_write_entry(dev->id, i, entry[i]);
2290 static struct sysdev_class ioapic_sysdev_class = {
2292 .suspend = ioapic_suspend,
2293 .resume = ioapic_resume,
2296 static int __init ioapic_init_sysfs(void)
2298 struct sys_device *dev;
2299 int i, size, error = 0;
2301 error = sysdev_class_register(&ioapic_sysdev_class);
2305 for (i = 0; i < nr_ioapics; i++) {
2306 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2307 * sizeof(struct IO_APIC_route_entry);
2308 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2309 if (!mp_ioapic_data[i]) {
2310 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2313 dev = &mp_ioapic_data[i]->dev;
2315 dev->cls = &ioapic_sysdev_class;
2316 error = sysdev_register(dev);
2318 kfree(mp_ioapic_data[i]);
2319 mp_ioapic_data[i] = NULL;
2320 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2328 device_initcall(ioapic_init_sysfs);
2331 * Dynamic irq allocate and deallocation
2333 int create_irq(void)
2335 /* Allocate an unused irq */
2336 int irq, new, vector = 0;
2337 unsigned long flags;
2338 struct irq_cfg *cfg_new;
2341 spin_lock_irqsave(&vector_lock, flags);
2342 for (new = (nr_irqs - 1); new >= 0; new--) {
2343 if (platform_legacy_irq(new))
2345 cfg_new = irq_cfg(new);
2346 if (cfg_new && cfg_new->vector != 0)
2349 cfg_new = irq_cfg_alloc(new);
2350 vector = __assign_irq_vector(new);
2351 if (likely(vector > 0))
2355 spin_unlock_irqrestore(&vector_lock, flags);
2358 set_intr_gate(vector, interrupt[irq]);
2359 dynamic_irq_init(irq);
2364 void destroy_irq(unsigned int irq)
2366 unsigned long flags;
2368 dynamic_irq_cleanup(irq);
2370 spin_lock_irqsave(&vector_lock, flags);
2371 clear_bit(irq_cfg(irq)->vector, used_vectors);
2372 irq_cfg(irq)->vector = 0;
2373 spin_unlock_irqrestore(&vector_lock, flags);
2377 * MSI message composition
2379 #ifdef CONFIG_PCI_MSI
2380 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2385 vector = assign_irq_vector(irq);
2387 dest = cpu_mask_to_apicid(TARGET_CPUS);
2389 msg->address_hi = MSI_ADDR_BASE_HI;
2392 ((INT_DEST_MODE == 0) ?
2393 MSI_ADDR_DEST_MODE_PHYSICAL:
2394 MSI_ADDR_DEST_MODE_LOGICAL) |
2395 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2396 MSI_ADDR_REDIRECTION_CPU:
2397 MSI_ADDR_REDIRECTION_LOWPRI) |
2398 MSI_ADDR_DEST_ID(dest);
2401 MSI_DATA_TRIGGER_EDGE |
2402 MSI_DATA_LEVEL_ASSERT |
2403 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2404 MSI_DATA_DELIVERY_FIXED:
2405 MSI_DATA_DELIVERY_LOWPRI) |
2406 MSI_DATA_VECTOR(vector);
2412 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2418 struct irq_desc *desc;
2420 cpus_and(tmp, mask, cpu_online_map);
2421 if (cpus_empty(tmp))
2424 vector = assign_irq_vector(irq);
2428 dest = cpu_mask_to_apicid(mask);
2430 read_msi_msg(irq, &msg);
2432 msg.data &= ~MSI_DATA_VECTOR_MASK;
2433 msg.data |= MSI_DATA_VECTOR(vector);
2434 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2435 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2437 write_msi_msg(irq, &msg);
2438 desc = irq_to_desc(irq);
2439 desc->affinity = mask;
2441 #endif /* CONFIG_SMP */
2444 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2445 * which implement the MSI or MSI-X Capability Structure.
2447 static struct irq_chip msi_chip = {
2449 .unmask = unmask_msi_irq,
2450 .mask = mask_msi_irq,
2451 .ack = ack_ioapic_irq,
2453 .set_affinity = set_msi_irq_affinity,
2455 .retrigger = ioapic_retrigger_irq,
2458 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2466 ret = msi_compose_msg(dev, irq, &msg);
2472 set_irq_msi(irq, desc);
2473 write_msi_msg(irq, &msg);
2475 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2481 void arch_teardown_msi_irq(unsigned int irq)
2486 #endif /* CONFIG_PCI_MSI */
2489 * Hypertransport interrupt support
2491 #ifdef CONFIG_HT_IRQ
2495 static void target_ht_irq(unsigned int irq, unsigned int dest)
2497 struct ht_irq_msg msg;
2498 fetch_ht_irq_msg(irq, &msg);
2500 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2501 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2503 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2504 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2506 write_ht_irq_msg(irq, &msg);
2509 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2513 struct irq_desc *desc;
2515 cpus_and(tmp, mask, cpu_online_map);
2516 if (cpus_empty(tmp))
2519 cpus_and(mask, tmp, CPU_MASK_ALL);
2521 dest = cpu_mask_to_apicid(mask);
2523 target_ht_irq(irq, dest);
2524 desc = irq_to_desc(irq);
2525 desc->affinity = mask;
2529 static struct irq_chip ht_irq_chip = {
2531 .mask = mask_ht_irq,
2532 .unmask = unmask_ht_irq,
2533 .ack = ack_ioapic_irq,
2535 .set_affinity = set_ht_irq_affinity,
2537 .retrigger = ioapic_retrigger_irq,
2540 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2544 vector = assign_irq_vector(irq);
2546 struct ht_irq_msg msg;
2551 cpu_set(vector >> 8, tmp);
2552 dest = cpu_mask_to_apicid(tmp);
2554 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2558 HT_IRQ_LOW_DEST_ID(dest) |
2559 HT_IRQ_LOW_VECTOR(vector) |
2560 ((INT_DEST_MODE == 0) ?
2561 HT_IRQ_LOW_DM_PHYSICAL :
2562 HT_IRQ_LOW_DM_LOGICAL) |
2563 HT_IRQ_LOW_RQEOI_EDGE |
2564 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2565 HT_IRQ_LOW_MT_FIXED :
2566 HT_IRQ_LOW_MT_ARBITRATED) |
2567 HT_IRQ_LOW_IRQ_MASKED;
2569 write_ht_irq_msg(irq, &msg);
2571 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2572 handle_edge_irq, "edge");
2576 #endif /* CONFIG_HT_IRQ */
2578 /* --------------------------------------------------------------------------
2579 ACPI-based IOAPIC Configuration
2580 -------------------------------------------------------------------------- */
2584 int __init io_apic_get_unique_id(int ioapic, int apic_id)
2586 union IO_APIC_reg_00 reg_00;
2587 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2589 unsigned long flags;
2593 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2594 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2595 * supports up to 16 on one shared APIC bus.
2597 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2598 * advantage of new APIC bus architecture.
2601 if (physids_empty(apic_id_map))
2602 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2604 spin_lock_irqsave(&ioapic_lock, flags);
2605 reg_00.raw = io_apic_read(ioapic, 0);
2606 spin_unlock_irqrestore(&ioapic_lock, flags);
2608 if (apic_id >= get_physical_broadcast()) {
2609 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2610 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2611 apic_id = reg_00.bits.ID;
2615 * Every APIC in a system must have a unique ID or we get lots of nice
2616 * 'stuck on smp_invalidate_needed IPI wait' messages.
2618 if (check_apicid_used(apic_id_map, apic_id)) {
2620 for (i = 0; i < get_physical_broadcast(); i++) {
2621 if (!check_apicid_used(apic_id_map, i))
2625 if (i == get_physical_broadcast())
2626 panic("Max apic_id exceeded!\n");
2628 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2629 "trying %d\n", ioapic, apic_id, i);
2634 tmp = apicid_to_cpu_present(apic_id);
2635 physids_or(apic_id_map, apic_id_map, tmp);
2637 if (reg_00.bits.ID != apic_id) {
2638 reg_00.bits.ID = apic_id;
2640 spin_lock_irqsave(&ioapic_lock, flags);
2641 io_apic_write(ioapic, 0, reg_00.raw);
2642 reg_00.raw = io_apic_read(ioapic, 0);
2643 spin_unlock_irqrestore(&ioapic_lock, flags);
2646 if (reg_00.bits.ID != apic_id) {
2647 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2652 apic_printk(APIC_VERBOSE, KERN_INFO
2653 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2659 int __init io_apic_get_version(int ioapic)
2661 union IO_APIC_reg_01 reg_01;
2662 unsigned long flags;
2664 spin_lock_irqsave(&ioapic_lock, flags);
2665 reg_01.raw = io_apic_read(ioapic, 1);
2666 spin_unlock_irqrestore(&ioapic_lock, flags);
2668 return reg_01.bits.version;
2672 int __init io_apic_get_redir_entries(int ioapic)
2674 union IO_APIC_reg_01 reg_01;
2675 unsigned long flags;
2677 spin_lock_irqsave(&ioapic_lock, flags);
2678 reg_01.raw = io_apic_read(ioapic, 1);
2679 spin_unlock_irqrestore(&ioapic_lock, flags);
2681 return reg_01.bits.entries;
2685 int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low)
2687 struct IO_APIC_route_entry entry;
2689 if (!IO_APIC_IRQ(irq)) {
2690 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2696 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2697 * Note that we mask (disable) IRQs now -- these get enabled when the
2698 * corresponding device driver registers for this IRQ.
2701 memset(&entry, 0, sizeof(entry));
2703 entry.delivery_mode = INT_DELIVERY_MODE;
2704 entry.dest_mode = INT_DEST_MODE;
2705 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2706 entry.trigger = edge_level;
2707 entry.polarity = active_high_low;
2711 * IRQs < 16 are already in the irq_2_pin[] map
2714 add_pin_to_irq(irq, ioapic, pin);
2716 entry.vector = assign_irq_vector(irq);
2718 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2719 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2720 mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq,
2721 edge_level, active_high_low);
2723 ioapic_register_intr(irq, entry.vector, edge_level);
2725 if (!ioapic && (irq < 16))
2726 disable_8259A_irq(irq);
2728 ioapic_write_entry(ioapic, pin, entry);
2733 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2737 if (skip_ioapic_setup)
2740 for (i = 0; i < mp_irq_entries; i++)
2741 if (mp_irqs[i].mp_irqtype == mp_INT &&
2742 mp_irqs[i].mp_srcbusirq == bus_irq)
2744 if (i >= mp_irq_entries)
2747 *trigger = irq_trigger(i);
2748 *polarity = irq_polarity(i);
2752 #endif /* CONFIG_ACPI */
2754 static int __init parse_disable_timer_pin_1(char *arg)
2756 disable_timer_pin_1 = 1;
2759 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2761 static int __init parse_enable_timer_pin_1(char *arg)
2763 disable_timer_pin_1 = -1;
2766 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2768 static int __init parse_noapic(char *arg)
2770 /* disable IO-APIC */
2771 disable_ioapic_setup();
2774 early_param("noapic", parse_noapic);
2776 void __init ioapic_init_mappings(void)
2778 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2781 for (i = 0; i < nr_ioapics; i++) {
2782 if (smp_found_config) {
2783 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2786 "WARNING: bogus zero IO-APIC "
2787 "address found in MPTABLE, "
2788 "disabling IO/APIC support!\n");
2789 smp_found_config = 0;
2790 skip_ioapic_setup = 1;
2791 goto fake_ioapic_page;
2795 ioapic_phys = (unsigned long)
2796 alloc_bootmem_pages(PAGE_SIZE);
2797 ioapic_phys = __pa(ioapic_phys);
2799 set_fixmap_nocache(idx, ioapic_phys);
2800 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
2801 __fix_to_virt(idx), ioapic_phys);