arch/x86/kernel/io_apic_32.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/mc146818rtc.h>
  29 #include <linux/compiler.h>
  30 #include <linux/acpi.h>
  31 #include <linux/module.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/pci.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39
  40 #include <asm/io.h>
  41 #include <asm/smp.h>
  42 #include <asm/desc.h>
  43 #include <asm/timer.h>
  44 #include <asm/i8259.h>
  45 #include <asm/nmi.h>
  46 #include <asm/msidef.h>
  47 #include <asm/hypertransport.h>
  48
  49 #include <mach_apic.h>
  50 #include <mach_apicdef.h>
  51
  52 int (*ioapic_renumber_irq)(int ioapic, int irq);
  53 atomic_t irq_mis_count;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 int timer_over_8254 __initdata = 1;
  62
  63 /*
  64  *      Is the SiS APIC rmw bug present ?
  65  *      -1 = don't know, 0 = no, 1 = yes
  66  */
  67 int sis_apic_bug = -1;
  68
  69 /*
  70  * # of IRQ routing registers
  71  */
  72 int nr_ioapic_registers[MAX_IO_APICS];
  73
  74 /* I/O APIC entries */
  75 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
  76 int nr_ioapics;
  77
  78 static int disable_timer_pin_1 __initdata;
  79
  80 /*
  81  * Rough estimation of how many shared IRQs there are, can
  82  * be changed anytime.
  83  */
  84 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  85 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  86
  87 /*
  88  * This is performance-critical, we want to do it O(1)
  89  *
  90  * the indexing order of this array favors 1:1 mappings
  91  * between pins and IRQs.
  92  */
  93
  94 static struct irq_pin_list {
  95         int apic, pin, next;
  96 } irq_2_pin[PIN_MAP_SIZE];
  97
  98 struct io_apic {
  99         unsigned int index;
 100         unsigned int unused[3];
 101         unsigned int data;
 102 };
 103
 104 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 105 {
 106         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 107                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 108 }
 109
 110 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 111 {
 112         struct io_apic __iomem *io_apic = io_apic_base(apic);
 113         writel(reg, &io_apic->index);
 114         return readl(&io_apic->data);
 115 }
 116
 117 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 118 {
 119         struct io_apic __iomem *io_apic = io_apic_base(apic);
 120         writel(reg, &io_apic->index);
 121         writel(value, &io_apic->data);
 122 }
 123
 124 /*
 125  * Re-write a value: to be used for read-modify-write
 126  * cycles where the read already set up the index register.
 127  *
 128  * Older SiS APIC requires we rewrite the index register
 129  */
 130 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 131 {
 132         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
 133         if (sis_apic_bug)
 134                 writel(reg, &io_apic->index);
 135         writel(value, &io_apic->data);
 136 }
 137
 138 union entry_union {
 139         struct { u32 w1, w2; };
 140         struct IO_APIC_route_entry entry;
 141 };
 142
 143 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 144 {
 145         union entry_union eu;
 146         unsigned long flags;
 147         spin_lock_irqsave(&ioapic_lock, flags);
 148         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 149         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 150         spin_unlock_irqrestore(&ioapic_lock, flags);
 151         return eu.entry;
 152 }
 153
 154 /*
 155  * When we write a new IO APIC routing entry, we need to write the high
 156  * word first! If the mask bit in the low word is clear, we will enable
 157  * the interrupt, and we need to make sure the entry is fully populated
 158  * before that happens.
 159  */
 160 static void
 161 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 162 {
 163         union entry_union eu;
 164         eu.entry = e;
 165         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 166         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 167 }
 168
 169 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 170 {
 171         unsigned long flags;
 172         spin_lock_irqsave(&ioapic_lock, flags);
 173         __ioapic_write_entry(apic, pin, e);
 174         spin_unlock_irqrestore(&ioapic_lock, flags);
 175 }
 176
 177 /*
 178  * When we mask an IO APIC routing entry, we need to write the low
 179  * word first, in order to set the mask bit before we change the
 180  * high bits!
 181  */
 182 static void ioapic_mask_entry(int apic, int pin)
 183 {
 184         unsigned long flags;
 185         union entry_union eu = { .entry.mask = 1 };
 186
 187         spin_lock_irqsave(&ioapic_lock, flags);
 188         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 189         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 190         spin_unlock_irqrestore(&ioapic_lock, flags);
 191 }
 192
 193 /*
 194  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 195  * shared ISA-space IRQs, so we have to support them. We are super
 196  * fast in the common case, and fast for shared ISA-space IRQs.
 197  */
 198 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 199 {
 200         static int first_free_entry = NR_IRQS;
 201         struct irq_pin_list *entry = irq_2_pin + irq;
 202
 203         while (entry->next)
 204                 entry = irq_2_pin + entry->next;
 205
 206         if (entry->pin != -1) {
 207                 entry->next = first_free_entry;
 208                 entry = irq_2_pin + entry->next;
 209                 if (++first_free_entry >= PIN_MAP_SIZE)
 210                         panic("io_apic.c: whoops");
 211         }
 212         entry->apic = apic;
 213         entry->pin = pin;
 214 }
 215
 216 /*
 217  * Reroute an IRQ to a different pin.
 218  */
 219 static void __init replace_pin_at_irq(unsigned int irq,
 220                                       int oldapic, int oldpin,
 221                                       int newapic, int newpin)
 222 {
 223         struct irq_pin_list *entry = irq_2_pin + irq;
 224
 225         while (1) {
 226                 if (entry->apic == oldapic && entry->pin == oldpin) {
 227                         entry->apic = newapic;
 228                         entry->pin = newpin;
 229                 }
 230                 if (!entry->next)
 231                         break;
 232                 entry = irq_2_pin + entry->next;
 233         }
 234 }
 235
 236 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 237 {
 238         struct irq_pin_list *entry = irq_2_pin + irq;
 239         unsigned int pin, reg;
 240
 241         for (;;) {
 242                 pin = entry->pin;
 243                 if (pin == -1)
 244                         break;
 245                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 246                 reg &= ~disable;
 247                 reg |= enable;
 248                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 249                 if (!entry->next)
 250                         break;
 251                 entry = irq_2_pin + entry->next;
 252         }
 253 }
 254
 255 /* mask = 1 */
 256 static void __mask_IO_APIC_irq (unsigned int irq)
 257 {
 258         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 259 }
 260
 261 /* mask = 0 */
 262 static void __unmask_IO_APIC_irq (unsigned int irq)
 263 {
 264         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 265 }
 266
 267 /* mask = 1, trigger = 0 */
 268 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 269 {
 270         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 271 }
 272
 273 /* mask = 0, trigger = 1 */
 274 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 275 {
 276         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 277 }
 278
 279 static void mask_IO_APIC_irq (unsigned int irq)
 280 {
 281         unsigned long flags;
 282
 283         spin_lock_irqsave(&ioapic_lock, flags);
 284         __mask_IO_APIC_irq(irq);
 285         spin_unlock_irqrestore(&ioapic_lock, flags);
 286 }
 287
 288 static void unmask_IO_APIC_irq (unsigned int irq)
 289 {
 290         unsigned long flags;
 291
 292         spin_lock_irqsave(&ioapic_lock, flags);
 293         __unmask_IO_APIC_irq(irq);
 294         spin_unlock_irqrestore(&ioapic_lock, flags);
 295 }
 296
 297 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 298 {
 299         struct IO_APIC_route_entry entry;
 300
 301         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 302         entry = ioapic_read_entry(apic, pin);
 303         if (entry.delivery_mode == dest_SMI)
 304                 return;
 305
 306         /*
 307          * Disable it in the IO-APIC irq-routing table:
 308          */
 309         ioapic_mask_entry(apic, pin);
 310 }
 311
 312 static void clear_IO_APIC (void)
 313 {
 314         int apic, pin;
 315
 316         for (apic = 0; apic < nr_ioapics; apic++)
 317                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 318                         clear_IO_APIC_pin(apic, pin);
 319 }
 320
 321 #ifdef CONFIG_SMP
 322 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 323 {
 324         unsigned long flags;
 325         int pin;
 326         struct irq_pin_list *entry = irq_2_pin + irq;
 327         unsigned int apicid_value;
 328         cpumask_t tmp;
 329
 330         cpus_and(tmp, cpumask, cpu_online_map);
 331         if (cpus_empty(tmp))
 332                 tmp = TARGET_CPUS;
 333
 334         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 335
 336         apicid_value = cpu_mask_to_apicid(cpumask);
 337         /* Prepare to do the io_apic_write */
 338         apicid_value = apicid_value << 24;
 339         spin_lock_irqsave(&ioapic_lock, flags);
 340         for (;;) {
 341                 pin = entry->pin;
 342                 if (pin == -1)
 343                         break;
 344                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 345                 if (!entry->next)
 346                         break;
 347                 entry = irq_2_pin + entry->next;
 348         }
 349         irq_desc[irq].affinity = cpumask;
 350         spin_unlock_irqrestore(&ioapic_lock, flags);
 351 }
 352
 353 #if defined(CONFIG_IRQBALANCE)
 354 # include <asm/processor.h>     /* kernel_thread() */
 355 # include <linux/kernel_stat.h> /* kstat */
 356 # include <linux/slab.h>                /* kmalloc() */
 357 # include <linux/timer.h>
 358
 359 #define IRQBALANCE_CHECK_ARCH -999
 360 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 361 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 362 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 363 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 364
 365 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 366 static int physical_balance __read_mostly;
 367 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 368
 369 static struct irq_cpu_info {
 370         unsigned long * last_irq;
 371         unsigned long * irq_delta;
 372         unsigned long irq;
 373 } irq_cpu_data[NR_CPUS];
 374
 375 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 376 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 377 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 378
 379 #define IDLE_ENOUGH(cpu,now) \
 380         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 381
 382 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 383
 384 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
 385
 386 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 387         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 388 };
 389
 390 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 391 {
 392         balance_irq_affinity[irq] = mask;
 393 }
 394
 395 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 396                         unsigned long now, int direction)
 397 {
 398         int search_idle = 1;
 399         int cpu = curr_cpu;
 400
 401         goto inside;
 402
 403         do {
 404                 if (unlikely(cpu == curr_cpu))
 405                         search_idle = 0;
 406 inside:
 407                 if (direction == 1) {
 408                         cpu++;
 409                         if (cpu >= NR_CPUS)
 410                                 cpu = 0;
 411                 } else {
 412                         cpu--;
 413                         if (cpu == -1)
 414                                 cpu = NR_CPUS-1;
 415                 }
 416         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 417                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 418
 419         return cpu;
 420 }
 421
 422 static inline void balance_irq(int cpu, int irq)
 423 {
 424         unsigned long now = jiffies;
 425         cpumask_t allowed_mask;
 426         unsigned int new_cpu;
 427
 428         if (irqbalance_disabled)
 429                 return;
 430
 431         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 432         new_cpu = move(cpu, allowed_mask, now, 1);
 433         if (cpu != new_cpu) {
 434                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 435         }
 436 }
 437
 438 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 439 {
 440         int i, j;
 441
 442         for_each_online_cpu(i) {
 443                 for (j = 0; j < NR_IRQS; j++) {
 444                         if (!irq_desc[j].action)
 445                                 continue;
 446                         /* Is it a significant load ?  */
 447                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 448                                                 useful_load_threshold)
 449                                 continue;
 450                         balance_irq(i, j);
 451                 }
 452         }
 453         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 454                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 455         return;
 456 }
 457
 458 static void do_irq_balance(void)
 459 {
 460         int i, j;
 461         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 462         unsigned long move_this_load = 0;
 463         int max_loaded = 0, min_loaded = 0;
 464         int load;
 465         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 466         int selected_irq;
 467         int tmp_loaded, first_attempt = 1;
 468         unsigned long tmp_cpu_irq;
 469         unsigned long imbalance = 0;
 470         cpumask_t allowed_mask, target_cpu_mask, tmp;
 471
 472         for_each_possible_cpu(i) {
 473                 int package_index;
 474                 CPU_IRQ(i) = 0;
 475                 if (!cpu_online(i))
 476                         continue;
 477                 package_index = CPU_TO_PACKAGEINDEX(i);
 478                 for (j = 0; j < NR_IRQS; j++) {
 479                         unsigned long value_now, delta;
 480                         /* Is this an active IRQ or balancing disabled ? */
 481                         if (!irq_desc[j].action || irq_balancing_disabled(j))
 482                                 continue;
 483                         if ( package_index == i )
 484                                 IRQ_DELTA(package_index,j) = 0;
 485                         /* Determine the total count per processor per IRQ */
 486                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 487
 488                         /* Determine the activity per processor per IRQ */
 489                         delta = value_now - LAST_CPU_IRQ(i,j);
 490
 491                         /* Update last_cpu_irq[][] for the next time */
 492                         LAST_CPU_IRQ(i,j) = value_now;
 493
 494                         /* Ignore IRQs whose rate is less than the clock */
 495                         if (delta < useful_load_threshold)
 496                                 continue;
 497                         /* update the load for the processor or package total */
 498                         IRQ_DELTA(package_index,j) += delta;
 499
 500                         /* Keep track of the higher numbered sibling as well */
 501                         if (i != package_index)
 502                                 CPU_IRQ(i) += delta;
 503                         /*
 504                          * We have sibling A and sibling B in the package
 505                          *
 506                          * cpu_irq[A] = load for cpu A + load for cpu B
 507                          * cpu_irq[B] = load for cpu B
 508                          */
 509                         CPU_IRQ(package_index) += delta;
 510                 }
 511         }
 512         /* Find the least loaded processor package */
 513         for_each_online_cpu(i) {
 514                 if (i != CPU_TO_PACKAGEINDEX(i))
 515                         continue;
 516                 if (min_cpu_irq > CPU_IRQ(i)) {
 517                         min_cpu_irq = CPU_IRQ(i);
 518                         min_loaded = i;
 519                 }
 520         }
 521         max_cpu_irq = ULONG_MAX;
 522
 523 tryanothercpu:
 524         /* Look for heaviest loaded processor.
 525          * We may come back to get the next heaviest loaded processor.
 526          * Skip processors with trivial loads.
 527          */
 528         tmp_cpu_irq = 0;
 529         tmp_loaded = -1;
 530         for_each_online_cpu(i) {
 531                 if (i != CPU_TO_PACKAGEINDEX(i))
 532                         continue;
 533                 if (max_cpu_irq <= CPU_IRQ(i))
 534                         continue;
 535                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 536                         tmp_cpu_irq = CPU_IRQ(i);
 537                         tmp_loaded = i;
 538                 }
 539         }
 540
 541         if (tmp_loaded == -1) {
 542          /* In the case of small number of heavy interrupt sources,
 543           * loading some of the cpus too much. We use Ingo's original
 544           * approach to rotate them around.
 545           */
 546                 if (!first_attempt && imbalance >= useful_load_threshold) {
 547                         rotate_irqs_among_cpus(useful_load_threshold);
 548                         return;
 549                 }
 550                 goto not_worth_the_effort;
 551         }
 552
 553         first_attempt = 0;              /* heaviest search */
 554         max_cpu_irq = tmp_cpu_irq;      /* load */
 555         max_loaded = tmp_loaded;        /* processor */
 556         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 557
 558         /* if imbalance is less than approx 10% of max load, then
 559          * observe diminishing returns action. - quit
 560          */
 561         if (imbalance < (max_cpu_irq >> 3))
 562                 goto not_worth_the_effort;
 563
 564 tryanotherirq:
 565         /* if we select an IRQ to move that can't go where we want, then
 566          * see if there is another one to try.
 567          */
 568         move_this_load = 0;
 569         selected_irq = -1;
 570         for (j = 0; j < NR_IRQS; j++) {
 571                 /* Is this an active IRQ? */
 572                 if (!irq_desc[j].action)
 573                         continue;
 574                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 575                         continue;
 576                 /* Try to find the IRQ that is closest to the imbalance
 577                  * without going over.
 578                  */
 579                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 580                         move_this_load = IRQ_DELTA(max_loaded,j);
 581                         selected_irq = j;
 582                 }
 583         }
 584         if (selected_irq == -1) {
 585                 goto tryanothercpu;
 586         }
 587
 588         imbalance = move_this_load;
 589
 590         /* For physical_balance case, we accumulated both load
 591          * values in the one of the siblings cpu_irq[],
 592          * to use the same code for physical and logical processors
 593          * as much as possible.
 594          *
 595          * NOTE: the cpu_irq[] array holds the sum of the load for
 596          * sibling A and sibling B in the slot for the lowest numbered
 597          * sibling (A), _AND_ the load for sibling B in the slot for
 598          * the higher numbered sibling.
 599          *
 600          * We seek the least loaded sibling by making the comparison
 601          * (A+B)/2 vs B
 602          */
 603         load = CPU_IRQ(min_loaded) >> 1;
 604         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
 605                 if (load > CPU_IRQ(j)) {
 606                         /* This won't change cpu_sibling_map[min_loaded] */
 607                         load = CPU_IRQ(j);
 608                         min_loaded = j;
 609                 }
 610         }
 611
 612         cpus_and(allowed_mask,
 613                 cpu_online_map,
 614                 balance_irq_affinity[selected_irq]);
 615         target_cpu_mask = cpumask_of_cpu(min_loaded);
 616         cpus_and(tmp, target_cpu_mask, allowed_mask);
 617
 618         if (!cpus_empty(tmp)) {
 619                 /* mark for change destination */
 620                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 621
 622                 /* Since we made a change, come back sooner to
 623                  * check for more variation.
 624                  */
 625                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 626                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 627                 return;
 628         }
 629         goto tryanotherirq;
 630
 631 not_worth_the_effort:
 632         /*
 633          * if we did not find an IRQ to move, then adjust the time interval
 634          * upward
 635          */
 636         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 637                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 638         return;
 639 }
 640
 641 static int balanced_irq(void *unused)
 642 {
 643         int i;
 644         unsigned long prev_balance_time = jiffies;
 645         long time_remaining = balanced_irq_interval;
 646
 647         /* push everything to CPU 0 to give us a starting point.  */
 648         for (i = 0 ; i < NR_IRQS ; i++) {
 649                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 650                 set_pending_irq(i, cpumask_of_cpu(0));
 651         }
 652
 653         set_freezable();
 654         for ( ; ; ) {
 655                 time_remaining = schedule_timeout_interruptible(time_remaining);
 656                 try_to_freeze();
 657                 if (time_after(jiffies,
 658                                 prev_balance_time+balanced_irq_interval)) {
 659                         preempt_disable();
 660                         do_irq_balance();
 661                         prev_balance_time = jiffies;
 662                         time_remaining = balanced_irq_interval;
 663                         preempt_enable();
 664                 }
 665         }
 666         return 0;
 667 }
 668
 669 static int __init balanced_irq_init(void)
 670 {
 671         int i;
 672         struct cpuinfo_x86 *c;
 673         cpumask_t tmp;
 674
 675         cpus_shift_right(tmp, cpu_online_map, 2);
 676         c = &boot_cpu_data;
 677         /* When not overwritten by the command line ask subarchitecture. */
 678         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 679                 irqbalance_disabled = NO_BALANCE_IRQ;
 680         if (irqbalance_disabled)
 681                 return 0;
 682
 683          /* disable irqbalance completely if there is only one processor online */
 684         if (num_online_cpus() < 2) {
 685                 irqbalance_disabled = 1;
 686                 return 0;
 687         }
 688         /*
 689          * Enable physical balance only if more than 1 physical processor
 690          * is present
 691          */
 692         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 693                 physical_balance = 1;
 694
 695         for_each_online_cpu(i) {
 696                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 697                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 698                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 699                         printk(KERN_ERR "balanced_irq_init: out of memory");
 700                         goto failed;
 701                 }
 702                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 703                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 704         }
 705
 706         printk(KERN_INFO "Starting balanced_irq\n");
 707         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
 708                 return 0;
 709         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 710 failed:
 711         for_each_possible_cpu(i) {
 712                 kfree(irq_cpu_data[i].irq_delta);
 713                 irq_cpu_data[i].irq_delta = NULL;
 714                 kfree(irq_cpu_data[i].last_irq);
 715                 irq_cpu_data[i].last_irq = NULL;
 716         }
 717         return 0;
 718 }
 719
 720 int __devinit irqbalance_disable(char *str)
 721 {
 722         irqbalance_disabled = 1;
 723         return 1;
 724 }
 725
 726 __setup("noirqbalance", irqbalance_disable);
 727
 728 late_initcall(balanced_irq_init);
 729 #endif /* CONFIG_IRQBALANCE */
 730 #endif /* CONFIG_SMP */
 731
 732 #ifndef CONFIG_SMP
 733 void send_IPI_self(int vector)
 734 {
 735         unsigned int cfg;
 736
 737         /*
 738          * Wait for idle.
 739          */
 740         apic_wait_icr_idle();
 741         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 742         /*
 743          * Send the IPI. The write to APIC_ICR fires this off.
 744          */
 745         apic_write_around(APIC_ICR, cfg);
 746 }
 747 #endif /* !CONFIG_SMP */
 748
 749
 750 /*
 751  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 752  * specific CPU-side IRQs.
 753  */
 754
 755 #define MAX_PIRQS 8
 756 static int pirq_entries [MAX_PIRQS];
 757 static int pirqs_enabled;
 758 int skip_ioapic_setup;
 759
 760 static int __init ioapic_pirq_setup(char *str)
 761 {
 762         int i, max;
 763         int ints[MAX_PIRQS+1];
 764
 765         get_options(str, ARRAY_SIZE(ints), ints);
 766
 767         for (i = 0; i < MAX_PIRQS; i++)
 768                 pirq_entries[i] = -1;
 769
 770         pirqs_enabled = 1;
 771         apic_printk(APIC_VERBOSE, KERN_INFO
 772                         "PIRQ redirection, working around broken MP-BIOS.\n");
 773         max = MAX_PIRQS;
 774         if (ints[0] < MAX_PIRQS)
 775                 max = ints[0];
 776
 777         for (i = 0; i < max; i++) {
 778                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 779                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 780                 /*
 781                  * PIRQs are mapped upside down, usually.
 782                  */
 783                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 784         }
 785         return 1;
 786 }
 787
 788 __setup("pirq=", ioapic_pirq_setup);
 789
 790 /*
 791  * Find the IRQ entry number of a certain pin.
 792  */
 793 static int find_irq_entry(int apic, int pin, int type)
 794 {
 795         int i;
 796
 797         for (i = 0; i < mp_irq_entries; i++)
 798                 if (mp_irqs[i].mpc_irqtype == type &&
 799                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 800                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 801                     mp_irqs[i].mpc_dstirq == pin)
 802                         return i;
 803
 804         return -1;
 805 }
 806
 807 /*
 808  * Find the pin to which IRQ[irq] (ISA) is connected
 809  */
 810 static int __init find_isa_irq_pin(int irq, int type)
 811 {
 812         int i;
 813
 814         for (i = 0; i < mp_irq_entries; i++) {
 815                 int lbus = mp_irqs[i].mpc_srcbus;
 816
 817                 if (test_bit(lbus, mp_bus_not_pci) &&
 818                     (mp_irqs[i].mpc_irqtype == type) &&
 819                     (mp_irqs[i].mpc_srcbusirq == irq))
 820
 821                         return mp_irqs[i].mpc_dstirq;
 822         }
 823         return -1;
 824 }
 825
 826 static int __init find_isa_irq_apic(int irq, int type)
 827 {
 828         int i;
 829
 830         for (i = 0; i < mp_irq_entries; i++) {
 831                 int lbus = mp_irqs[i].mpc_srcbus;
 832
 833                 if (test_bit(lbus, mp_bus_not_pci) &&
 834                     (mp_irqs[i].mpc_irqtype == type) &&
 835                     (mp_irqs[i].mpc_srcbusirq == irq))
 836                         break;
 837         }
 838         if (i < mp_irq_entries) {
 839                 int apic;
 840                 for(apic = 0; apic < nr_ioapics; apic++) {
 841                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 842                                 return apic;
 843                 }
 844         }
 845
 846         return -1;
 847 }
 848
 849 /*
 850  * Find a specific PCI IRQ entry.
 851  * Not an __init, possibly needed by modules
 852  */
 853 static int pin_2_irq(int idx, int apic, int pin);
 854
 855 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 856 {
 857         int apic, i, best_guess = -1;
 858
 859         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 860                 "slot:%d, pin:%d.\n", bus, slot, pin);
 861         if (mp_bus_id_to_pci_bus[bus] == -1) {
 862                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 863                 return -1;
 864         }
 865         for (i = 0; i < mp_irq_entries; i++) {
 866                 int lbus = mp_irqs[i].mpc_srcbus;
 867
 868                 for (apic = 0; apic < nr_ioapics; apic++)
 869                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 870                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 871                                 break;
 872
 873                 if (!test_bit(lbus, mp_bus_not_pci) &&
 874                     !mp_irqs[i].mpc_irqtype &&
 875                     (bus == lbus) &&
 876                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 877                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 878
 879                         if (!(apic || IO_APIC_IRQ(irq)))
 880                                 continue;
 881
 882                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 883                                 return irq;
 884                         /*
 885                          * Use the first all-but-pin matching entry as a
 886                          * best-guess fuzzy result for broken mptables.
 887                          */
 888                         if (best_guess < 0)
 889                                 best_guess = irq;
 890                 }
 891         }
 892         return best_guess;
 893 }
 894 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 895
 896 /*
 897  * This function currently is only a helper for the i386 smp boot process where
 898  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 899  * so mask in all cases should simply be TARGET_CPUS
 900  */
 901 #ifdef CONFIG_SMP
 902 void __init setup_ioapic_dest(void)
 903 {
 904         int pin, ioapic, irq, irq_entry;
 905
 906         if (skip_ioapic_setup == 1)
 907                 return;
 908
 909         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 910                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 911                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 912                         if (irq_entry == -1)
 913                                 continue;
 914                         irq = pin_2_irq(irq_entry, ioapic, pin);
 915                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 916                 }
 917
 918         }
 919 }
 920 #endif
 921
 922 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
 923 /*
 924  * EISA Edge/Level control register, ELCR
 925  */
 926 static int EISA_ELCR(unsigned int irq)
 927 {
 928         if (irq < 16) {
 929                 unsigned int port = 0x4d0 + (irq >> 3);
 930                 return (inb(port) >> (irq & 7)) & 1;
 931         }
 932         apic_printk(APIC_VERBOSE, KERN_INFO
 933                         "Broken MPtable reports ISA irq %d\n", irq);
 934         return 0;
 935 }
 936 #endif
 937
 938 /* ISA interrupts are always polarity zero edge triggered,
 939  * when listed as conforming in the MP table. */
 940
 941 #define default_ISA_trigger(idx)        (0)
 942 #define default_ISA_polarity(idx)       (0)
 943
 944 /* EISA interrupts are always polarity zero and can be edge or level
 945  * trigger depending on the ELCR value.  If an interrupt is listed as
 946  * EISA conforming in the MP table, that means its trigger type must
 947  * be read in from the ELCR */
 948
 949 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 950 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
 951
 952 /* PCI interrupts are always polarity one level triggered,
 953  * when listed as conforming in the MP table. */
 954
 955 #define default_PCI_trigger(idx)        (1)
 956 #define default_PCI_polarity(idx)       (1)
 957
 958 /* MCA interrupts are always polarity zero level triggered,
 959  * when listed as conforming in the MP table. */
 960
 961 #define default_MCA_trigger(idx)        (1)
 962 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
 963
 964 static int MPBIOS_polarity(int idx)
 965 {
 966         int bus = mp_irqs[idx].mpc_srcbus;
 967         int polarity;
 968
 969         /*
 970          * Determine IRQ line polarity (high active or low active):
 971          */
 972         switch (mp_irqs[idx].mpc_irqflag & 3)
 973         {
 974                 case 0: /* conforms, ie. bus-type dependent polarity */
 975                 {
 976                         polarity = test_bit(bus, mp_bus_not_pci)?
 977                                 default_ISA_polarity(idx):
 978                                 default_PCI_polarity(idx);
 979                         break;
 980                 }
 981                 case 1: /* high active */
 982                 {
 983                         polarity = 0;
 984                         break;
 985                 }
 986                 case 2: /* reserved */
 987                 {
 988                         printk(KERN_WARNING "broken BIOS!!\n");
 989                         polarity = 1;
 990                         break;
 991                 }
 992                 case 3: /* low active */
 993                 {
 994                         polarity = 1;
 995                         break;
 996                 }
 997                 default: /* invalid */
 998                 {
 999                         printk(KERN_WARNING "broken BIOS!!\n");
1000                         polarity = 1;
1001                         break;
1002                 }
1003         }
1004         return polarity;
1005 }
1006
1007 static int MPBIOS_trigger(int idx)
1008 {
1009         int bus = mp_irqs[idx].mpc_srcbus;
1010         int trigger;
1011
1012         /*
1013          * Determine IRQ trigger mode (edge or level sensitive):
1014          */
1015         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1016         {
1017                 case 0: /* conforms, ie. bus-type dependent */
1018                 {
1019                         trigger = test_bit(bus, mp_bus_not_pci)?
1020                                         default_ISA_trigger(idx):
1021                                         default_PCI_trigger(idx);
1022 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1023                         switch (mp_bus_id_to_type[bus])
1024                         {
1025                                 case MP_BUS_ISA: /* ISA pin */
1026                                 {
1027                                         /* set before the switch */
1028                                         break;
1029                                 }
1030                                 case MP_BUS_EISA: /* EISA pin */
1031                                 {
1032                                         trigger = default_EISA_trigger(idx);
1033                                         break;
1034                                 }
1035                                 case MP_BUS_PCI: /* PCI pin */
1036                                 {
1037                                         /* set before the switch */
1038                                         break;
1039                                 }
1040                                 case MP_BUS_MCA: /* MCA pin */
1041                                 {
1042                                         trigger = default_MCA_trigger(idx);
1043                                         break;
1044                                 }
1045                                 default:
1046                                 {
1047                                         printk(KERN_WARNING "broken BIOS!!\n");
1048                                         trigger = 1;
1049                                         break;
1050                                 }
1051                         }
1052 #endif
1053                         break;
1054                 }
1055                 case 1: /* edge */
1056                 {
1057                         trigger = 0;
1058                         break;
1059                 }
1060                 case 2: /* reserved */
1061                 {
1062                         printk(KERN_WARNING "broken BIOS!!\n");
1063                         trigger = 1;
1064                         break;
1065                 }
1066                 case 3: /* level */
1067                 {
1068                         trigger = 1;
1069                         break;
1070                 }
1071                 default: /* invalid */
1072                 {
1073                         printk(KERN_WARNING "broken BIOS!!\n");
1074                         trigger = 0;
1075                         break;
1076                 }
1077         }
1078         return trigger;
1079 }
1080
1081 static inline int irq_polarity(int idx)
1082 {
1083         return MPBIOS_polarity(idx);
1084 }
1085
1086 static inline int irq_trigger(int idx)
1087 {
1088         return MPBIOS_trigger(idx);
1089 }
1090
1091 static int pin_2_irq(int idx, int apic, int pin)
1092 {
1093         int irq, i;
1094         int bus = mp_irqs[idx].mpc_srcbus;
1095
1096         /*
1097          * Debugging check, we are in big trouble if this message pops up!
1098          */
1099         if (mp_irqs[idx].mpc_dstirq != pin)
1100                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1101
1102         if (test_bit(bus, mp_bus_not_pci))
1103                 irq = mp_irqs[idx].mpc_srcbusirq;
1104         else {
1105                 /*
1106                  * PCI IRQs are mapped in order
1107                  */
1108                 i = irq = 0;
1109                 while (i < apic)
1110                         irq += nr_ioapic_registers[i++];
1111                 irq += pin;
1112
1113                 /*
1114                  * For MPS mode, so far only needed by ES7000 platform
1115                  */
1116                 if (ioapic_renumber_irq)
1117                         irq = ioapic_renumber_irq(apic, irq);
1118         }
1119
1120         /*
1121          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1122          */
1123         if ((pin >= 16) && (pin <= 23)) {
1124                 if (pirq_entries[pin-16] != -1) {
1125                         if (!pirq_entries[pin-16]) {
1126                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1127                                                 "disabling PIRQ%d\n", pin-16);
1128                         } else {
1129                                 irq = pirq_entries[pin-16];
1130                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1131                                                 "using PIRQ%d -> IRQ %d\n",
1132                                                 pin-16, irq);
1133                         }
1134                 }
1135         }
1136         return irq;
1137 }
1138
1139 static inline int IO_APIC_irq_trigger(int irq)
1140 {
1141         int apic, idx, pin;
1142
1143         for (apic = 0; apic < nr_ioapics; apic++) {
1144                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1145                         idx = find_irq_entry(apic,pin,mp_INT);
1146                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1147                                 return irq_trigger(idx);
1148                 }
1149         }
1150         /*
1151          * nonexistent IRQs are edge default
1152          */
1153         return 0;
1154 }
1155
1156 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1157 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1158
1159 static int __assign_irq_vector(int irq)
1160 {
1161         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1162         int vector, offset;
1163
1164         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1165
1166         if (irq_vector[irq] > 0)
1167                 return irq_vector[irq];
1168
1169         vector = current_vector;
1170         offset = current_offset;
1171 next:
1172         vector += 8;
1173         if (vector >= FIRST_SYSTEM_VECTOR) {
1174                 offset = (offset + 1) % 8;
1175                 vector = FIRST_DEVICE_VECTOR + offset;
1176         }
1177         if (vector == current_vector)
1178                 return -ENOSPC;
1179         if (test_and_set_bit(vector, used_vectors))
1180                 goto next;
1181
1182         current_vector = vector;
1183         current_offset = offset;
1184         irq_vector[irq] = vector;
1185
1186         return vector;
1187 }
1188
1189 static int assign_irq_vector(int irq)
1190 {
1191         unsigned long flags;
1192         int vector;
1193
1194         spin_lock_irqsave(&vector_lock, flags);
1195         vector = __assign_irq_vector(irq);
1196         spin_unlock_irqrestore(&vector_lock, flags);
1197
1198         return vector;
1199 }
1200 static struct irq_chip ioapic_chip;
1201
1202 #define IOAPIC_AUTO     -1
1203 #define IOAPIC_EDGE     0
1204 #define IOAPIC_LEVEL    1
1205
1206 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1207 {
1208         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1209             trigger == IOAPIC_LEVEL) {
1210                 irq_desc[irq].status |= IRQ_LEVEL;
1211                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1212                                          handle_fasteoi_irq, "fasteoi");
1213         } else {
1214                 irq_desc[irq].status &= ~IRQ_LEVEL;
1215                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1216                                          handle_edge_irq, "edge");
1217         }
1218         set_intr_gate(vector, interrupt[irq]);
1219 }
1220
1221 static void __init setup_IO_APIC_irqs(void)
1222 {
1223         struct IO_APIC_route_entry entry;
1224         int apic, pin, idx, irq, first_notcon = 1, vector;
1225         unsigned long flags;
1226
1227         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1228
1229         for (apic = 0; apic < nr_ioapics; apic++) {
1230         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1231
1232                 /*
1233                  * add it to the IO-APIC irq-routing table:
1234                  */
1235                 memset(&entry,0,sizeof(entry));
1236
1237                 entry.delivery_mode = INT_DELIVERY_MODE;
1238                 entry.dest_mode = INT_DEST_MODE;
1239                 entry.mask = 0;                         /* enable IRQ */
1240                 entry.dest.logical.logical_dest =
1241                                         cpu_mask_to_apicid(TARGET_CPUS);
1242
1243                 idx = find_irq_entry(apic,pin,mp_INT);
1244                 if (idx == -1) {
1245                         if (first_notcon) {
1246                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1247                                                 " IO-APIC (apicid-pin) %d-%d",
1248                                                 mp_ioapics[apic].mpc_apicid,
1249                                                 pin);
1250                                 first_notcon = 0;
1251                         } else
1252                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1253                                         mp_ioapics[apic].mpc_apicid, pin);
1254                         continue;
1255                 }
1256
1257                 if (!first_notcon) {
1258                         apic_printk(APIC_VERBOSE, " not connected.\n");
1259                         first_notcon = 1;
1260                 }
1261
1262                 entry.trigger = irq_trigger(idx);
1263                 entry.polarity = irq_polarity(idx);
1264
1265                 if (irq_trigger(idx)) {
1266                         entry.trigger = 1;
1267                         entry.mask = 1;
1268                 }
1269
1270                 irq = pin_2_irq(idx, apic, pin);
1271                 /*
1272                  * skip adding the timer int on secondary nodes, which causes
1273                  * a small but painful rift in the time-space continuum
1274                  */
1275                 if (multi_timer_check(apic, irq))
1276                         continue;
1277                 else
1278                         add_pin_to_irq(irq, apic, pin);
1279
1280                 if (!apic && !IO_APIC_IRQ(irq))
1281                         continue;
1282
1283                 if (IO_APIC_IRQ(irq)) {
1284                         vector = assign_irq_vector(irq);
1285                         entry.vector = vector;
1286                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1287
1288                         if (!apic && (irq < 16))
1289                                 disable_8259A_irq(irq);
1290                 }
1291                 spin_lock_irqsave(&ioapic_lock, flags);
1292                 __ioapic_write_entry(apic, pin, entry);
1293                 spin_unlock_irqrestore(&ioapic_lock, flags);
1294         }
1295         }
1296
1297         if (!first_notcon)
1298                 apic_printk(APIC_VERBOSE, " not connected.\n");
1299 }
1300
1301 /*
1302  * Set up the 8259A-master output pin:
1303  */
1304 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1305 {
1306         struct IO_APIC_route_entry entry;
1307
1308         memset(&entry,0,sizeof(entry));
1309
1310         disable_8259A_irq(0);
1311
1312         /* mask LVT0 */
1313         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1314
1315         /*
1316          * We use logical delivery to get the timer IRQ
1317          * to the first CPU.
1318          */
1319         entry.dest_mode = INT_DEST_MODE;
1320         entry.mask = 0;                                 /* unmask IRQ now */
1321         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1322         entry.delivery_mode = INT_DELIVERY_MODE;
1323         entry.polarity = 0;
1324         entry.trigger = 0;
1325         entry.vector = vector;
1326
1327         /*
1328          * The timer IRQ doesn't have to know that behind the
1329          * scene we have a 8259A-master in AEOI mode ...
1330          */
1331         irq_desc[0].chip = &ioapic_chip;
1332         set_irq_handler(0, handle_edge_irq);
1333
1334         /*
1335          * Add it to the IO-APIC irq-routing table:
1336          */
1337         ioapic_write_entry(apic, pin, entry);
1338
1339         enable_8259A_irq(0);
1340 }
1341
1342 void __init print_IO_APIC(void)
1343 {
1344         int apic, i;
1345         union IO_APIC_reg_00 reg_00;
1346         union IO_APIC_reg_01 reg_01;
1347         union IO_APIC_reg_02 reg_02;
1348         union IO_APIC_reg_03 reg_03;
1349         unsigned long flags;
1350
1351         if (apic_verbosity == APIC_QUIET)
1352                 return;
1353
1354         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1355         for (i = 0; i < nr_ioapics; i++)
1356                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1357                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1358
1359         /*
1360          * We are a bit conservative about what we expect.  We have to
1361          * know about every hardware change ASAP.
1362          */
1363         printk(KERN_INFO "testing the IO APIC.......................\n");
1364
1365         for (apic = 0; apic < nr_ioapics; apic++) {
1366
1367         spin_lock_irqsave(&ioapic_lock, flags);
1368         reg_00.raw = io_apic_read(apic, 0);
1369         reg_01.raw = io_apic_read(apic, 1);
1370         if (reg_01.bits.version >= 0x10)
1371                 reg_02.raw = io_apic_read(apic, 2);
1372         if (reg_01.bits.version >= 0x20)
1373                 reg_03.raw = io_apic_read(apic, 3);
1374         spin_unlock_irqrestore(&ioapic_lock, flags);
1375
1376         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1377         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1378         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1379         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1380         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1381
1382         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1383         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1384
1385         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1386         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1387
1388         /*
1389          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1390          * but the value of reg_02 is read as the previous read register
1391          * value, so ignore it if reg_02 == reg_01.
1392          */
1393         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1394                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1395                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1396         }
1397
1398         /*
1399          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1400          * or reg_03, but the value of reg_0[23] is read as the previous read
1401          * register value, so ignore it if reg_03 == reg_0[12].
1402          */
1403         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1404             reg_03.raw != reg_01.raw) {
1405                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1406                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1407         }
1408
1409         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1410
1411         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1412                           " Stat Dest Deli Vect:   \n");
1413
1414         for (i = 0; i <= reg_01.bits.entries; i++) {
1415                 struct IO_APIC_route_entry entry;
1416
1417                 entry = ioapic_read_entry(apic, i);
1418
1419                 printk(KERN_DEBUG " %02x %03X %02X  ",
1420                         i,
1421                         entry.dest.logical.logical_dest,
1422                         entry.dest.physical.physical_dest
1423                 );
1424
1425                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1426                         entry.mask,
1427                         entry.trigger,
1428                         entry.irr,
1429                         entry.polarity,
1430                         entry.delivery_status,
1431                         entry.dest_mode,
1432                         entry.delivery_mode,
1433                         entry.vector
1434                 );
1435         }
1436         }
1437         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1438         for (i = 0; i < NR_IRQS; i++) {
1439                 struct irq_pin_list *entry = irq_2_pin + i;
1440                 if (entry->pin < 0)
1441                         continue;
1442                 printk(KERN_DEBUG "IRQ%d ", i);
1443                 for (;;) {
1444                         printk("-> %d:%d", entry->apic, entry->pin);
1445                         if (!entry->next)
1446                                 break;
1447                         entry = irq_2_pin + entry->next;
1448                 }
1449                 printk("\n");
1450         }
1451
1452         printk(KERN_INFO ".................................... done.\n");
1453
1454         return;
1455 }
1456
1457 #if 0
1458
1459 static void print_APIC_bitfield (int base)
1460 {
1461         unsigned int v;
1462         int i, j;
1463
1464         if (apic_verbosity == APIC_QUIET)
1465                 return;
1466
1467         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1468         for (i = 0; i < 8; i++) {
1469                 v = apic_read(base + i*0x10);
1470                 for (j = 0; j < 32; j++) {
1471                         if (v & (1<<j))
1472                                 printk("1");
1473                         else
1474                                 printk("0");
1475                 }
1476                 printk("\n");
1477         }
1478 }
1479
1480 void /*__init*/ print_local_APIC(void * dummy)
1481 {
1482         unsigned int v, ver, maxlvt;
1483
1484         if (apic_verbosity == APIC_QUIET)
1485                 return;
1486
1487         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1488                 smp_processor_id(), hard_smp_processor_id());
1489         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v,
1490                         GET_APIC_ID(read_apic_id()));
1491         v = apic_read(APIC_LVR);
1492         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1493         ver = GET_APIC_VERSION(v);
1494         maxlvt = lapic_get_maxlvt();
1495
1496         v = apic_read(APIC_TASKPRI);
1497         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1498
1499         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1500                 v = apic_read(APIC_ARBPRI);
1501                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1502                         v & APIC_ARBPRI_MASK);
1503                 v = apic_read(APIC_PROCPRI);
1504                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1505         }
1506
1507         v = apic_read(APIC_EOI);
1508         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1509         v = apic_read(APIC_RRR);
1510         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1511         v = apic_read(APIC_LDR);
1512         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1513         v = apic_read(APIC_DFR);
1514         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1515         v = apic_read(APIC_SPIV);
1516         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1517
1518         printk(KERN_DEBUG "... APIC ISR field:\n");
1519         print_APIC_bitfield(APIC_ISR);
1520         printk(KERN_DEBUG "... APIC TMR field:\n");
1521         print_APIC_bitfield(APIC_TMR);
1522         printk(KERN_DEBUG "... APIC IRR field:\n");
1523         print_APIC_bitfield(APIC_IRR);
1524
1525         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1526                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1527                         apic_write(APIC_ESR, 0);
1528                 v = apic_read(APIC_ESR);
1529                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1530         }
1531
1532         v = apic_read(APIC_ICR);
1533         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1534         v = apic_read(APIC_ICR2);
1535         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1536
1537         v = apic_read(APIC_LVTT);
1538         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1539
1540         if (maxlvt > 3) {                       /* PC is LVT#4. */
1541                 v = apic_read(APIC_LVTPC);
1542                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1543         }
1544         v = apic_read(APIC_LVT0);
1545         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1546         v = apic_read(APIC_LVT1);
1547         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1548
1549         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1550                 v = apic_read(APIC_LVTERR);
1551                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1552         }
1553
1554         v = apic_read(APIC_TMICT);
1555         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1556         v = apic_read(APIC_TMCCT);
1557         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1558         v = apic_read(APIC_TDCR);
1559         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1560         printk("\n");
1561 }
1562
1563 void print_all_local_APICs (void)
1564 {
1565         on_each_cpu(print_local_APIC, NULL, 1, 1);
1566 }
1567
1568 void /*__init*/ print_PIC(void)
1569 {
1570         unsigned int v;
1571         unsigned long flags;
1572
1573         if (apic_verbosity == APIC_QUIET)
1574                 return;
1575
1576         printk(KERN_DEBUG "\nprinting PIC contents\n");
1577
1578         spin_lock_irqsave(&i8259A_lock, flags);
1579
1580         v = inb(0xa1) << 8 | inb(0x21);
1581         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1582
1583         v = inb(0xa0) << 8 | inb(0x20);
1584         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1585
1586         outb(0x0b,0xa0);
1587         outb(0x0b,0x20);
1588         v = inb(0xa0) << 8 | inb(0x20);
1589         outb(0x0a,0xa0);
1590         outb(0x0a,0x20);
1591
1592         spin_unlock_irqrestore(&i8259A_lock, flags);
1593
1594         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1595
1596         v = inb(0x4d1) << 8 | inb(0x4d0);
1597         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1598 }
1599
1600 #endif  /*  0  */
1601
1602 static void __init enable_IO_APIC(void)
1603 {
1604         union IO_APIC_reg_01 reg_01;
1605         int i8259_apic, i8259_pin;
1606         int i, apic;
1607         unsigned long flags;
1608
1609         for (i = 0; i < PIN_MAP_SIZE; i++) {
1610                 irq_2_pin[i].pin = -1;
1611                 irq_2_pin[i].next = 0;
1612         }
1613         if (!pirqs_enabled)
1614                 for (i = 0; i < MAX_PIRQS; i++)
1615                         pirq_entries[i] = -1;
1616
1617         /*
1618          * The number of IO-APIC IRQ registers (== #pins):
1619          */
1620         for (apic = 0; apic < nr_ioapics; apic++) {
1621                 spin_lock_irqsave(&ioapic_lock, flags);
1622                 reg_01.raw = io_apic_read(apic, 1);
1623                 spin_unlock_irqrestore(&ioapic_lock, flags);
1624                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1625         }
1626         for(apic = 0; apic < nr_ioapics; apic++) {
1627                 int pin;
1628                 /* See if any of the pins is in ExtINT mode */
1629                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1630                         struct IO_APIC_route_entry entry;
1631                         entry = ioapic_read_entry(apic, pin);
1632
1633
1634                         /* If the interrupt line is enabled and in ExtInt mode
1635                          * I have found the pin where the i8259 is connected.
1636                          */
1637                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1638                                 ioapic_i8259.apic = apic;
1639                                 ioapic_i8259.pin  = pin;
1640                                 goto found_i8259;
1641                         }
1642                 }
1643         }
1644  found_i8259:
1645         /* Look to see what if the MP table has reported the ExtINT */
1646         /* If we could not find the appropriate pin by looking at the ioapic
1647          * the i8259 probably is not connected the ioapic but give the
1648          * mptable a chance anyway.
1649          */
1650         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1651         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1652         /* Trust the MP table if nothing is setup in the hardware */
1653         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1654                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1655                 ioapic_i8259.pin  = i8259_pin;
1656                 ioapic_i8259.apic = i8259_apic;
1657         }
1658         /* Complain if the MP table and the hardware disagree */
1659         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1660                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1661         {
1662                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1663         }
1664
1665         /*
1666          * Do not trust the IO-APIC being empty at bootup
1667          */
1668         clear_IO_APIC();
1669 }
1670
1671 /*
1672  * Not an __init, needed by the reboot code
1673  */
1674 void disable_IO_APIC(void)
1675 {
1676         /*
1677          * Clear the IO-APIC before rebooting:
1678          */
1679         clear_IO_APIC();
1680
1681         /*
1682          * If the i8259 is routed through an IOAPIC
1683          * Put that IOAPIC in virtual wire mode
1684          * so legacy interrupts can be delivered.
1685          */
1686         if (ioapic_i8259.pin != -1) {
1687                 struct IO_APIC_route_entry entry;
1688
1689                 memset(&entry, 0, sizeof(entry));
1690                 entry.mask            = 0; /* Enabled */
1691                 entry.trigger         = 0; /* Edge */
1692                 entry.irr             = 0;
1693                 entry.polarity        = 0; /* High */
1694                 entry.delivery_status = 0;
1695                 entry.dest_mode       = 0; /* Physical */
1696                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1697                 entry.vector          = 0;
1698                 entry.dest.physical.physical_dest =
1699                                         GET_APIC_ID(read_apic_id());
1700
1701                 /*
1702                  * Add it to the IO-APIC irq-routing table:
1703                  */
1704                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1705         }
1706         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1707 }
1708
1709 /*
1710  * function to set the IO-APIC physical IDs based on the
1711  * values stored in the MPC table.
1712  *
1713  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1714  */
1715
1716 #ifndef CONFIG_X86_NUMAQ
1717 static void __init setup_ioapic_ids_from_mpc(void)
1718 {
1719         union IO_APIC_reg_00 reg_00;
1720         physid_mask_t phys_id_present_map;
1721         int apic;
1722         int i;
1723         unsigned char old_id;
1724         unsigned long flags;
1725
1726         /*
1727          * Don't check I/O APIC IDs for xAPIC systems.  They have
1728          * no meaning without the serial APIC bus.
1729          */
1730         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1731                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1732                 return;
1733         /*
1734          * This is broken; anything with a real cpu count has to
1735          * circumvent this idiocy regardless.
1736          */
1737         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1738
1739         /*
1740          * Set the IOAPIC ID to the value stored in the MPC table.
1741          */
1742         for (apic = 0; apic < nr_ioapics; apic++) {
1743
1744                 /* Read the register 0 value */
1745                 spin_lock_irqsave(&ioapic_lock, flags);
1746                 reg_00.raw = io_apic_read(apic, 0);
1747                 spin_unlock_irqrestore(&ioapic_lock, flags);
1748
1749                 old_id = mp_ioapics[apic].mpc_apicid;
1750
1751                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1752                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1753                                 apic, mp_ioapics[apic].mpc_apicid);
1754                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1755                                 reg_00.bits.ID);
1756                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1757                 }
1758
1759                 /*
1760                  * Sanity check, is the ID really free? Every APIC in a
1761                  * system must have a unique ID or we get lots of nice
1762                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1763                  */
1764                 if (check_apicid_used(phys_id_present_map,
1765                                         mp_ioapics[apic].mpc_apicid)) {
1766                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1767                                 apic, mp_ioapics[apic].mpc_apicid);
1768                         for (i = 0; i < get_physical_broadcast(); i++)
1769                                 if (!physid_isset(i, phys_id_present_map))
1770                                         break;
1771                         if (i >= get_physical_broadcast())
1772                                 panic("Max APIC ID exceeded!\n");
1773                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1774                                 i);
1775                         physid_set(i, phys_id_present_map);
1776                         mp_ioapics[apic].mpc_apicid = i;
1777                 } else {
1778                         physid_mask_t tmp;
1779                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1780                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1781                                         "phys_id_present_map\n",
1782                                         mp_ioapics[apic].mpc_apicid);
1783                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1784                 }
1785
1786
1787                 /*
1788                  * We need to adjust the IRQ routing table
1789                  * if the ID changed.
1790                  */
1791                 if (old_id != mp_ioapics[apic].mpc_apicid)
1792                         for (i = 0; i < mp_irq_entries; i++)
1793                                 if (mp_irqs[i].mpc_dstapic == old_id)
1794                                         mp_irqs[i].mpc_dstapic
1795                                                 = mp_ioapics[apic].mpc_apicid;
1796
1797                 /*
1798                  * Read the right value from the MPC table and
1799                  * write it into the ID register.
1800                  */
1801                 apic_printk(APIC_VERBOSE, KERN_INFO
1802                         "...changing IO-APIC physical APIC ID to %d ...",
1803                         mp_ioapics[apic].mpc_apicid);
1804
1805                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1806                 spin_lock_irqsave(&ioapic_lock, flags);
1807                 io_apic_write(apic, 0, reg_00.raw);
1808                 spin_unlock_irqrestore(&ioapic_lock, flags);
1809
1810                 /*
1811                  * Sanity check
1812                  */
1813                 spin_lock_irqsave(&ioapic_lock, flags);
1814                 reg_00.raw = io_apic_read(apic, 0);
1815                 spin_unlock_irqrestore(&ioapic_lock, flags);
1816                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1817                         printk("could not set ID!\n");
1818                 else
1819                         apic_printk(APIC_VERBOSE, " ok.\n");
1820         }
1821 }
1822 #else
1823 static void __init setup_ioapic_ids_from_mpc(void) { }
1824 #endif
1825
1826 int no_timer_check __initdata;
1827
1828 static int __init notimercheck(char *s)
1829 {
1830         no_timer_check = 1;
1831         return 1;
1832 }
1833 __setup("no_timer_check", notimercheck);
1834
1835 /*
1836  * There is a nasty bug in some older SMP boards, their mptable lies
1837  * about the timer IRQ. We do the following to work around the situation:
1838  *
1839  *      - timer IRQ defaults to IO-APIC IRQ
1840  *      - if this function detects that timer IRQs are defunct, then we fall
1841  *        back to ISA timer IRQs
1842  */
1843 static int __init timer_irq_works(void)
1844 {
1845         unsigned long t1 = jiffies;
1846         unsigned long flags;
1847
1848         if (no_timer_check)
1849                 return 1;
1850
1851         local_save_flags(flags);
1852         local_irq_enable();
1853         /* Let ten ticks pass... */
1854         mdelay((10 * 1000) / HZ);
1855         local_irq_restore(flags);
1856
1857         /*
1858          * Expect a few ticks at least, to be sure some possible
1859          * glue logic does not lock up after one or two first
1860          * ticks in a non-ExtINT mode.  Also the local APIC
1861          * might have cached one ExtINT interrupt.  Finally, at
1862          * least one tick may be lost due to delays.
1863          */
1864         if (time_after(jiffies, t1 + 4))
1865                 return 1;
1866
1867         return 0;
1868 }
1869
1870 /*
1871  * In the SMP+IOAPIC case it might happen that there are an unspecified
1872  * number of pending IRQ events unhandled. These cases are very rare,
1873  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1874  * better to do it this way as thus we do not have to be aware of
1875  * 'pending' interrupts in the IRQ path, except at this point.
1876  */
1877 /*
1878  * Edge triggered needs to resend any interrupt
1879  * that was delayed but this is now handled in the device
1880  * independent code.
1881  */
1882
1883 /*
1884  * Startup quirk:
1885  *
1886  * Starting up a edge-triggered IO-APIC interrupt is
1887  * nasty - we need to make sure that we get the edge.
1888  * If it is already asserted for some reason, we need
1889  * return 1 to indicate that is was pending.
1890  *
1891  * This is not complete - we should be able to fake
1892  * an edge even if it isn't on the 8259A...
1893  *
1894  * (We do this for level-triggered IRQs too - it cannot hurt.)
1895  */
1896 static unsigned int startup_ioapic_irq(unsigned int irq)
1897 {
1898         int was_pending = 0;
1899         unsigned long flags;
1900
1901         spin_lock_irqsave(&ioapic_lock, flags);
1902         if (irq < 16) {
1903                 disable_8259A_irq(irq);
1904                 if (i8259A_irq_pending(irq))
1905                         was_pending = 1;
1906         }
1907         __unmask_IO_APIC_irq(irq);
1908         spin_unlock_irqrestore(&ioapic_lock, flags);
1909
1910         return was_pending;
1911 }
1912
1913 static void ack_ioapic_irq(unsigned int irq)
1914 {
1915         move_native_irq(irq);
1916         ack_APIC_irq();
1917 }
1918
1919 static void ack_ioapic_quirk_irq(unsigned int irq)
1920 {
1921         unsigned long v;
1922         int i;
1923
1924         move_native_irq(irq);
1925 /*
1926  * It appears there is an erratum which affects at least version 0x11
1927  * of I/O APIC (that's the 82093AA and cores integrated into various
1928  * chipsets).  Under certain conditions a level-triggered interrupt is
1929  * erroneously delivered as edge-triggered one but the respective IRR
1930  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1931  * message but it will never arrive and further interrupts are blocked
1932  * from the source.  The exact reason is so far unknown, but the
1933  * phenomenon was observed when two consecutive interrupt requests
1934  * from a given source get delivered to the same CPU and the source is
1935  * temporarily disabled in between.
1936  *
1937  * A workaround is to simulate an EOI message manually.  We achieve it
1938  * by setting the trigger mode to edge and then to level when the edge
1939  * trigger mode gets detected in the TMR of a local APIC for a
1940  * level-triggered interrupt.  We mask the source for the time of the
1941  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1942  * The idea is from Manfred Spraul.  --macro
1943  */
1944         i = irq_vector[irq];
1945
1946         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1947
1948         ack_APIC_irq();
1949
1950         if (!(v & (1 << (i & 0x1f)))) {
1951                 atomic_inc(&irq_mis_count);
1952                 spin_lock(&ioapic_lock);
1953                 __mask_and_edge_IO_APIC_irq(irq);
1954                 __unmask_and_level_IO_APIC_irq(irq);
1955                 spin_unlock(&ioapic_lock);
1956         }
1957 }
1958
1959 static int ioapic_retrigger_irq(unsigned int irq)
1960 {
1961         send_IPI_self(irq_vector[irq]);
1962
1963         return 1;
1964 }
1965
1966 static struct irq_chip ioapic_chip __read_mostly = {
1967         .name           = "IO-APIC",
1968         .startup        = startup_ioapic_irq,
1969         .mask           = mask_IO_APIC_irq,
1970         .unmask         = unmask_IO_APIC_irq,
1971         .ack            = ack_ioapic_irq,
1972         .eoi            = ack_ioapic_quirk_irq,
1973 #ifdef CONFIG_SMP
1974         .set_affinity   = set_ioapic_affinity_irq,
1975 #endif
1976         .retrigger      = ioapic_retrigger_irq,
1977 };
1978
1979
1980 static inline void init_IO_APIC_traps(void)
1981 {
1982         int irq;
1983
1984         /*
1985          * NOTE! The local APIC isn't very good at handling
1986          * multiple interrupts at the same interrupt level.
1987          * As the interrupt level is determined by taking the
1988          * vector number and shifting that right by 4, we
1989          * want to spread these out a bit so that they don't
1990          * all fall in the same interrupt level.
1991          *
1992          * Also, we've got to be careful not to trash gate
1993          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1994          */
1995         for (irq = 0; irq < NR_IRQS ; irq++) {
1996                 int tmp = irq;
1997                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1998                         /*
1999                          * Hmm.. We don't have an entry for this,
2000                          * so default to an old-fashioned 8259
2001                          * interrupt if we can..
2002                          */
2003                         if (irq < 16)
2004                                 make_8259A_irq(irq);
2005                         else
2006                                 /* Strange. Oh, well.. */
2007                                 irq_desc[irq].chip = &no_irq_chip;
2008                 }
2009         }
2010 }
2011
2012 /*
2013  * The local APIC irq-chip implementation:
2014  */
2015
2016 static void ack_apic(unsigned int irq)
2017 {
2018         ack_APIC_irq();
2019 }
2020
2021 static void mask_lapic_irq (unsigned int irq)
2022 {
2023         unsigned long v;
2024
2025         v = apic_read(APIC_LVT0);
2026         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2027 }
2028
2029 static void unmask_lapic_irq (unsigned int irq)
2030 {
2031         unsigned long v;
2032
2033         v = apic_read(APIC_LVT0);
2034         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2035 }
2036
2037 static struct irq_chip lapic_chip __read_mostly = {
2038         .name           = "local-APIC-edge",
2039         .mask           = mask_lapic_irq,
2040         .unmask         = unmask_lapic_irq,
2041         .eoi            = ack_apic,
2042 };
2043
2044 static void __init setup_nmi(void)
2045 {
2046         /*
2047          * Dirty trick to enable the NMI watchdog ...
2048          * We put the 8259A master into AEOI mode and
2049          * unmask on all local APICs LVT0 as NMI.
2050          *
2051          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2052          * is from Maciej W. Rozycki - so we do not have to EOI from
2053          * the NMI handler or the timer interrupt.
2054          */
2055         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2056
2057         enable_NMI_through_LVT0();
2058
2059         apic_printk(APIC_VERBOSE, " done.\n");
2060 }
2061
2062 /*
2063  * This looks a bit hackish but it's about the only one way of sending
2064  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2065  * not support the ExtINT mode, unfortunately.  We need to send these
2066  * cycles as some i82489DX-based boards have glue logic that keeps the
2067  * 8259A interrupt line asserted until INTA.  --macro
2068  */
2069 static inline void unlock_ExtINT_logic(void)
2070 {
2071         int apic, pin, i;
2072         struct IO_APIC_route_entry entry0, entry1;
2073         unsigned char save_control, save_freq_select;
2074
2075         pin  = find_isa_irq_pin(8, mp_INT);
2076         if (pin == -1) {
2077                 WARN_ON_ONCE(1);
2078                 return;
2079         }
2080         apic = find_isa_irq_apic(8, mp_INT);
2081         if (apic == -1) {
2082                 WARN_ON_ONCE(1);
2083                 return;
2084         }
2085
2086         entry0 = ioapic_read_entry(apic, pin);
2087         clear_IO_APIC_pin(apic, pin);
2088
2089         memset(&entry1, 0, sizeof(entry1));
2090
2091         entry1.dest_mode = 0;                   /* physical delivery */
2092         entry1.mask = 0;                        /* unmask IRQ now */
2093         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2094         entry1.delivery_mode = dest_ExtINT;
2095         entry1.polarity = entry0.polarity;
2096         entry1.trigger = 0;
2097         entry1.vector = 0;
2098
2099         ioapic_write_entry(apic, pin, entry1);
2100
2101         save_control = CMOS_READ(RTC_CONTROL);
2102         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2103         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2104                    RTC_FREQ_SELECT);
2105         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2106
2107         i = 100;
2108         while (i-- > 0) {
2109                 mdelay(10);
2110                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2111                         i -= 10;
2112         }
2113
2114         CMOS_WRITE(save_control, RTC_CONTROL);
2115         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2116         clear_IO_APIC_pin(apic, pin);
2117
2118         ioapic_write_entry(apic, pin, entry0);
2119 }
2120
2121 /*
2122  * This code may look a bit paranoid, but it's supposed to cooperate with
2123  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2124  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2125  * fanatically on his truly buggy board.
2126  */
2127 static inline void __init check_timer(void)
2128 {
2129         int apic1, pin1, apic2, pin2;
2130         int vector;
2131         unsigned int ver;
2132         unsigned long flags;
2133
2134         local_irq_save(flags);
2135
2136         ver = apic_read(APIC_LVR);
2137         ver = GET_APIC_VERSION(ver);
2138
2139         /*
2140          * get/set the timer IRQ vector:
2141          */
2142         disable_8259A_irq(0);
2143         vector = assign_irq_vector(0);
2144         set_intr_gate(vector, interrupt[0]);
2145
2146         /*
2147          * Subtle, code in do_timer_interrupt() expects an AEOI
2148          * mode for the 8259A whenever interrupts are routed
2149          * through I/O APICs.  Also IRQ0 has to be enabled in
2150          * the 8259A which implies the virtual wire has to be
2151          * disabled in the local APIC.  Finally timer interrupts
2152          * need to be acknowledged manually in the 8259A for
2153          * timer_interrupt() and for the i82489DX when using
2154          * the NMI watchdog.
2155          */
2156         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2157         init_8259A(1);
2158         timer_ack = !cpu_has_tsc;
2159         timer_ack |= (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2160         if (timer_over_8254 > 0)
2161                 enable_8259A_irq(0);
2162
2163         pin1  = find_isa_irq_pin(0, mp_INT);
2164         apic1 = find_isa_irq_apic(0, mp_INT);
2165         pin2  = ioapic_i8259.pin;
2166         apic2 = ioapic_i8259.apic;
2167
2168         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2169                 vector, apic1, pin1, apic2, pin2);
2170
2171         if (pin1 != -1) {
2172                 /*
2173                  * Ok, does IRQ0 through the IOAPIC work?
2174                  */
2175                 unmask_IO_APIC_irq(0);
2176                 if (timer_irq_works()) {
2177                         if (nmi_watchdog == NMI_IO_APIC) {
2178                                 disable_8259A_irq(0);
2179                                 setup_nmi();
2180                                 enable_8259A_irq(0);
2181                         }
2182                         if (disable_timer_pin_1 > 0)
2183                                 clear_IO_APIC_pin(0, pin1);
2184                         goto out;
2185                 }
2186                 clear_IO_APIC_pin(apic1, pin1);
2187                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2188                                 "IO-APIC\n");
2189         }
2190
2191         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2192         if (pin2 != -1) {
2193                 printk("\n..... (found pin %d) ...", pin2);
2194                 /*
2195                  * legacy devices should be connected to IO APIC #0
2196                  */
2197                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2198                 if (timer_irq_works()) {
2199                         printk("works.\n");
2200                         if (pin1 != -1)
2201                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2202                         else
2203                                 add_pin_to_irq(0, apic2, pin2);
2204                         if (nmi_watchdog == NMI_IO_APIC) {
2205                                 setup_nmi();
2206                         }
2207                         goto out;
2208                 }
2209                 /*
2210                  * Cleanup, just in case ...
2211                  */
2212                 clear_IO_APIC_pin(apic2, pin2);
2213         }
2214         printk(" failed.\n");
2215
2216         if (nmi_watchdog == NMI_IO_APIC) {
2217                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2218                 nmi_watchdog = 0;
2219         }
2220
2221         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2222
2223         disable_8259A_irq(0);
2224         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2225                                       "fasteoi");
2226         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2227         enable_8259A_irq(0);
2228
2229         if (timer_irq_works()) {
2230                 printk(" works.\n");
2231                 goto out;
2232         }
2233         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2234         printk(" failed.\n");
2235
2236         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2237
2238         timer_ack = 0;
2239         init_8259A(0);
2240         make_8259A_irq(0);
2241         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2242
2243         unlock_ExtINT_logic();
2244
2245         if (timer_irq_works()) {
2246                 printk(" works.\n");
2247                 goto out;
2248         }
2249         printk(" failed :(.\n");
2250         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2251                 "report.  Then try booting with the 'noapic' option");
2252 out:
2253         local_irq_restore(flags);
2254 }
2255
2256 /*
2257  *
2258  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2259  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2260  *   Linux doesn't really care, as it's not actually used
2261  *   for any interrupt handling anyway.
2262  */
2263 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2264
2265 void __init setup_IO_APIC(void)
2266 {
2267         int i;
2268
2269         /* Reserve all the system vectors. */
2270         for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2271                 set_bit(i, used_vectors);
2272
2273         enable_IO_APIC();
2274
2275         if (acpi_ioapic)
2276                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2277         else
2278                 io_apic_irqs = ~PIC_IRQS;
2279
2280         printk("ENABLING IO-APIC IRQs\n");
2281
2282         /*
2283          * Set up IO-APIC IRQ routing.
2284          */
2285         if (!acpi_ioapic)
2286                 setup_ioapic_ids_from_mpc();
2287         sync_Arb_IDs();
2288         setup_IO_APIC_irqs();
2289         init_IO_APIC_traps();
2290         check_timer();
2291         if (!acpi_ioapic)
2292                 print_IO_APIC();
2293 }
2294
2295 static int __init setup_disable_8254_timer(char *s)
2296 {
2297         timer_over_8254 = -1;
2298         return 1;
2299 }
2300 static int __init setup_enable_8254_timer(char *s)
2301 {
2302         timer_over_8254 = 2;
2303         return 1;
2304 }
2305
2306 __setup("disable_8254_timer", setup_disable_8254_timer);
2307 __setup("enable_8254_timer", setup_enable_8254_timer);
2308
2309 /*
2310  *      Called after all the initialization is done. If we didnt find any
2311  *      APIC bugs then we can allow the modify fast path
2312  */
2313
2314 static int __init io_apic_bug_finalize(void)
2315 {
2316         if(sis_apic_bug == -1)
2317                 sis_apic_bug = 0;
2318         return 0;
2319 }
2320
2321 late_initcall(io_apic_bug_finalize);
2322
2323 struct sysfs_ioapic_data {
2324         struct sys_device dev;
2325         struct IO_APIC_route_entry entry[0];
2326 };
2327 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2328
2329 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2330 {
2331         struct IO_APIC_route_entry *entry;
2332         struct sysfs_ioapic_data *data;
2333         int i;
2334
2335         data = container_of(dev, struct sysfs_ioapic_data, dev);
2336         entry = data->entry;
2337         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2338                 entry[i] = ioapic_read_entry(dev->id, i);
2339
2340         return 0;
2341 }
2342
2343 static int ioapic_resume(struct sys_device *dev)
2344 {
2345         struct IO_APIC_route_entry *entry;
2346         struct sysfs_ioapic_data *data;
2347         unsigned long flags;
2348         union IO_APIC_reg_00 reg_00;
2349         int i;
2350
2351         data = container_of(dev, struct sysfs_ioapic_data, dev);
2352         entry = data->entry;
2353
2354         spin_lock_irqsave(&ioapic_lock, flags);
2355         reg_00.raw = io_apic_read(dev->id, 0);
2356         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2357                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2358                 io_apic_write(dev->id, 0, reg_00.raw);
2359         }
2360         spin_unlock_irqrestore(&ioapic_lock, flags);
2361         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2362                 ioapic_write_entry(dev->id, i, entry[i]);
2363
2364         return 0;
2365 }
2366
2367 static struct sysdev_class ioapic_sysdev_class = {
2368         .name = "ioapic",
2369         .suspend = ioapic_suspend,
2370         .resume = ioapic_resume,
2371 };
2372
2373 static int __init ioapic_init_sysfs(void)
2374 {
2375         struct sys_device * dev;
2376         int i, size, error = 0;
2377
2378         error = sysdev_class_register(&ioapic_sysdev_class);
2379         if (error)
2380                 return error;
2381
2382         for (i = 0; i < nr_ioapics; i++ ) {
2383                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2384                         * sizeof(struct IO_APIC_route_entry);
2385                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2386                 if (!mp_ioapic_data[i]) {
2387                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2388                         continue;
2389                 }
2390                 memset(mp_ioapic_data[i], 0, size);
2391                 dev = &mp_ioapic_data[i]->dev;
2392                 dev->id = i;
2393                 dev->cls = &ioapic_sysdev_class;
2394                 error = sysdev_register(dev);
2395                 if (error) {
2396                         kfree(mp_ioapic_data[i]);
2397                         mp_ioapic_data[i] = NULL;
2398                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2399                         continue;
2400                 }
2401         }
2402
2403         return 0;
2404 }
2405
2406 device_initcall(ioapic_init_sysfs);
2407
2408 /*
2409  * Dynamic irq allocate and deallocation
2410  */
2411 int create_irq(void)
2412 {
2413         /* Allocate an unused irq */
2414         int irq, new, vector = 0;
2415         unsigned long flags;
2416
2417         irq = -ENOSPC;
2418         spin_lock_irqsave(&vector_lock, flags);
2419         for (new = (NR_IRQS - 1); new >= 0; new--) {
2420                 if (platform_legacy_irq(new))
2421                         continue;
2422                 if (irq_vector[new] != 0)
2423                         continue;
2424                 vector = __assign_irq_vector(new);
2425                 if (likely(vector > 0))
2426                         irq = new;
2427                 break;
2428         }
2429         spin_unlock_irqrestore(&vector_lock, flags);
2430
2431         if (irq >= 0) {
2432                 set_intr_gate(vector, interrupt[irq]);
2433                 dynamic_irq_init(irq);
2434         }
2435         return irq;
2436 }
2437
2438 void destroy_irq(unsigned int irq)
2439 {
2440         unsigned long flags;
2441
2442         dynamic_irq_cleanup(irq);
2443
2444         spin_lock_irqsave(&vector_lock, flags);
2445         irq_vector[irq] = 0;
2446         spin_unlock_irqrestore(&vector_lock, flags);
2447 }
2448
2449 /*
2450  * MSI message composition
2451  */
2452 #ifdef CONFIG_PCI_MSI
2453 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2454 {
2455         int vector;
2456         unsigned dest;
2457
2458         vector = assign_irq_vector(irq);
2459         if (vector >= 0) {
2460                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2461
2462                 msg->address_hi = MSI_ADDR_BASE_HI;
2463                 msg->address_lo =
2464                         MSI_ADDR_BASE_LO |
2465                         ((INT_DEST_MODE == 0) ?
2466                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2467                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2468                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2469                                 MSI_ADDR_REDIRECTION_CPU:
2470                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2471                         MSI_ADDR_DEST_ID(dest);
2472
2473                 msg->data =
2474                         MSI_DATA_TRIGGER_EDGE |
2475                         MSI_DATA_LEVEL_ASSERT |
2476                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2477                                 MSI_DATA_DELIVERY_FIXED:
2478                                 MSI_DATA_DELIVERY_LOWPRI) |
2479                         MSI_DATA_VECTOR(vector);
2480         }
2481         return vector;
2482 }
2483
2484 #ifdef CONFIG_SMP
2485 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2486 {
2487         struct msi_msg msg;
2488         unsigned int dest;
2489         cpumask_t tmp;
2490         int vector;
2491
2492         cpus_and(tmp, mask, cpu_online_map);
2493         if (cpus_empty(tmp))
2494                 tmp = TARGET_CPUS;
2495
2496         vector = assign_irq_vector(irq);
2497         if (vector < 0)
2498                 return;
2499
2500         dest = cpu_mask_to_apicid(mask);
2501
2502         read_msi_msg(irq, &msg);
2503
2504         msg.data &= ~MSI_DATA_VECTOR_MASK;
2505         msg.data |= MSI_DATA_VECTOR(vector);
2506         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2507         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2508
2509         write_msi_msg(irq, &msg);
2510         irq_desc[irq].affinity = mask;
2511 }
2512 #endif /* CONFIG_SMP */
2513
2514 /*
2515  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2516  * which implement the MSI or MSI-X Capability Structure.
2517  */
2518 static struct irq_chip msi_chip = {
2519         .name           = "PCI-MSI",
2520         .unmask         = unmask_msi_irq,
2521         .mask           = mask_msi_irq,
2522         .ack            = ack_ioapic_irq,
2523 #ifdef CONFIG_SMP
2524         .set_affinity   = set_msi_irq_affinity,
2525 #endif
2526         .retrigger      = ioapic_retrigger_irq,
2527 };
2528
2529 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2530 {
2531         struct msi_msg msg;
2532         int irq, ret;
2533         irq = create_irq();
2534         if (irq < 0)
2535                 return irq;
2536
2537         ret = msi_compose_msg(dev, irq, &msg);
2538         if (ret < 0) {
2539                 destroy_irq(irq);
2540                 return ret;
2541         }
2542
2543         set_irq_msi(irq, desc);
2544         write_msi_msg(irq, &msg);
2545
2546         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2547                                       "edge");
2548
2549         return 0;
2550 }
2551
2552 void arch_teardown_msi_irq(unsigned int irq)
2553 {
2554         destroy_irq(irq);
2555 }
2556
2557 #endif /* CONFIG_PCI_MSI */
2558
2559 /*
2560  * Hypertransport interrupt support
2561  */
2562 #ifdef CONFIG_HT_IRQ
2563
2564 #ifdef CONFIG_SMP
2565
2566 static void target_ht_irq(unsigned int irq, unsigned int dest)
2567 {
2568         struct ht_irq_msg msg;
2569         fetch_ht_irq_msg(irq, &msg);
2570
2571         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2572         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2573
2574         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2575         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2576
2577         write_ht_irq_msg(irq, &msg);
2578 }
2579
2580 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2581 {
2582         unsigned int dest;
2583         cpumask_t tmp;
2584
2585         cpus_and(tmp, mask, cpu_online_map);
2586         if (cpus_empty(tmp))
2587                 tmp = TARGET_CPUS;
2588
2589         cpus_and(mask, tmp, CPU_MASK_ALL);
2590
2591         dest = cpu_mask_to_apicid(mask);
2592
2593         target_ht_irq(irq, dest);
2594         irq_desc[irq].affinity = mask;
2595 }
2596 #endif
2597
2598 static struct irq_chip ht_irq_chip = {
2599         .name           = "PCI-HT",
2600         .mask           = mask_ht_irq,
2601         .unmask         = unmask_ht_irq,
2602         .ack            = ack_ioapic_irq,
2603 #ifdef CONFIG_SMP
2604         .set_affinity   = set_ht_irq_affinity,
2605 #endif
2606         .retrigger      = ioapic_retrigger_irq,
2607 };
2608
2609 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2610 {
2611         int vector;
2612
2613         vector = assign_irq_vector(irq);
2614         if (vector >= 0) {
2615                 struct ht_irq_msg msg;
2616                 unsigned dest;
2617                 cpumask_t tmp;
2618
2619                 cpus_clear(tmp);
2620                 cpu_set(vector >> 8, tmp);
2621                 dest = cpu_mask_to_apicid(tmp);
2622
2623                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2624
2625                 msg.address_lo =
2626                         HT_IRQ_LOW_BASE |
2627                         HT_IRQ_LOW_DEST_ID(dest) |
2628                         HT_IRQ_LOW_VECTOR(vector) |
2629                         ((INT_DEST_MODE == 0) ?
2630                                 HT_IRQ_LOW_DM_PHYSICAL :
2631                                 HT_IRQ_LOW_DM_LOGICAL) |
2632                         HT_IRQ_LOW_RQEOI_EDGE |
2633                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2634                                 HT_IRQ_LOW_MT_FIXED :
2635                                 HT_IRQ_LOW_MT_ARBITRATED) |
2636                         HT_IRQ_LOW_IRQ_MASKED;
2637
2638                 write_ht_irq_msg(irq, &msg);
2639
2640                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2641                                               handle_edge_irq, "edge");
2642         }
2643         return vector;
2644 }
2645 #endif /* CONFIG_HT_IRQ */
2646
2647 /* --------------------------------------------------------------------------
2648                           ACPI-based IOAPIC Configuration
2649    -------------------------------------------------------------------------- */
2650
2651 #ifdef CONFIG_ACPI
2652
2653 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2654 {
2655         union IO_APIC_reg_00 reg_00;
2656         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2657         physid_mask_t tmp;
2658         unsigned long flags;
2659         int i = 0;
2660
2661         /*
2662          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2663          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2664          * supports up to 16 on one shared APIC bus.
2665          *
2666          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2667          *      advantage of new APIC bus architecture.
2668          */
2669
2670         if (physids_empty(apic_id_map))
2671                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2672
2673         spin_lock_irqsave(&ioapic_lock, flags);
2674         reg_00.raw = io_apic_read(ioapic, 0);
2675         spin_unlock_irqrestore(&ioapic_lock, flags);
2676
2677         if (apic_id >= get_physical_broadcast()) {
2678                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2679                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2680                 apic_id = reg_00.bits.ID;
2681         }
2682
2683         /*
2684          * Every APIC in a system must have a unique ID or we get lots of nice
2685          * 'stuck on smp_invalidate_needed IPI wait' messages.
2686          */
2687         if (check_apicid_used(apic_id_map, apic_id)) {
2688
2689                 for (i = 0; i < get_physical_broadcast(); i++) {
2690                         if (!check_apicid_used(apic_id_map, i))
2691                                 break;
2692                 }
2693
2694                 if (i == get_physical_broadcast())
2695                         panic("Max apic_id exceeded!\n");
2696
2697                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2698                         "trying %d\n", ioapic, apic_id, i);
2699
2700                 apic_id = i;
2701         }
2702
2703         tmp = apicid_to_cpu_present(apic_id);
2704         physids_or(apic_id_map, apic_id_map, tmp);
2705
2706         if (reg_00.bits.ID != apic_id) {
2707                 reg_00.bits.ID = apic_id;
2708
2709                 spin_lock_irqsave(&ioapic_lock, flags);
2710                 io_apic_write(ioapic, 0, reg_00.raw);
2711                 reg_00.raw = io_apic_read(ioapic, 0);
2712                 spin_unlock_irqrestore(&ioapic_lock, flags);
2713
2714                 /* Sanity check */
2715                 if (reg_00.bits.ID != apic_id) {
2716                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2717                         return -1;
2718                 }
2719         }
2720
2721         apic_printk(APIC_VERBOSE, KERN_INFO
2722                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2723
2724         return apic_id;
2725 }
2726
2727
2728 int __init io_apic_get_version (int ioapic)
2729 {
2730         union IO_APIC_reg_01    reg_01;
2731         unsigned long flags;
2732
2733         spin_lock_irqsave(&ioapic_lock, flags);
2734         reg_01.raw = io_apic_read(ioapic, 1);
2735         spin_unlock_irqrestore(&ioapic_lock, flags);
2736
2737         return reg_01.bits.version;
2738 }
2739
2740
2741 int __init io_apic_get_redir_entries (int ioapic)
2742 {
2743         union IO_APIC_reg_01    reg_01;
2744         unsigned long flags;
2745
2746         spin_lock_irqsave(&ioapic_lock, flags);
2747         reg_01.raw = io_apic_read(ioapic, 1);
2748         spin_unlock_irqrestore(&ioapic_lock, flags);
2749
2750         return reg_01.bits.entries;
2751 }
2752
2753
2754 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2755 {
2756         struct IO_APIC_route_entry entry;
2757         unsigned long flags;
2758
2759         if (!IO_APIC_IRQ(irq)) {
2760                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2761                         ioapic);
2762                 return -EINVAL;
2763         }
2764
2765         /*
2766          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2767          * Note that we mask (disable) IRQs now -- these get enabled when the
2768          * corresponding device driver registers for this IRQ.
2769          */
2770
2771         memset(&entry,0,sizeof(entry));
2772
2773         entry.delivery_mode = INT_DELIVERY_MODE;
2774         entry.dest_mode = INT_DEST_MODE;
2775         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2776         entry.trigger = edge_level;
2777         entry.polarity = active_high_low;
2778         entry.mask  = 1;
2779
2780         /*
2781          * IRQs < 16 are already in the irq_2_pin[] map
2782          */
2783         if (irq >= 16)
2784                 add_pin_to_irq(irq, ioapic, pin);
2785
2786         entry.vector = assign_irq_vector(irq);
2787
2788         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2789                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2790                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2791                 edge_level, active_high_low);
2792
2793         ioapic_register_intr(irq, entry.vector, edge_level);
2794
2795         if (!ioapic && (irq < 16))
2796                 disable_8259A_irq(irq);
2797
2798         spin_lock_irqsave(&ioapic_lock, flags);
2799         __ioapic_write_entry(ioapic, pin, entry);
2800         spin_unlock_irqrestore(&ioapic_lock, flags);
2801
2802         return 0;
2803 }
2804
2805 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2806 {
2807         int i;
2808
2809         if (skip_ioapic_setup)
2810                 return -1;
2811
2812         for (i = 0; i < mp_irq_entries; i++)
2813                 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2814                     mp_irqs[i].mpc_srcbusirq == bus_irq)
2815                         break;
2816         if (i >= mp_irq_entries)
2817                 return -1;
2818
2819         *trigger = irq_trigger(i);
2820         *polarity = irq_polarity(i);
2821         return 0;
2822 }
2823
2824 #endif /* CONFIG_ACPI */
2825
2826 static int __init parse_disable_timer_pin_1(char *arg)
2827 {
2828         disable_timer_pin_1 = 1;
2829         return 0;
2830 }
2831 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2832
2833 static int __init parse_enable_timer_pin_1(char *arg)
2834 {
2835         disable_timer_pin_1 = -1;
2836         return 0;
2837 }
2838 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2839
2840 static int __init parse_noapic(char *arg)
2841 {
2842         /* disable IO-APIC */
2843         disable_ioapic_setup();
2844         return 0;
2845 }
2846 early_param("noapic", parse_noapic);