arch/x86/kernel/io_apic_32.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/mc146818rtc.h>
  29 #include <linux/compiler.h>
  30 #include <linux/acpi.h>
  31 #include <linux/module.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/pci.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39
  40 #include <asm/io.h>
  41 #include <asm/smp.h>
  42 #include <asm/desc.h>
  43 #include <asm/timer.h>
  44 #include <asm/i8259.h>
  45 #include <asm/nmi.h>
  46 #include <asm/msidef.h>
  47 #include <asm/hypertransport.h>
  48
  49 #include <mach_apic.h>
  50 #include <mach_apicdef.h>
  51
  52 int (*ioapic_renumber_irq)(int ioapic, int irq);
  53 atomic_t irq_mis_count;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 int timer_over_8254 __initdata = 1;
  62
  63 /*
  64  *      Is the SiS APIC rmw bug present ?
  65  *      -1 = don't know, 0 = no, 1 = yes
  66  */
  67 int sis_apic_bug = -1;
  68
  69 /*
  70  * # of IRQ routing registers
  71  */
  72 int nr_ioapic_registers[MAX_IO_APICS];
  73
  74 /* I/O APIC entries */
  75 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
  76 int nr_ioapics;
  77
  78 /* MP IRQ source entries */
  79 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
  80
  81 /* # of MP IRQ source entries */
  82 int mp_irq_entries;
  83
  84 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  85 int mp_bus_id_to_type[MAX_MP_BUSSES];
  86 #endif
  87
  88 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  89
  90 static int disable_timer_pin_1 __initdata;
  91
  92 /*
  93  * Rough estimation of how many shared IRQs there are, can
  94  * be changed anytime.
  95  */
  96 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  97 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  98
  99 /*
 100  * This is performance-critical, we want to do it O(1)
 101  *
 102  * the indexing order of this array favors 1:1 mappings
 103  * between pins and IRQs.
 104  */
 105
 106 static struct irq_pin_list {
 107         int apic, pin, next;
 108 } irq_2_pin[PIN_MAP_SIZE];
 109
 110 struct io_apic {
 111         unsigned int index;
 112         unsigned int unused[3];
 113         unsigned int data;
 114 };
 115
 116 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 117 {
 118         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 119                 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
 120 }
 121
 122 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 123 {
 124         struct io_apic __iomem *io_apic = io_apic_base(apic);
 125         writel(reg, &io_apic->index);
 126         return readl(&io_apic->data);
 127 }
 128
 129 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 130 {
 131         struct io_apic __iomem *io_apic = io_apic_base(apic);
 132         writel(reg, &io_apic->index);
 133         writel(value, &io_apic->data);
 134 }
 135
 136 /*
 137  * Re-write a value: to be used for read-modify-write
 138  * cycles where the read already set up the index register.
 139  *
 140  * Older SiS APIC requires we rewrite the index register
 141  */
 142 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 143 {
 144         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
 145         if (sis_apic_bug)
 146                 writel(reg, &io_apic->index);
 147         writel(value, &io_apic->data);
 148 }
 149
 150 union entry_union {
 151         struct { u32 w1, w2; };
 152         struct IO_APIC_route_entry entry;
 153 };
 154
 155 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 156 {
 157         union entry_union eu;
 158         unsigned long flags;
 159         spin_lock_irqsave(&ioapic_lock, flags);
 160         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 161         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 162         spin_unlock_irqrestore(&ioapic_lock, flags);
 163         return eu.entry;
 164 }
 165
 166 /*
 167  * When we write a new IO APIC routing entry, we need to write the high
 168  * word first! If the mask bit in the low word is clear, we will enable
 169  * the interrupt, and we need to make sure the entry is fully populated
 170  * before that happens.
 171  */
 172 static void
 173 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 174 {
 175         union entry_union eu;
 176         eu.entry = e;
 177         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 178         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 179 }
 180
 181 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 182 {
 183         unsigned long flags;
 184         spin_lock_irqsave(&ioapic_lock, flags);
 185         __ioapic_write_entry(apic, pin, e);
 186         spin_unlock_irqrestore(&ioapic_lock, flags);
 187 }
 188
 189 /*
 190  * When we mask an IO APIC routing entry, we need to write the low
 191  * word first, in order to set the mask bit before we change the
 192  * high bits!
 193  */
 194 static void ioapic_mask_entry(int apic, int pin)
 195 {
 196         unsigned long flags;
 197         union entry_union eu = { .entry.mask = 1 };
 198
 199         spin_lock_irqsave(&ioapic_lock, flags);
 200         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 201         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 202         spin_unlock_irqrestore(&ioapic_lock, flags);
 203 }
 204
 205 /*
 206  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 207  * shared ISA-space IRQs, so we have to support them. We are super
 208  * fast in the common case, and fast for shared ISA-space IRQs.
 209  */
 210 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 211 {
 212         static int first_free_entry = NR_IRQS;
 213         struct irq_pin_list *entry = irq_2_pin + irq;
 214
 215         while (entry->next)
 216                 entry = irq_2_pin + entry->next;
 217
 218         if (entry->pin != -1) {
 219                 entry->next = first_free_entry;
 220                 entry = irq_2_pin + entry->next;
 221                 if (++first_free_entry >= PIN_MAP_SIZE)
 222                         panic("io_apic.c: whoops");
 223         }
 224         entry->apic = apic;
 225         entry->pin = pin;
 226 }
 227
 228 /*
 229  * Reroute an IRQ to a different pin.
 230  */
 231 static void __init replace_pin_at_irq(unsigned int irq,
 232                                       int oldapic, int oldpin,
 233                                       int newapic, int newpin)
 234 {
 235         struct irq_pin_list *entry = irq_2_pin + irq;
 236
 237         while (1) {
 238                 if (entry->apic == oldapic && entry->pin == oldpin) {
 239                         entry->apic = newapic;
 240                         entry->pin = newpin;
 241                 }
 242                 if (!entry->next)
 243                         break;
 244                 entry = irq_2_pin + entry->next;
 245         }
 246 }
 247
 248 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 249 {
 250         struct irq_pin_list *entry = irq_2_pin + irq;
 251         unsigned int pin, reg;
 252
 253         for (;;) {
 254                 pin = entry->pin;
 255                 if (pin == -1)
 256                         break;
 257                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 258                 reg &= ~disable;
 259                 reg |= enable;
 260                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 261                 if (!entry->next)
 262                         break;
 263                 entry = irq_2_pin + entry->next;
 264         }
 265 }
 266
 267 /* mask = 1 */
 268 static void __mask_IO_APIC_irq (unsigned int irq)
 269 {
 270         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 271 }
 272
 273 /* mask = 0 */
 274 static void __unmask_IO_APIC_irq (unsigned int irq)
 275 {
 276         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 277 }
 278
 279 /* mask = 1, trigger = 0 */
 280 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 281 {
 282         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 283 }
 284
 285 /* mask = 0, trigger = 1 */
 286 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 287 {
 288         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 289 }
 290
 291 static void mask_IO_APIC_irq (unsigned int irq)
 292 {
 293         unsigned long flags;
 294
 295         spin_lock_irqsave(&ioapic_lock, flags);
 296         __mask_IO_APIC_irq(irq);
 297         spin_unlock_irqrestore(&ioapic_lock, flags);
 298 }
 299
 300 static void unmask_IO_APIC_irq (unsigned int irq)
 301 {
 302         unsigned long flags;
 303
 304         spin_lock_irqsave(&ioapic_lock, flags);
 305         __unmask_IO_APIC_irq(irq);
 306         spin_unlock_irqrestore(&ioapic_lock, flags);
 307 }
 308
 309 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 310 {
 311         struct IO_APIC_route_entry entry;
 312
 313         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 314         entry = ioapic_read_entry(apic, pin);
 315         if (entry.delivery_mode == dest_SMI)
 316                 return;
 317
 318         /*
 319          * Disable it in the IO-APIC irq-routing table:
 320          */
 321         ioapic_mask_entry(apic, pin);
 322 }
 323
 324 static void clear_IO_APIC (void)
 325 {
 326         int apic, pin;
 327
 328         for (apic = 0; apic < nr_ioapics; apic++)
 329                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 330                         clear_IO_APIC_pin(apic, pin);
 331 }
 332
 333 #ifdef CONFIG_SMP
 334 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 335 {
 336         unsigned long flags;
 337         int pin;
 338         struct irq_pin_list *entry = irq_2_pin + irq;
 339         unsigned int apicid_value;
 340         cpumask_t tmp;
 341
 342         cpus_and(tmp, cpumask, cpu_online_map);
 343         if (cpus_empty(tmp))
 344                 tmp = TARGET_CPUS;
 345
 346         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 347
 348         apicid_value = cpu_mask_to_apicid(cpumask);
 349         /* Prepare to do the io_apic_write */
 350         apicid_value = apicid_value << 24;
 351         spin_lock_irqsave(&ioapic_lock, flags);
 352         for (;;) {
 353                 pin = entry->pin;
 354                 if (pin == -1)
 355                         break;
 356                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 357                 if (!entry->next)
 358                         break;
 359                 entry = irq_2_pin + entry->next;
 360         }
 361         irq_desc[irq].affinity = cpumask;
 362         spin_unlock_irqrestore(&ioapic_lock, flags);
 363 }
 364
 365 #if defined(CONFIG_IRQBALANCE)
 366 # include <asm/processor.h>     /* kernel_thread() */
 367 # include <linux/kernel_stat.h> /* kstat */
 368 # include <linux/slab.h>                /* kmalloc() */
 369 # include <linux/timer.h>
 370
 371 #define IRQBALANCE_CHECK_ARCH -999
 372 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 373 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 374 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 375 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 376
 377 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 378 static int physical_balance __read_mostly;
 379 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 380
 381 static struct irq_cpu_info {
 382         unsigned long * last_irq;
 383         unsigned long * irq_delta;
 384         unsigned long irq;
 385 } irq_cpu_data[NR_CPUS];
 386
 387 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 388 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 389 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 390
 391 #define IDLE_ENOUGH(cpu,now) \
 392         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 393
 394 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 395
 396 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
 397
 398 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 399         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 400 };
 401
 402 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 403 {
 404         balance_irq_affinity[irq] = mask;
 405 }
 406
 407 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 408                         unsigned long now, int direction)
 409 {
 410         int search_idle = 1;
 411         int cpu = curr_cpu;
 412
 413         goto inside;
 414
 415         do {
 416                 if (unlikely(cpu == curr_cpu))
 417                         search_idle = 0;
 418 inside:
 419                 if (direction == 1) {
 420                         cpu++;
 421                         if (cpu >= NR_CPUS)
 422                                 cpu = 0;
 423                 } else {
 424                         cpu--;
 425                         if (cpu == -1)
 426                                 cpu = NR_CPUS-1;
 427                 }
 428         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 429                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 430
 431         return cpu;
 432 }
 433
 434 static inline void balance_irq(int cpu, int irq)
 435 {
 436         unsigned long now = jiffies;
 437         cpumask_t allowed_mask;
 438         unsigned int new_cpu;
 439
 440         if (irqbalance_disabled)
 441                 return;
 442
 443         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 444         new_cpu = move(cpu, allowed_mask, now, 1);
 445         if (cpu != new_cpu) {
 446                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 447         }
 448 }
 449
 450 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 451 {
 452         int i, j;
 453
 454         for_each_online_cpu(i) {
 455                 for (j = 0; j < NR_IRQS; j++) {
 456                         if (!irq_desc[j].action)
 457                                 continue;
 458                         /* Is it a significant load ?  */
 459                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 460                                                 useful_load_threshold)
 461                                 continue;
 462                         balance_irq(i, j);
 463                 }
 464         }
 465         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 466                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 467         return;
 468 }
 469
 470 static void do_irq_balance(void)
 471 {
 472         int i, j;
 473         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 474         unsigned long move_this_load = 0;
 475         int max_loaded = 0, min_loaded = 0;
 476         int load;
 477         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 478         int selected_irq;
 479         int tmp_loaded, first_attempt = 1;
 480         unsigned long tmp_cpu_irq;
 481         unsigned long imbalance = 0;
 482         cpumask_t allowed_mask, target_cpu_mask, tmp;
 483
 484         for_each_possible_cpu(i) {
 485                 int package_index;
 486                 CPU_IRQ(i) = 0;
 487                 if (!cpu_online(i))
 488                         continue;
 489                 package_index = CPU_TO_PACKAGEINDEX(i);
 490                 for (j = 0; j < NR_IRQS; j++) {
 491                         unsigned long value_now, delta;
 492                         /* Is this an active IRQ or balancing disabled ? */
 493                         if (!irq_desc[j].action || irq_balancing_disabled(j))
 494                                 continue;
 495                         if ( package_index == i )
 496                                 IRQ_DELTA(package_index,j) = 0;
 497                         /* Determine the total count per processor per IRQ */
 498                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 499
 500                         /* Determine the activity per processor per IRQ */
 501                         delta = value_now - LAST_CPU_IRQ(i,j);
 502
 503                         /* Update last_cpu_irq[][] for the next time */
 504                         LAST_CPU_IRQ(i,j) = value_now;
 505
 506                         /* Ignore IRQs whose rate is less than the clock */
 507                         if (delta < useful_load_threshold)
 508                                 continue;
 509                         /* update the load for the processor or package total */
 510                         IRQ_DELTA(package_index,j) += delta;
 511
 512                         /* Keep track of the higher numbered sibling as well */
 513                         if (i != package_index)
 514                                 CPU_IRQ(i) += delta;
 515                         /*
 516                          * We have sibling A and sibling B in the package
 517                          *
 518                          * cpu_irq[A] = load for cpu A + load for cpu B
 519                          * cpu_irq[B] = load for cpu B
 520                          */
 521                         CPU_IRQ(package_index) += delta;
 522                 }
 523         }
 524         /* Find the least loaded processor package */
 525         for_each_online_cpu(i) {
 526                 if (i != CPU_TO_PACKAGEINDEX(i))
 527                         continue;
 528                 if (min_cpu_irq > CPU_IRQ(i)) {
 529                         min_cpu_irq = CPU_IRQ(i);
 530                         min_loaded = i;
 531                 }
 532         }
 533         max_cpu_irq = ULONG_MAX;
 534
 535 tryanothercpu:
 536         /* Look for heaviest loaded processor.
 537          * We may come back to get the next heaviest loaded processor.
 538          * Skip processors with trivial loads.
 539          */
 540         tmp_cpu_irq = 0;
 541         tmp_loaded = -1;
 542         for_each_online_cpu(i) {
 543                 if (i != CPU_TO_PACKAGEINDEX(i))
 544                         continue;
 545                 if (max_cpu_irq <= CPU_IRQ(i))
 546                         continue;
 547                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 548                         tmp_cpu_irq = CPU_IRQ(i);
 549                         tmp_loaded = i;
 550                 }
 551         }
 552
 553         if (tmp_loaded == -1) {
 554          /* In the case of small number of heavy interrupt sources,
 555           * loading some of the cpus too much. We use Ingo's original
 556           * approach to rotate them around.
 557           */
 558                 if (!first_attempt && imbalance >= useful_load_threshold) {
 559                         rotate_irqs_among_cpus(useful_load_threshold);
 560                         return;
 561                 }
 562                 goto not_worth_the_effort;
 563         }
 564
 565         first_attempt = 0;              /* heaviest search */
 566         max_cpu_irq = tmp_cpu_irq;      /* load */
 567         max_loaded = tmp_loaded;        /* processor */
 568         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 569
 570         /* if imbalance is less than approx 10% of max load, then
 571          * observe diminishing returns action. - quit
 572          */
 573         if (imbalance < (max_cpu_irq >> 3))
 574                 goto not_worth_the_effort;
 575
 576 tryanotherirq:
 577         /* if we select an IRQ to move that can't go where we want, then
 578          * see if there is another one to try.
 579          */
 580         move_this_load = 0;
 581         selected_irq = -1;
 582         for (j = 0; j < NR_IRQS; j++) {
 583                 /* Is this an active IRQ? */
 584                 if (!irq_desc[j].action)
 585                         continue;
 586                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 587                         continue;
 588                 /* Try to find the IRQ that is closest to the imbalance
 589                  * without going over.
 590                  */
 591                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 592                         move_this_load = IRQ_DELTA(max_loaded,j);
 593                         selected_irq = j;
 594                 }
 595         }
 596         if (selected_irq == -1) {
 597                 goto tryanothercpu;
 598         }
 599
 600         imbalance = move_this_load;
 601
 602         /* For physical_balance case, we accumulated both load
 603          * values in the one of the siblings cpu_irq[],
 604          * to use the same code for physical and logical processors
 605          * as much as possible.
 606          *
 607          * NOTE: the cpu_irq[] array holds the sum of the load for
 608          * sibling A and sibling B in the slot for the lowest numbered
 609          * sibling (A), _AND_ the load for sibling B in the slot for
 610          * the higher numbered sibling.
 611          *
 612          * We seek the least loaded sibling by making the comparison
 613          * (A+B)/2 vs B
 614          */
 615         load = CPU_IRQ(min_loaded) >> 1;
 616         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
 617                 if (load > CPU_IRQ(j)) {
 618                         /* This won't change cpu_sibling_map[min_loaded] */
 619                         load = CPU_IRQ(j);
 620                         min_loaded = j;
 621                 }
 622         }
 623
 624         cpus_and(allowed_mask,
 625                 cpu_online_map,
 626                 balance_irq_affinity[selected_irq]);
 627         target_cpu_mask = cpumask_of_cpu(min_loaded);
 628         cpus_and(tmp, target_cpu_mask, allowed_mask);
 629
 630         if (!cpus_empty(tmp)) {
 631                 /* mark for change destination */
 632                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 633
 634                 /* Since we made a change, come back sooner to
 635                  * check for more variation.
 636                  */
 637                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 638                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 639                 return;
 640         }
 641         goto tryanotherirq;
 642
 643 not_worth_the_effort:
 644         /*
 645          * if we did not find an IRQ to move, then adjust the time interval
 646          * upward
 647          */
 648         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 649                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 650         return;
 651 }
 652
 653 static int balanced_irq(void *unused)
 654 {
 655         int i;
 656         unsigned long prev_balance_time = jiffies;
 657         long time_remaining = balanced_irq_interval;
 658
 659         /* push everything to CPU 0 to give us a starting point.  */
 660         for (i = 0 ; i < NR_IRQS ; i++) {
 661                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 662                 set_pending_irq(i, cpumask_of_cpu(0));
 663         }
 664
 665         set_freezable();
 666         for ( ; ; ) {
 667                 time_remaining = schedule_timeout_interruptible(time_remaining);
 668                 try_to_freeze();
 669                 if (time_after(jiffies,
 670                                 prev_balance_time+balanced_irq_interval)) {
 671                         preempt_disable();
 672                         do_irq_balance();
 673                         prev_balance_time = jiffies;
 674                         time_remaining = balanced_irq_interval;
 675                         preempt_enable();
 676                 }
 677         }
 678         return 0;
 679 }
 680
 681 static int __init balanced_irq_init(void)
 682 {
 683         int i;
 684         struct cpuinfo_x86 *c;
 685         cpumask_t tmp;
 686
 687         cpus_shift_right(tmp, cpu_online_map, 2);
 688         c = &boot_cpu_data;
 689         /* When not overwritten by the command line ask subarchitecture. */
 690         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 691                 irqbalance_disabled = NO_BALANCE_IRQ;
 692         if (irqbalance_disabled)
 693                 return 0;
 694
 695          /* disable irqbalance completely if there is only one processor online */
 696         if (num_online_cpus() < 2) {
 697                 irqbalance_disabled = 1;
 698                 return 0;
 699         }
 700         /*
 701          * Enable physical balance only if more than 1 physical processor
 702          * is present
 703          */
 704         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 705                 physical_balance = 1;
 706
 707         for_each_online_cpu(i) {
 708                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 709                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 710                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 711                         printk(KERN_ERR "balanced_irq_init: out of memory");
 712                         goto failed;
 713                 }
 714                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 715                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 716         }
 717
 718         printk(KERN_INFO "Starting balanced_irq\n");
 719         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
 720                 return 0;
 721         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 722 failed:
 723         for_each_possible_cpu(i) {
 724                 kfree(irq_cpu_data[i].irq_delta);
 725                 irq_cpu_data[i].irq_delta = NULL;
 726                 kfree(irq_cpu_data[i].last_irq);
 727                 irq_cpu_data[i].last_irq = NULL;
 728         }
 729         return 0;
 730 }
 731
 732 int __devinit irqbalance_disable(char *str)
 733 {
 734         irqbalance_disabled = 1;
 735         return 1;
 736 }
 737
 738 __setup("noirqbalance", irqbalance_disable);
 739
 740 late_initcall(balanced_irq_init);
 741 #endif /* CONFIG_IRQBALANCE */
 742 #endif /* CONFIG_SMP */
 743
 744 #ifndef CONFIG_SMP
 745 void send_IPI_self(int vector)
 746 {
 747         unsigned int cfg;
 748
 749         /*
 750          * Wait for idle.
 751          */
 752         apic_wait_icr_idle();
 753         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 754         /*
 755          * Send the IPI. The write to APIC_ICR fires this off.
 756          */
 757         apic_write_around(APIC_ICR, cfg);
 758 }
 759 #endif /* !CONFIG_SMP */
 760
 761
 762 /*
 763  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 764  * specific CPU-side IRQs.
 765  */
 766
 767 #define MAX_PIRQS 8
 768 static int pirq_entries [MAX_PIRQS];
 769 static int pirqs_enabled;
 770 int skip_ioapic_setup;
 771
 772 static int __init ioapic_pirq_setup(char *str)
 773 {
 774         int i, max;
 775         int ints[MAX_PIRQS+1];
 776
 777         get_options(str, ARRAY_SIZE(ints), ints);
 778
 779         for (i = 0; i < MAX_PIRQS; i++)
 780                 pirq_entries[i] = -1;
 781
 782         pirqs_enabled = 1;
 783         apic_printk(APIC_VERBOSE, KERN_INFO
 784                         "PIRQ redirection, working around broken MP-BIOS.\n");
 785         max = MAX_PIRQS;
 786         if (ints[0] < MAX_PIRQS)
 787                 max = ints[0];
 788
 789         for (i = 0; i < max; i++) {
 790                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 791                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 792                 /*
 793                  * PIRQs are mapped upside down, usually.
 794                  */
 795                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 796         }
 797         return 1;
 798 }
 799
 800 __setup("pirq=", ioapic_pirq_setup);
 801
 802 /*
 803  * Find the IRQ entry number of a certain pin.
 804  */
 805 static int find_irq_entry(int apic, int pin, int type)
 806 {
 807         int i;
 808
 809         for (i = 0; i < mp_irq_entries; i++)
 810                 if (mp_irqs[i].mp_irqtype == type &&
 811                     (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
 812                      mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
 813                     mp_irqs[i].mp_dstirq == pin)
 814                         return i;
 815
 816         return -1;
 817 }
 818
 819 /*
 820  * Find the pin to which IRQ[irq] (ISA) is connected
 821  */
 822 static int __init find_isa_irq_pin(int irq, int type)
 823 {
 824         int i;
 825
 826         for (i = 0; i < mp_irq_entries; i++) {
 827                 int lbus = mp_irqs[i].mp_srcbus;
 828
 829                 if (test_bit(lbus, mp_bus_not_pci) &&
 830                     (mp_irqs[i].mp_irqtype == type) &&
 831                     (mp_irqs[i].mp_srcbusirq == irq))
 832
 833                         return mp_irqs[i].mp_dstirq;
 834         }
 835         return -1;
 836 }
 837
 838 static int __init find_isa_irq_apic(int irq, int type)
 839 {
 840         int i;
 841
 842         for (i = 0; i < mp_irq_entries; i++) {
 843                 int lbus = mp_irqs[i].mp_srcbus;
 844
 845                 if (test_bit(lbus, mp_bus_not_pci) &&
 846                     (mp_irqs[i].mp_irqtype == type) &&
 847                     (mp_irqs[i].mp_srcbusirq == irq))
 848                         break;
 849         }
 850         if (i < mp_irq_entries) {
 851                 int apic;
 852                 for(apic = 0; apic < nr_ioapics; apic++) {
 853                         if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
 854                                 return apic;
 855                 }
 856         }
 857
 858         return -1;
 859 }
 860
 861 /*
 862  * Find a specific PCI IRQ entry.
 863  * Not an __init, possibly needed by modules
 864  */
 865 static int pin_2_irq(int idx, int apic, int pin);
 866
 867 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 868 {
 869         int apic, i, best_guess = -1;
 870
 871         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 872                 "slot:%d, pin:%d.\n", bus, slot, pin);
 873         if (test_bit(bus, mp_bus_not_pci)) {
 874                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 875                 return -1;
 876         }
 877         for (i = 0; i < mp_irq_entries; i++) {
 878                 int lbus = mp_irqs[i].mp_srcbus;
 879
 880                 for (apic = 0; apic < nr_ioapics; apic++)
 881                         if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
 882                             mp_irqs[i].mp_dstapic == MP_APIC_ALL)
 883                                 break;
 884
 885                 if (!test_bit(lbus, mp_bus_not_pci) &&
 886                     !mp_irqs[i].mp_irqtype &&
 887                     (bus == lbus) &&
 888                     (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
 889                         int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
 890
 891                         if (!(apic || IO_APIC_IRQ(irq)))
 892                                 continue;
 893
 894                         if (pin == (mp_irqs[i].mp_srcbusirq & 3))
 895                                 return irq;
 896                         /*
 897                          * Use the first all-but-pin matching entry as a
 898                          * best-guess fuzzy result for broken mptables.
 899                          */
 900                         if (best_guess < 0)
 901                                 best_guess = irq;
 902                 }
 903         }
 904         return best_guess;
 905 }
 906 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 907
 908 /*
 909  * This function currently is only a helper for the i386 smp boot process where
 910  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 911  * so mask in all cases should simply be TARGET_CPUS
 912  */
 913 #ifdef CONFIG_SMP
 914 void __init setup_ioapic_dest(void)
 915 {
 916         int pin, ioapic, irq, irq_entry;
 917
 918         if (skip_ioapic_setup == 1)
 919                 return;
 920
 921         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 922                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 923                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 924                         if (irq_entry == -1)
 925                                 continue;
 926                         irq = pin_2_irq(irq_entry, ioapic, pin);
 927                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 928                 }
 929
 930         }
 931 }
 932 #endif
 933
 934 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
 935 /*
 936  * EISA Edge/Level control register, ELCR
 937  */
 938 static int EISA_ELCR(unsigned int irq)
 939 {
 940         if (irq < 16) {
 941                 unsigned int port = 0x4d0 + (irq >> 3);
 942                 return (inb(port) >> (irq & 7)) & 1;
 943         }
 944         apic_printk(APIC_VERBOSE, KERN_INFO
 945                         "Broken MPtable reports ISA irq %d\n", irq);
 946         return 0;
 947 }
 948 #endif
 949
 950 /* ISA interrupts are always polarity zero edge triggered,
 951  * when listed as conforming in the MP table. */
 952
 953 #define default_ISA_trigger(idx)        (0)
 954 #define default_ISA_polarity(idx)       (0)
 955
 956 /* EISA interrupts are always polarity zero and can be edge or level
 957  * trigger depending on the ELCR value.  If an interrupt is listed as
 958  * EISA conforming in the MP table, that means its trigger type must
 959  * be read in from the ELCR */
 960
 961 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
 962 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
 963
 964 /* PCI interrupts are always polarity one level triggered,
 965  * when listed as conforming in the MP table. */
 966
 967 #define default_PCI_trigger(idx)        (1)
 968 #define default_PCI_polarity(idx)       (1)
 969
 970 /* MCA interrupts are always polarity zero level triggered,
 971  * when listed as conforming in the MP table. */
 972
 973 #define default_MCA_trigger(idx)        (1)
 974 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
 975
 976 static int MPBIOS_polarity(int idx)
 977 {
 978         int bus = mp_irqs[idx].mp_srcbus;
 979         int polarity;
 980
 981         /*
 982          * Determine IRQ line polarity (high active or low active):
 983          */
 984         switch (mp_irqs[idx].mp_irqflag & 3)
 985         {
 986                 case 0: /* conforms, ie. bus-type dependent polarity */
 987                 {
 988                         polarity = test_bit(bus, mp_bus_not_pci)?
 989                                 default_ISA_polarity(idx):
 990                                 default_PCI_polarity(idx);
 991                         break;
 992                 }
 993                 case 1: /* high active */
 994                 {
 995                         polarity = 0;
 996                         break;
 997                 }
 998                 case 2: /* reserved */
 999                 {
1000                         printk(KERN_WARNING "broken BIOS!!\n");
1001                         polarity = 1;
1002                         break;
1003                 }
1004                 case 3: /* low active */
1005                 {
1006                         polarity = 1;
1007                         break;
1008                 }
1009                 default: /* invalid */
1010                 {
1011                         printk(KERN_WARNING "broken BIOS!!\n");
1012                         polarity = 1;
1013                         break;
1014                 }
1015         }
1016         return polarity;
1017 }
1018
1019 static int MPBIOS_trigger(int idx)
1020 {
1021         int bus = mp_irqs[idx].mp_srcbus;
1022         int trigger;
1023
1024         /*
1025          * Determine IRQ trigger mode (edge or level sensitive):
1026          */
1027         switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1028         {
1029                 case 0: /* conforms, ie. bus-type dependent */
1030                 {
1031                         trigger = test_bit(bus, mp_bus_not_pci)?
1032                                         default_ISA_trigger(idx):
1033                                         default_PCI_trigger(idx);
1034 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1035                         switch (mp_bus_id_to_type[bus])
1036                         {
1037                                 case MP_BUS_ISA: /* ISA pin */
1038                                 {
1039                                         /* set before the switch */
1040                                         break;
1041                                 }
1042                                 case MP_BUS_EISA: /* EISA pin */
1043                                 {
1044                                         trigger = default_EISA_trigger(idx);
1045                                         break;
1046                                 }
1047                                 case MP_BUS_PCI: /* PCI pin */
1048                                 {
1049                                         /* set before the switch */
1050                                         break;
1051                                 }
1052                                 case MP_BUS_MCA: /* MCA pin */
1053                                 {
1054                                         trigger = default_MCA_trigger(idx);
1055                                         break;
1056                                 }
1057                                 default:
1058                                 {
1059                                         printk(KERN_WARNING "broken BIOS!!\n");
1060                                         trigger = 1;
1061                                         break;
1062                                 }
1063                         }
1064 #endif
1065                         break;
1066                 }
1067                 case 1: /* edge */
1068                 {
1069                         trigger = 0;
1070                         break;
1071                 }
1072                 case 2: /* reserved */
1073                 {
1074                         printk(KERN_WARNING "broken BIOS!!\n");
1075                         trigger = 1;
1076                         break;
1077                 }
1078                 case 3: /* level */
1079                 {
1080                         trigger = 1;
1081                         break;
1082                 }
1083                 default: /* invalid */
1084                 {
1085                         printk(KERN_WARNING "broken BIOS!!\n");
1086                         trigger = 0;
1087                         break;
1088                 }
1089         }
1090         return trigger;
1091 }
1092
1093 static inline int irq_polarity(int idx)
1094 {
1095         return MPBIOS_polarity(idx);
1096 }
1097
1098 static inline int irq_trigger(int idx)
1099 {
1100         return MPBIOS_trigger(idx);
1101 }
1102
1103 static int pin_2_irq(int idx, int apic, int pin)
1104 {
1105         int irq, i;
1106         int bus = mp_irqs[idx].mp_srcbus;
1107
1108         /*
1109          * Debugging check, we are in big trouble if this message pops up!
1110          */
1111         if (mp_irqs[idx].mp_dstirq != pin)
1112                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1113
1114         if (test_bit(bus, mp_bus_not_pci))
1115                 irq = mp_irqs[idx].mp_srcbusirq;
1116         else {
1117                 /*
1118                  * PCI IRQs are mapped in order
1119                  */
1120                 i = irq = 0;
1121                 while (i < apic)
1122                         irq += nr_ioapic_registers[i++];
1123                 irq += pin;
1124
1125                 /*
1126                  * For MPS mode, so far only needed by ES7000 platform
1127                  */
1128                 if (ioapic_renumber_irq)
1129                         irq = ioapic_renumber_irq(apic, irq);
1130         }
1131
1132         /*
1133          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1134          */
1135         if ((pin >= 16) && (pin <= 23)) {
1136                 if (pirq_entries[pin-16] != -1) {
1137                         if (!pirq_entries[pin-16]) {
1138                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1139                                                 "disabling PIRQ%d\n", pin-16);
1140                         } else {
1141                                 irq = pirq_entries[pin-16];
1142                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1143                                                 "using PIRQ%d -> IRQ %d\n",
1144                                                 pin-16, irq);
1145                         }
1146                 }
1147         }
1148         return irq;
1149 }
1150
1151 static inline int IO_APIC_irq_trigger(int irq)
1152 {
1153         int apic, idx, pin;
1154
1155         for (apic = 0; apic < nr_ioapics; apic++) {
1156                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1157                         idx = find_irq_entry(apic,pin,mp_INT);
1158                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1159                                 return irq_trigger(idx);
1160                 }
1161         }
1162         /*
1163          * nonexistent IRQs are edge default
1164          */
1165         return 0;
1166 }
1167
1168 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1169 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1170
1171 static int __assign_irq_vector(int irq)
1172 {
1173         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1174         int vector, offset;
1175
1176         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1177
1178         if (irq_vector[irq] > 0)
1179                 return irq_vector[irq];
1180
1181         vector = current_vector;
1182         offset = current_offset;
1183 next:
1184         vector += 8;
1185         if (vector >= FIRST_SYSTEM_VECTOR) {
1186                 offset = (offset + 1) % 8;
1187                 vector = FIRST_DEVICE_VECTOR + offset;
1188         }
1189         if (vector == current_vector)
1190                 return -ENOSPC;
1191         if (test_and_set_bit(vector, used_vectors))
1192                 goto next;
1193
1194         current_vector = vector;
1195         current_offset = offset;
1196         irq_vector[irq] = vector;
1197
1198         return vector;
1199 }
1200
1201 static int assign_irq_vector(int irq)
1202 {
1203         unsigned long flags;
1204         int vector;
1205
1206         spin_lock_irqsave(&vector_lock, flags);
1207         vector = __assign_irq_vector(irq);
1208         spin_unlock_irqrestore(&vector_lock, flags);
1209
1210         return vector;
1211 }
1212 static struct irq_chip ioapic_chip;
1213
1214 #define IOAPIC_AUTO     -1
1215 #define IOAPIC_EDGE     0
1216 #define IOAPIC_LEVEL    1
1217
1218 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1219 {
1220         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1221             trigger == IOAPIC_LEVEL) {
1222                 irq_desc[irq].status |= IRQ_LEVEL;
1223                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1224                                          handle_fasteoi_irq, "fasteoi");
1225         } else {
1226                 irq_desc[irq].status &= ~IRQ_LEVEL;
1227                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1228                                          handle_edge_irq, "edge");
1229         }
1230         set_intr_gate(vector, interrupt[irq]);
1231 }
1232
1233 static void __init setup_IO_APIC_irqs(void)
1234 {
1235         struct IO_APIC_route_entry entry;
1236         int apic, pin, idx, irq, first_notcon = 1, vector;
1237
1238         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1239
1240         for (apic = 0; apic < nr_ioapics; apic++) {
1241         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1242
1243                 /*
1244                  * add it to the IO-APIC irq-routing table:
1245                  */
1246                 memset(&entry,0,sizeof(entry));
1247
1248                 entry.delivery_mode = INT_DELIVERY_MODE;
1249                 entry.dest_mode = INT_DEST_MODE;
1250                 entry.mask = 0;                         /* enable IRQ */
1251                 entry.dest.logical.logical_dest =
1252                                         cpu_mask_to_apicid(TARGET_CPUS);
1253
1254                 idx = find_irq_entry(apic,pin,mp_INT);
1255                 if (idx == -1) {
1256                         if (first_notcon) {
1257                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1258                                                 " IO-APIC (apicid-pin) %d-%d",
1259                                                 mp_ioapics[apic].mp_apicid,
1260                                                 pin);
1261                                 first_notcon = 0;
1262                         } else
1263                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1264                                         mp_ioapics[apic].mp_apicid, pin);
1265                         continue;
1266                 }
1267
1268                 if (!first_notcon) {
1269                         apic_printk(APIC_VERBOSE, " not connected.\n");
1270                         first_notcon = 1;
1271                 }
1272
1273                 entry.trigger = irq_trigger(idx);
1274                 entry.polarity = irq_polarity(idx);
1275
1276                 if (irq_trigger(idx)) {
1277                         entry.trigger = 1;
1278                         entry.mask = 1;
1279                 }
1280
1281                 irq = pin_2_irq(idx, apic, pin);
1282                 /*
1283                  * skip adding the timer int on secondary nodes, which causes
1284                  * a small but painful rift in the time-space continuum
1285                  */
1286                 if (multi_timer_check(apic, irq))
1287                         continue;
1288                 else
1289                         add_pin_to_irq(irq, apic, pin);
1290
1291                 if (!apic && !IO_APIC_IRQ(irq))
1292                         continue;
1293
1294                 if (IO_APIC_IRQ(irq)) {
1295                         vector = assign_irq_vector(irq);
1296                         entry.vector = vector;
1297                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1298
1299                         if (!apic && (irq < 16))
1300                                 disable_8259A_irq(irq);
1301                 }
1302                 ioapic_write_entry(apic, pin, entry);
1303         }
1304         }
1305
1306         if (!first_notcon)
1307                 apic_printk(APIC_VERBOSE, " not connected.\n");
1308 }
1309
1310 /*
1311  * Set up the 8259A-master output pin:
1312  */
1313 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1314 {
1315         struct IO_APIC_route_entry entry;
1316
1317         memset(&entry,0,sizeof(entry));
1318
1319         disable_8259A_irq(0);
1320
1321         /* mask LVT0 */
1322         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1323
1324         /*
1325          * We use logical delivery to get the timer IRQ
1326          * to the first CPU.
1327          */
1328         entry.dest_mode = INT_DEST_MODE;
1329         entry.mask = 0;                                 /* unmask IRQ now */
1330         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1331         entry.delivery_mode = INT_DELIVERY_MODE;
1332         entry.polarity = 0;
1333         entry.trigger = 0;
1334         entry.vector = vector;
1335
1336         /*
1337          * The timer IRQ doesn't have to know that behind the
1338          * scene we have a 8259A-master in AEOI mode ...
1339          */
1340         irq_desc[0].chip = &ioapic_chip;
1341         set_irq_handler(0, handle_edge_irq);
1342
1343         /*
1344          * Add it to the IO-APIC irq-routing table:
1345          */
1346         ioapic_write_entry(apic, pin, entry);
1347
1348         enable_8259A_irq(0);
1349 }
1350
1351 void __init print_IO_APIC(void)
1352 {
1353         int apic, i;
1354         union IO_APIC_reg_00 reg_00;
1355         union IO_APIC_reg_01 reg_01;
1356         union IO_APIC_reg_02 reg_02;
1357         union IO_APIC_reg_03 reg_03;
1358         unsigned long flags;
1359
1360         if (apic_verbosity == APIC_QUIET)
1361                 return;
1362
1363         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1364         for (i = 0; i < nr_ioapics; i++)
1365                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1366                        mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1367
1368         /*
1369          * We are a bit conservative about what we expect.  We have to
1370          * know about every hardware change ASAP.
1371          */
1372         printk(KERN_INFO "testing the IO APIC.......................\n");
1373
1374         for (apic = 0; apic < nr_ioapics; apic++) {
1375
1376         spin_lock_irqsave(&ioapic_lock, flags);
1377         reg_00.raw = io_apic_read(apic, 0);
1378         reg_01.raw = io_apic_read(apic, 1);
1379         if (reg_01.bits.version >= 0x10)
1380                 reg_02.raw = io_apic_read(apic, 2);
1381         if (reg_01.bits.version >= 0x20)
1382                 reg_03.raw = io_apic_read(apic, 3);
1383         spin_unlock_irqrestore(&ioapic_lock, flags);
1384
1385         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1386         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1387         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1388         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1389         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1390
1391         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1392         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1393
1394         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1395         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1396
1397         /*
1398          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1399          * but the value of reg_02 is read as the previous read register
1400          * value, so ignore it if reg_02 == reg_01.
1401          */
1402         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1403                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1404                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1405         }
1406
1407         /*
1408          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1409          * or reg_03, but the value of reg_0[23] is read as the previous read
1410          * register value, so ignore it if reg_03 == reg_0[12].
1411          */
1412         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1413             reg_03.raw != reg_01.raw) {
1414                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1415                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1416         }
1417
1418         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1419
1420         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1421                           " Stat Dest Deli Vect:   \n");
1422
1423         for (i = 0; i <= reg_01.bits.entries; i++) {
1424                 struct IO_APIC_route_entry entry;
1425
1426                 entry = ioapic_read_entry(apic, i);
1427
1428                 printk(KERN_DEBUG " %02x %03X %02X  ",
1429                         i,
1430                         entry.dest.logical.logical_dest,
1431                         entry.dest.physical.physical_dest
1432                 );
1433
1434                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1435                         entry.mask,
1436                         entry.trigger,
1437                         entry.irr,
1438                         entry.polarity,
1439                         entry.delivery_status,
1440                         entry.dest_mode,
1441                         entry.delivery_mode,
1442                         entry.vector
1443                 );
1444         }
1445         }
1446         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1447         for (i = 0; i < NR_IRQS; i++) {
1448                 struct irq_pin_list *entry = irq_2_pin + i;
1449                 if (entry->pin < 0)
1450                         continue;
1451                 printk(KERN_DEBUG "IRQ%d ", i);
1452                 for (;;) {
1453                         printk("-> %d:%d", entry->apic, entry->pin);
1454                         if (!entry->next)
1455                                 break;
1456                         entry = irq_2_pin + entry->next;
1457                 }
1458                 printk("\n");
1459         }
1460
1461         printk(KERN_INFO ".................................... done.\n");
1462
1463         return;
1464 }
1465
1466 #if 0
1467
1468 static void print_APIC_bitfield (int base)
1469 {
1470         unsigned int v;
1471         int i, j;
1472
1473         if (apic_verbosity == APIC_QUIET)
1474                 return;
1475
1476         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1477         for (i = 0; i < 8; i++) {
1478                 v = apic_read(base + i*0x10);
1479                 for (j = 0; j < 32; j++) {
1480                         if (v & (1<<j))
1481                                 printk("1");
1482                         else
1483                                 printk("0");
1484                 }
1485                 printk("\n");
1486         }
1487 }
1488
1489 void /*__init*/ print_local_APIC(void * dummy)
1490 {
1491         unsigned int v, ver, maxlvt;
1492
1493         if (apic_verbosity == APIC_QUIET)
1494                 return;
1495
1496         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1497                 smp_processor_id(), hard_smp_processor_id());
1498         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v,
1499                         GET_APIC_ID(read_apic_id()));
1500         v = apic_read(APIC_LVR);
1501         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1502         ver = GET_APIC_VERSION(v);
1503         maxlvt = lapic_get_maxlvt();
1504
1505         v = apic_read(APIC_TASKPRI);
1506         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1507
1508         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1509                 v = apic_read(APIC_ARBPRI);
1510                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1511                         v & APIC_ARBPRI_MASK);
1512                 v = apic_read(APIC_PROCPRI);
1513                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1514         }
1515
1516         v = apic_read(APIC_EOI);
1517         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1518         v = apic_read(APIC_RRR);
1519         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1520         v = apic_read(APIC_LDR);
1521         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1522         v = apic_read(APIC_DFR);
1523         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1524         v = apic_read(APIC_SPIV);
1525         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1526
1527         printk(KERN_DEBUG "... APIC ISR field:\n");
1528         print_APIC_bitfield(APIC_ISR);
1529         printk(KERN_DEBUG "... APIC TMR field:\n");
1530         print_APIC_bitfield(APIC_TMR);
1531         printk(KERN_DEBUG "... APIC IRR field:\n");
1532         print_APIC_bitfield(APIC_IRR);
1533
1534         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1535                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1536                         apic_write(APIC_ESR, 0);
1537                 v = apic_read(APIC_ESR);
1538                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1539         }
1540
1541         v = apic_read(APIC_ICR);
1542         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1543         v = apic_read(APIC_ICR2);
1544         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1545
1546         v = apic_read(APIC_LVTT);
1547         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1548
1549         if (maxlvt > 3) {                       /* PC is LVT#4. */
1550                 v = apic_read(APIC_LVTPC);
1551                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1552         }
1553         v = apic_read(APIC_LVT0);
1554         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1555         v = apic_read(APIC_LVT1);
1556         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1557
1558         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1559                 v = apic_read(APIC_LVTERR);
1560                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1561         }
1562
1563         v = apic_read(APIC_TMICT);
1564         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1565         v = apic_read(APIC_TMCCT);
1566         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1567         v = apic_read(APIC_TDCR);
1568         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1569         printk("\n");
1570 }
1571
1572 void print_all_local_APICs (void)
1573 {
1574         on_each_cpu(print_local_APIC, NULL, 1, 1);
1575 }
1576
1577 void /*__init*/ print_PIC(void)
1578 {
1579         unsigned int v;
1580         unsigned long flags;
1581
1582         if (apic_verbosity == APIC_QUIET)
1583                 return;
1584
1585         printk(KERN_DEBUG "\nprinting PIC contents\n");
1586
1587         spin_lock_irqsave(&i8259A_lock, flags);
1588
1589         v = inb(0xa1) << 8 | inb(0x21);
1590         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1591
1592         v = inb(0xa0) << 8 | inb(0x20);
1593         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1594
1595         outb(0x0b,0xa0);
1596         outb(0x0b,0x20);
1597         v = inb(0xa0) << 8 | inb(0x20);
1598         outb(0x0a,0xa0);
1599         outb(0x0a,0x20);
1600
1601         spin_unlock_irqrestore(&i8259A_lock, flags);
1602
1603         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1604
1605         v = inb(0x4d1) << 8 | inb(0x4d0);
1606         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1607 }
1608
1609 #endif  /*  0  */
1610
1611 static void __init enable_IO_APIC(void)
1612 {
1613         union IO_APIC_reg_01 reg_01;
1614         int i8259_apic, i8259_pin;
1615         int i, apic;
1616         unsigned long flags;
1617
1618         for (i = 0; i < PIN_MAP_SIZE; i++) {
1619                 irq_2_pin[i].pin = -1;
1620                 irq_2_pin[i].next = 0;
1621         }
1622         if (!pirqs_enabled)
1623                 for (i = 0; i < MAX_PIRQS; i++)
1624                         pirq_entries[i] = -1;
1625
1626         /*
1627          * The number of IO-APIC IRQ registers (== #pins):
1628          */
1629         for (apic = 0; apic < nr_ioapics; apic++) {
1630                 spin_lock_irqsave(&ioapic_lock, flags);
1631                 reg_01.raw = io_apic_read(apic, 1);
1632                 spin_unlock_irqrestore(&ioapic_lock, flags);
1633                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1634         }
1635         for(apic = 0; apic < nr_ioapics; apic++) {
1636                 int pin;
1637                 /* See if any of the pins is in ExtINT mode */
1638                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1639                         struct IO_APIC_route_entry entry;
1640                         entry = ioapic_read_entry(apic, pin);
1641
1642
1643                         /* If the interrupt line is enabled and in ExtInt mode
1644                          * I have found the pin where the i8259 is connected.
1645                          */
1646                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1647                                 ioapic_i8259.apic = apic;
1648                                 ioapic_i8259.pin  = pin;
1649                                 goto found_i8259;
1650                         }
1651                 }
1652         }
1653  found_i8259:
1654         /* Look to see what if the MP table has reported the ExtINT */
1655         /* If we could not find the appropriate pin by looking at the ioapic
1656          * the i8259 probably is not connected the ioapic but give the
1657          * mptable a chance anyway.
1658          */
1659         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1660         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1661         /* Trust the MP table if nothing is setup in the hardware */
1662         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1663                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1664                 ioapic_i8259.pin  = i8259_pin;
1665                 ioapic_i8259.apic = i8259_apic;
1666         }
1667         /* Complain if the MP table and the hardware disagree */
1668         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1669                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1670         {
1671                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1672         }
1673
1674         /*
1675          * Do not trust the IO-APIC being empty at bootup
1676          */
1677         clear_IO_APIC();
1678 }
1679
1680 /*
1681  * Not an __init, needed by the reboot code
1682  */
1683 void disable_IO_APIC(void)
1684 {
1685         /*
1686          * Clear the IO-APIC before rebooting:
1687          */
1688         clear_IO_APIC();
1689
1690         /*
1691          * If the i8259 is routed through an IOAPIC
1692          * Put that IOAPIC in virtual wire mode
1693          * so legacy interrupts can be delivered.
1694          */
1695         if (ioapic_i8259.pin != -1) {
1696                 struct IO_APIC_route_entry entry;
1697
1698                 memset(&entry, 0, sizeof(entry));
1699                 entry.mask            = 0; /* Enabled */
1700                 entry.trigger         = 0; /* Edge */
1701                 entry.irr             = 0;
1702                 entry.polarity        = 0; /* High */
1703                 entry.delivery_status = 0;
1704                 entry.dest_mode       = 0; /* Physical */
1705                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1706                 entry.vector          = 0;
1707                 entry.dest.physical.physical_dest =
1708                                         GET_APIC_ID(read_apic_id());
1709
1710                 /*
1711                  * Add it to the IO-APIC irq-routing table:
1712                  */
1713                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1714         }
1715         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1716 }
1717
1718 /*
1719  * function to set the IO-APIC physical IDs based on the
1720  * values stored in the MPC table.
1721  *
1722  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1723  */
1724
1725 #ifndef CONFIG_X86_NUMAQ
1726 static void __init setup_ioapic_ids_from_mpc(void)
1727 {
1728         union IO_APIC_reg_00 reg_00;
1729         physid_mask_t phys_id_present_map;
1730         int apic;
1731         int i;
1732         unsigned char old_id;
1733         unsigned long flags;
1734
1735         /*
1736          * Don't check I/O APIC IDs for xAPIC systems.  They have
1737          * no meaning without the serial APIC bus.
1738          */
1739         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1740                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1741                 return;
1742         /*
1743          * This is broken; anything with a real cpu count has to
1744          * circumvent this idiocy regardless.
1745          */
1746         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1747
1748         /*
1749          * Set the IOAPIC ID to the value stored in the MPC table.
1750          */
1751         for (apic = 0; apic < nr_ioapics; apic++) {
1752
1753                 /* Read the register 0 value */
1754                 spin_lock_irqsave(&ioapic_lock, flags);
1755                 reg_00.raw = io_apic_read(apic, 0);
1756                 spin_unlock_irqrestore(&ioapic_lock, flags);
1757
1758                 old_id = mp_ioapics[apic].mp_apicid;
1759
1760                 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1761                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1762                                 apic, mp_ioapics[apic].mp_apicid);
1763                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1764                                 reg_00.bits.ID);
1765                         mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1766                 }
1767
1768                 /*
1769                  * Sanity check, is the ID really free? Every APIC in a
1770                  * system must have a unique ID or we get lots of nice
1771                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1772                  */
1773                 if (check_apicid_used(phys_id_present_map,
1774                                         mp_ioapics[apic].mp_apicid)) {
1775                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1776                                 apic, mp_ioapics[apic].mp_apicid);
1777                         for (i = 0; i < get_physical_broadcast(); i++)
1778                                 if (!physid_isset(i, phys_id_present_map))
1779                                         break;
1780                         if (i >= get_physical_broadcast())
1781                                 panic("Max APIC ID exceeded!\n");
1782                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1783                                 i);
1784                         physid_set(i, phys_id_present_map);
1785                         mp_ioapics[apic].mp_apicid = i;
1786                 } else {
1787                         physid_mask_t tmp;
1788                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1789                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1790                                         "phys_id_present_map\n",
1791                                         mp_ioapics[apic].mp_apicid);
1792                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1793                 }
1794
1795
1796                 /*
1797                  * We need to adjust the IRQ routing table
1798                  * if the ID changed.
1799                  */
1800                 if (old_id != mp_ioapics[apic].mp_apicid)
1801                         for (i = 0; i < mp_irq_entries; i++)
1802                                 if (mp_irqs[i].mp_dstapic == old_id)
1803                                         mp_irqs[i].mp_dstapic
1804                                                 = mp_ioapics[apic].mp_apicid;
1805
1806                 /*
1807                  * Read the right value from the MPC table and
1808                  * write it into the ID register.
1809                  */
1810                 apic_printk(APIC_VERBOSE, KERN_INFO
1811                         "...changing IO-APIC physical APIC ID to %d ...",
1812                         mp_ioapics[apic].mp_apicid);
1813
1814                 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1815                 spin_lock_irqsave(&ioapic_lock, flags);
1816                 io_apic_write(apic, 0, reg_00.raw);
1817                 spin_unlock_irqrestore(&ioapic_lock, flags);
1818
1819                 /*
1820                  * Sanity check
1821                  */
1822                 spin_lock_irqsave(&ioapic_lock, flags);
1823                 reg_00.raw = io_apic_read(apic, 0);
1824                 spin_unlock_irqrestore(&ioapic_lock, flags);
1825                 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1826                         printk("could not set ID!\n");
1827                 else
1828                         apic_printk(APIC_VERBOSE, " ok.\n");
1829         }
1830 }
1831 #else
1832 static void __init setup_ioapic_ids_from_mpc(void) { }
1833 #endif
1834
1835 int no_timer_check __initdata;
1836
1837 static int __init notimercheck(char *s)
1838 {
1839         no_timer_check = 1;
1840         return 1;
1841 }
1842 __setup("no_timer_check", notimercheck);
1843
1844 /*
1845  * There is a nasty bug in some older SMP boards, their mptable lies
1846  * about the timer IRQ. We do the following to work around the situation:
1847  *
1848  *      - timer IRQ defaults to IO-APIC IRQ
1849  *      - if this function detects that timer IRQs are defunct, then we fall
1850  *        back to ISA timer IRQs
1851  */
1852 static int __init timer_irq_works(void)
1853 {
1854         unsigned long t1 = jiffies;
1855         unsigned long flags;
1856
1857         if (no_timer_check)
1858                 return 1;
1859
1860         local_save_flags(flags);
1861         local_irq_enable();
1862         /* Let ten ticks pass... */
1863         mdelay((10 * 1000) / HZ);
1864         local_irq_restore(flags);
1865
1866         /*
1867          * Expect a few ticks at least, to be sure some possible
1868          * glue logic does not lock up after one or two first
1869          * ticks in a non-ExtINT mode.  Also the local APIC
1870          * might have cached one ExtINT interrupt.  Finally, at
1871          * least one tick may be lost due to delays.
1872          */
1873         if (time_after(jiffies, t1 + 4))
1874                 return 1;
1875
1876         return 0;
1877 }
1878
1879 /*
1880  * In the SMP+IOAPIC case it might happen that there are an unspecified
1881  * number of pending IRQ events unhandled. These cases are very rare,
1882  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1883  * better to do it this way as thus we do not have to be aware of
1884  * 'pending' interrupts in the IRQ path, except at this point.
1885  */
1886 /*
1887  * Edge triggered needs to resend any interrupt
1888  * that was delayed but this is now handled in the device
1889  * independent code.
1890  */
1891
1892 /*
1893  * Startup quirk:
1894  *
1895  * Starting up a edge-triggered IO-APIC interrupt is
1896  * nasty - we need to make sure that we get the edge.
1897  * If it is already asserted for some reason, we need
1898  * return 1 to indicate that is was pending.
1899  *
1900  * This is not complete - we should be able to fake
1901  * an edge even if it isn't on the 8259A...
1902  *
1903  * (We do this for level-triggered IRQs too - it cannot hurt.)
1904  */
1905 static unsigned int startup_ioapic_irq(unsigned int irq)
1906 {
1907         int was_pending = 0;
1908         unsigned long flags;
1909
1910         spin_lock_irqsave(&ioapic_lock, flags);
1911         if (irq < 16) {
1912                 disable_8259A_irq(irq);
1913                 if (i8259A_irq_pending(irq))
1914                         was_pending = 1;
1915         }
1916         __unmask_IO_APIC_irq(irq);
1917         spin_unlock_irqrestore(&ioapic_lock, flags);
1918
1919         return was_pending;
1920 }
1921
1922 static void ack_ioapic_irq(unsigned int irq)
1923 {
1924         move_native_irq(irq);
1925         ack_APIC_irq();
1926 }
1927
1928 static void ack_ioapic_quirk_irq(unsigned int irq)
1929 {
1930         unsigned long v;
1931         int i;
1932
1933         move_native_irq(irq);
1934 /*
1935  * It appears there is an erratum which affects at least version 0x11
1936  * of I/O APIC (that's the 82093AA and cores integrated into various
1937  * chipsets).  Under certain conditions a level-triggered interrupt is
1938  * erroneously delivered as edge-triggered one but the respective IRR
1939  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1940  * message but it will never arrive and further interrupts are blocked
1941  * from the source.  The exact reason is so far unknown, but the
1942  * phenomenon was observed when two consecutive interrupt requests
1943  * from a given source get delivered to the same CPU and the source is
1944  * temporarily disabled in between.
1945  *
1946  * A workaround is to simulate an EOI message manually.  We achieve it
1947  * by setting the trigger mode to edge and then to level when the edge
1948  * trigger mode gets detected in the TMR of a local APIC for a
1949  * level-triggered interrupt.  We mask the source for the time of the
1950  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1951  * The idea is from Manfred Spraul.  --macro
1952  */
1953         i = irq_vector[irq];
1954
1955         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1956
1957         ack_APIC_irq();
1958
1959         if (!(v & (1 << (i & 0x1f)))) {
1960                 atomic_inc(&irq_mis_count);
1961                 spin_lock(&ioapic_lock);
1962                 __mask_and_edge_IO_APIC_irq(irq);
1963                 __unmask_and_level_IO_APIC_irq(irq);
1964                 spin_unlock(&ioapic_lock);
1965         }
1966 }
1967
1968 static int ioapic_retrigger_irq(unsigned int irq)
1969 {
1970         send_IPI_self(irq_vector[irq]);
1971
1972         return 1;
1973 }
1974
1975 static struct irq_chip ioapic_chip __read_mostly = {
1976         .name           = "IO-APIC",
1977         .startup        = startup_ioapic_irq,
1978         .mask           = mask_IO_APIC_irq,
1979         .unmask         = unmask_IO_APIC_irq,
1980         .ack            = ack_ioapic_irq,
1981         .eoi            = ack_ioapic_quirk_irq,
1982 #ifdef CONFIG_SMP
1983         .set_affinity   = set_ioapic_affinity_irq,
1984 #endif
1985         .retrigger      = ioapic_retrigger_irq,
1986 };
1987
1988
1989 static inline void init_IO_APIC_traps(void)
1990 {
1991         int irq;
1992
1993         /*
1994          * NOTE! The local APIC isn't very good at handling
1995          * multiple interrupts at the same interrupt level.
1996          * As the interrupt level is determined by taking the
1997          * vector number and shifting that right by 4, we
1998          * want to spread these out a bit so that they don't
1999          * all fall in the same interrupt level.
2000          *
2001          * Also, we've got to be careful not to trash gate
2002          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2003          */
2004         for (irq = 0; irq < NR_IRQS ; irq++) {
2005                 if (IO_APIC_IRQ(irq) && !irq_vector[irq]) {
2006                         /*
2007                          * Hmm.. We don't have an entry for this,
2008                          * so default to an old-fashioned 8259
2009                          * interrupt if we can..
2010                          */
2011                         if (irq < 16)
2012                                 make_8259A_irq(irq);
2013                         else
2014                                 /* Strange. Oh, well.. */
2015                                 irq_desc[irq].chip = &no_irq_chip;
2016                 }
2017         }
2018 }
2019
2020 /*
2021  * The local APIC irq-chip implementation:
2022  */
2023
2024 static void ack_apic(unsigned int irq)
2025 {
2026         ack_APIC_irq();
2027 }
2028
2029 static void mask_lapic_irq (unsigned int irq)
2030 {
2031         unsigned long v;
2032
2033         v = apic_read(APIC_LVT0);
2034         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2035 }
2036
2037 static void unmask_lapic_irq (unsigned int irq)
2038 {
2039         unsigned long v;
2040
2041         v = apic_read(APIC_LVT0);
2042         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2043 }
2044
2045 static struct irq_chip lapic_chip __read_mostly = {
2046         .name           = "local-APIC-edge",
2047         .mask           = mask_lapic_irq,
2048         .unmask         = unmask_lapic_irq,
2049         .eoi            = ack_apic,
2050 };
2051
2052 static void __init setup_nmi(void)
2053 {
2054         /*
2055          * Dirty trick to enable the NMI watchdog ...
2056          * We put the 8259A master into AEOI mode and
2057          * unmask on all local APICs LVT0 as NMI.
2058          *
2059          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2060          * is from Maciej W. Rozycki - so we do not have to EOI from
2061          * the NMI handler or the timer interrupt.
2062          */
2063         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2064
2065         enable_NMI_through_LVT0();
2066
2067         apic_printk(APIC_VERBOSE, " done.\n");
2068 }
2069
2070 /*
2071  * This looks a bit hackish but it's about the only one way of sending
2072  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2073  * not support the ExtINT mode, unfortunately.  We need to send these
2074  * cycles as some i82489DX-based boards have glue logic that keeps the
2075  * 8259A interrupt line asserted until INTA.  --macro
2076  */
2077 static inline void __init unlock_ExtINT_logic(void)
2078 {
2079         int apic, pin, i;
2080         struct IO_APIC_route_entry entry0, entry1;
2081         unsigned char save_control, save_freq_select;
2082
2083         pin  = find_isa_irq_pin(8, mp_INT);
2084         if (pin == -1) {
2085                 WARN_ON_ONCE(1);
2086                 return;
2087         }
2088         apic = find_isa_irq_apic(8, mp_INT);
2089         if (apic == -1) {
2090                 WARN_ON_ONCE(1);
2091                 return;
2092         }
2093
2094         entry0 = ioapic_read_entry(apic, pin);
2095         clear_IO_APIC_pin(apic, pin);
2096
2097         memset(&entry1, 0, sizeof(entry1));
2098
2099         entry1.dest_mode = 0;                   /* physical delivery */
2100         entry1.mask = 0;                        /* unmask IRQ now */
2101         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2102         entry1.delivery_mode = dest_ExtINT;
2103         entry1.polarity = entry0.polarity;
2104         entry1.trigger = 0;
2105         entry1.vector = 0;
2106
2107         ioapic_write_entry(apic, pin, entry1);
2108
2109         save_control = CMOS_READ(RTC_CONTROL);
2110         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2111         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2112                    RTC_FREQ_SELECT);
2113         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2114
2115         i = 100;
2116         while (i-- > 0) {
2117                 mdelay(10);
2118                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2119                         i -= 10;
2120         }
2121
2122         CMOS_WRITE(save_control, RTC_CONTROL);
2123         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2124         clear_IO_APIC_pin(apic, pin);
2125
2126         ioapic_write_entry(apic, pin, entry0);
2127 }
2128
2129 /*
2130  * This code may look a bit paranoid, but it's supposed to cooperate with
2131  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2132  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2133  * fanatically on his truly buggy board.
2134  */
2135 static inline void __init check_timer(void)
2136 {
2137         int apic1, pin1, apic2, pin2;
2138         int vector;
2139         unsigned int ver;
2140         unsigned long flags;
2141
2142         local_irq_save(flags);
2143
2144         ver = apic_read(APIC_LVR);
2145         ver = GET_APIC_VERSION(ver);
2146
2147         /*
2148          * get/set the timer IRQ vector:
2149          */
2150         disable_8259A_irq(0);
2151         vector = assign_irq_vector(0);
2152         set_intr_gate(vector, interrupt[0]);
2153
2154         /*
2155          * Subtle, code in do_timer_interrupt() expects an AEOI
2156          * mode for the 8259A whenever interrupts are routed
2157          * through I/O APICs.  Also IRQ0 has to be enabled in
2158          * the 8259A which implies the virtual wire has to be
2159          * disabled in the local APIC.  Finally timer interrupts
2160          * need to be acknowledged manually in the 8259A for
2161          * timer_interrupt() and for the i82489DX when using
2162          * the NMI watchdog.
2163          */
2164         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2165         init_8259A(1);
2166         timer_ack = !cpu_has_tsc;
2167         timer_ack |= (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2168         if (timer_over_8254 > 0)
2169                 enable_8259A_irq(0);
2170
2171         pin1  = find_isa_irq_pin(0, mp_INT);
2172         apic1 = find_isa_irq_apic(0, mp_INT);
2173         pin2  = ioapic_i8259.pin;
2174         apic2 = ioapic_i8259.apic;
2175
2176         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2177                 vector, apic1, pin1, apic2, pin2);
2178
2179         if (pin1 != -1) {
2180                 /*
2181                  * Ok, does IRQ0 through the IOAPIC work?
2182                  */
2183                 unmask_IO_APIC_irq(0);
2184                 if (timer_irq_works()) {
2185                         if (nmi_watchdog == NMI_IO_APIC) {
2186                                 disable_8259A_irq(0);
2187                                 setup_nmi();
2188                                 enable_8259A_irq(0);
2189                         }
2190                         if (disable_timer_pin_1 > 0)
2191                                 clear_IO_APIC_pin(0, pin1);
2192                         goto out;
2193                 }
2194                 clear_IO_APIC_pin(apic1, pin1);
2195                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2196                                 "IO-APIC\n");
2197         }
2198
2199         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2200         if (pin2 != -1) {
2201                 printk("\n..... (found pin %d) ...", pin2);
2202                 /*
2203                  * legacy devices should be connected to IO APIC #0
2204                  */
2205                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2206                 if (timer_irq_works()) {
2207                         printk("works.\n");
2208                         if (pin1 != -1)
2209                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2210                         else
2211                                 add_pin_to_irq(0, apic2, pin2);
2212                         if (nmi_watchdog == NMI_IO_APIC) {
2213                                 setup_nmi();
2214                         }
2215                         goto out;
2216                 }
2217                 /*
2218                  * Cleanup, just in case ...
2219                  */
2220                 clear_IO_APIC_pin(apic2, pin2);
2221         }
2222         printk(" failed.\n");
2223
2224         if (nmi_watchdog == NMI_IO_APIC) {
2225                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2226                 nmi_watchdog = 0;
2227         }
2228
2229         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2230
2231         disable_8259A_irq(0);
2232         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2233                                       "fasteoi");
2234         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2235         enable_8259A_irq(0);
2236
2237         if (timer_irq_works()) {
2238                 printk(" works.\n");
2239                 goto out;
2240         }
2241         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2242         printk(" failed.\n");
2243
2244         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2245
2246         timer_ack = 0;
2247         init_8259A(0);
2248         make_8259A_irq(0);
2249         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2250
2251         unlock_ExtINT_logic();
2252
2253         if (timer_irq_works()) {
2254                 printk(" works.\n");
2255                 goto out;
2256         }
2257         printk(" failed :(.\n");
2258         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2259                 "report.  Then try booting with the 'noapic' option");
2260 out:
2261         local_irq_restore(flags);
2262 }
2263
2264 /*
2265  *
2266  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2267  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2268  *   Linux doesn't really care, as it's not actually used
2269  *   for any interrupt handling anyway.
2270  */
2271 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2272
2273 void __init setup_IO_APIC(void)
2274 {
2275         int i;
2276
2277         /* Reserve all the system vectors. */
2278         for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2279                 set_bit(i, used_vectors);
2280
2281         enable_IO_APIC();
2282
2283         if (acpi_ioapic)
2284                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2285         else
2286                 io_apic_irqs = ~PIC_IRQS;
2287
2288         printk("ENABLING IO-APIC IRQs\n");
2289
2290         /*
2291          * Set up IO-APIC IRQ routing.
2292          */
2293         if (!acpi_ioapic)
2294                 setup_ioapic_ids_from_mpc();
2295         sync_Arb_IDs();
2296         setup_IO_APIC_irqs();
2297         init_IO_APIC_traps();
2298         check_timer();
2299         if (!acpi_ioapic)
2300                 print_IO_APIC();
2301 }
2302
2303 static int __init setup_disable_8254_timer(char *s)
2304 {
2305         timer_over_8254 = -1;
2306         return 1;
2307 }
2308 static int __init setup_enable_8254_timer(char *s)
2309 {
2310         timer_over_8254 = 2;
2311         return 1;
2312 }
2313
2314 __setup("disable_8254_timer", setup_disable_8254_timer);
2315 __setup("enable_8254_timer", setup_enable_8254_timer);
2316
2317 /*
2318  *      Called after all the initialization is done. If we didnt find any
2319  *      APIC bugs then we can allow the modify fast path
2320  */
2321
2322 static int __init io_apic_bug_finalize(void)
2323 {
2324         if(sis_apic_bug == -1)
2325                 sis_apic_bug = 0;
2326         return 0;
2327 }
2328
2329 late_initcall(io_apic_bug_finalize);
2330
2331 struct sysfs_ioapic_data {
2332         struct sys_device dev;
2333         struct IO_APIC_route_entry entry[0];
2334 };
2335 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2336
2337 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2338 {
2339         struct IO_APIC_route_entry *entry;
2340         struct sysfs_ioapic_data *data;
2341         int i;
2342
2343         data = container_of(dev, struct sysfs_ioapic_data, dev);
2344         entry = data->entry;
2345         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2346                 entry[i] = ioapic_read_entry(dev->id, i);
2347
2348         return 0;
2349 }
2350
2351 static int ioapic_resume(struct sys_device *dev)
2352 {
2353         struct IO_APIC_route_entry *entry;
2354         struct sysfs_ioapic_data *data;
2355         unsigned long flags;
2356         union IO_APIC_reg_00 reg_00;
2357         int i;
2358
2359         data = container_of(dev, struct sysfs_ioapic_data, dev);
2360         entry = data->entry;
2361
2362         spin_lock_irqsave(&ioapic_lock, flags);
2363         reg_00.raw = io_apic_read(dev->id, 0);
2364         if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2365                 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2366                 io_apic_write(dev->id, 0, reg_00.raw);
2367         }
2368         spin_unlock_irqrestore(&ioapic_lock, flags);
2369         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2370                 ioapic_write_entry(dev->id, i, entry[i]);
2371
2372         return 0;
2373 }
2374
2375 static struct sysdev_class ioapic_sysdev_class = {
2376         .name = "ioapic",
2377         .suspend = ioapic_suspend,
2378         .resume = ioapic_resume,
2379 };
2380
2381 static int __init ioapic_init_sysfs(void)
2382 {
2383         struct sys_device * dev;
2384         int i, size, error = 0;
2385
2386         error = sysdev_class_register(&ioapic_sysdev_class);
2387         if (error)
2388                 return error;
2389
2390         for (i = 0; i < nr_ioapics; i++ ) {
2391                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2392                         * sizeof(struct IO_APIC_route_entry);
2393                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2394                 if (!mp_ioapic_data[i]) {
2395                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2396                         continue;
2397                 }
2398                 memset(mp_ioapic_data[i], 0, size);
2399                 dev = &mp_ioapic_data[i]->dev;
2400                 dev->id = i;
2401                 dev->cls = &ioapic_sysdev_class;
2402                 error = sysdev_register(dev);
2403                 if (error) {
2404                         kfree(mp_ioapic_data[i]);
2405                         mp_ioapic_data[i] = NULL;
2406                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2407                         continue;
2408                 }
2409         }
2410
2411         return 0;
2412 }
2413
2414 device_initcall(ioapic_init_sysfs);
2415
2416 /*
2417  * Dynamic irq allocate and deallocation
2418  */
2419 int create_irq(void)
2420 {
2421         /* Allocate an unused irq */
2422         int irq, new, vector = 0;
2423         unsigned long flags;
2424
2425         irq = -ENOSPC;
2426         spin_lock_irqsave(&vector_lock, flags);
2427         for (new = (NR_IRQS - 1); new >= 0; new--) {
2428                 if (platform_legacy_irq(new))
2429                         continue;
2430                 if (irq_vector[new] != 0)
2431                         continue;
2432                 vector = __assign_irq_vector(new);
2433                 if (likely(vector > 0))
2434                         irq = new;
2435                 break;
2436         }
2437         spin_unlock_irqrestore(&vector_lock, flags);
2438
2439         if (irq >= 0) {
2440                 set_intr_gate(vector, interrupt[irq]);
2441                 dynamic_irq_init(irq);
2442         }
2443         return irq;
2444 }
2445
2446 void destroy_irq(unsigned int irq)
2447 {
2448         unsigned long flags;
2449
2450         dynamic_irq_cleanup(irq);
2451
2452         spin_lock_irqsave(&vector_lock, flags);
2453         clear_bit(irq_vector[irq], used_vectors);
2454         irq_vector[irq] = 0;
2455         spin_unlock_irqrestore(&vector_lock, flags);
2456 }
2457
2458 /*
2459  * MSI message composition
2460  */
2461 #ifdef CONFIG_PCI_MSI
2462 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2463 {
2464         int vector;
2465         unsigned dest;
2466
2467         vector = assign_irq_vector(irq);
2468         if (vector >= 0) {
2469                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2470
2471                 msg->address_hi = MSI_ADDR_BASE_HI;
2472                 msg->address_lo =
2473                         MSI_ADDR_BASE_LO |
2474                         ((INT_DEST_MODE == 0) ?
2475                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2476                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2477                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2478                                 MSI_ADDR_REDIRECTION_CPU:
2479                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2480                         MSI_ADDR_DEST_ID(dest);
2481
2482                 msg->data =
2483                         MSI_DATA_TRIGGER_EDGE |
2484                         MSI_DATA_LEVEL_ASSERT |
2485                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2486                                 MSI_DATA_DELIVERY_FIXED:
2487                                 MSI_DATA_DELIVERY_LOWPRI) |
2488                         MSI_DATA_VECTOR(vector);
2489         }
2490         return vector;
2491 }
2492
2493 #ifdef CONFIG_SMP
2494 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2495 {
2496         struct msi_msg msg;
2497         unsigned int dest;
2498         cpumask_t tmp;
2499         int vector;
2500
2501         cpus_and(tmp, mask, cpu_online_map);
2502         if (cpus_empty(tmp))
2503                 tmp = TARGET_CPUS;
2504
2505         vector = assign_irq_vector(irq);
2506         if (vector < 0)
2507                 return;
2508
2509         dest = cpu_mask_to_apicid(mask);
2510
2511         read_msi_msg(irq, &msg);
2512
2513         msg.data &= ~MSI_DATA_VECTOR_MASK;
2514         msg.data |= MSI_DATA_VECTOR(vector);
2515         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2516         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2517
2518         write_msi_msg(irq, &msg);
2519         irq_desc[irq].affinity = mask;
2520 }
2521 #endif /* CONFIG_SMP */
2522
2523 /*
2524  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2525  * which implement the MSI or MSI-X Capability Structure.
2526  */
2527 static struct irq_chip msi_chip = {
2528         .name           = "PCI-MSI",
2529         .unmask         = unmask_msi_irq,
2530         .mask           = mask_msi_irq,
2531         .ack            = ack_ioapic_irq,
2532 #ifdef CONFIG_SMP
2533         .set_affinity   = set_msi_irq_affinity,
2534 #endif
2535         .retrigger      = ioapic_retrigger_irq,
2536 };
2537
2538 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2539 {
2540         struct msi_msg msg;
2541         int irq, ret;
2542         irq = create_irq();
2543         if (irq < 0)
2544                 return irq;
2545
2546         ret = msi_compose_msg(dev, irq, &msg);
2547         if (ret < 0) {
2548                 destroy_irq(irq);
2549                 return ret;
2550         }
2551
2552         set_irq_msi(irq, desc);
2553         write_msi_msg(irq, &msg);
2554
2555         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2556                                       "edge");
2557
2558         return 0;
2559 }
2560
2561 void arch_teardown_msi_irq(unsigned int irq)
2562 {
2563         destroy_irq(irq);
2564 }
2565
2566 #endif /* CONFIG_PCI_MSI */
2567
2568 /*
2569  * Hypertransport interrupt support
2570  */
2571 #ifdef CONFIG_HT_IRQ
2572
2573 #ifdef CONFIG_SMP
2574
2575 static void target_ht_irq(unsigned int irq, unsigned int dest)
2576 {
2577         struct ht_irq_msg msg;
2578         fetch_ht_irq_msg(irq, &msg);
2579
2580         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2581         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2582
2583         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2584         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2585
2586         write_ht_irq_msg(irq, &msg);
2587 }
2588
2589 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2590 {
2591         unsigned int dest;
2592         cpumask_t tmp;
2593
2594         cpus_and(tmp, mask, cpu_online_map);
2595         if (cpus_empty(tmp))
2596                 tmp = TARGET_CPUS;
2597
2598         cpus_and(mask, tmp, CPU_MASK_ALL);
2599
2600         dest = cpu_mask_to_apicid(mask);
2601
2602         target_ht_irq(irq, dest);
2603         irq_desc[irq].affinity = mask;
2604 }
2605 #endif
2606
2607 static struct irq_chip ht_irq_chip = {
2608         .name           = "PCI-HT",
2609         .mask           = mask_ht_irq,
2610         .unmask         = unmask_ht_irq,
2611         .ack            = ack_ioapic_irq,
2612 #ifdef CONFIG_SMP
2613         .set_affinity   = set_ht_irq_affinity,
2614 #endif
2615         .retrigger      = ioapic_retrigger_irq,
2616 };
2617
2618 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2619 {
2620         int vector;
2621
2622         vector = assign_irq_vector(irq);
2623         if (vector >= 0) {
2624                 struct ht_irq_msg msg;
2625                 unsigned dest;
2626                 cpumask_t tmp;
2627
2628                 cpus_clear(tmp);
2629                 cpu_set(vector >> 8, tmp);
2630                 dest = cpu_mask_to_apicid(tmp);
2631
2632                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2633
2634                 msg.address_lo =
2635                         HT_IRQ_LOW_BASE |
2636                         HT_IRQ_LOW_DEST_ID(dest) |
2637                         HT_IRQ_LOW_VECTOR(vector) |
2638                         ((INT_DEST_MODE == 0) ?
2639                                 HT_IRQ_LOW_DM_PHYSICAL :
2640                                 HT_IRQ_LOW_DM_LOGICAL) |
2641                         HT_IRQ_LOW_RQEOI_EDGE |
2642                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2643                                 HT_IRQ_LOW_MT_FIXED :
2644                                 HT_IRQ_LOW_MT_ARBITRATED) |
2645                         HT_IRQ_LOW_IRQ_MASKED;
2646
2647                 write_ht_irq_msg(irq, &msg);
2648
2649                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2650                                               handle_edge_irq, "edge");
2651         }
2652         return vector;
2653 }
2654 #endif /* CONFIG_HT_IRQ */
2655
2656 /* --------------------------------------------------------------------------
2657                           ACPI-based IOAPIC Configuration
2658    -------------------------------------------------------------------------- */
2659
2660 #ifdef CONFIG_ACPI
2661
2662 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2663 {
2664         union IO_APIC_reg_00 reg_00;
2665         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2666         physid_mask_t tmp;
2667         unsigned long flags;
2668         int i = 0;
2669
2670         /*
2671          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2672          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2673          * supports up to 16 on one shared APIC bus.
2674          *
2675          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2676          *      advantage of new APIC bus architecture.
2677          */
2678
2679         if (physids_empty(apic_id_map))
2680                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2681
2682         spin_lock_irqsave(&ioapic_lock, flags);
2683         reg_00.raw = io_apic_read(ioapic, 0);
2684         spin_unlock_irqrestore(&ioapic_lock, flags);
2685
2686         if (apic_id >= get_physical_broadcast()) {
2687                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2688                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2689                 apic_id = reg_00.bits.ID;
2690         }
2691
2692         /*
2693          * Every APIC in a system must have a unique ID or we get lots of nice
2694          * 'stuck on smp_invalidate_needed IPI wait' messages.
2695          */
2696         if (check_apicid_used(apic_id_map, apic_id)) {
2697
2698                 for (i = 0; i < get_physical_broadcast(); i++) {
2699                         if (!check_apicid_used(apic_id_map, i))
2700                                 break;
2701                 }
2702
2703                 if (i == get_physical_broadcast())
2704                         panic("Max apic_id exceeded!\n");
2705
2706                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2707                         "trying %d\n", ioapic, apic_id, i);
2708
2709                 apic_id = i;
2710         }
2711
2712         tmp = apicid_to_cpu_present(apic_id);
2713         physids_or(apic_id_map, apic_id_map, tmp);
2714
2715         if (reg_00.bits.ID != apic_id) {
2716                 reg_00.bits.ID = apic_id;
2717
2718                 spin_lock_irqsave(&ioapic_lock, flags);
2719                 io_apic_write(ioapic, 0, reg_00.raw);
2720                 reg_00.raw = io_apic_read(ioapic, 0);
2721                 spin_unlock_irqrestore(&ioapic_lock, flags);
2722
2723                 /* Sanity check */
2724                 if (reg_00.bits.ID != apic_id) {
2725                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2726                         return -1;
2727                 }
2728         }
2729
2730         apic_printk(APIC_VERBOSE, KERN_INFO
2731                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2732
2733         return apic_id;
2734 }
2735
2736
2737 int __init io_apic_get_version (int ioapic)
2738 {
2739         union IO_APIC_reg_01    reg_01;
2740         unsigned long flags;
2741
2742         spin_lock_irqsave(&ioapic_lock, flags);
2743         reg_01.raw = io_apic_read(ioapic, 1);
2744         spin_unlock_irqrestore(&ioapic_lock, flags);
2745
2746         return reg_01.bits.version;
2747 }
2748
2749
2750 int __init io_apic_get_redir_entries (int ioapic)
2751 {
2752         union IO_APIC_reg_01    reg_01;
2753         unsigned long flags;
2754
2755         spin_lock_irqsave(&ioapic_lock, flags);
2756         reg_01.raw = io_apic_read(ioapic, 1);
2757         spin_unlock_irqrestore(&ioapic_lock, flags);
2758
2759         return reg_01.bits.entries;
2760 }
2761
2762
2763 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2764 {
2765         struct IO_APIC_route_entry entry;
2766
2767         if (!IO_APIC_IRQ(irq)) {
2768                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2769                         ioapic);
2770                 return -EINVAL;
2771         }
2772
2773         /*
2774          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2775          * Note that we mask (disable) IRQs now -- these get enabled when the
2776          * corresponding device driver registers for this IRQ.
2777          */
2778
2779         memset(&entry,0,sizeof(entry));
2780
2781         entry.delivery_mode = INT_DELIVERY_MODE;
2782         entry.dest_mode = INT_DEST_MODE;
2783         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2784         entry.trigger = edge_level;
2785         entry.polarity = active_high_low;
2786         entry.mask  = 1;
2787
2788         /*
2789          * IRQs < 16 are already in the irq_2_pin[] map
2790          */
2791         if (irq >= 16)
2792                 add_pin_to_irq(irq, ioapic, pin);
2793
2794         entry.vector = assign_irq_vector(irq);
2795
2796         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2797                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2798                 mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq,
2799                 edge_level, active_high_low);
2800
2801         ioapic_register_intr(irq, entry.vector, edge_level);
2802
2803         if (!ioapic && (irq < 16))
2804                 disable_8259A_irq(irq);
2805
2806         ioapic_write_entry(ioapic, pin, entry);
2807
2808         return 0;
2809 }
2810
2811 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2812 {
2813         int i;
2814
2815         if (skip_ioapic_setup)
2816                 return -1;
2817
2818         for (i = 0; i < mp_irq_entries; i++)
2819                 if (mp_irqs[i].mp_irqtype == mp_INT &&
2820                     mp_irqs[i].mp_srcbusirq == bus_irq)
2821                         break;
2822         if (i >= mp_irq_entries)
2823                 return -1;
2824
2825         *trigger = irq_trigger(i);
2826         *polarity = irq_polarity(i);
2827         return 0;
2828 }
2829
2830 #endif /* CONFIG_ACPI */
2831
2832 static int __init parse_disable_timer_pin_1(char *arg)
2833 {
2834         disable_timer_pin_1 = 1;
2835         return 0;
2836 }
2837 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2838
2839 static int __init parse_enable_timer_pin_1(char *arg)
2840 {
2841         disable_timer_pin_1 = -1;
2842         return 0;
2843 }
2844 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2845
2846 static int __init parse_noapic(char *arg)
2847 {
2848         /* disable IO-APIC */
2849         disable_ioapic_setup();
2850         return 0;
2851 }
2852 early_param("noapic", parse_noapic);