2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
61 #include <asm/uv/uv_hub.h>
62 #include <asm/uv/uv_irq.h>
65 #include <mach_apic.h>
66 #include <mach_apicdef.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
88 /* MP IRQ source entries */
89 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100 int skip_ioapic_setup;
102 static int __init parse_noapic(char *str)
104 /* disable IO-APIC */
105 disable_ioapic_setup();
108 early_param("noapic", parse_noapic);
114 struct irq_pin_list *irq_2_pin;
116 cpumask_t old_domain;
117 unsigned move_cleanup_count;
119 u8 move_in_progress : 1;
122 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
123 static struct irq_cfg irq_cfg_legacy[] __initdata = {
124 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
125 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
126 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
127 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
128 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
129 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
130 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
131 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
132 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
133 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
134 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
135 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
136 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
137 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
138 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
139 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
142 static struct irq_cfg irq_cfg_init = { .irq = -1U, };
144 static void init_one_irq_cfg(struct irq_cfg *cfg)
146 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
149 static struct irq_cfg *irq_cfgx;
151 static void __init init_work(void *data)
153 struct dyn_array *da = data;
160 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
162 legacy_count = ARRAY_SIZE(irq_cfg_legacy);
163 for (i = legacy_count; i < *da->nr; i++)
164 init_one_irq_cfg(&cfg[i]);
167 #define for_each_irq_cfg(irq, cfg) \
168 for (irq = 0, cfg = &irq_cfgx[irq]; irq < nr_irqs; irq++, cfg = &irq_cfgx[irq])
170 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irqs, PAGE_SIZE, init_work);
172 struct irq_cfg *irq_cfg(unsigned int irq)
175 return &irq_cfgx[irq];
179 struct irq_cfg *irq_cfg_alloc(unsigned int irq)
185 * This is performance-critical, we want to do it O(1)
187 * the indexing order of this array favors 1:1 mappings
188 * between pins and IRQs.
191 struct irq_pin_list {
193 struct irq_pin_list *next;
196 static struct irq_pin_list *irq_2_pin_head;
197 /* fill one page ? */
198 static int nr_irq_2_pin = 0x100;
199 static struct irq_pin_list *irq_2_pin_ptr;
200 static void __init irq_2_pin_init_work(void *data)
202 struct dyn_array *da = data;
203 struct irq_pin_list *pin;
208 for (i = 1; i < *da->nr; i++)
209 pin[i-1].next = &pin[i];
211 irq_2_pin_ptr = &pin[0];
213 DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
215 static struct irq_pin_list *get_one_free_irq_2_pin(void)
217 struct irq_pin_list *pin;
223 irq_2_pin_ptr = pin->next;
229 * we run out of pre-allocate ones, allocate more
231 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
234 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
237 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
238 nr_irq_2_pin, PAGE_SIZE, 0);
241 panic("can not get more irq_2_pin\n");
243 for (i = 1; i < nr_irq_2_pin; i++)
244 pin[i-1].next = &pin[i];
246 irq_2_pin_ptr = pin->next;
254 unsigned int unused[3];
258 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
260 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
261 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
264 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
266 struct io_apic __iomem *io_apic = io_apic_base(apic);
267 writel(reg, &io_apic->index);
268 return readl(&io_apic->data);
271 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
273 struct io_apic __iomem *io_apic = io_apic_base(apic);
274 writel(reg, &io_apic->index);
275 writel(value, &io_apic->data);
279 * Re-write a value: to be used for read-modify-write
280 * cycles where the read already set up the index register.
282 * Older SiS APIC requires we rewrite the index register
284 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
286 struct io_apic __iomem *io_apic = io_apic_base(apic);
288 writel(reg, &io_apic->index);
289 writel(value, &io_apic->data);
292 static bool io_apic_level_ack_pending(unsigned int irq)
294 struct irq_pin_list *entry;
296 struct irq_cfg *cfg = irq_cfg(irq);
298 spin_lock_irqsave(&ioapic_lock, flags);
299 entry = cfg->irq_2_pin;
307 reg = io_apic_read(entry->apic, 0x10 + pin*2);
308 /* Is the remote IRR bit set? */
309 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
310 spin_unlock_irqrestore(&ioapic_lock, flags);
317 spin_unlock_irqrestore(&ioapic_lock, flags);
323 struct { u32 w1, w2; };
324 struct IO_APIC_route_entry entry;
327 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
329 union entry_union eu;
331 spin_lock_irqsave(&ioapic_lock, flags);
332 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
333 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
334 spin_unlock_irqrestore(&ioapic_lock, flags);
339 * When we write a new IO APIC routing entry, we need to write the high
340 * word first! If the mask bit in the low word is clear, we will enable
341 * the interrupt, and we need to make sure the entry is fully populated
342 * before that happens.
345 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
347 union entry_union eu;
349 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
350 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
353 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
356 spin_lock_irqsave(&ioapic_lock, flags);
357 __ioapic_write_entry(apic, pin, e);
358 spin_unlock_irqrestore(&ioapic_lock, flags);
362 * When we mask an IO APIC routing entry, we need to write the low
363 * word first, in order to set the mask bit before we change the
366 static void ioapic_mask_entry(int apic, int pin)
369 union entry_union eu = { .entry.mask = 1 };
371 spin_lock_irqsave(&ioapic_lock, flags);
372 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
373 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
374 spin_unlock_irqrestore(&ioapic_lock, flags);
378 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
382 struct irq_pin_list *entry;
385 entry = cfg->irq_2_pin;
394 #ifdef CONFIG_INTR_REMAP
396 * With interrupt-remapping, destination information comes
397 * from interrupt-remapping table entry.
399 if (!irq_remapped(irq))
400 io_apic_write(apic, 0x11 + pin*2, dest);
402 io_apic_write(apic, 0x11 + pin*2, dest);
404 reg = io_apic_read(apic, 0x10 + pin*2);
405 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
407 io_apic_modify(apic, 0x10 + pin*2, reg);
414 static int assign_irq_vector(int irq, cpumask_t mask);
416 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
422 struct irq_desc *desc;
424 cpus_and(tmp, mask, cpu_online_map);
429 if (assign_irq_vector(irq, mask))
432 cpus_and(tmp, cfg->domain, mask);
433 dest = cpu_mask_to_apicid(tmp);
435 * Only the high 8 bits are valid.
437 dest = SET_APIC_LOGICAL_ID(dest);
439 desc = irq_to_desc(irq);
440 spin_lock_irqsave(&ioapic_lock, flags);
441 __target_IO_APIC_irq(irq, dest, cfg->vector);
442 desc->affinity = mask;
443 spin_unlock_irqrestore(&ioapic_lock, flags);
445 #endif /* CONFIG_SMP */
448 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
449 * shared ISA-space IRQs, so we have to support them. We are super
450 * fast in the common case, and fast for shared ISA-space IRQs.
452 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
455 struct irq_pin_list *entry;
457 /* first time to refer irq_cfg, so with new */
458 cfg = irq_cfg_alloc(irq);
459 entry = cfg->irq_2_pin;
461 entry = get_one_free_irq_2_pin();
462 cfg->irq_2_pin = entry;
468 while (entry->next) {
469 /* not again, please */
470 if (entry->apic == apic && entry->pin == pin)
476 entry->next = get_one_free_irq_2_pin();
483 * Reroute an IRQ to a different pin.
485 static void __init replace_pin_at_irq(unsigned int irq,
486 int oldapic, int oldpin,
487 int newapic, int newpin)
489 struct irq_cfg *cfg = irq_cfg(irq);
490 struct irq_pin_list *entry = cfg->irq_2_pin;
494 if (entry->apic == oldapic && entry->pin == oldpin) {
495 entry->apic = newapic;
498 /* every one is different, right? */
504 /* why? call replace before add? */
506 add_pin_to_irq(irq, newapic, newpin);
509 static inline void io_apic_modify_irq(unsigned int irq,
510 int mask_and, int mask_or,
511 void (*final)(struct irq_pin_list *entry))
515 struct irq_pin_list *entry;
518 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
521 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
524 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
530 static void __unmask_IO_APIC_irq(unsigned int irq)
532 io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED, 0, NULL);
536 void io_apic_sync(struct irq_pin_list *entry)
539 * Synchronize the IO-APIC and the CPU by doing
540 * a dummy read from the IO-APIC
542 struct io_apic __iomem *io_apic;
543 io_apic = io_apic_base(entry->apic);
544 readl(&io_apic->data);
547 static void __mask_IO_APIC_irq(unsigned int irq)
549 io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
551 #else /* CONFIG_X86_32 */
552 static void __mask_IO_APIC_irq(unsigned int irq)
554 io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, NULL);
557 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
559 io_apic_modify_irq(irq, ~IO_APIC_REDIR_LEVEL_TRIGGER,
560 IO_APIC_REDIR_MASKED, NULL);
563 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
565 io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED,
566 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
568 #endif /* CONFIG_X86_32 */
570 static void mask_IO_APIC_irq (unsigned int irq)
574 spin_lock_irqsave(&ioapic_lock, flags);
575 __mask_IO_APIC_irq(irq);
576 spin_unlock_irqrestore(&ioapic_lock, flags);
579 static void unmask_IO_APIC_irq (unsigned int irq)
583 spin_lock_irqsave(&ioapic_lock, flags);
584 __unmask_IO_APIC_irq(irq);
585 spin_unlock_irqrestore(&ioapic_lock, flags);
588 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
590 struct IO_APIC_route_entry entry;
592 /* Check delivery_mode to be sure we're not clearing an SMI pin */
593 entry = ioapic_read_entry(apic, pin);
594 if (entry.delivery_mode == dest_SMI)
597 * Disable it in the IO-APIC irq-routing table:
599 ioapic_mask_entry(apic, pin);
602 static void clear_IO_APIC (void)
606 for (apic = 0; apic < nr_ioapics; apic++)
607 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
608 clear_IO_APIC_pin(apic, pin);
611 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
612 void send_IPI_self(int vector)
619 apic_wait_icr_idle();
620 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
622 * Send the IPI. The write to APIC_ICR fires this off.
624 apic_write(APIC_ICR, cfg);
626 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
630 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
631 * specific CPU-side IRQs.
635 static int pirq_entries [MAX_PIRQS];
636 static int pirqs_enabled;
638 static int __init ioapic_pirq_setup(char *str)
641 int ints[MAX_PIRQS+1];
643 get_options(str, ARRAY_SIZE(ints), ints);
645 for (i = 0; i < MAX_PIRQS; i++)
646 pirq_entries[i] = -1;
649 apic_printk(APIC_VERBOSE, KERN_INFO
650 "PIRQ redirection, working around broken MP-BIOS.\n");
652 if (ints[0] < MAX_PIRQS)
655 for (i = 0; i < max; i++) {
656 apic_printk(APIC_VERBOSE, KERN_DEBUG
657 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
659 * PIRQs are mapped upside down, usually.
661 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
666 __setup("pirq=", ioapic_pirq_setup);
667 #endif /* CONFIG_X86_32 */
669 #ifdef CONFIG_INTR_REMAP
670 /* I/O APIC RTE contents at the OS boot up */
671 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
674 * Saves and masks all the unmasked IO-APIC RTE's
676 int save_mask_IO_APIC_setup(void)
678 union IO_APIC_reg_01 reg_01;
683 * The number of IO-APIC IRQ registers (== #pins):
685 for (apic = 0; apic < nr_ioapics; apic++) {
686 spin_lock_irqsave(&ioapic_lock, flags);
687 reg_01.raw = io_apic_read(apic, 1);
688 spin_unlock_irqrestore(&ioapic_lock, flags);
689 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
692 for (apic = 0; apic < nr_ioapics; apic++) {
693 early_ioapic_entries[apic] =
694 kzalloc(sizeof(struct IO_APIC_route_entry) *
695 nr_ioapic_registers[apic], GFP_KERNEL);
696 if (!early_ioapic_entries[apic])
700 for (apic = 0; apic < nr_ioapics; apic++)
701 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
702 struct IO_APIC_route_entry entry;
704 entry = early_ioapic_entries[apic][pin] =
705 ioapic_read_entry(apic, pin);
708 ioapic_write_entry(apic, pin, entry);
716 kfree(early_ioapic_entries[apic--]);
717 memset(early_ioapic_entries, 0,
718 ARRAY_SIZE(early_ioapic_entries));
723 void restore_IO_APIC_setup(void)
727 for (apic = 0; apic < nr_ioapics; apic++) {
728 if (!early_ioapic_entries[apic])
730 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
731 ioapic_write_entry(apic, pin,
732 early_ioapic_entries[apic][pin]);
733 kfree(early_ioapic_entries[apic]);
734 early_ioapic_entries[apic] = NULL;
738 void reinit_intr_remapped_IO_APIC(int intr_remapping)
741 * for now plain restore of previous settings.
742 * TBD: In the case of OS enabling interrupt-remapping,
743 * IO-APIC RTE's need to be setup to point to interrupt-remapping
744 * table entries. for now, do a plain restore, and wait for
745 * the setup_IO_APIC_irqs() to do proper initialization.
747 restore_IO_APIC_setup();
752 * Find the IRQ entry number of a certain pin.
754 static int find_irq_entry(int apic, int pin, int type)
758 for (i = 0; i < mp_irq_entries; i++)
759 if (mp_irqs[i].mp_irqtype == type &&
760 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
761 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
762 mp_irqs[i].mp_dstirq == pin)
769 * Find the pin to which IRQ[irq] (ISA) is connected
771 static int __init find_isa_irq_pin(int irq, int type)
775 for (i = 0; i < mp_irq_entries; i++) {
776 int lbus = mp_irqs[i].mp_srcbus;
778 if (test_bit(lbus, mp_bus_not_pci) &&
779 (mp_irqs[i].mp_irqtype == type) &&
780 (mp_irqs[i].mp_srcbusirq == irq))
782 return mp_irqs[i].mp_dstirq;
787 static int __init find_isa_irq_apic(int irq, int type)
791 for (i = 0; i < mp_irq_entries; i++) {
792 int lbus = mp_irqs[i].mp_srcbus;
794 if (test_bit(lbus, mp_bus_not_pci) &&
795 (mp_irqs[i].mp_irqtype == type) &&
796 (mp_irqs[i].mp_srcbusirq == irq))
799 if (i < mp_irq_entries) {
801 for(apic = 0; apic < nr_ioapics; apic++) {
802 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
811 * Find a specific PCI IRQ entry.
812 * Not an __init, possibly needed by modules
814 static int pin_2_irq(int idx, int apic, int pin);
816 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
818 int apic, i, best_guess = -1;
820 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
822 if (test_bit(bus, mp_bus_not_pci)) {
823 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
826 for (i = 0; i < mp_irq_entries; i++) {
827 int lbus = mp_irqs[i].mp_srcbus;
829 for (apic = 0; apic < nr_ioapics; apic++)
830 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
831 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
834 if (!test_bit(lbus, mp_bus_not_pci) &&
835 !mp_irqs[i].mp_irqtype &&
837 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
838 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
840 if (!(apic || IO_APIC_IRQ(irq)))
843 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
846 * Use the first all-but-pin matching entry as a
847 * best-guess fuzzy result for broken mptables.
856 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
858 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
860 * EISA Edge/Level control register, ELCR
862 static int EISA_ELCR(unsigned int irq)
865 unsigned int port = 0x4d0 + (irq >> 3);
866 return (inb(port) >> (irq & 7)) & 1;
868 apic_printk(APIC_VERBOSE, KERN_INFO
869 "Broken MPtable reports ISA irq %d\n", irq);
875 /* ISA interrupts are always polarity zero edge triggered,
876 * when listed as conforming in the MP table. */
878 #define default_ISA_trigger(idx) (0)
879 #define default_ISA_polarity(idx) (0)
881 /* EISA interrupts are always polarity zero and can be edge or level
882 * trigger depending on the ELCR value. If an interrupt is listed as
883 * EISA conforming in the MP table, that means its trigger type must
884 * be read in from the ELCR */
886 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
887 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
889 /* PCI interrupts are always polarity one level triggered,
890 * when listed as conforming in the MP table. */
892 #define default_PCI_trigger(idx) (1)
893 #define default_PCI_polarity(idx) (1)
895 /* MCA interrupts are always polarity zero level triggered,
896 * when listed as conforming in the MP table. */
898 #define default_MCA_trigger(idx) (1)
899 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
901 static int MPBIOS_polarity(int idx)
903 int bus = mp_irqs[idx].mp_srcbus;
907 * Determine IRQ line polarity (high active or low active):
909 switch (mp_irqs[idx].mp_irqflag & 3)
911 case 0: /* conforms, ie. bus-type dependent polarity */
912 if (test_bit(bus, mp_bus_not_pci))
913 polarity = default_ISA_polarity(idx);
915 polarity = default_PCI_polarity(idx);
917 case 1: /* high active */
922 case 2: /* reserved */
924 printk(KERN_WARNING "broken BIOS!!\n");
928 case 3: /* low active */
933 default: /* invalid */
935 printk(KERN_WARNING "broken BIOS!!\n");
943 static int MPBIOS_trigger(int idx)
945 int bus = mp_irqs[idx].mp_srcbus;
949 * Determine IRQ trigger mode (edge or level sensitive):
951 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
953 case 0: /* conforms, ie. bus-type dependent */
954 if (test_bit(bus, mp_bus_not_pci))
955 trigger = default_ISA_trigger(idx);
957 trigger = default_PCI_trigger(idx);
958 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
959 switch (mp_bus_id_to_type[bus]) {
960 case MP_BUS_ISA: /* ISA pin */
962 /* set before the switch */
965 case MP_BUS_EISA: /* EISA pin */
967 trigger = default_EISA_trigger(idx);
970 case MP_BUS_PCI: /* PCI pin */
972 /* set before the switch */
975 case MP_BUS_MCA: /* MCA pin */
977 trigger = default_MCA_trigger(idx);
982 printk(KERN_WARNING "broken BIOS!!\n");
994 case 2: /* reserved */
996 printk(KERN_WARNING "broken BIOS!!\n");
1005 default: /* invalid */
1007 printk(KERN_WARNING "broken BIOS!!\n");
1015 static inline int irq_polarity(int idx)
1017 return MPBIOS_polarity(idx);
1020 static inline int irq_trigger(int idx)
1022 return MPBIOS_trigger(idx);
1025 int (*ioapic_renumber_irq)(int ioapic, int irq);
1026 static int pin_2_irq(int idx, int apic, int pin)
1029 int bus = mp_irqs[idx].mp_srcbus;
1032 * Debugging check, we are in big trouble if this message pops up!
1034 if (mp_irqs[idx].mp_dstirq != pin)
1035 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1037 if (test_bit(bus, mp_bus_not_pci)) {
1038 irq = mp_irqs[idx].mp_srcbusirq;
1041 * PCI IRQs are mapped in order
1045 irq += nr_ioapic_registers[i++];
1048 * For MPS mode, so far only needed by ES7000 platform
1050 if (ioapic_renumber_irq)
1051 irq = ioapic_renumber_irq(apic, irq);
1054 #ifdef CONFIG_X86_32
1056 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1058 if ((pin >= 16) && (pin <= 23)) {
1059 if (pirq_entries[pin-16] != -1) {
1060 if (!pirq_entries[pin-16]) {
1061 apic_printk(APIC_VERBOSE, KERN_DEBUG
1062 "disabling PIRQ%d\n", pin-16);
1064 irq = pirq_entries[pin-16];
1065 apic_printk(APIC_VERBOSE, KERN_DEBUG
1066 "using PIRQ%d -> IRQ %d\n",
1076 void lock_vector_lock(void)
1078 /* Used to the online set of cpus does not change
1079 * during assign_irq_vector.
1081 spin_lock(&vector_lock);
1084 void unlock_vector_lock(void)
1086 spin_unlock(&vector_lock);
1089 static int __assign_irq_vector(int irq, cpumask_t mask)
1092 * NOTE! The local APIC isn't very good at handling
1093 * multiple interrupts at the same interrupt level.
1094 * As the interrupt level is determined by taking the
1095 * vector number and shifting that right by 4, we
1096 * want to spread these out a bit so that they don't
1097 * all fall in the same interrupt level.
1099 * Also, we've got to be careful not to trash gate
1100 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1102 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1103 unsigned int old_vector;
1105 struct irq_cfg *cfg;
1109 /* Only try and allocate irqs on cpus that are present */
1110 cpus_and(mask, mask, cpu_online_map);
1112 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1115 old_vector = cfg->vector;
1118 cpus_and(tmp, cfg->domain, mask);
1119 if (!cpus_empty(tmp))
1123 for_each_cpu_mask_nr(cpu, mask) {
1124 cpumask_t domain, new_mask;
1128 domain = vector_allocation_domain(cpu);
1129 cpus_and(new_mask, domain, cpu_online_map);
1131 vector = current_vector;
1132 offset = current_offset;
1135 if (vector >= first_system_vector) {
1136 /* If we run out of vectors on large boxen, must share them. */
1137 offset = (offset + 1) % 8;
1138 vector = FIRST_DEVICE_VECTOR + offset;
1140 if (unlikely(current_vector == vector))
1142 #ifdef CONFIG_X86_64
1143 if (vector == IA32_SYSCALL_VECTOR)
1146 if (vector == SYSCALL_VECTOR)
1149 for_each_cpu_mask_nr(new_cpu, new_mask)
1150 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1153 current_vector = vector;
1154 current_offset = offset;
1156 cfg->move_in_progress = 1;
1157 cfg->old_domain = cfg->domain;
1159 for_each_cpu_mask_nr(new_cpu, new_mask)
1160 per_cpu(vector_irq, new_cpu)[vector] = irq;
1161 cfg->vector = vector;
1162 cfg->domain = domain;
1168 static int assign_irq_vector(int irq, cpumask_t mask)
1171 unsigned long flags;
1173 spin_lock_irqsave(&vector_lock, flags);
1174 err = __assign_irq_vector(irq, mask);
1175 spin_unlock_irqrestore(&vector_lock, flags);
1179 static void __clear_irq_vector(int irq)
1181 struct irq_cfg *cfg;
1186 BUG_ON(!cfg->vector);
1188 vector = cfg->vector;
1189 cpus_and(mask, cfg->domain, cpu_online_map);
1190 for_each_cpu_mask_nr(cpu, mask)
1191 per_cpu(vector_irq, cpu)[vector] = -1;
1194 cpus_clear(cfg->domain);
1197 void __setup_vector_irq(int cpu)
1199 /* Initialize vector_irq on a new cpu */
1200 /* This function must be called with vector_lock held */
1202 struct irq_cfg *cfg;
1204 /* Mark the inuse vectors */
1205 for_each_irq_cfg(irq, cfg) {
1206 if (!cpu_isset(cpu, cfg->domain))
1208 vector = cfg->vector;
1209 per_cpu(vector_irq, cpu)[vector] = irq;
1211 /* Mark the free vectors */
1212 for (vector = 0; vector < NR_VECTORS; ++vector) {
1213 irq = per_cpu(vector_irq, cpu)[vector];
1218 if (!cpu_isset(cpu, cfg->domain))
1219 per_cpu(vector_irq, cpu)[vector] = -1;
1223 static struct irq_chip ioapic_chip;
1224 #ifdef CONFIG_INTR_REMAP
1225 static struct irq_chip ir_ioapic_chip;
1228 #define IOAPIC_AUTO -1
1229 #define IOAPIC_EDGE 0
1230 #define IOAPIC_LEVEL 1
1232 #ifdef CONFIG_X86_32
1233 static inline int IO_APIC_irq_trigger(int irq)
1237 for (apic = 0; apic < nr_ioapics; apic++) {
1238 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1239 idx = find_irq_entry(apic, pin, mp_INT);
1240 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1241 return irq_trigger(idx);
1245 * nonexistent IRQs are edge default
1250 static inline int IO_APIC_irq_trigger(int irq)
1256 static void ioapic_register_intr(int irq, unsigned long trigger)
1258 struct irq_desc *desc;
1260 desc = irq_to_desc(irq);
1262 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1263 trigger == IOAPIC_LEVEL)
1264 desc->status |= IRQ_LEVEL;
1266 desc->status &= ~IRQ_LEVEL;
1268 #ifdef CONFIG_INTR_REMAP
1269 if (irq_remapped(irq)) {
1270 desc->status |= IRQ_MOVE_PCNTXT;
1272 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1276 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1277 handle_edge_irq, "edge");
1281 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1282 trigger == IOAPIC_LEVEL)
1283 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1287 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1288 handle_edge_irq, "edge");
1291 static int setup_ioapic_entry(int apic, int irq,
1292 struct IO_APIC_route_entry *entry,
1293 unsigned int destination, int trigger,
1294 int polarity, int vector)
1297 * add it to the IO-APIC irq-routing table:
1299 memset(entry,0,sizeof(*entry));
1301 #ifdef CONFIG_INTR_REMAP
1302 if (intr_remapping_enabled) {
1303 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1305 struct IR_IO_APIC_route_entry *ir_entry =
1306 (struct IR_IO_APIC_route_entry *) entry;
1310 panic("No mapping iommu for ioapic %d\n", apic);
1312 index = alloc_irte(iommu, irq, 1);
1314 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1316 memset(&irte, 0, sizeof(irte));
1319 irte.dst_mode = INT_DEST_MODE;
1320 irte.trigger_mode = trigger;
1321 irte.dlvry_mode = INT_DELIVERY_MODE;
1322 irte.vector = vector;
1323 irte.dest_id = IRTE_DEST(destination);
1325 modify_irte(irq, &irte);
1327 ir_entry->index2 = (index >> 15) & 0x1;
1329 ir_entry->format = 1;
1330 ir_entry->index = (index & 0x7fff);
1334 entry->delivery_mode = INT_DELIVERY_MODE;
1335 entry->dest_mode = INT_DEST_MODE;
1336 entry->dest = destination;
1339 entry->mask = 0; /* enable IRQ */
1340 entry->trigger = trigger;
1341 entry->polarity = polarity;
1342 entry->vector = vector;
1344 /* Mask level triggered irqs.
1345 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1352 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1353 int trigger, int polarity)
1355 struct irq_cfg *cfg;
1356 struct IO_APIC_route_entry entry;
1359 if (!IO_APIC_IRQ(irq))
1365 if (assign_irq_vector(irq, mask))
1368 cpus_and(mask, cfg->domain, mask);
1370 apic_printk(APIC_VERBOSE,KERN_DEBUG
1371 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1372 "IRQ %d Mode:%i Active:%i)\n",
1373 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1374 irq, trigger, polarity);
1377 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1378 cpu_mask_to_apicid(mask), trigger, polarity,
1380 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1381 mp_ioapics[apic].mp_apicid, pin);
1382 __clear_irq_vector(irq);
1386 ioapic_register_intr(irq, trigger);
1388 disable_8259A_irq(irq);
1390 ioapic_write_entry(apic, pin, entry);
1393 static void __init setup_IO_APIC_irqs(void)
1395 int apic, pin, idx, irq;
1398 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1400 for (apic = 0; apic < nr_ioapics; apic++) {
1401 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1403 idx = find_irq_entry(apic, pin, mp_INT);
1407 apic_printk(APIC_VERBOSE,
1408 KERN_DEBUG " %d-%d",
1409 mp_ioapics[apic].mp_apicid,
1412 apic_printk(APIC_VERBOSE, " %d-%d",
1413 mp_ioapics[apic].mp_apicid,
1418 apic_printk(APIC_VERBOSE,
1419 " (apicid-pin) not connected\n");
1423 irq = pin_2_irq(idx, apic, pin);
1424 #ifdef CONFIG_X86_32
1425 if (multi_timer_check(apic, irq))
1428 add_pin_to_irq(irq, apic, pin);
1430 setup_IO_APIC_irq(apic, pin, irq,
1431 irq_trigger(idx), irq_polarity(idx));
1436 apic_printk(APIC_VERBOSE,
1437 " (apicid-pin) not connected\n");
1441 * Set up the timer pin, possibly with the 8259A-master behind.
1443 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1446 struct IO_APIC_route_entry entry;
1448 #ifdef CONFIG_INTR_REMAP
1449 if (intr_remapping_enabled)
1453 memset(&entry, 0, sizeof(entry));
1456 * We use logical delivery to get the timer IRQ
1459 entry.dest_mode = INT_DEST_MODE;
1460 entry.mask = 1; /* mask IRQ now */
1461 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1462 entry.delivery_mode = INT_DELIVERY_MODE;
1465 entry.vector = vector;
1468 * The timer IRQ doesn't have to know that behind the
1469 * scene we may have a 8259A-master in AEOI mode ...
1471 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1474 * Add it to the IO-APIC irq-routing table:
1476 ioapic_write_entry(apic, pin, entry);
1480 __apicdebuginit(void) print_IO_APIC(void)
1483 union IO_APIC_reg_00 reg_00;
1484 union IO_APIC_reg_01 reg_01;
1485 union IO_APIC_reg_02 reg_02;
1486 union IO_APIC_reg_03 reg_03;
1487 unsigned long flags;
1488 struct irq_cfg *cfg;
1491 if (apic_verbosity == APIC_QUIET)
1494 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1495 for (i = 0; i < nr_ioapics; i++)
1496 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1497 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1500 * We are a bit conservative about what we expect. We have to
1501 * know about every hardware change ASAP.
1503 printk(KERN_INFO "testing the IO APIC.......................\n");
1505 for (apic = 0; apic < nr_ioapics; apic++) {
1507 spin_lock_irqsave(&ioapic_lock, flags);
1508 reg_00.raw = io_apic_read(apic, 0);
1509 reg_01.raw = io_apic_read(apic, 1);
1510 if (reg_01.bits.version >= 0x10)
1511 reg_02.raw = io_apic_read(apic, 2);
1512 if (reg_01.bits.version >= 0x20)
1513 reg_03.raw = io_apic_read(apic, 3);
1514 spin_unlock_irqrestore(&ioapic_lock, flags);
1517 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1518 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1519 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1520 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1521 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1523 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1524 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1526 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1527 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1530 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1531 * but the value of reg_02 is read as the previous read register
1532 * value, so ignore it if reg_02 == reg_01.
1534 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1535 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1536 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1540 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1541 * or reg_03, but the value of reg_0[23] is read as the previous read
1542 * register value, so ignore it if reg_03 == reg_0[12].
1544 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1545 reg_03.raw != reg_01.raw) {
1546 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1547 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1550 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1552 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1553 " Stat Dmod Deli Vect: \n");
1555 for (i = 0; i <= reg_01.bits.entries; i++) {
1556 struct IO_APIC_route_entry entry;
1558 entry = ioapic_read_entry(apic, i);
1560 printk(KERN_DEBUG " %02x %03X ",
1565 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1570 entry.delivery_status,
1572 entry.delivery_mode,
1577 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1578 for_each_irq_cfg(irq, cfg) {
1579 struct irq_pin_list *entry = cfg->irq_2_pin;
1582 printk(KERN_DEBUG "IRQ%d ", irq);
1584 printk("-> %d:%d", entry->apic, entry->pin);
1587 entry = entry->next;
1592 printk(KERN_INFO ".................................... done.\n");
1597 __apicdebuginit(void) print_APIC_bitfield(int base)
1602 if (apic_verbosity == APIC_QUIET)
1605 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1606 for (i = 0; i < 8; i++) {
1607 v = apic_read(base + i*0x10);
1608 for (j = 0; j < 32; j++) {
1618 __apicdebuginit(void) print_local_APIC(void *dummy)
1620 unsigned int v, ver, maxlvt;
1623 if (apic_verbosity == APIC_QUIET)
1626 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1627 smp_processor_id(), hard_smp_processor_id());
1628 v = apic_read(APIC_ID);
1629 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1630 v = apic_read(APIC_LVR);
1631 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1632 ver = GET_APIC_VERSION(v);
1633 maxlvt = lapic_get_maxlvt();
1635 v = apic_read(APIC_TASKPRI);
1636 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1638 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1639 if (!APIC_XAPIC(ver)) {
1640 v = apic_read(APIC_ARBPRI);
1641 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1642 v & APIC_ARBPRI_MASK);
1644 v = apic_read(APIC_PROCPRI);
1645 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1649 * Remote read supported only in the 82489DX and local APIC for
1650 * Pentium processors.
1652 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1653 v = apic_read(APIC_RRR);
1654 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1657 v = apic_read(APIC_LDR);
1658 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1659 if (!x2apic_enabled()) {
1660 v = apic_read(APIC_DFR);
1661 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1663 v = apic_read(APIC_SPIV);
1664 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1666 printk(KERN_DEBUG "... APIC ISR field:\n");
1667 print_APIC_bitfield(APIC_ISR);
1668 printk(KERN_DEBUG "... APIC TMR field:\n");
1669 print_APIC_bitfield(APIC_TMR);
1670 printk(KERN_DEBUG "... APIC IRR field:\n");
1671 print_APIC_bitfield(APIC_IRR);
1673 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1674 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1675 apic_write(APIC_ESR, 0);
1677 v = apic_read(APIC_ESR);
1678 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1681 icr = apic_icr_read();
1682 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1683 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1685 v = apic_read(APIC_LVTT);
1686 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1688 if (maxlvt > 3) { /* PC is LVT#4. */
1689 v = apic_read(APIC_LVTPC);
1690 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1692 v = apic_read(APIC_LVT0);
1693 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1694 v = apic_read(APIC_LVT1);
1695 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1697 if (maxlvt > 2) { /* ERR is LVT#3. */
1698 v = apic_read(APIC_LVTERR);
1699 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1702 v = apic_read(APIC_TMICT);
1703 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1704 v = apic_read(APIC_TMCCT);
1705 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1706 v = apic_read(APIC_TDCR);
1707 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1711 __apicdebuginit(void) print_all_local_APICs(void)
1716 for_each_online_cpu(cpu)
1717 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1721 __apicdebuginit(void) print_PIC(void)
1724 unsigned long flags;
1726 if (apic_verbosity == APIC_QUIET)
1729 printk(KERN_DEBUG "\nprinting PIC contents\n");
1731 spin_lock_irqsave(&i8259A_lock, flags);
1733 v = inb(0xa1) << 8 | inb(0x21);
1734 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1736 v = inb(0xa0) << 8 | inb(0x20);
1737 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1741 v = inb(0xa0) << 8 | inb(0x20);
1745 spin_unlock_irqrestore(&i8259A_lock, flags);
1747 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1749 v = inb(0x4d1) << 8 | inb(0x4d0);
1750 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1753 __apicdebuginit(int) print_all_ICs(void)
1756 print_all_local_APICs();
1762 fs_initcall(print_all_ICs);
1765 /* Where if anywhere is the i8259 connect in external int mode */
1766 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1768 void __init enable_IO_APIC(void)
1770 union IO_APIC_reg_01 reg_01;
1771 int i8259_apic, i8259_pin;
1773 unsigned long flags;
1775 #ifdef CONFIG_X86_32
1778 for (i = 0; i < MAX_PIRQS; i++)
1779 pirq_entries[i] = -1;
1783 * The number of IO-APIC IRQ registers (== #pins):
1785 for (apic = 0; apic < nr_ioapics; apic++) {
1786 spin_lock_irqsave(&ioapic_lock, flags);
1787 reg_01.raw = io_apic_read(apic, 1);
1788 spin_unlock_irqrestore(&ioapic_lock, flags);
1789 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1791 for(apic = 0; apic < nr_ioapics; apic++) {
1793 /* See if any of the pins is in ExtINT mode */
1794 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1795 struct IO_APIC_route_entry entry;
1796 entry = ioapic_read_entry(apic, pin);
1798 /* If the interrupt line is enabled and in ExtInt mode
1799 * I have found the pin where the i8259 is connected.
1801 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1802 ioapic_i8259.apic = apic;
1803 ioapic_i8259.pin = pin;
1809 /* Look to see what if the MP table has reported the ExtINT */
1810 /* If we could not find the appropriate pin by looking at the ioapic
1811 * the i8259 probably is not connected the ioapic but give the
1812 * mptable a chance anyway.
1814 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1815 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1816 /* Trust the MP table if nothing is setup in the hardware */
1817 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1818 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1819 ioapic_i8259.pin = i8259_pin;
1820 ioapic_i8259.apic = i8259_apic;
1822 /* Complain if the MP table and the hardware disagree */
1823 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1824 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1826 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1830 * Do not trust the IO-APIC being empty at bootup
1836 * Not an __init, needed by the reboot code
1838 void disable_IO_APIC(void)
1841 * Clear the IO-APIC before rebooting:
1846 * If the i8259 is routed through an IOAPIC
1847 * Put that IOAPIC in virtual wire mode
1848 * so legacy interrupts can be delivered.
1850 if (ioapic_i8259.pin != -1) {
1851 struct IO_APIC_route_entry entry;
1853 memset(&entry, 0, sizeof(entry));
1854 entry.mask = 0; /* Enabled */
1855 entry.trigger = 0; /* Edge */
1857 entry.polarity = 0; /* High */
1858 entry.delivery_status = 0;
1859 entry.dest_mode = 0; /* Physical */
1860 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1862 entry.dest = read_apic_id();
1865 * Add it to the IO-APIC irq-routing table:
1867 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1870 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1873 #ifdef CONFIG_X86_32
1875 * function to set the IO-APIC physical IDs based on the
1876 * values stored in the MPC table.
1878 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1881 static void __init setup_ioapic_ids_from_mpc(void)
1883 union IO_APIC_reg_00 reg_00;
1884 physid_mask_t phys_id_present_map;
1887 unsigned char old_id;
1888 unsigned long flags;
1890 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1894 * Don't check I/O APIC IDs for xAPIC systems. They have
1895 * no meaning without the serial APIC bus.
1897 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1898 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1901 * This is broken; anything with a real cpu count has to
1902 * circumvent this idiocy regardless.
1904 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1907 * Set the IOAPIC ID to the value stored in the MPC table.
1909 for (apic = 0; apic < nr_ioapics; apic++) {
1911 /* Read the register 0 value */
1912 spin_lock_irqsave(&ioapic_lock, flags);
1913 reg_00.raw = io_apic_read(apic, 0);
1914 spin_unlock_irqrestore(&ioapic_lock, flags);
1916 old_id = mp_ioapics[apic].mp_apicid;
1918 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1919 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1920 apic, mp_ioapics[apic].mp_apicid);
1921 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1923 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1927 * Sanity check, is the ID really free? Every APIC in a
1928 * system must have a unique ID or we get lots of nice
1929 * 'stuck on smp_invalidate_needed IPI wait' messages.
1931 if (check_apicid_used(phys_id_present_map,
1932 mp_ioapics[apic].mp_apicid)) {
1933 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1934 apic, mp_ioapics[apic].mp_apicid);
1935 for (i = 0; i < get_physical_broadcast(); i++)
1936 if (!physid_isset(i, phys_id_present_map))
1938 if (i >= get_physical_broadcast())
1939 panic("Max APIC ID exceeded!\n");
1940 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1942 physid_set(i, phys_id_present_map);
1943 mp_ioapics[apic].mp_apicid = i;
1946 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1947 apic_printk(APIC_VERBOSE, "Setting %d in the "
1948 "phys_id_present_map\n",
1949 mp_ioapics[apic].mp_apicid);
1950 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1955 * We need to adjust the IRQ routing table
1956 * if the ID changed.
1958 if (old_id != mp_ioapics[apic].mp_apicid)
1959 for (i = 0; i < mp_irq_entries; i++)
1960 if (mp_irqs[i].mp_dstapic == old_id)
1961 mp_irqs[i].mp_dstapic
1962 = mp_ioapics[apic].mp_apicid;
1965 * Read the right value from the MPC table and
1966 * write it into the ID register.
1968 apic_printk(APIC_VERBOSE, KERN_INFO
1969 "...changing IO-APIC physical APIC ID to %d ...",
1970 mp_ioapics[apic].mp_apicid);
1972 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1973 spin_lock_irqsave(&ioapic_lock, flags);
1974 io_apic_write(apic, 0, reg_00.raw);
1975 spin_unlock_irqrestore(&ioapic_lock, flags);
1980 spin_lock_irqsave(&ioapic_lock, flags);
1981 reg_00.raw = io_apic_read(apic, 0);
1982 spin_unlock_irqrestore(&ioapic_lock, flags);
1983 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1984 printk("could not set ID!\n");
1986 apic_printk(APIC_VERBOSE, " ok.\n");
1991 int no_timer_check __initdata;
1993 static int __init notimercheck(char *s)
1998 __setup("no_timer_check", notimercheck);
2001 * There is a nasty bug in some older SMP boards, their mptable lies
2002 * about the timer IRQ. We do the following to work around the situation:
2004 * - timer IRQ defaults to IO-APIC IRQ
2005 * - if this function detects that timer IRQs are defunct, then we fall
2006 * back to ISA timer IRQs
2008 static int __init timer_irq_works(void)
2010 unsigned long t1 = jiffies;
2011 unsigned long flags;
2016 local_save_flags(flags);
2018 /* Let ten ticks pass... */
2019 mdelay((10 * 1000) / HZ);
2020 local_irq_restore(flags);
2023 * Expect a few ticks at least, to be sure some possible
2024 * glue logic does not lock up after one or two first
2025 * ticks in a non-ExtINT mode. Also the local APIC
2026 * might have cached one ExtINT interrupt. Finally, at
2027 * least one tick may be lost due to delays.
2031 if (time_after(jiffies, t1 + 4))
2037 * In the SMP+IOAPIC case it might happen that there are an unspecified
2038 * number of pending IRQ events unhandled. These cases are very rare,
2039 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2040 * better to do it this way as thus we do not have to be aware of
2041 * 'pending' interrupts in the IRQ path, except at this point.
2044 * Edge triggered needs to resend any interrupt
2045 * that was delayed but this is now handled in the device
2050 * Starting up a edge-triggered IO-APIC interrupt is
2051 * nasty - we need to make sure that we get the edge.
2052 * If it is already asserted for some reason, we need
2053 * return 1 to indicate that is was pending.
2055 * This is not complete - we should be able to fake
2056 * an edge even if it isn't on the 8259A...
2059 static unsigned int startup_ioapic_irq(unsigned int irq)
2061 int was_pending = 0;
2062 unsigned long flags;
2064 spin_lock_irqsave(&ioapic_lock, flags);
2066 disable_8259A_irq(irq);
2067 if (i8259A_irq_pending(irq))
2070 __unmask_IO_APIC_irq(irq);
2071 spin_unlock_irqrestore(&ioapic_lock, flags);
2076 #ifdef CONFIG_X86_64
2077 static int ioapic_retrigger_irq(unsigned int irq)
2080 struct irq_cfg *cfg = irq_cfg(irq);
2081 unsigned long flags;
2083 spin_lock_irqsave(&vector_lock, flags);
2084 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2085 spin_unlock_irqrestore(&vector_lock, flags);
2090 static int ioapic_retrigger_irq(unsigned int irq)
2092 send_IPI_self(irq_cfg(irq)->vector);
2099 * Level and edge triggered IO-APIC interrupts need different handling,
2100 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2101 * handled with the level-triggered descriptor, but that one has slightly
2102 * more overhead. Level-triggered interrupts cannot be handled with the
2103 * edge-triggered handler, without risking IRQ storms and other ugly
2109 #ifdef CONFIG_INTR_REMAP
2110 static void ir_irq_migration(struct work_struct *work);
2112 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2115 * Migrate the IO-APIC irq in the presence of intr-remapping.
2117 * For edge triggered, irq migration is a simple atomic update(of vector
2118 * and cpu destination) of IRTE and flush the hardware cache.
2120 * For level triggered, we need to modify the io-apic RTE aswell with the update
2121 * vector information, along with modifying IRTE with vector and destination.
2122 * So irq migration for level triggered is little bit more complex compared to
2123 * edge triggered migration. But the good news is, we use the same algorithm
2124 * for level triggered migration as we have today, only difference being,
2125 * we now initiate the irq migration from process context instead of the
2126 * interrupt context.
2128 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2129 * suppression) to the IO-APIC, level triggered irq migration will also be
2130 * as simple as edge triggered migration and we can do the irq migration
2131 * with a simple atomic update to IO-APIC RTE.
2133 static void migrate_ioapic_irq(int irq, cpumask_t mask)
2135 struct irq_cfg *cfg;
2136 struct irq_desc *desc;
2137 cpumask_t tmp, cleanup_mask;
2139 int modify_ioapic_rte;
2141 unsigned long flags;
2143 cpus_and(tmp, mask, cpu_online_map);
2144 if (cpus_empty(tmp))
2147 if (get_irte(irq, &irte))
2150 if (assign_irq_vector(irq, mask))
2154 cpus_and(tmp, cfg->domain, mask);
2155 dest = cpu_mask_to_apicid(tmp);
2157 desc = irq_to_desc(irq);
2158 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2159 if (modify_ioapic_rte) {
2160 spin_lock_irqsave(&ioapic_lock, flags);
2161 __target_IO_APIC_irq(irq, dest, cfg->vector);
2162 spin_unlock_irqrestore(&ioapic_lock, flags);
2165 irte.vector = cfg->vector;
2166 irte.dest_id = IRTE_DEST(dest);
2169 * Modified the IRTE and flushes the Interrupt entry cache.
2171 modify_irte(irq, &irte);
2173 if (cfg->move_in_progress) {
2174 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2175 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2176 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2177 cfg->move_in_progress = 0;
2180 desc->affinity = mask;
2183 static int migrate_irq_remapped_level(int irq)
2186 struct irq_desc *desc = irq_to_desc(irq);
2188 mask_IO_APIC_irq(irq);
2190 if (io_apic_level_ack_pending(irq)) {
2192 * Interrupt in progress. Migrating irq now will change the
2193 * vector information in the IO-APIC RTE and that will confuse
2194 * the EOI broadcast performed by cpu.
2195 * So, delay the irq migration to the next instance.
2197 schedule_delayed_work(&ir_migration_work, 1);
2201 /* everthing is clear. we have right of way */
2202 migrate_ioapic_irq(irq, desc->pending_mask);
2205 desc->status &= ~IRQ_MOVE_PENDING;
2206 cpus_clear(desc->pending_mask);
2209 unmask_IO_APIC_irq(irq);
2213 static void ir_irq_migration(struct work_struct *work)
2216 struct irq_desc *desc;
2218 for_each_irq_desc(irq, desc) {
2219 if (desc->status & IRQ_MOVE_PENDING) {
2220 unsigned long flags;
2222 spin_lock_irqsave(&desc->lock, flags);
2223 if (!desc->chip->set_affinity ||
2224 !(desc->status & IRQ_MOVE_PENDING)) {
2225 desc->status &= ~IRQ_MOVE_PENDING;
2226 spin_unlock_irqrestore(&desc->lock, flags);
2230 desc->chip->set_affinity(irq, desc->pending_mask);
2231 spin_unlock_irqrestore(&desc->lock, flags);
2237 * Migrates the IRQ destination in the process context.
2239 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2241 struct irq_desc *desc = irq_to_desc(irq);
2243 if (desc->status & IRQ_LEVEL) {
2244 desc->status |= IRQ_MOVE_PENDING;
2245 desc->pending_mask = mask;
2246 migrate_irq_remapped_level(irq);
2250 migrate_ioapic_irq(irq, mask);
2254 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2256 unsigned vector, me;
2258 #ifdef CONFIG_X86_64
2263 me = smp_processor_id();
2264 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2266 struct irq_desc *desc;
2267 struct irq_cfg *cfg;
2268 irq = __get_cpu_var(vector_irq)[vector];
2270 desc = irq_to_desc(irq);
2275 spin_lock(&desc->lock);
2276 if (!cfg->move_cleanup_count)
2279 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2282 __get_cpu_var(vector_irq)[vector] = -1;
2283 cfg->move_cleanup_count--;
2285 spin_unlock(&desc->lock);
2291 static void irq_complete_move(unsigned int irq)
2293 struct irq_cfg *cfg = irq_cfg(irq);
2294 unsigned vector, me;
2296 if (likely(!cfg->move_in_progress))
2299 vector = ~get_irq_regs()->orig_ax;
2300 me = smp_processor_id();
2301 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2302 cpumask_t cleanup_mask;
2304 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2305 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2306 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2307 cfg->move_in_progress = 0;
2311 static inline void irq_complete_move(unsigned int irq) {}
2313 #ifdef CONFIG_INTR_REMAP
2314 static void ack_x2apic_level(unsigned int irq)
2319 static void ack_x2apic_edge(unsigned int irq)
2325 static void ack_apic_edge(unsigned int irq)
2327 irq_complete_move(irq);
2328 move_native_irq(irq);
2332 #ifdef CONFIG_X86_32
2333 atomic_t irq_mis_count;
2336 static void ack_apic_level(unsigned int irq)
2338 #ifdef CONFIG_X86_32
2342 int do_unmask_irq = 0;
2344 irq_complete_move(irq);
2345 #ifdef CONFIG_GENERIC_PENDING_IRQ
2346 /* If we are moving the irq we need to mask it */
2347 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2349 mask_IO_APIC_irq(irq);
2353 #ifdef CONFIG_X86_32
2355 * It appears there is an erratum which affects at least version 0x11
2356 * of I/O APIC (that's the 82093AA and cores integrated into various
2357 * chipsets). Under certain conditions a level-triggered interrupt is
2358 * erroneously delivered as edge-triggered one but the respective IRR
2359 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2360 * message but it will never arrive and further interrupts are blocked
2361 * from the source. The exact reason is so far unknown, but the
2362 * phenomenon was observed when two consecutive interrupt requests
2363 * from a given source get delivered to the same CPU and the source is
2364 * temporarily disabled in between.
2366 * A workaround is to simulate an EOI message manually. We achieve it
2367 * by setting the trigger mode to edge and then to level when the edge
2368 * trigger mode gets detected in the TMR of a local APIC for a
2369 * level-triggered interrupt. We mask the source for the time of the
2370 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2371 * The idea is from Manfred Spraul. --macro
2373 i = irq_cfg(irq)->vector;
2375 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2379 * We must acknowledge the irq before we move it or the acknowledge will
2380 * not propagate properly.
2384 /* Now we can move and renable the irq */
2385 if (unlikely(do_unmask_irq)) {
2386 /* Only migrate the irq if the ack has been received.
2388 * On rare occasions the broadcast level triggered ack gets
2389 * delayed going to ioapics, and if we reprogram the
2390 * vector while Remote IRR is still set the irq will never
2393 * To prevent this scenario we read the Remote IRR bit
2394 * of the ioapic. This has two effects.
2395 * - On any sane system the read of the ioapic will
2396 * flush writes (and acks) going to the ioapic from
2398 * - We get to see if the ACK has actually been delivered.
2400 * Based on failed experiments of reprogramming the
2401 * ioapic entry from outside of irq context starting
2402 * with masking the ioapic entry and then polling until
2403 * Remote IRR was clear before reprogramming the
2404 * ioapic I don't trust the Remote IRR bit to be
2405 * completey accurate.
2407 * However there appears to be no other way to plug
2408 * this race, so if the Remote IRR bit is not
2409 * accurate and is causing problems then it is a hardware bug
2410 * and you can go talk to the chipset vendor about it.
2412 if (!io_apic_level_ack_pending(irq))
2413 move_masked_irq(irq);
2414 unmask_IO_APIC_irq(irq);
2417 #ifdef CONFIG_X86_32
2418 if (!(v & (1 << (i & 0x1f)))) {
2419 atomic_inc(&irq_mis_count);
2420 spin_lock(&ioapic_lock);
2421 __mask_and_edge_IO_APIC_irq(irq);
2422 __unmask_and_level_IO_APIC_irq(irq);
2423 spin_unlock(&ioapic_lock);
2428 static struct irq_chip ioapic_chip __read_mostly = {
2430 .startup = startup_ioapic_irq,
2431 .mask = mask_IO_APIC_irq,
2432 .unmask = unmask_IO_APIC_irq,
2433 .ack = ack_apic_edge,
2434 .eoi = ack_apic_level,
2436 .set_affinity = set_ioapic_affinity_irq,
2438 .retrigger = ioapic_retrigger_irq,
2441 #ifdef CONFIG_INTR_REMAP
2442 static struct irq_chip ir_ioapic_chip __read_mostly = {
2443 .name = "IR-IO-APIC",
2444 .startup = startup_ioapic_irq,
2445 .mask = mask_IO_APIC_irq,
2446 .unmask = unmask_IO_APIC_irq,
2447 .ack = ack_x2apic_edge,
2448 .eoi = ack_x2apic_level,
2450 .set_affinity = set_ir_ioapic_affinity_irq,
2452 .retrigger = ioapic_retrigger_irq,
2456 static inline void init_IO_APIC_traps(void)
2459 struct irq_desc *desc;
2460 struct irq_cfg *cfg;
2463 * NOTE! The local APIC isn't very good at handling
2464 * multiple interrupts at the same interrupt level.
2465 * As the interrupt level is determined by taking the
2466 * vector number and shifting that right by 4, we
2467 * want to spread these out a bit so that they don't
2468 * all fall in the same interrupt level.
2470 * Also, we've got to be careful not to trash gate
2471 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2473 for_each_irq_cfg(irq, cfg) {
2474 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2476 * Hmm.. We don't have an entry for this,
2477 * so default to an old-fashioned 8259
2478 * interrupt if we can..
2481 make_8259A_irq(irq);
2483 desc = irq_to_desc(irq);
2484 /* Strange. Oh, well.. */
2485 desc->chip = &no_irq_chip;
2492 * The local APIC irq-chip implementation:
2495 static void mask_lapic_irq(unsigned int irq)
2499 v = apic_read(APIC_LVT0);
2500 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2503 static void unmask_lapic_irq(unsigned int irq)
2507 v = apic_read(APIC_LVT0);
2508 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2511 static void ack_lapic_irq (unsigned int irq)
2516 static struct irq_chip lapic_chip __read_mostly = {
2517 .name = "local-APIC",
2518 .mask = mask_lapic_irq,
2519 .unmask = unmask_lapic_irq,
2520 .ack = ack_lapic_irq,
2523 static void lapic_register_intr(int irq)
2525 struct irq_desc *desc;
2527 desc = irq_to_desc(irq);
2528 desc->status &= ~IRQ_LEVEL;
2529 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2533 static void __init setup_nmi(void)
2536 * Dirty trick to enable the NMI watchdog ...
2537 * We put the 8259A master into AEOI mode and
2538 * unmask on all local APICs LVT0 as NMI.
2540 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2541 * is from Maciej W. Rozycki - so we do not have to EOI from
2542 * the NMI handler or the timer interrupt.
2544 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2546 enable_NMI_through_LVT0();
2548 apic_printk(APIC_VERBOSE, " done.\n");
2552 * This looks a bit hackish but it's about the only one way of sending
2553 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2554 * not support the ExtINT mode, unfortunately. We need to send these
2555 * cycles as some i82489DX-based boards have glue logic that keeps the
2556 * 8259A interrupt line asserted until INTA. --macro
2558 static inline void __init unlock_ExtINT_logic(void)
2561 struct IO_APIC_route_entry entry0, entry1;
2562 unsigned char save_control, save_freq_select;
2564 pin = find_isa_irq_pin(8, mp_INT);
2569 apic = find_isa_irq_apic(8, mp_INT);
2575 entry0 = ioapic_read_entry(apic, pin);
2576 clear_IO_APIC_pin(apic, pin);
2578 memset(&entry1, 0, sizeof(entry1));
2580 entry1.dest_mode = 0; /* physical delivery */
2581 entry1.mask = 0; /* unmask IRQ now */
2582 entry1.dest = hard_smp_processor_id();
2583 entry1.delivery_mode = dest_ExtINT;
2584 entry1.polarity = entry0.polarity;
2588 ioapic_write_entry(apic, pin, entry1);
2590 save_control = CMOS_READ(RTC_CONTROL);
2591 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2592 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2594 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2599 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2603 CMOS_WRITE(save_control, RTC_CONTROL);
2604 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2605 clear_IO_APIC_pin(apic, pin);
2607 ioapic_write_entry(apic, pin, entry0);
2610 static int disable_timer_pin_1 __initdata;
2611 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2612 static int __init disable_timer_pin_setup(char *arg)
2614 disable_timer_pin_1 = 1;
2617 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2619 int timer_through_8259 __initdata;
2622 * This code may look a bit paranoid, but it's supposed to cooperate with
2623 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2624 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2625 * fanatically on his truly buggy board.
2627 * FIXME: really need to revamp this for all platforms.
2629 static inline void __init check_timer(void)
2631 struct irq_cfg *cfg = irq_cfg(0);
2632 int apic1, pin1, apic2, pin2;
2633 unsigned long flags;
2637 local_irq_save(flags);
2639 ver = apic_read(APIC_LVR);
2640 ver = GET_APIC_VERSION(ver);
2643 * get/set the timer IRQ vector:
2645 disable_8259A_irq(0);
2646 assign_irq_vector(0, TARGET_CPUS);
2649 * As IRQ0 is to be enabled in the 8259A, the virtual
2650 * wire has to be disabled in the local APIC. Also
2651 * timer interrupts need to be acknowledged manually in
2652 * the 8259A for the i82489DX when using the NMI
2653 * watchdog as that APIC treats NMIs as level-triggered.
2654 * The AEOI mode will finish them in the 8259A
2657 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2659 #ifdef CONFIG_X86_32
2660 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2663 pin1 = find_isa_irq_pin(0, mp_INT);
2664 apic1 = find_isa_irq_apic(0, mp_INT);
2665 pin2 = ioapic_i8259.pin;
2666 apic2 = ioapic_i8259.apic;
2668 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2669 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2670 cfg->vector, apic1, pin1, apic2, pin2);
2673 * Some BIOS writers are clueless and report the ExtINTA
2674 * I/O APIC input from the cascaded 8259A as the timer
2675 * interrupt input. So just in case, if only one pin
2676 * was found above, try it both directly and through the
2680 #ifdef CONFIG_INTR_REMAP
2681 if (intr_remapping_enabled)
2682 panic("BIOS bug: timer not connected to IO-APIC");
2687 } else if (pin2 == -1) {
2694 * Ok, does IRQ0 through the IOAPIC work?
2697 add_pin_to_irq(0, apic1, pin1);
2698 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2700 unmask_IO_APIC_irq(0);
2701 if (timer_irq_works()) {
2702 if (nmi_watchdog == NMI_IO_APIC) {
2704 enable_8259A_irq(0);
2706 if (disable_timer_pin_1 > 0)
2707 clear_IO_APIC_pin(0, pin1);
2710 #ifdef CONFIG_INTR_REMAP
2711 if (intr_remapping_enabled)
2712 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2714 clear_IO_APIC_pin(apic1, pin1);
2716 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2717 "8254 timer not connected to IO-APIC\n");
2719 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2720 "(IRQ0) through the 8259A ...\n");
2721 apic_printk(APIC_QUIET, KERN_INFO
2722 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2724 * legacy devices should be connected to IO APIC #0
2726 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2727 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2728 unmask_IO_APIC_irq(0);
2729 enable_8259A_irq(0);
2730 if (timer_irq_works()) {
2731 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2732 timer_through_8259 = 1;
2733 if (nmi_watchdog == NMI_IO_APIC) {
2734 disable_8259A_irq(0);
2736 enable_8259A_irq(0);
2741 * Cleanup, just in case ...
2743 disable_8259A_irq(0);
2744 clear_IO_APIC_pin(apic2, pin2);
2745 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2748 if (nmi_watchdog == NMI_IO_APIC) {
2749 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2750 "through the IO-APIC - disabling NMI Watchdog!\n");
2751 nmi_watchdog = NMI_NONE;
2753 #ifdef CONFIG_X86_32
2757 apic_printk(APIC_QUIET, KERN_INFO
2758 "...trying to set up timer as Virtual Wire IRQ...\n");
2760 lapic_register_intr(0);
2761 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2762 enable_8259A_irq(0);
2764 if (timer_irq_works()) {
2765 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2768 disable_8259A_irq(0);
2769 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2770 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2772 apic_printk(APIC_QUIET, KERN_INFO
2773 "...trying to set up timer as ExtINT IRQ...\n");
2777 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2779 unlock_ExtINT_logic();
2781 if (timer_irq_works()) {
2782 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2785 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2786 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2787 "report. Then try booting with the 'noapic' option.\n");
2789 local_irq_restore(flags);
2793 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2794 * to devices. However there may be an I/O APIC pin available for
2795 * this interrupt regardless. The pin may be left unconnected, but
2796 * typically it will be reused as an ExtINT cascade interrupt for
2797 * the master 8259A. In the MPS case such a pin will normally be
2798 * reported as an ExtINT interrupt in the MP table. With ACPI
2799 * there is no provision for ExtINT interrupts, and in the absence
2800 * of an override it would be treated as an ordinary ISA I/O APIC
2801 * interrupt, that is edge-triggered and unmasked by default. We
2802 * used to do this, but it caused problems on some systems because
2803 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2804 * the same ExtINT cascade interrupt to drive the local APIC of the
2805 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2806 * the I/O APIC in all cases now. No actual device should request
2807 * it anyway. --macro
2809 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2811 void __init setup_IO_APIC(void)
2814 #ifdef CONFIG_X86_32
2818 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2822 io_apic_irqs = ~PIC_IRQS;
2824 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2826 * Set up IO-APIC IRQ routing.
2828 #ifdef CONFIG_X86_32
2830 setup_ioapic_ids_from_mpc();
2833 setup_IO_APIC_irqs();
2834 init_IO_APIC_traps();
2839 * Called after all the initialization is done. If we didnt find any
2840 * APIC bugs then we can allow the modify fast path
2843 static int __init io_apic_bug_finalize(void)
2845 if (sis_apic_bug == -1)
2850 late_initcall(io_apic_bug_finalize);
2852 struct sysfs_ioapic_data {
2853 struct sys_device dev;
2854 struct IO_APIC_route_entry entry[0];
2856 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2858 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2860 struct IO_APIC_route_entry *entry;
2861 struct sysfs_ioapic_data *data;
2864 data = container_of(dev, struct sysfs_ioapic_data, dev);
2865 entry = data->entry;
2866 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2867 *entry = ioapic_read_entry(dev->id, i);
2872 static int ioapic_resume(struct sys_device *dev)
2874 struct IO_APIC_route_entry *entry;
2875 struct sysfs_ioapic_data *data;
2876 unsigned long flags;
2877 union IO_APIC_reg_00 reg_00;
2880 data = container_of(dev, struct sysfs_ioapic_data, dev);
2881 entry = data->entry;
2883 spin_lock_irqsave(&ioapic_lock, flags);
2884 reg_00.raw = io_apic_read(dev->id, 0);
2885 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2886 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2887 io_apic_write(dev->id, 0, reg_00.raw);
2889 spin_unlock_irqrestore(&ioapic_lock, flags);
2890 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2891 ioapic_write_entry(dev->id, i, entry[i]);
2896 static struct sysdev_class ioapic_sysdev_class = {
2898 .suspend = ioapic_suspend,
2899 .resume = ioapic_resume,
2902 static int __init ioapic_init_sysfs(void)
2904 struct sys_device * dev;
2907 error = sysdev_class_register(&ioapic_sysdev_class);
2911 for (i = 0; i < nr_ioapics; i++ ) {
2912 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2913 * sizeof(struct IO_APIC_route_entry);
2914 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2915 if (!mp_ioapic_data[i]) {
2916 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2919 dev = &mp_ioapic_data[i]->dev;
2921 dev->cls = &ioapic_sysdev_class;
2922 error = sysdev_register(dev);
2924 kfree(mp_ioapic_data[i]);
2925 mp_ioapic_data[i] = NULL;
2926 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2934 device_initcall(ioapic_init_sysfs);
2937 * Dynamic irq allocate and deallocation
2939 unsigned int create_irq_nr(unsigned int irq_want)
2941 /* Allocate an unused irq */
2944 unsigned long flags;
2945 struct irq_cfg *cfg_new;
2947 irq_want = nr_irqs - 1;
2950 spin_lock_irqsave(&vector_lock, flags);
2951 for (new = irq_want; new > 0; new--) {
2952 if (platform_legacy_irq(new))
2954 cfg_new = irq_cfg(new);
2955 if (cfg_new && cfg_new->vector != 0)
2957 /* check if need to create one */
2959 cfg_new = irq_cfg_alloc(new);
2960 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2964 spin_unlock_irqrestore(&vector_lock, flags);
2967 dynamic_irq_init(irq);
2972 int create_irq(void)
2976 irq = create_irq_nr(nr_irqs - 1);
2984 void destroy_irq(unsigned int irq)
2986 unsigned long flags;
2988 dynamic_irq_cleanup(irq);
2990 #ifdef CONFIG_INTR_REMAP
2993 spin_lock_irqsave(&vector_lock, flags);
2994 __clear_irq_vector(irq);
2995 spin_unlock_irqrestore(&vector_lock, flags);
2999 * MSI message composition
3001 #ifdef CONFIG_PCI_MSI
3002 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3004 struct irq_cfg *cfg;
3010 err = assign_irq_vector(irq, tmp);
3015 cpus_and(tmp, cfg->domain, tmp);
3016 dest = cpu_mask_to_apicid(tmp);
3018 #ifdef CONFIG_INTR_REMAP
3019 if (irq_remapped(irq)) {
3024 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3025 BUG_ON(ir_index == -1);
3027 memset (&irte, 0, sizeof(irte));
3030 irte.dst_mode = INT_DEST_MODE;
3031 irte.trigger_mode = 0; /* edge */
3032 irte.dlvry_mode = INT_DELIVERY_MODE;
3033 irte.vector = cfg->vector;
3034 irte.dest_id = IRTE_DEST(dest);
3036 modify_irte(irq, &irte);
3038 msg->address_hi = MSI_ADDR_BASE_HI;
3039 msg->data = sub_handle;
3040 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3042 MSI_ADDR_IR_INDEX1(ir_index) |
3043 MSI_ADDR_IR_INDEX2(ir_index);
3047 msg->address_hi = MSI_ADDR_BASE_HI;
3050 ((INT_DEST_MODE == 0) ?
3051 MSI_ADDR_DEST_MODE_PHYSICAL:
3052 MSI_ADDR_DEST_MODE_LOGICAL) |
3053 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3054 MSI_ADDR_REDIRECTION_CPU:
3055 MSI_ADDR_REDIRECTION_LOWPRI) |
3056 MSI_ADDR_DEST_ID(dest);
3059 MSI_DATA_TRIGGER_EDGE |
3060 MSI_DATA_LEVEL_ASSERT |
3061 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3062 MSI_DATA_DELIVERY_FIXED:
3063 MSI_DATA_DELIVERY_LOWPRI) |
3064 MSI_DATA_VECTOR(cfg->vector);
3070 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3072 struct irq_cfg *cfg;
3076 struct irq_desc *desc;
3078 cpus_and(tmp, mask, cpu_online_map);
3079 if (cpus_empty(tmp))
3082 if (assign_irq_vector(irq, mask))
3086 cpus_and(tmp, cfg->domain, mask);
3087 dest = cpu_mask_to_apicid(tmp);
3089 read_msi_msg(irq, &msg);
3091 msg.data &= ~MSI_DATA_VECTOR_MASK;
3092 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3093 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3094 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3096 write_msi_msg(irq, &msg);
3097 desc = irq_to_desc(irq);
3098 desc->affinity = mask;
3101 #ifdef CONFIG_INTR_REMAP
3103 * Migrate the MSI irq to another cpumask. This migration is
3104 * done in the process context using interrupt-remapping hardware.
3106 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3108 struct irq_cfg *cfg;
3110 cpumask_t tmp, cleanup_mask;
3112 struct irq_desc *desc;
3114 cpus_and(tmp, mask, cpu_online_map);
3115 if (cpus_empty(tmp))
3118 if (get_irte(irq, &irte))
3121 if (assign_irq_vector(irq, mask))
3125 cpus_and(tmp, cfg->domain, mask);
3126 dest = cpu_mask_to_apicid(tmp);
3128 irte.vector = cfg->vector;
3129 irte.dest_id = IRTE_DEST(dest);
3132 * atomically update the IRTE with the new destination and vector.
3134 modify_irte(irq, &irte);
3137 * After this point, all the interrupts will start arriving
3138 * at the new destination. So, time to cleanup the previous
3139 * vector allocation.
3141 if (cfg->move_in_progress) {
3142 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3143 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3144 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3145 cfg->move_in_progress = 0;
3148 desc = irq_to_desc(irq);
3149 desc->affinity = mask;
3152 #endif /* CONFIG_SMP */
3155 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3156 * which implement the MSI or MSI-X Capability Structure.
3158 static struct irq_chip msi_chip = {
3160 .unmask = unmask_msi_irq,
3161 .mask = mask_msi_irq,
3162 .ack = ack_apic_edge,
3164 .set_affinity = set_msi_irq_affinity,
3166 .retrigger = ioapic_retrigger_irq,
3169 #ifdef CONFIG_INTR_REMAP
3170 static struct irq_chip msi_ir_chip = {
3171 .name = "IR-PCI-MSI",
3172 .unmask = unmask_msi_irq,
3173 .mask = mask_msi_irq,
3174 .ack = ack_x2apic_edge,
3176 .set_affinity = ir_set_msi_irq_affinity,
3178 .retrigger = ioapic_retrigger_irq,
3182 * Map the PCI dev to the corresponding remapping hardware unit
3183 * and allocate 'nvec' consecutive interrupt-remapping table entries
3186 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3188 struct intel_iommu *iommu;
3191 iommu = map_dev_to_ir(dev);
3194 "Unable to map PCI %s to iommu\n", pci_name(dev));
3198 index = alloc_irte(iommu, irq, nvec);
3201 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3209 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
3214 ret = msi_compose_msg(dev, irq, &msg);
3218 set_irq_msi(irq, desc);
3219 write_msi_msg(irq, &msg);
3221 #ifdef CONFIG_INTR_REMAP
3222 if (irq_remapped(irq)) {
3223 struct irq_desc *desc = irq_to_desc(irq);
3225 * irq migration in process context
3227 desc->status |= IRQ_MOVE_PCNTXT;
3228 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3231 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3233 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3238 static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
3242 irq = dev->bus->number;
3250 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3254 unsigned int irq_want;
3256 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3258 irq = create_irq_nr(irq_want);
3262 #ifdef CONFIG_INTR_REMAP
3263 if (!intr_remapping_enabled)
3266 ret = msi_alloc_irte(dev, irq, 1);
3271 ret = setup_msi_irq(dev, desc, irq);
3278 #ifdef CONFIG_INTR_REMAP
3285 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3288 int ret, sub_handle;
3289 struct msi_desc *desc;
3290 unsigned int irq_want;
3292 #ifdef CONFIG_INTR_REMAP
3293 struct intel_iommu *iommu = 0;
3297 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3299 list_for_each_entry(desc, &dev->msi_list, list) {
3300 irq = create_irq_nr(irq_want--);
3303 #ifdef CONFIG_INTR_REMAP
3304 if (!intr_remapping_enabled)
3309 * allocate the consecutive block of IRTE's
3312 index = msi_alloc_irte(dev, irq, nvec);
3318 iommu = map_dev_to_ir(dev);
3324 * setup the mapping between the irq and the IRTE
3325 * base index, the sub_handle pointing to the
3326 * appropriate interrupt remap table entry.
3328 set_irte_irq(irq, iommu, index, sub_handle);
3332 ret = setup_msi_irq(dev, desc, irq);
3344 void arch_teardown_msi_irq(unsigned int irq)
3351 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3353 struct irq_cfg *cfg;
3357 struct irq_desc *desc;
3359 cpus_and(tmp, mask, cpu_online_map);
3360 if (cpus_empty(tmp))
3363 if (assign_irq_vector(irq, mask))
3367 cpus_and(tmp, cfg->domain, mask);
3368 dest = cpu_mask_to_apicid(tmp);
3370 dmar_msi_read(irq, &msg);
3372 msg.data &= ~MSI_DATA_VECTOR_MASK;
3373 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3374 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3375 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3377 dmar_msi_write(irq, &msg);
3378 desc = irq_to_desc(irq);
3379 desc->affinity = mask;
3381 #endif /* CONFIG_SMP */
3383 struct irq_chip dmar_msi_type = {
3385 .unmask = dmar_msi_unmask,
3386 .mask = dmar_msi_mask,
3387 .ack = ack_apic_edge,
3389 .set_affinity = dmar_msi_set_affinity,
3391 .retrigger = ioapic_retrigger_irq,
3394 int arch_setup_dmar_msi(unsigned int irq)
3399 ret = msi_compose_msg(NULL, irq, &msg);
3402 dmar_msi_write(irq, &msg);
3403 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3409 #ifdef CONFIG_HPET_TIMER
3412 static void hpet_msi_set_affinity(unsigned int irq, cpumask_t mask)
3414 struct irq_cfg *cfg;
3415 struct irq_desc *desc;
3420 cpus_and(tmp, mask, cpu_online_map);
3421 if (cpus_empty(tmp))
3424 if (assign_irq_vector(irq, mask))
3428 cpus_and(tmp, cfg->domain, mask);
3429 dest = cpu_mask_to_apicid(tmp);
3431 hpet_msi_read(irq, &msg);
3433 msg.data &= ~MSI_DATA_VECTOR_MASK;
3434 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3435 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3436 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3438 hpet_msi_write(irq, &msg);
3439 desc = irq_to_desc(irq);
3440 desc->affinity = mask;
3442 #endif /* CONFIG_SMP */
3444 struct irq_chip hpet_msi_type = {
3446 .unmask = hpet_msi_unmask,
3447 .mask = hpet_msi_mask,
3448 .ack = ack_apic_edge,
3450 .set_affinity = hpet_msi_set_affinity,
3452 .retrigger = ioapic_retrigger_irq,
3455 int arch_setup_hpet_msi(unsigned int irq)
3460 ret = msi_compose_msg(NULL, irq, &msg);
3464 hpet_msi_write(irq, &msg);
3465 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3472 #endif /* CONFIG_PCI_MSI */
3474 * Hypertransport interrupt support
3476 #ifdef CONFIG_HT_IRQ
3480 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3482 struct ht_irq_msg msg;
3483 fetch_ht_irq_msg(irq, &msg);
3485 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3486 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3488 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3489 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3491 write_ht_irq_msg(irq, &msg);
3494 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3496 struct irq_cfg *cfg;
3499 struct irq_desc *desc;
3501 cpus_and(tmp, mask, cpu_online_map);
3502 if (cpus_empty(tmp))
3505 if (assign_irq_vector(irq, mask))
3509 cpus_and(tmp, cfg->domain, mask);
3510 dest = cpu_mask_to_apicid(tmp);
3512 target_ht_irq(irq, dest, cfg->vector);
3513 desc = irq_to_desc(irq);
3514 desc->affinity = mask;
3518 static struct irq_chip ht_irq_chip = {
3520 .mask = mask_ht_irq,
3521 .unmask = unmask_ht_irq,
3522 .ack = ack_apic_edge,
3524 .set_affinity = set_ht_irq_affinity,
3526 .retrigger = ioapic_retrigger_irq,
3529 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3531 struct irq_cfg *cfg;
3536 err = assign_irq_vector(irq, tmp);
3538 struct ht_irq_msg msg;
3542 cpus_and(tmp, cfg->domain, tmp);
3543 dest = cpu_mask_to_apicid(tmp);
3545 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3549 HT_IRQ_LOW_DEST_ID(dest) |
3550 HT_IRQ_LOW_VECTOR(cfg->vector) |
3551 ((INT_DEST_MODE == 0) ?
3552 HT_IRQ_LOW_DM_PHYSICAL :
3553 HT_IRQ_LOW_DM_LOGICAL) |
3554 HT_IRQ_LOW_RQEOI_EDGE |
3555 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3556 HT_IRQ_LOW_MT_FIXED :
3557 HT_IRQ_LOW_MT_ARBITRATED) |
3558 HT_IRQ_LOW_IRQ_MASKED;
3560 write_ht_irq_msg(irq, &msg);
3562 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3563 handle_edge_irq, "edge");
3565 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3569 #endif /* CONFIG_HT_IRQ */
3571 #ifdef CONFIG_X86_64
3573 * Re-target the irq to the specified CPU and enable the specified MMR located
3574 * on the specified blade to allow the sending of MSIs to the specified CPU.
3576 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3577 unsigned long mmr_offset)
3579 const cpumask_t *eligible_cpu = get_cpu_mask(cpu);
3580 struct irq_cfg *cfg;
3582 unsigned long mmr_value;
3583 struct uv_IO_APIC_route_entry *entry;
3584 unsigned long flags;
3587 err = assign_irq_vector(irq, *eligible_cpu);
3591 spin_lock_irqsave(&vector_lock, flags);
3592 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3594 spin_unlock_irqrestore(&vector_lock, flags);
3599 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3600 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3602 entry->vector = cfg->vector;
3603 entry->delivery_mode = INT_DELIVERY_MODE;
3604 entry->dest_mode = INT_DEST_MODE;
3605 entry->polarity = 0;
3608 entry->dest = cpu_mask_to_apicid(*eligible_cpu);
3610 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3611 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3617 * Disable the specified MMR located on the specified blade so that MSIs are
3618 * longer allowed to be sent.
3620 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3622 unsigned long mmr_value;
3623 struct uv_IO_APIC_route_entry *entry;
3627 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3628 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3632 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3633 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3635 #endif /* CONFIG_X86_64 */
3637 int __init io_apic_get_redir_entries (int ioapic)
3639 union IO_APIC_reg_01 reg_01;
3640 unsigned long flags;
3642 spin_lock_irqsave(&ioapic_lock, flags);
3643 reg_01.raw = io_apic_read(ioapic, 1);
3644 spin_unlock_irqrestore(&ioapic_lock, flags);
3646 return reg_01.bits.entries;
3649 int __init probe_nr_irqs(void)
3656 int nr_min = NR_IRQS;
3659 for (idx = 0; idx < nr_ioapics; idx++)
3660 nr += io_apic_get_redir_entries(idx) + 1;
3662 /* double it for hotplug and msi and nmi */
3665 /* something wrong ? */
3672 /* --------------------------------------------------------------------------
3673 ACPI-based IOAPIC Configuration
3674 -------------------------------------------------------------------------- */
3678 #ifdef CONFIG_X86_32
3679 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3681 union IO_APIC_reg_00 reg_00;
3682 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3684 unsigned long flags;
3688 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3689 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3690 * supports up to 16 on one shared APIC bus.
3692 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3693 * advantage of new APIC bus architecture.
3696 if (physids_empty(apic_id_map))
3697 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3699 spin_lock_irqsave(&ioapic_lock, flags);
3700 reg_00.raw = io_apic_read(ioapic, 0);
3701 spin_unlock_irqrestore(&ioapic_lock, flags);
3703 if (apic_id >= get_physical_broadcast()) {
3704 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3705 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3706 apic_id = reg_00.bits.ID;
3710 * Every APIC in a system must have a unique ID or we get lots of nice
3711 * 'stuck on smp_invalidate_needed IPI wait' messages.
3713 if (check_apicid_used(apic_id_map, apic_id)) {
3715 for (i = 0; i < get_physical_broadcast(); i++) {
3716 if (!check_apicid_used(apic_id_map, i))
3720 if (i == get_physical_broadcast())
3721 panic("Max apic_id exceeded!\n");
3723 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3724 "trying %d\n", ioapic, apic_id, i);
3729 tmp = apicid_to_cpu_present(apic_id);
3730 physids_or(apic_id_map, apic_id_map, tmp);
3732 if (reg_00.bits.ID != apic_id) {
3733 reg_00.bits.ID = apic_id;
3735 spin_lock_irqsave(&ioapic_lock, flags);
3736 io_apic_write(ioapic, 0, reg_00.raw);
3737 reg_00.raw = io_apic_read(ioapic, 0);
3738 spin_unlock_irqrestore(&ioapic_lock, flags);
3741 if (reg_00.bits.ID != apic_id) {
3742 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3747 apic_printk(APIC_VERBOSE, KERN_INFO
3748 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3753 int __init io_apic_get_version(int ioapic)
3755 union IO_APIC_reg_01 reg_01;
3756 unsigned long flags;
3758 spin_lock_irqsave(&ioapic_lock, flags);
3759 reg_01.raw = io_apic_read(ioapic, 1);
3760 spin_unlock_irqrestore(&ioapic_lock, flags);
3762 return reg_01.bits.version;
3766 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3768 if (!IO_APIC_IRQ(irq)) {
3769 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3775 * IRQs < 16 are already in the irq_2_pin[] map
3778 add_pin_to_irq(irq, ioapic, pin);
3780 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
3786 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3790 if (skip_ioapic_setup)
3793 for (i = 0; i < mp_irq_entries; i++)
3794 if (mp_irqs[i].mp_irqtype == mp_INT &&
3795 mp_irqs[i].mp_srcbusirq == bus_irq)
3797 if (i >= mp_irq_entries)
3800 *trigger = irq_trigger(i);
3801 *polarity = irq_polarity(i);
3805 #endif /* CONFIG_ACPI */
3808 * This function currently is only a helper for the i386 smp boot process where
3809 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3810 * so mask in all cases should simply be TARGET_CPUS
3813 void __init setup_ioapic_dest(void)
3815 int pin, ioapic, irq, irq_entry;
3816 struct irq_cfg *cfg;
3818 if (skip_ioapic_setup == 1)
3821 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3822 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3823 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3824 if (irq_entry == -1)
3826 irq = pin_2_irq(irq_entry, ioapic, pin);
3828 /* setup_IO_APIC_irqs could fail to get vector for some device
3829 * when you have too many devices, because at that time only boot
3834 setup_IO_APIC_irq(ioapic, pin, irq,
3835 irq_trigger(irq_entry),
3836 irq_polarity(irq_entry));
3837 #ifdef CONFIG_INTR_REMAP
3838 else if (intr_remapping_enabled)
3839 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3842 set_ioapic_affinity_irq(irq, TARGET_CPUS);
3849 #define IOAPIC_RESOURCE_NAME_SIZE 11
3851 static struct resource *ioapic_resources;
3853 static struct resource * __init ioapic_setup_resources(void)
3856 struct resource *res;
3860 if (nr_ioapics <= 0)
3863 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3866 mem = alloc_bootmem(n);
3870 mem += sizeof(struct resource) * nr_ioapics;
3872 for (i = 0; i < nr_ioapics; i++) {
3874 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3875 sprintf(mem, "IOAPIC %u", i);
3876 mem += IOAPIC_RESOURCE_NAME_SIZE;
3880 ioapic_resources = res;
3885 void __init ioapic_init_mappings(void)
3887 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3889 struct resource *ioapic_res;
3891 ioapic_res = ioapic_setup_resources();
3892 for (i = 0; i < nr_ioapics; i++) {
3893 if (smp_found_config) {
3894 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3895 #ifdef CONFIG_X86_32
3898 "WARNING: bogus zero IO-APIC "
3899 "address found in MPTABLE, "
3900 "disabling IO/APIC support!\n");
3901 smp_found_config = 0;
3902 skip_ioapic_setup = 1;
3903 goto fake_ioapic_page;
3907 #ifdef CONFIG_X86_32
3910 ioapic_phys = (unsigned long)
3911 alloc_bootmem_pages(PAGE_SIZE);
3912 ioapic_phys = __pa(ioapic_phys);
3914 set_fixmap_nocache(idx, ioapic_phys);
3915 apic_printk(APIC_VERBOSE,
3916 "mapped IOAPIC to %08lx (%08lx)\n",
3917 __fix_to_virt(idx), ioapic_phys);
3920 if (ioapic_res != NULL) {
3921 ioapic_res->start = ioapic_phys;
3922 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3928 static int __init ioapic_insert_resources(void)
3931 struct resource *r = ioapic_resources;
3935 "IO APIC resources could be not be allocated.\n");
3939 for (i = 0; i < nr_ioapics; i++) {
3940 insert_resource(&iomem_resource, r);
3947 /* Insert the IO APIC resources after PCI initialization has occured to handle
3948 * IO APICS that are mapped in on a BAR in PCI space. */
3949 late_initcall(ioapic_insert_resources);