2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
61 #include <asm/uv/uv_hub.h>
62 #include <asm/uv/uv_irq.h>
65 #include <mach_apic.h>
66 #include <mach_apicdef.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
88 /* MP IRQ source entries */
89 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100 int skip_ioapic_setup;
102 static int __init parse_noapic(char *str)
104 /* disable IO-APIC */
105 disable_ioapic_setup();
108 early_param("noapic", parse_noapic);
113 * This is performance-critical, we want to do it O(1)
115 * the indexing order of this array favors 1:1 mappings
116 * between pins and IRQs.
119 struct irq_pin_list {
121 struct irq_pin_list *next;
124 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
126 struct irq_pin_list *pin;
129 node = cpu_to_node(cpu);
131 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
132 printk(KERN_DEBUG " alloc irq_2_pin on cpu %d node %d\n", cpu, node);
138 struct irq_pin_list *irq_2_pin;
140 cpumask_t old_domain;
141 unsigned move_cleanup_count;
143 u8 move_in_progress : 1;
146 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
147 #ifdef CONFIG_SPARSE_IRQ
148 static struct irq_cfg irq_cfgx[] = {
150 static struct irq_cfg irq_cfgx[NR_IRQS] = {
152 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
153 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
154 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
155 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
156 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
157 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
158 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
159 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
160 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
161 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
162 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
163 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
164 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
165 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
166 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
167 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
170 void __init arch_early_irq_init(void)
173 struct irq_desc *desc;
178 count = ARRAY_SIZE(irq_cfgx);
180 for (i = 0; i < count; i++) {
181 desc = irq_to_desc(i);
182 desc->chip_data = &cfg[i];
186 #ifdef CONFIG_SPARSE_IRQ
187 static struct irq_cfg *irq_cfg(unsigned int irq)
189 struct irq_cfg *cfg = NULL;
190 struct irq_desc *desc;
192 desc = irq_to_desc(irq);
194 cfg = desc->chip_data;
199 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
204 node = cpu_to_node(cpu);
206 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
207 printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node);
212 void arch_init_chip_data(struct irq_desc *desc, int cpu)
216 cfg = desc->chip_data;
218 desc->chip_data = get_one_free_irq_cfg(cpu);
219 if (!desc->chip_data) {
220 printk(KERN_ERR "can not alloc irq_cfg\n");
227 static struct irq_cfg *irq_cfg(unsigned int irq)
229 return irq < nr_irqs ? irq_cfgx + irq : NULL;
234 static inline void set_extra_move_desc(struct irq_desc *desc, cpumask_t mask)
240 unsigned int unused[3];
244 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
246 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
247 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
250 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
252 struct io_apic __iomem *io_apic = io_apic_base(apic);
253 writel(reg, &io_apic->index);
254 return readl(&io_apic->data);
257 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
259 struct io_apic __iomem *io_apic = io_apic_base(apic);
260 writel(reg, &io_apic->index);
261 writel(value, &io_apic->data);
265 * Re-write a value: to be used for read-modify-write
266 * cycles where the read already set up the index register.
268 * Older SiS APIC requires we rewrite the index register
270 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
272 struct io_apic __iomem *io_apic = io_apic_base(apic);
275 writel(reg, &io_apic->index);
276 writel(value, &io_apic->data);
279 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
281 struct irq_pin_list *entry;
284 spin_lock_irqsave(&ioapic_lock, flags);
285 entry = cfg->irq_2_pin;
293 reg = io_apic_read(entry->apic, 0x10 + pin*2);
294 /* Is the remote IRR bit set? */
295 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
296 spin_unlock_irqrestore(&ioapic_lock, flags);
303 spin_unlock_irqrestore(&ioapic_lock, flags);
309 struct { u32 w1, w2; };
310 struct IO_APIC_route_entry entry;
313 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
315 union entry_union eu;
317 spin_lock_irqsave(&ioapic_lock, flags);
318 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
319 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
320 spin_unlock_irqrestore(&ioapic_lock, flags);
325 * When we write a new IO APIC routing entry, we need to write the high
326 * word first! If the mask bit in the low word is clear, we will enable
327 * the interrupt, and we need to make sure the entry is fully populated
328 * before that happens.
331 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
333 union entry_union eu;
335 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
336 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
339 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
342 spin_lock_irqsave(&ioapic_lock, flags);
343 __ioapic_write_entry(apic, pin, e);
344 spin_unlock_irqrestore(&ioapic_lock, flags);
348 * When we mask an IO APIC routing entry, we need to write the low
349 * word first, in order to set the mask bit before we change the
352 static void ioapic_mask_entry(int apic, int pin)
355 union entry_union eu = { .entry.mask = 1 };
357 spin_lock_irqsave(&ioapic_lock, flags);
358 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
359 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
360 spin_unlock_irqrestore(&ioapic_lock, flags);
364 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
367 struct irq_pin_list *entry;
368 u8 vector = cfg->vector;
370 entry = cfg->irq_2_pin;
379 #ifdef CONFIG_INTR_REMAP
381 * With interrupt-remapping, destination information comes
382 * from interrupt-remapping table entry.
384 if (!irq_remapped(irq))
385 io_apic_write(apic, 0x11 + pin*2, dest);
387 io_apic_write(apic, 0x11 + pin*2, dest);
389 reg = io_apic_read(apic, 0x10 + pin*2);
390 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
392 io_apic_modify(apic, 0x10 + pin*2, reg);
399 static int assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask);
401 static void set_ioapic_affinity_irq_desc(struct irq_desc *desc, cpumask_t mask)
409 cpus_and(tmp, mask, cpu_online_map);
414 cfg = desc->chip_data;
415 if (assign_irq_vector(irq, cfg, mask))
418 set_extra_move_desc(desc, mask);
420 cpus_and(tmp, cfg->domain, mask);
421 dest = cpu_mask_to_apicid(tmp);
423 * Only the high 8 bits are valid.
425 dest = SET_APIC_LOGICAL_ID(dest);
427 spin_lock_irqsave(&ioapic_lock, flags);
428 __target_IO_APIC_irq(irq, dest, cfg);
429 desc->affinity = mask;
430 spin_unlock_irqrestore(&ioapic_lock, flags);
433 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
435 struct irq_desc *desc;
437 desc = irq_to_desc(irq);
439 set_ioapic_affinity_irq_desc(desc, mask);
441 #endif /* CONFIG_SMP */
444 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
445 * shared ISA-space IRQs, so we have to support them. We are super
446 * fast in the common case, and fast for shared ISA-space IRQs.
448 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
450 struct irq_pin_list *entry;
452 entry = cfg->irq_2_pin;
454 entry = get_one_free_irq_2_pin(cpu);
456 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
460 cfg->irq_2_pin = entry;
466 while (entry->next) {
467 /* not again, please */
468 if (entry->apic == apic && entry->pin == pin)
474 entry->next = get_one_free_irq_2_pin(cpu);
481 * Reroute an IRQ to a different pin.
483 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
484 int oldapic, int oldpin,
485 int newapic, int newpin)
487 struct irq_pin_list *entry = cfg->irq_2_pin;
491 if (entry->apic == oldapic && entry->pin == oldpin) {
492 entry->apic = newapic;
495 /* every one is different, right? */
501 /* why? call replace before add? */
503 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
506 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
507 int mask_and, int mask_or,
508 void (*final)(struct irq_pin_list *entry))
511 struct irq_pin_list *entry;
513 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
516 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
519 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
525 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
527 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
531 void io_apic_sync(struct irq_pin_list *entry)
534 * Synchronize the IO-APIC and the CPU by doing
535 * a dummy read from the IO-APIC
537 struct io_apic __iomem *io_apic;
538 io_apic = io_apic_base(entry->apic);
539 readl(&io_apic->data);
542 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
544 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
546 #else /* CONFIG_X86_32 */
547 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
549 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
552 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
554 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
555 IO_APIC_REDIR_MASKED, NULL);
558 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
560 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
561 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
563 #endif /* CONFIG_X86_32 */
565 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
567 struct irq_cfg *cfg = desc->chip_data;
572 spin_lock_irqsave(&ioapic_lock, flags);
573 __mask_IO_APIC_irq(cfg);
574 spin_unlock_irqrestore(&ioapic_lock, flags);
577 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
579 struct irq_cfg *cfg = desc->chip_data;
582 spin_lock_irqsave(&ioapic_lock, flags);
583 __unmask_IO_APIC_irq(cfg);
584 spin_unlock_irqrestore(&ioapic_lock, flags);
587 static void mask_IO_APIC_irq(unsigned int irq)
589 struct irq_desc *desc = irq_to_desc(irq);
591 mask_IO_APIC_irq_desc(desc);
593 static void unmask_IO_APIC_irq(unsigned int irq)
595 struct irq_desc *desc = irq_to_desc(irq);
597 unmask_IO_APIC_irq_desc(desc);
600 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
602 struct IO_APIC_route_entry entry;
604 /* Check delivery_mode to be sure we're not clearing an SMI pin */
605 entry = ioapic_read_entry(apic, pin);
606 if (entry.delivery_mode == dest_SMI)
609 * Disable it in the IO-APIC irq-routing table:
611 ioapic_mask_entry(apic, pin);
614 static void clear_IO_APIC (void)
618 for (apic = 0; apic < nr_ioapics; apic++)
619 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
620 clear_IO_APIC_pin(apic, pin);
623 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
624 void send_IPI_self(int vector)
631 apic_wait_icr_idle();
632 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
634 * Send the IPI. The write to APIC_ICR fires this off.
636 apic_write(APIC_ICR, cfg);
638 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
642 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
643 * specific CPU-side IRQs.
647 static int pirq_entries [MAX_PIRQS];
648 static int pirqs_enabled;
650 static int __init ioapic_pirq_setup(char *str)
653 int ints[MAX_PIRQS+1];
655 get_options(str, ARRAY_SIZE(ints), ints);
657 for (i = 0; i < MAX_PIRQS; i++)
658 pirq_entries[i] = -1;
661 apic_printk(APIC_VERBOSE, KERN_INFO
662 "PIRQ redirection, working around broken MP-BIOS.\n");
664 if (ints[0] < MAX_PIRQS)
667 for (i = 0; i < max; i++) {
668 apic_printk(APIC_VERBOSE, KERN_DEBUG
669 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
671 * PIRQs are mapped upside down, usually.
673 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
678 __setup("pirq=", ioapic_pirq_setup);
679 #endif /* CONFIG_X86_32 */
681 #ifdef CONFIG_INTR_REMAP
682 /* I/O APIC RTE contents at the OS boot up */
683 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
686 * Saves and masks all the unmasked IO-APIC RTE's
688 int save_mask_IO_APIC_setup(void)
690 union IO_APIC_reg_01 reg_01;
695 * The number of IO-APIC IRQ registers (== #pins):
697 for (apic = 0; apic < nr_ioapics; apic++) {
698 spin_lock_irqsave(&ioapic_lock, flags);
699 reg_01.raw = io_apic_read(apic, 1);
700 spin_unlock_irqrestore(&ioapic_lock, flags);
701 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
704 for (apic = 0; apic < nr_ioapics; apic++) {
705 early_ioapic_entries[apic] =
706 kzalloc(sizeof(struct IO_APIC_route_entry) *
707 nr_ioapic_registers[apic], GFP_KERNEL);
708 if (!early_ioapic_entries[apic])
712 for (apic = 0; apic < nr_ioapics; apic++)
713 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
714 struct IO_APIC_route_entry entry;
716 entry = early_ioapic_entries[apic][pin] =
717 ioapic_read_entry(apic, pin);
720 ioapic_write_entry(apic, pin, entry);
728 kfree(early_ioapic_entries[apic--]);
729 memset(early_ioapic_entries, 0,
730 ARRAY_SIZE(early_ioapic_entries));
735 void restore_IO_APIC_setup(void)
739 for (apic = 0; apic < nr_ioapics; apic++) {
740 if (!early_ioapic_entries[apic])
742 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
743 ioapic_write_entry(apic, pin,
744 early_ioapic_entries[apic][pin]);
745 kfree(early_ioapic_entries[apic]);
746 early_ioapic_entries[apic] = NULL;
750 void reinit_intr_remapped_IO_APIC(int intr_remapping)
753 * for now plain restore of previous settings.
754 * TBD: In the case of OS enabling interrupt-remapping,
755 * IO-APIC RTE's need to be setup to point to interrupt-remapping
756 * table entries. for now, do a plain restore, and wait for
757 * the setup_IO_APIC_irqs() to do proper initialization.
759 restore_IO_APIC_setup();
764 * Find the IRQ entry number of a certain pin.
766 static int find_irq_entry(int apic, int pin, int type)
770 for (i = 0; i < mp_irq_entries; i++)
771 if (mp_irqs[i].mp_irqtype == type &&
772 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
773 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
774 mp_irqs[i].mp_dstirq == pin)
781 * Find the pin to which IRQ[irq] (ISA) is connected
783 static int __init find_isa_irq_pin(int irq, int type)
787 for (i = 0; i < mp_irq_entries; i++) {
788 int lbus = mp_irqs[i].mp_srcbus;
790 if (test_bit(lbus, mp_bus_not_pci) &&
791 (mp_irqs[i].mp_irqtype == type) &&
792 (mp_irqs[i].mp_srcbusirq == irq))
794 return mp_irqs[i].mp_dstirq;
799 static int __init find_isa_irq_apic(int irq, int type)
803 for (i = 0; i < mp_irq_entries; i++) {
804 int lbus = mp_irqs[i].mp_srcbus;
806 if (test_bit(lbus, mp_bus_not_pci) &&
807 (mp_irqs[i].mp_irqtype == type) &&
808 (mp_irqs[i].mp_srcbusirq == irq))
811 if (i < mp_irq_entries) {
813 for(apic = 0; apic < nr_ioapics; apic++) {
814 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
823 * Find a specific PCI IRQ entry.
824 * Not an __init, possibly needed by modules
826 static int pin_2_irq(int idx, int apic, int pin);
828 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
830 int apic, i, best_guess = -1;
832 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
834 if (test_bit(bus, mp_bus_not_pci)) {
835 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
838 for (i = 0; i < mp_irq_entries; i++) {
839 int lbus = mp_irqs[i].mp_srcbus;
841 for (apic = 0; apic < nr_ioapics; apic++)
842 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
843 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
846 if (!test_bit(lbus, mp_bus_not_pci) &&
847 !mp_irqs[i].mp_irqtype &&
849 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
850 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
852 if (!(apic || IO_APIC_IRQ(irq)))
855 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
858 * Use the first all-but-pin matching entry as a
859 * best-guess fuzzy result for broken mptables.
868 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
870 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
872 * EISA Edge/Level control register, ELCR
874 static int EISA_ELCR(unsigned int irq)
876 if (irq < NR_IRQS_LEGACY) {
877 unsigned int port = 0x4d0 + (irq >> 3);
878 return (inb(port) >> (irq & 7)) & 1;
880 apic_printk(APIC_VERBOSE, KERN_INFO
881 "Broken MPtable reports ISA irq %d\n", irq);
887 /* ISA interrupts are always polarity zero edge triggered,
888 * when listed as conforming in the MP table. */
890 #define default_ISA_trigger(idx) (0)
891 #define default_ISA_polarity(idx) (0)
893 /* EISA interrupts are always polarity zero and can be edge or level
894 * trigger depending on the ELCR value. If an interrupt is listed as
895 * EISA conforming in the MP table, that means its trigger type must
896 * be read in from the ELCR */
898 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
899 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
901 /* PCI interrupts are always polarity one level triggered,
902 * when listed as conforming in the MP table. */
904 #define default_PCI_trigger(idx) (1)
905 #define default_PCI_polarity(idx) (1)
907 /* MCA interrupts are always polarity zero level triggered,
908 * when listed as conforming in the MP table. */
910 #define default_MCA_trigger(idx) (1)
911 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
913 static int MPBIOS_polarity(int idx)
915 int bus = mp_irqs[idx].mp_srcbus;
919 * Determine IRQ line polarity (high active or low active):
921 switch (mp_irqs[idx].mp_irqflag & 3)
923 case 0: /* conforms, ie. bus-type dependent polarity */
924 if (test_bit(bus, mp_bus_not_pci))
925 polarity = default_ISA_polarity(idx);
927 polarity = default_PCI_polarity(idx);
929 case 1: /* high active */
934 case 2: /* reserved */
936 printk(KERN_WARNING "broken BIOS!!\n");
940 case 3: /* low active */
945 default: /* invalid */
947 printk(KERN_WARNING "broken BIOS!!\n");
955 static int MPBIOS_trigger(int idx)
957 int bus = mp_irqs[idx].mp_srcbus;
961 * Determine IRQ trigger mode (edge or level sensitive):
963 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
965 case 0: /* conforms, ie. bus-type dependent */
966 if (test_bit(bus, mp_bus_not_pci))
967 trigger = default_ISA_trigger(idx);
969 trigger = default_PCI_trigger(idx);
970 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
971 switch (mp_bus_id_to_type[bus]) {
972 case MP_BUS_ISA: /* ISA pin */
974 /* set before the switch */
977 case MP_BUS_EISA: /* EISA pin */
979 trigger = default_EISA_trigger(idx);
982 case MP_BUS_PCI: /* PCI pin */
984 /* set before the switch */
987 case MP_BUS_MCA: /* MCA pin */
989 trigger = default_MCA_trigger(idx);
994 printk(KERN_WARNING "broken BIOS!!\n");
1006 case 2: /* reserved */
1008 printk(KERN_WARNING "broken BIOS!!\n");
1017 default: /* invalid */
1019 printk(KERN_WARNING "broken BIOS!!\n");
1027 static inline int irq_polarity(int idx)
1029 return MPBIOS_polarity(idx);
1032 static inline int irq_trigger(int idx)
1034 return MPBIOS_trigger(idx);
1037 int (*ioapic_renumber_irq)(int ioapic, int irq);
1038 static int pin_2_irq(int idx, int apic, int pin)
1041 int bus = mp_irqs[idx].mp_srcbus;
1044 * Debugging check, we are in big trouble if this message pops up!
1046 if (mp_irqs[idx].mp_dstirq != pin)
1047 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1049 if (test_bit(bus, mp_bus_not_pci)) {
1050 irq = mp_irqs[idx].mp_srcbusirq;
1053 * PCI IRQs are mapped in order
1057 irq += nr_ioapic_registers[i++];
1060 * For MPS mode, so far only needed by ES7000 platform
1062 if (ioapic_renumber_irq)
1063 irq = ioapic_renumber_irq(apic, irq);
1066 #ifdef CONFIG_X86_32
1068 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1070 if ((pin >= 16) && (pin <= 23)) {
1071 if (pirq_entries[pin-16] != -1) {
1072 if (!pirq_entries[pin-16]) {
1073 apic_printk(APIC_VERBOSE, KERN_DEBUG
1074 "disabling PIRQ%d\n", pin-16);
1076 irq = pirq_entries[pin-16];
1077 apic_printk(APIC_VERBOSE, KERN_DEBUG
1078 "using PIRQ%d -> IRQ %d\n",
1088 void lock_vector_lock(void)
1090 /* Used to the online set of cpus does not change
1091 * during assign_irq_vector.
1093 spin_lock(&vector_lock);
1096 void unlock_vector_lock(void)
1098 spin_unlock(&vector_lock);
1101 static int __assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask)
1104 * NOTE! The local APIC isn't very good at handling
1105 * multiple interrupts at the same interrupt level.
1106 * As the interrupt level is determined by taking the
1107 * vector number and shifting that right by 4, we
1108 * want to spread these out a bit so that they don't
1109 * all fall in the same interrupt level.
1111 * Also, we've got to be careful not to trash gate
1112 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1114 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1115 unsigned int old_vector;
1118 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1121 /* Only try and allocate irqs on cpus that are present */
1122 cpus_and(mask, mask, cpu_online_map);
1124 old_vector = cfg->vector;
1127 cpus_and(tmp, cfg->domain, mask);
1128 if (!cpus_empty(tmp))
1132 for_each_cpu_mask_nr(cpu, mask) {
1133 cpumask_t domain, new_mask;
1137 domain = vector_allocation_domain(cpu);
1138 cpus_and(new_mask, domain, cpu_online_map);
1140 vector = current_vector;
1141 offset = current_offset;
1144 if (vector >= first_system_vector) {
1145 /* If we run out of vectors on large boxen, must share them. */
1146 offset = (offset + 1) % 8;
1147 vector = FIRST_DEVICE_VECTOR + offset;
1149 if (unlikely(current_vector == vector))
1151 #ifdef CONFIG_X86_64
1152 if (vector == IA32_SYSCALL_VECTOR)
1155 if (vector == SYSCALL_VECTOR)
1158 for_each_cpu_mask_nr(new_cpu, new_mask)
1159 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1162 current_vector = vector;
1163 current_offset = offset;
1165 cfg->move_in_progress = 1;
1166 cfg->old_domain = cfg->domain;
1168 for_each_cpu_mask_nr(new_cpu, new_mask)
1169 per_cpu(vector_irq, new_cpu)[vector] = irq;
1170 cfg->vector = vector;
1171 cfg->domain = domain;
1177 static int assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask)
1180 unsigned long flags;
1182 spin_lock_irqsave(&vector_lock, flags);
1183 err = __assign_irq_vector(irq, cfg, mask);
1184 spin_unlock_irqrestore(&vector_lock, flags);
1188 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1193 BUG_ON(!cfg->vector);
1195 vector = cfg->vector;
1196 cpus_and(mask, cfg->domain, cpu_online_map);
1197 for_each_cpu_mask_nr(cpu, mask)
1198 per_cpu(vector_irq, cpu)[vector] = -1;
1201 cpus_clear(cfg->domain);
1203 if (likely(!cfg->move_in_progress))
1205 cpus_and(mask, cfg->old_domain, cpu_online_map);
1206 for_each_cpu_mask_nr(cpu, mask) {
1207 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1209 if (per_cpu(vector_irq, cpu)[vector] != irq)
1211 per_cpu(vector_irq, cpu)[vector] = -1;
1215 cfg->move_in_progress = 0;
1218 void __setup_vector_irq(int cpu)
1220 /* Initialize vector_irq on a new cpu */
1221 /* This function must be called with vector_lock held */
1223 struct irq_cfg *cfg;
1224 struct irq_desc *desc;
1226 /* Mark the inuse vectors */
1227 for_each_irq_desc(irq, desc) {
1230 cfg = desc->chip_data;
1231 if (!cpu_isset(cpu, cfg->domain))
1233 vector = cfg->vector;
1234 per_cpu(vector_irq, cpu)[vector] = irq;
1236 /* Mark the free vectors */
1237 for (vector = 0; vector < NR_VECTORS; ++vector) {
1238 irq = per_cpu(vector_irq, cpu)[vector];
1243 if (!cpu_isset(cpu, cfg->domain))
1244 per_cpu(vector_irq, cpu)[vector] = -1;
1248 static struct irq_chip ioapic_chip;
1249 #ifdef CONFIG_INTR_REMAP
1250 static struct irq_chip ir_ioapic_chip;
1253 #define IOAPIC_AUTO -1
1254 #define IOAPIC_EDGE 0
1255 #define IOAPIC_LEVEL 1
1257 #ifdef CONFIG_X86_32
1258 static inline int IO_APIC_irq_trigger(int irq)
1262 for (apic = 0; apic < nr_ioapics; apic++) {
1263 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1264 idx = find_irq_entry(apic, pin, mp_INT);
1265 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1266 return irq_trigger(idx);
1270 * nonexistent IRQs are edge default
1275 static inline int IO_APIC_irq_trigger(int irq)
1281 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1284 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1285 trigger == IOAPIC_LEVEL)
1286 desc->status |= IRQ_LEVEL;
1288 desc->status &= ~IRQ_LEVEL;
1290 #ifdef CONFIG_INTR_REMAP
1291 if (irq_remapped(irq)) {
1292 desc->status |= IRQ_MOVE_PCNTXT;
1294 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1298 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1299 handle_edge_irq, "edge");
1303 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1304 trigger == IOAPIC_LEVEL)
1305 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1309 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1310 handle_edge_irq, "edge");
1313 static int setup_ioapic_entry(int apic, int irq,
1314 struct IO_APIC_route_entry *entry,
1315 unsigned int destination, int trigger,
1316 int polarity, int vector)
1319 * add it to the IO-APIC irq-routing table:
1321 memset(entry,0,sizeof(*entry));
1323 #ifdef CONFIG_INTR_REMAP
1324 if (intr_remapping_enabled) {
1325 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1327 struct IR_IO_APIC_route_entry *ir_entry =
1328 (struct IR_IO_APIC_route_entry *) entry;
1332 panic("No mapping iommu for ioapic %d\n", apic);
1334 index = alloc_irte(iommu, irq, 1);
1336 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1338 memset(&irte, 0, sizeof(irte));
1341 irte.dst_mode = INT_DEST_MODE;
1342 irte.trigger_mode = trigger;
1343 irte.dlvry_mode = INT_DELIVERY_MODE;
1344 irte.vector = vector;
1345 irte.dest_id = IRTE_DEST(destination);
1347 modify_irte(irq, &irte);
1349 ir_entry->index2 = (index >> 15) & 0x1;
1351 ir_entry->format = 1;
1352 ir_entry->index = (index & 0x7fff);
1356 entry->delivery_mode = INT_DELIVERY_MODE;
1357 entry->dest_mode = INT_DEST_MODE;
1358 entry->dest = destination;
1361 entry->mask = 0; /* enable IRQ */
1362 entry->trigger = trigger;
1363 entry->polarity = polarity;
1364 entry->vector = vector;
1366 /* Mask level triggered irqs.
1367 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1374 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc,
1375 int trigger, int polarity)
1377 struct irq_cfg *cfg;
1378 struct IO_APIC_route_entry entry;
1381 if (!IO_APIC_IRQ(irq))
1384 cfg = desc->chip_data;
1387 if (assign_irq_vector(irq, cfg, mask))
1390 cpus_and(mask, cfg->domain, mask);
1392 apic_printk(APIC_VERBOSE,KERN_DEBUG
1393 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1394 "IRQ %d Mode:%i Active:%i)\n",
1395 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1396 irq, trigger, polarity);
1399 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1400 cpu_mask_to_apicid(mask), trigger, polarity,
1402 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1403 mp_ioapics[apic].mp_apicid, pin);
1404 __clear_irq_vector(irq, cfg);
1408 ioapic_register_intr(irq, desc, trigger);
1409 if (irq < NR_IRQS_LEGACY)
1410 disable_8259A_irq(irq);
1412 ioapic_write_entry(apic, pin, entry);
1415 static void __init setup_IO_APIC_irqs(void)
1417 int apic, pin, idx, irq;
1419 struct irq_desc *desc;
1420 struct irq_cfg *cfg;
1421 int cpu = boot_cpu_id;
1423 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1425 for (apic = 0; apic < nr_ioapics; apic++) {
1426 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1428 idx = find_irq_entry(apic, pin, mp_INT);
1432 apic_printk(APIC_VERBOSE,
1433 KERN_DEBUG " %d-%d",
1434 mp_ioapics[apic].mp_apicid,
1437 apic_printk(APIC_VERBOSE, " %d-%d",
1438 mp_ioapics[apic].mp_apicid,
1443 apic_printk(APIC_VERBOSE,
1444 " (apicid-pin) not connected\n");
1448 irq = pin_2_irq(idx, apic, pin);
1449 #ifdef CONFIG_X86_32
1450 if (multi_timer_check(apic, irq))
1453 desc = irq_to_desc_alloc_cpu(irq, cpu);
1455 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1458 cfg = desc->chip_data;
1459 add_pin_to_irq_cpu(cfg, cpu, apic, pin);
1461 setup_IO_APIC_irq(apic, pin, irq, desc,
1462 irq_trigger(idx), irq_polarity(idx));
1467 apic_printk(APIC_VERBOSE,
1468 " (apicid-pin) not connected\n");
1472 * Set up the timer pin, possibly with the 8259A-master behind.
1474 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1477 struct IO_APIC_route_entry entry;
1479 #ifdef CONFIG_INTR_REMAP
1480 if (intr_remapping_enabled)
1484 memset(&entry, 0, sizeof(entry));
1487 * We use logical delivery to get the timer IRQ
1490 entry.dest_mode = INT_DEST_MODE;
1491 entry.mask = 1; /* mask IRQ now */
1492 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1493 entry.delivery_mode = INT_DELIVERY_MODE;
1496 entry.vector = vector;
1499 * The timer IRQ doesn't have to know that behind the
1500 * scene we may have a 8259A-master in AEOI mode ...
1502 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1505 * Add it to the IO-APIC irq-routing table:
1507 ioapic_write_entry(apic, pin, entry);
1511 __apicdebuginit(void) print_IO_APIC(void)
1514 union IO_APIC_reg_00 reg_00;
1515 union IO_APIC_reg_01 reg_01;
1516 union IO_APIC_reg_02 reg_02;
1517 union IO_APIC_reg_03 reg_03;
1518 unsigned long flags;
1519 struct irq_cfg *cfg;
1520 struct irq_desc *desc;
1523 if (apic_verbosity == APIC_QUIET)
1526 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1527 for (i = 0; i < nr_ioapics; i++)
1528 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1529 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1532 * We are a bit conservative about what we expect. We have to
1533 * know about every hardware change ASAP.
1535 printk(KERN_INFO "testing the IO APIC.......................\n");
1537 for (apic = 0; apic < nr_ioapics; apic++) {
1539 spin_lock_irqsave(&ioapic_lock, flags);
1540 reg_00.raw = io_apic_read(apic, 0);
1541 reg_01.raw = io_apic_read(apic, 1);
1542 if (reg_01.bits.version >= 0x10)
1543 reg_02.raw = io_apic_read(apic, 2);
1544 if (reg_01.bits.version >= 0x20)
1545 reg_03.raw = io_apic_read(apic, 3);
1546 spin_unlock_irqrestore(&ioapic_lock, flags);
1549 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1550 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1551 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1552 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1553 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1555 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1556 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1558 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1559 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1562 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1563 * but the value of reg_02 is read as the previous read register
1564 * value, so ignore it if reg_02 == reg_01.
1566 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1567 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1568 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1572 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1573 * or reg_03, but the value of reg_0[23] is read as the previous read
1574 * register value, so ignore it if reg_03 == reg_0[12].
1576 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1577 reg_03.raw != reg_01.raw) {
1578 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1579 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1582 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1584 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1585 " Stat Dmod Deli Vect: \n");
1587 for (i = 0; i <= reg_01.bits.entries; i++) {
1588 struct IO_APIC_route_entry entry;
1590 entry = ioapic_read_entry(apic, i);
1592 printk(KERN_DEBUG " %02x %03X ",
1597 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1602 entry.delivery_status,
1604 entry.delivery_mode,
1609 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1610 for_each_irq_desc(irq, desc) {
1611 struct irq_pin_list *entry;
1615 cfg = desc->chip_data;
1616 entry = cfg->irq_2_pin;
1619 printk(KERN_DEBUG "IRQ%d ", irq);
1621 printk("-> %d:%d", entry->apic, entry->pin);
1624 entry = entry->next;
1629 printk(KERN_INFO ".................................... done.\n");
1634 __apicdebuginit(void) print_APIC_bitfield(int base)
1639 if (apic_verbosity == APIC_QUIET)
1642 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1643 for (i = 0; i < 8; i++) {
1644 v = apic_read(base + i*0x10);
1645 for (j = 0; j < 32; j++) {
1655 __apicdebuginit(void) print_local_APIC(void *dummy)
1657 unsigned int v, ver, maxlvt;
1660 if (apic_verbosity == APIC_QUIET)
1663 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1664 smp_processor_id(), hard_smp_processor_id());
1665 v = apic_read(APIC_ID);
1666 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1667 v = apic_read(APIC_LVR);
1668 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1669 ver = GET_APIC_VERSION(v);
1670 maxlvt = lapic_get_maxlvt();
1672 v = apic_read(APIC_TASKPRI);
1673 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1675 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1676 if (!APIC_XAPIC(ver)) {
1677 v = apic_read(APIC_ARBPRI);
1678 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1679 v & APIC_ARBPRI_MASK);
1681 v = apic_read(APIC_PROCPRI);
1682 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1686 * Remote read supported only in the 82489DX and local APIC for
1687 * Pentium processors.
1689 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1690 v = apic_read(APIC_RRR);
1691 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1694 v = apic_read(APIC_LDR);
1695 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1696 if (!x2apic_enabled()) {
1697 v = apic_read(APIC_DFR);
1698 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1700 v = apic_read(APIC_SPIV);
1701 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1703 printk(KERN_DEBUG "... APIC ISR field:\n");
1704 print_APIC_bitfield(APIC_ISR);
1705 printk(KERN_DEBUG "... APIC TMR field:\n");
1706 print_APIC_bitfield(APIC_TMR);
1707 printk(KERN_DEBUG "... APIC IRR field:\n");
1708 print_APIC_bitfield(APIC_IRR);
1710 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1711 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1712 apic_write(APIC_ESR, 0);
1714 v = apic_read(APIC_ESR);
1715 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1718 icr = apic_icr_read();
1719 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1720 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1722 v = apic_read(APIC_LVTT);
1723 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1725 if (maxlvt > 3) { /* PC is LVT#4. */
1726 v = apic_read(APIC_LVTPC);
1727 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1729 v = apic_read(APIC_LVT0);
1730 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1731 v = apic_read(APIC_LVT1);
1732 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1734 if (maxlvt > 2) { /* ERR is LVT#3. */
1735 v = apic_read(APIC_LVTERR);
1736 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1739 v = apic_read(APIC_TMICT);
1740 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1741 v = apic_read(APIC_TMCCT);
1742 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1743 v = apic_read(APIC_TDCR);
1744 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1748 __apicdebuginit(void) print_all_local_APICs(void)
1753 for_each_online_cpu(cpu)
1754 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1758 __apicdebuginit(void) print_PIC(void)
1761 unsigned long flags;
1763 if (apic_verbosity == APIC_QUIET)
1766 printk(KERN_DEBUG "\nprinting PIC contents\n");
1768 spin_lock_irqsave(&i8259A_lock, flags);
1770 v = inb(0xa1) << 8 | inb(0x21);
1771 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1773 v = inb(0xa0) << 8 | inb(0x20);
1774 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1778 v = inb(0xa0) << 8 | inb(0x20);
1782 spin_unlock_irqrestore(&i8259A_lock, flags);
1784 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1786 v = inb(0x4d1) << 8 | inb(0x4d0);
1787 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1790 __apicdebuginit(int) print_all_ICs(void)
1793 print_all_local_APICs();
1799 fs_initcall(print_all_ICs);
1802 /* Where if anywhere is the i8259 connect in external int mode */
1803 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1805 void __init enable_IO_APIC(void)
1807 union IO_APIC_reg_01 reg_01;
1808 int i8259_apic, i8259_pin;
1810 unsigned long flags;
1812 #ifdef CONFIG_X86_32
1815 for (i = 0; i < MAX_PIRQS; i++)
1816 pirq_entries[i] = -1;
1820 * The number of IO-APIC IRQ registers (== #pins):
1822 for (apic = 0; apic < nr_ioapics; apic++) {
1823 spin_lock_irqsave(&ioapic_lock, flags);
1824 reg_01.raw = io_apic_read(apic, 1);
1825 spin_unlock_irqrestore(&ioapic_lock, flags);
1826 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1828 for(apic = 0; apic < nr_ioapics; apic++) {
1830 /* See if any of the pins is in ExtINT mode */
1831 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1832 struct IO_APIC_route_entry entry;
1833 entry = ioapic_read_entry(apic, pin);
1835 /* If the interrupt line is enabled and in ExtInt mode
1836 * I have found the pin where the i8259 is connected.
1838 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1839 ioapic_i8259.apic = apic;
1840 ioapic_i8259.pin = pin;
1846 /* Look to see what if the MP table has reported the ExtINT */
1847 /* If we could not find the appropriate pin by looking at the ioapic
1848 * the i8259 probably is not connected the ioapic but give the
1849 * mptable a chance anyway.
1851 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1852 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1853 /* Trust the MP table if nothing is setup in the hardware */
1854 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1855 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1856 ioapic_i8259.pin = i8259_pin;
1857 ioapic_i8259.apic = i8259_apic;
1859 /* Complain if the MP table and the hardware disagree */
1860 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1861 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1863 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1867 * Do not trust the IO-APIC being empty at bootup
1873 * Not an __init, needed by the reboot code
1875 void disable_IO_APIC(void)
1878 * Clear the IO-APIC before rebooting:
1883 * If the i8259 is routed through an IOAPIC
1884 * Put that IOAPIC in virtual wire mode
1885 * so legacy interrupts can be delivered.
1887 if (ioapic_i8259.pin != -1) {
1888 struct IO_APIC_route_entry entry;
1890 memset(&entry, 0, sizeof(entry));
1891 entry.mask = 0; /* Enabled */
1892 entry.trigger = 0; /* Edge */
1894 entry.polarity = 0; /* High */
1895 entry.delivery_status = 0;
1896 entry.dest_mode = 0; /* Physical */
1897 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1899 entry.dest = read_apic_id();
1902 * Add it to the IO-APIC irq-routing table:
1904 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1907 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1910 #ifdef CONFIG_X86_32
1912 * function to set the IO-APIC physical IDs based on the
1913 * values stored in the MPC table.
1915 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1918 static void __init setup_ioapic_ids_from_mpc(void)
1920 union IO_APIC_reg_00 reg_00;
1921 physid_mask_t phys_id_present_map;
1924 unsigned char old_id;
1925 unsigned long flags;
1927 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1931 * Don't check I/O APIC IDs for xAPIC systems. They have
1932 * no meaning without the serial APIC bus.
1934 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1935 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1938 * This is broken; anything with a real cpu count has to
1939 * circumvent this idiocy regardless.
1941 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1944 * Set the IOAPIC ID to the value stored in the MPC table.
1946 for (apic = 0; apic < nr_ioapics; apic++) {
1948 /* Read the register 0 value */
1949 spin_lock_irqsave(&ioapic_lock, flags);
1950 reg_00.raw = io_apic_read(apic, 0);
1951 spin_unlock_irqrestore(&ioapic_lock, flags);
1953 old_id = mp_ioapics[apic].mp_apicid;
1955 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1956 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1957 apic, mp_ioapics[apic].mp_apicid);
1958 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1960 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1964 * Sanity check, is the ID really free? Every APIC in a
1965 * system must have a unique ID or we get lots of nice
1966 * 'stuck on smp_invalidate_needed IPI wait' messages.
1968 if (check_apicid_used(phys_id_present_map,
1969 mp_ioapics[apic].mp_apicid)) {
1970 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1971 apic, mp_ioapics[apic].mp_apicid);
1972 for (i = 0; i < get_physical_broadcast(); i++)
1973 if (!physid_isset(i, phys_id_present_map))
1975 if (i >= get_physical_broadcast())
1976 panic("Max APIC ID exceeded!\n");
1977 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1979 physid_set(i, phys_id_present_map);
1980 mp_ioapics[apic].mp_apicid = i;
1983 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1984 apic_printk(APIC_VERBOSE, "Setting %d in the "
1985 "phys_id_present_map\n",
1986 mp_ioapics[apic].mp_apicid);
1987 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1992 * We need to adjust the IRQ routing table
1993 * if the ID changed.
1995 if (old_id != mp_ioapics[apic].mp_apicid)
1996 for (i = 0; i < mp_irq_entries; i++)
1997 if (mp_irqs[i].mp_dstapic == old_id)
1998 mp_irqs[i].mp_dstapic
1999 = mp_ioapics[apic].mp_apicid;
2002 * Read the right value from the MPC table and
2003 * write it into the ID register.
2005 apic_printk(APIC_VERBOSE, KERN_INFO
2006 "...changing IO-APIC physical APIC ID to %d ...",
2007 mp_ioapics[apic].mp_apicid);
2009 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
2010 spin_lock_irqsave(&ioapic_lock, flags);
2011 io_apic_write(apic, 0, reg_00.raw);
2012 spin_unlock_irqrestore(&ioapic_lock, flags);
2017 spin_lock_irqsave(&ioapic_lock, flags);
2018 reg_00.raw = io_apic_read(apic, 0);
2019 spin_unlock_irqrestore(&ioapic_lock, flags);
2020 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
2021 printk("could not set ID!\n");
2023 apic_printk(APIC_VERBOSE, " ok.\n");
2028 int no_timer_check __initdata;
2030 static int __init notimercheck(char *s)
2035 __setup("no_timer_check", notimercheck);
2038 * There is a nasty bug in some older SMP boards, their mptable lies
2039 * about the timer IRQ. We do the following to work around the situation:
2041 * - timer IRQ defaults to IO-APIC IRQ
2042 * - if this function detects that timer IRQs are defunct, then we fall
2043 * back to ISA timer IRQs
2045 static int __init timer_irq_works(void)
2047 unsigned long t1 = jiffies;
2048 unsigned long flags;
2053 local_save_flags(flags);
2055 /* Let ten ticks pass... */
2056 mdelay((10 * 1000) / HZ);
2057 local_irq_restore(flags);
2060 * Expect a few ticks at least, to be sure some possible
2061 * glue logic does not lock up after one or two first
2062 * ticks in a non-ExtINT mode. Also the local APIC
2063 * might have cached one ExtINT interrupt. Finally, at
2064 * least one tick may be lost due to delays.
2068 if (time_after(jiffies, t1 + 4))
2074 * In the SMP+IOAPIC case it might happen that there are an unspecified
2075 * number of pending IRQ events unhandled. These cases are very rare,
2076 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2077 * better to do it this way as thus we do not have to be aware of
2078 * 'pending' interrupts in the IRQ path, except at this point.
2081 * Edge triggered needs to resend any interrupt
2082 * that was delayed but this is now handled in the device
2087 * Starting up a edge-triggered IO-APIC interrupt is
2088 * nasty - we need to make sure that we get the edge.
2089 * If it is already asserted for some reason, we need
2090 * return 1 to indicate that is was pending.
2092 * This is not complete - we should be able to fake
2093 * an edge even if it isn't on the 8259A...
2096 static unsigned int startup_ioapic_irq(unsigned int irq)
2098 int was_pending = 0;
2099 unsigned long flags;
2100 struct irq_cfg *cfg;
2102 spin_lock_irqsave(&ioapic_lock, flags);
2103 if (irq < NR_IRQS_LEGACY) {
2104 disable_8259A_irq(irq);
2105 if (i8259A_irq_pending(irq))
2109 __unmask_IO_APIC_irq(cfg);
2110 spin_unlock_irqrestore(&ioapic_lock, flags);
2115 #ifdef CONFIG_X86_64
2116 static int ioapic_retrigger_irq(unsigned int irq)
2119 struct irq_cfg *cfg = irq_cfg(irq);
2120 unsigned long flags;
2122 spin_lock_irqsave(&vector_lock, flags);
2123 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2124 spin_unlock_irqrestore(&vector_lock, flags);
2129 static int ioapic_retrigger_irq(unsigned int irq)
2131 send_IPI_self(irq_cfg(irq)->vector);
2138 * Level and edge triggered IO-APIC interrupts need different handling,
2139 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2140 * handled with the level-triggered descriptor, but that one has slightly
2141 * more overhead. Level-triggered interrupts cannot be handled with the
2142 * edge-triggered handler, without risking IRQ storms and other ugly
2148 #ifdef CONFIG_INTR_REMAP
2149 static void ir_irq_migration(struct work_struct *work);
2151 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2154 * Migrate the IO-APIC irq in the presence of intr-remapping.
2156 * For edge triggered, irq migration is a simple atomic update(of vector
2157 * and cpu destination) of IRTE and flush the hardware cache.
2159 * For level triggered, we need to modify the io-apic RTE aswell with the update
2160 * vector information, along with modifying IRTE with vector and destination.
2161 * So irq migration for level triggered is little bit more complex compared to
2162 * edge triggered migration. But the good news is, we use the same algorithm
2163 * for level triggered migration as we have today, only difference being,
2164 * we now initiate the irq migration from process context instead of the
2165 * interrupt context.
2167 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2168 * suppression) to the IO-APIC, level triggered irq migration will also be
2169 * as simple as edge triggered migration and we can do the irq migration
2170 * with a simple atomic update to IO-APIC RTE.
2172 static void migrate_ioapic_irq_desc(struct irq_desc *desc, cpumask_t mask)
2174 struct irq_cfg *cfg;
2175 cpumask_t tmp, cleanup_mask;
2177 int modify_ioapic_rte;
2179 unsigned long flags;
2182 cpus_and(tmp, mask, cpu_online_map);
2183 if (cpus_empty(tmp))
2187 if (get_irte(irq, &irte))
2190 cfg = desc->chip_data;
2191 if (assign_irq_vector(irq, cfg, mask))
2194 set_extra_move_desc(desc, mask);
2196 cpus_and(tmp, cfg->domain, mask);
2197 dest = cpu_mask_to_apicid(tmp);
2199 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2200 if (modify_ioapic_rte) {
2201 spin_lock_irqsave(&ioapic_lock, flags);
2202 __target_IO_APIC_irq(irq, dest, cfg);
2203 spin_unlock_irqrestore(&ioapic_lock, flags);
2206 irte.vector = cfg->vector;
2207 irte.dest_id = IRTE_DEST(dest);
2210 * Modified the IRTE and flushes the Interrupt entry cache.
2212 modify_irte(irq, &irte);
2214 if (cfg->move_in_progress) {
2215 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2216 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2217 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2218 cfg->move_in_progress = 0;
2221 desc->affinity = mask;
2224 static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2227 struct irq_cfg *cfg = desc->chip_data;
2229 mask_IO_APIC_irq_desc(desc);
2231 if (io_apic_level_ack_pending(cfg)) {
2233 * Interrupt in progress. Migrating irq now will change the
2234 * vector information in the IO-APIC RTE and that will confuse
2235 * the EOI broadcast performed by cpu.
2236 * So, delay the irq migration to the next instance.
2238 schedule_delayed_work(&ir_migration_work, 1);
2242 /* everthing is clear. we have right of way */
2243 migrate_ioapic_irq_desc(desc, desc->pending_mask);
2246 desc->status &= ~IRQ_MOVE_PENDING;
2247 cpus_clear(desc->pending_mask);
2250 unmask_IO_APIC_irq_desc(desc);
2255 static void ir_irq_migration(struct work_struct *work)
2258 struct irq_desc *desc;
2260 for_each_irq_desc(irq, desc) {
2264 if (desc->status & IRQ_MOVE_PENDING) {
2265 unsigned long flags;
2267 spin_lock_irqsave(&desc->lock, flags);
2268 if (!desc->chip->set_affinity ||
2269 !(desc->status & IRQ_MOVE_PENDING)) {
2270 desc->status &= ~IRQ_MOVE_PENDING;
2271 spin_unlock_irqrestore(&desc->lock, flags);
2275 desc->chip->set_affinity(irq, desc->pending_mask);
2276 spin_unlock_irqrestore(&desc->lock, flags);
2282 * Migrates the IRQ destination in the process context.
2284 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, cpumask_t mask)
2286 if (desc->status & IRQ_LEVEL) {
2287 desc->status |= IRQ_MOVE_PENDING;
2288 desc->pending_mask = mask;
2289 migrate_irq_remapped_level_desc(desc);
2293 migrate_ioapic_irq_desc(desc, mask);
2295 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2297 struct irq_desc *desc = irq_to_desc(irq);
2299 set_ir_ioapic_affinity_irq_desc(desc, mask);
2303 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2305 unsigned vector, me;
2307 #ifdef CONFIG_X86_64
2312 me = smp_processor_id();
2313 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2315 struct irq_desc *desc;
2316 struct irq_cfg *cfg;
2317 irq = __get_cpu_var(vector_irq)[vector];
2322 desc = irq_to_desc(irq);
2327 spin_lock(&desc->lock);
2328 if (!cfg->move_cleanup_count)
2331 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2334 __get_cpu_var(vector_irq)[vector] = -1;
2335 cfg->move_cleanup_count--;
2337 spin_unlock(&desc->lock);
2343 static void irq_complete_move(struct irq_desc **descp)
2345 struct irq_desc *desc = *descp;
2346 struct irq_cfg *cfg = desc->chip_data;
2347 unsigned vector, me;
2349 if (likely(!cfg->move_in_progress))
2352 vector = ~get_irq_regs()->orig_ax;
2353 me = smp_processor_id();
2354 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2355 cpumask_t cleanup_mask;
2357 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2358 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2359 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2360 cfg->move_in_progress = 0;
2364 static inline void irq_complete_move(struct irq_desc **descp) {}
2367 #ifdef CONFIG_INTR_REMAP
2368 static void ack_x2apic_level(unsigned int irq)
2373 static void ack_x2apic_edge(unsigned int irq)
2380 static void ack_apic_edge(unsigned int irq)
2382 struct irq_desc *desc = irq_to_desc(irq);
2384 irq_complete_move(&desc);
2385 move_native_irq(irq);
2389 atomic_t irq_mis_count;
2391 static void ack_apic_level(unsigned int irq)
2393 struct irq_desc *desc = irq_to_desc(irq);
2395 #ifdef CONFIG_X86_32
2399 struct irq_cfg *cfg;
2400 int do_unmask_irq = 0;
2402 irq_complete_move(&desc);
2403 #ifdef CONFIG_GENERIC_PENDING_IRQ
2404 /* If we are moving the irq we need to mask it */
2405 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2407 mask_IO_APIC_irq_desc(desc);
2411 #ifdef CONFIG_X86_32
2413 * It appears there is an erratum which affects at least version 0x11
2414 * of I/O APIC (that's the 82093AA and cores integrated into various
2415 * chipsets). Under certain conditions a level-triggered interrupt is
2416 * erroneously delivered as edge-triggered one but the respective IRR
2417 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2418 * message but it will never arrive and further interrupts are blocked
2419 * from the source. The exact reason is so far unknown, but the
2420 * phenomenon was observed when two consecutive interrupt requests
2421 * from a given source get delivered to the same CPU and the source is
2422 * temporarily disabled in between.
2424 * A workaround is to simulate an EOI message manually. We achieve it
2425 * by setting the trigger mode to edge and then to level when the edge
2426 * trigger mode gets detected in the TMR of a local APIC for a
2427 * level-triggered interrupt. We mask the source for the time of the
2428 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2429 * The idea is from Manfred Spraul. --macro
2431 cfg = desc->chip_data;
2434 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2438 * We must acknowledge the irq before we move it or the acknowledge will
2439 * not propagate properly.
2443 /* Now we can move and renable the irq */
2444 if (unlikely(do_unmask_irq)) {
2445 /* Only migrate the irq if the ack has been received.
2447 * On rare occasions the broadcast level triggered ack gets
2448 * delayed going to ioapics, and if we reprogram the
2449 * vector while Remote IRR is still set the irq will never
2452 * To prevent this scenario we read the Remote IRR bit
2453 * of the ioapic. This has two effects.
2454 * - On any sane system the read of the ioapic will
2455 * flush writes (and acks) going to the ioapic from
2457 * - We get to see if the ACK has actually been delivered.
2459 * Based on failed experiments of reprogramming the
2460 * ioapic entry from outside of irq context starting
2461 * with masking the ioapic entry and then polling until
2462 * Remote IRR was clear before reprogramming the
2463 * ioapic I don't trust the Remote IRR bit to be
2464 * completey accurate.
2466 * However there appears to be no other way to plug
2467 * this race, so if the Remote IRR bit is not
2468 * accurate and is causing problems then it is a hardware bug
2469 * and you can go talk to the chipset vendor about it.
2471 cfg = desc->chip_data;
2472 if (!io_apic_level_ack_pending(cfg))
2473 move_masked_irq(irq);
2474 unmask_IO_APIC_irq_desc(desc);
2477 #ifdef CONFIG_X86_32
2478 if (!(v & (1 << (i & 0x1f)))) {
2479 atomic_inc(&irq_mis_count);
2480 spin_lock(&ioapic_lock);
2481 __mask_and_edge_IO_APIC_irq(cfg);
2482 __unmask_and_level_IO_APIC_irq(cfg);
2483 spin_unlock(&ioapic_lock);
2488 static struct irq_chip ioapic_chip __read_mostly = {
2490 .startup = startup_ioapic_irq,
2491 .mask = mask_IO_APIC_irq,
2492 .unmask = unmask_IO_APIC_irq,
2493 .ack = ack_apic_edge,
2494 .eoi = ack_apic_level,
2496 .set_affinity = set_ioapic_affinity_irq,
2498 .retrigger = ioapic_retrigger_irq,
2501 #ifdef CONFIG_INTR_REMAP
2502 static struct irq_chip ir_ioapic_chip __read_mostly = {
2503 .name = "IR-IO-APIC",
2504 .startup = startup_ioapic_irq,
2505 .mask = mask_IO_APIC_irq,
2506 .unmask = unmask_IO_APIC_irq,
2507 .ack = ack_x2apic_edge,
2508 .eoi = ack_x2apic_level,
2510 .set_affinity = set_ir_ioapic_affinity_irq,
2512 .retrigger = ioapic_retrigger_irq,
2516 static inline void init_IO_APIC_traps(void)
2519 struct irq_desc *desc;
2520 struct irq_cfg *cfg;
2523 * NOTE! The local APIC isn't very good at handling
2524 * multiple interrupts at the same interrupt level.
2525 * As the interrupt level is determined by taking the
2526 * vector number and shifting that right by 4, we
2527 * want to spread these out a bit so that they don't
2528 * all fall in the same interrupt level.
2530 * Also, we've got to be careful not to trash gate
2531 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2533 for_each_irq_desc(irq, desc) {
2537 cfg = desc->chip_data;
2538 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2540 * Hmm.. We don't have an entry for this,
2541 * so default to an old-fashioned 8259
2542 * interrupt if we can..
2544 if (irq < NR_IRQS_LEGACY)
2545 make_8259A_irq(irq);
2547 /* Strange. Oh, well.. */
2548 desc->chip = &no_irq_chip;
2554 * The local APIC irq-chip implementation:
2557 static void mask_lapic_irq(unsigned int irq)
2561 v = apic_read(APIC_LVT0);
2562 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2565 static void unmask_lapic_irq(unsigned int irq)
2569 v = apic_read(APIC_LVT0);
2570 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2573 static void ack_lapic_irq(unsigned int irq)
2578 static struct irq_chip lapic_chip __read_mostly = {
2579 .name = "local-APIC",
2580 .mask = mask_lapic_irq,
2581 .unmask = unmask_lapic_irq,
2582 .ack = ack_lapic_irq,
2585 static void lapic_register_intr(int irq, struct irq_desc *desc)
2587 desc->status &= ~IRQ_LEVEL;
2588 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2592 static void __init setup_nmi(void)
2595 * Dirty trick to enable the NMI watchdog ...
2596 * We put the 8259A master into AEOI mode and
2597 * unmask on all local APICs LVT0 as NMI.
2599 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2600 * is from Maciej W. Rozycki - so we do not have to EOI from
2601 * the NMI handler or the timer interrupt.
2603 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2605 enable_NMI_through_LVT0();
2607 apic_printk(APIC_VERBOSE, " done.\n");
2611 * This looks a bit hackish but it's about the only one way of sending
2612 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2613 * not support the ExtINT mode, unfortunately. We need to send these
2614 * cycles as some i82489DX-based boards have glue logic that keeps the
2615 * 8259A interrupt line asserted until INTA. --macro
2617 static inline void __init unlock_ExtINT_logic(void)
2620 struct IO_APIC_route_entry entry0, entry1;
2621 unsigned char save_control, save_freq_select;
2623 pin = find_isa_irq_pin(8, mp_INT);
2628 apic = find_isa_irq_apic(8, mp_INT);
2634 entry0 = ioapic_read_entry(apic, pin);
2635 clear_IO_APIC_pin(apic, pin);
2637 memset(&entry1, 0, sizeof(entry1));
2639 entry1.dest_mode = 0; /* physical delivery */
2640 entry1.mask = 0; /* unmask IRQ now */
2641 entry1.dest = hard_smp_processor_id();
2642 entry1.delivery_mode = dest_ExtINT;
2643 entry1.polarity = entry0.polarity;
2647 ioapic_write_entry(apic, pin, entry1);
2649 save_control = CMOS_READ(RTC_CONTROL);
2650 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2651 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2653 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2658 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2662 CMOS_WRITE(save_control, RTC_CONTROL);
2663 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2664 clear_IO_APIC_pin(apic, pin);
2666 ioapic_write_entry(apic, pin, entry0);
2669 static int disable_timer_pin_1 __initdata;
2670 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2671 static int __init disable_timer_pin_setup(char *arg)
2673 disable_timer_pin_1 = 1;
2676 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2678 int timer_through_8259 __initdata;
2681 * This code may look a bit paranoid, but it's supposed to cooperate with
2682 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2683 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2684 * fanatically on his truly buggy board.
2686 * FIXME: really need to revamp this for all platforms.
2688 static inline void __init check_timer(void)
2690 struct irq_desc *desc = irq_to_desc(0);
2691 struct irq_cfg *cfg = desc->chip_data;
2692 int cpu = boot_cpu_id;
2693 int apic1, pin1, apic2, pin2;
2694 unsigned long flags;
2698 local_irq_save(flags);
2700 ver = apic_read(APIC_LVR);
2701 ver = GET_APIC_VERSION(ver);
2704 * get/set the timer IRQ vector:
2706 disable_8259A_irq(0);
2707 assign_irq_vector(0, cfg, TARGET_CPUS);
2710 * As IRQ0 is to be enabled in the 8259A, the virtual
2711 * wire has to be disabled in the local APIC. Also
2712 * timer interrupts need to be acknowledged manually in
2713 * the 8259A for the i82489DX when using the NMI
2714 * watchdog as that APIC treats NMIs as level-triggered.
2715 * The AEOI mode will finish them in the 8259A
2718 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2720 #ifdef CONFIG_X86_32
2721 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2724 pin1 = find_isa_irq_pin(0, mp_INT);
2725 apic1 = find_isa_irq_apic(0, mp_INT);
2726 pin2 = ioapic_i8259.pin;
2727 apic2 = ioapic_i8259.apic;
2729 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2730 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2731 cfg->vector, apic1, pin1, apic2, pin2);
2734 * Some BIOS writers are clueless and report the ExtINTA
2735 * I/O APIC input from the cascaded 8259A as the timer
2736 * interrupt input. So just in case, if only one pin
2737 * was found above, try it both directly and through the
2741 #ifdef CONFIG_INTR_REMAP
2742 if (intr_remapping_enabled)
2743 panic("BIOS bug: timer not connected to IO-APIC");
2748 } else if (pin2 == -1) {
2755 * Ok, does IRQ0 through the IOAPIC work?
2758 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2759 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2761 unmask_IO_APIC_irq_desc(desc);
2762 if (timer_irq_works()) {
2763 if (nmi_watchdog == NMI_IO_APIC) {
2765 enable_8259A_irq(0);
2767 if (disable_timer_pin_1 > 0)
2768 clear_IO_APIC_pin(0, pin1);
2771 #ifdef CONFIG_INTR_REMAP
2772 if (intr_remapping_enabled)
2773 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2775 clear_IO_APIC_pin(apic1, pin1);
2777 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2778 "8254 timer not connected to IO-APIC\n");
2780 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2781 "(IRQ0) through the 8259A ...\n");
2782 apic_printk(APIC_QUIET, KERN_INFO
2783 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2785 * legacy devices should be connected to IO APIC #0
2787 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2788 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2789 unmask_IO_APIC_irq_desc(desc);
2790 enable_8259A_irq(0);
2791 if (timer_irq_works()) {
2792 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2793 timer_through_8259 = 1;
2794 if (nmi_watchdog == NMI_IO_APIC) {
2795 disable_8259A_irq(0);
2797 enable_8259A_irq(0);
2802 * Cleanup, just in case ...
2804 disable_8259A_irq(0);
2805 clear_IO_APIC_pin(apic2, pin2);
2806 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2809 if (nmi_watchdog == NMI_IO_APIC) {
2810 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2811 "through the IO-APIC - disabling NMI Watchdog!\n");
2812 nmi_watchdog = NMI_NONE;
2814 #ifdef CONFIG_X86_32
2818 apic_printk(APIC_QUIET, KERN_INFO
2819 "...trying to set up timer as Virtual Wire IRQ...\n");
2821 lapic_register_intr(0, desc);
2822 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2823 enable_8259A_irq(0);
2825 if (timer_irq_works()) {
2826 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2829 disable_8259A_irq(0);
2830 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2831 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2833 apic_printk(APIC_QUIET, KERN_INFO
2834 "...trying to set up timer as ExtINT IRQ...\n");
2838 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2840 unlock_ExtINT_logic();
2842 if (timer_irq_works()) {
2843 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2846 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2847 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2848 "report. Then try booting with the 'noapic' option.\n");
2850 local_irq_restore(flags);
2854 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2855 * to devices. However there may be an I/O APIC pin available for
2856 * this interrupt regardless. The pin may be left unconnected, but
2857 * typically it will be reused as an ExtINT cascade interrupt for
2858 * the master 8259A. In the MPS case such a pin will normally be
2859 * reported as an ExtINT interrupt in the MP table. With ACPI
2860 * there is no provision for ExtINT interrupts, and in the absence
2861 * of an override it would be treated as an ordinary ISA I/O APIC
2862 * interrupt, that is edge-triggered and unmasked by default. We
2863 * used to do this, but it caused problems on some systems because
2864 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2865 * the same ExtINT cascade interrupt to drive the local APIC of the
2866 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2867 * the I/O APIC in all cases now. No actual device should request
2868 * it anyway. --macro
2870 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2872 void __init setup_IO_APIC(void)
2875 #ifdef CONFIG_X86_32
2879 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2883 io_apic_irqs = ~PIC_IRQS;
2885 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2887 * Set up IO-APIC IRQ routing.
2889 #ifdef CONFIG_X86_32
2891 setup_ioapic_ids_from_mpc();
2894 setup_IO_APIC_irqs();
2895 init_IO_APIC_traps();
2900 * Called after all the initialization is done. If we didnt find any
2901 * APIC bugs then we can allow the modify fast path
2904 static int __init io_apic_bug_finalize(void)
2906 if (sis_apic_bug == -1)
2911 late_initcall(io_apic_bug_finalize);
2913 struct sysfs_ioapic_data {
2914 struct sys_device dev;
2915 struct IO_APIC_route_entry entry[0];
2917 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2919 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2921 struct IO_APIC_route_entry *entry;
2922 struct sysfs_ioapic_data *data;
2925 data = container_of(dev, struct sysfs_ioapic_data, dev);
2926 entry = data->entry;
2927 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2928 *entry = ioapic_read_entry(dev->id, i);
2933 static int ioapic_resume(struct sys_device *dev)
2935 struct IO_APIC_route_entry *entry;
2936 struct sysfs_ioapic_data *data;
2937 unsigned long flags;
2938 union IO_APIC_reg_00 reg_00;
2941 data = container_of(dev, struct sysfs_ioapic_data, dev);
2942 entry = data->entry;
2944 spin_lock_irqsave(&ioapic_lock, flags);
2945 reg_00.raw = io_apic_read(dev->id, 0);
2946 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2947 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2948 io_apic_write(dev->id, 0, reg_00.raw);
2950 spin_unlock_irqrestore(&ioapic_lock, flags);
2951 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2952 ioapic_write_entry(dev->id, i, entry[i]);
2957 static struct sysdev_class ioapic_sysdev_class = {
2959 .suspend = ioapic_suspend,
2960 .resume = ioapic_resume,
2963 static int __init ioapic_init_sysfs(void)
2965 struct sys_device * dev;
2968 error = sysdev_class_register(&ioapic_sysdev_class);
2972 for (i = 0; i < nr_ioapics; i++ ) {
2973 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2974 * sizeof(struct IO_APIC_route_entry);
2975 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2976 if (!mp_ioapic_data[i]) {
2977 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2980 dev = &mp_ioapic_data[i]->dev;
2982 dev->cls = &ioapic_sysdev_class;
2983 error = sysdev_register(dev);
2985 kfree(mp_ioapic_data[i]);
2986 mp_ioapic_data[i] = NULL;
2987 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2995 device_initcall(ioapic_init_sysfs);
2998 * Dynamic irq allocate and deallocation
3000 unsigned int create_irq_nr(unsigned int irq_want)
3002 /* Allocate an unused irq */
3005 unsigned long flags;
3006 struct irq_cfg *cfg_new = NULL;
3007 int cpu = boot_cpu_id;
3008 struct irq_desc *desc_new = NULL;
3011 spin_lock_irqsave(&vector_lock, flags);
3012 for (new = irq_want; new < NR_IRQS; new++) {
3013 if (platform_legacy_irq(new))
3016 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3018 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3021 cfg_new = desc_new->chip_data;
3023 if (cfg_new->vector != 0)
3025 if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0)
3029 spin_unlock_irqrestore(&vector_lock, flags);
3032 dynamic_irq_init(irq);
3033 /* restore it, in case dynamic_irq_init clear it */
3035 desc_new->chip_data = cfg_new;
3040 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3041 int create_irq(void)
3043 unsigned int irq_want;
3046 irq_want = nr_irqs_gsi;
3047 irq = create_irq_nr(irq_want);
3055 void destroy_irq(unsigned int irq)
3057 unsigned long flags;
3058 struct irq_cfg *cfg;
3059 struct irq_desc *desc;
3061 /* store it, in case dynamic_irq_cleanup clear it */
3062 desc = irq_to_desc(irq);
3063 cfg = desc->chip_data;
3064 dynamic_irq_cleanup(irq);
3065 /* connect back irq_cfg */
3067 desc->chip_data = cfg;
3069 #ifdef CONFIG_INTR_REMAP
3072 spin_lock_irqsave(&vector_lock, flags);
3073 __clear_irq_vector(irq, cfg);
3074 spin_unlock_irqrestore(&vector_lock, flags);
3078 * MSI message composition
3080 #ifdef CONFIG_PCI_MSI
3081 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3083 struct irq_cfg *cfg;
3090 err = assign_irq_vector(irq, cfg, tmp);
3094 cpus_and(tmp, cfg->domain, tmp);
3095 dest = cpu_mask_to_apicid(tmp);
3097 #ifdef CONFIG_INTR_REMAP
3098 if (irq_remapped(irq)) {
3103 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3104 BUG_ON(ir_index == -1);
3106 memset (&irte, 0, sizeof(irte));
3109 irte.dst_mode = INT_DEST_MODE;
3110 irte.trigger_mode = 0; /* edge */
3111 irte.dlvry_mode = INT_DELIVERY_MODE;
3112 irte.vector = cfg->vector;
3113 irte.dest_id = IRTE_DEST(dest);
3115 modify_irte(irq, &irte);
3117 msg->address_hi = MSI_ADDR_BASE_HI;
3118 msg->data = sub_handle;
3119 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3121 MSI_ADDR_IR_INDEX1(ir_index) |
3122 MSI_ADDR_IR_INDEX2(ir_index);
3126 msg->address_hi = MSI_ADDR_BASE_HI;
3129 ((INT_DEST_MODE == 0) ?
3130 MSI_ADDR_DEST_MODE_PHYSICAL:
3131 MSI_ADDR_DEST_MODE_LOGICAL) |
3132 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3133 MSI_ADDR_REDIRECTION_CPU:
3134 MSI_ADDR_REDIRECTION_LOWPRI) |
3135 MSI_ADDR_DEST_ID(dest);
3138 MSI_DATA_TRIGGER_EDGE |
3139 MSI_DATA_LEVEL_ASSERT |
3140 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3141 MSI_DATA_DELIVERY_FIXED:
3142 MSI_DATA_DELIVERY_LOWPRI) |
3143 MSI_DATA_VECTOR(cfg->vector);
3149 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3151 struct irq_desc *desc = irq_to_desc(irq);
3152 struct irq_cfg *cfg;
3157 cpus_and(tmp, mask, cpu_online_map);
3158 if (cpus_empty(tmp))
3161 cfg = desc->chip_data;
3162 if (assign_irq_vector(irq, cfg, mask))
3165 set_extra_move_desc(desc, mask);
3167 cpus_and(tmp, cfg->domain, mask);
3168 dest = cpu_mask_to_apicid(tmp);
3170 read_msi_msg_desc(desc, &msg);
3172 msg.data &= ~MSI_DATA_VECTOR_MASK;
3173 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3174 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3175 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3177 write_msi_msg_desc(desc, &msg);
3178 desc->affinity = mask;
3180 #ifdef CONFIG_INTR_REMAP
3182 * Migrate the MSI irq to another cpumask. This migration is
3183 * done in the process context using interrupt-remapping hardware.
3185 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3187 struct irq_desc *desc = irq_to_desc(irq);
3188 struct irq_cfg *cfg;
3190 cpumask_t tmp, cleanup_mask;
3193 cpus_and(tmp, mask, cpu_online_map);
3194 if (cpus_empty(tmp))
3197 if (get_irte(irq, &irte))
3200 cfg = desc->chip_data;
3201 if (assign_irq_vector(irq, cfg, mask))
3204 set_extra_move_desc(desc, mask);
3206 cpus_and(tmp, cfg->domain, mask);
3207 dest = cpu_mask_to_apicid(tmp);
3209 irte.vector = cfg->vector;
3210 irte.dest_id = IRTE_DEST(dest);
3213 * atomically update the IRTE with the new destination and vector.
3215 modify_irte(irq, &irte);
3218 * After this point, all the interrupts will start arriving
3219 * at the new destination. So, time to cleanup the previous
3220 * vector allocation.
3222 if (cfg->move_in_progress) {
3223 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3224 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3225 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3226 cfg->move_in_progress = 0;
3229 desc->affinity = mask;
3233 #endif /* CONFIG_SMP */
3236 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3237 * which implement the MSI or MSI-X Capability Structure.
3239 static struct irq_chip msi_chip = {
3241 .unmask = unmask_msi_irq,
3242 .mask = mask_msi_irq,
3243 .ack = ack_apic_edge,
3245 .set_affinity = set_msi_irq_affinity,
3247 .retrigger = ioapic_retrigger_irq,
3250 #ifdef CONFIG_INTR_REMAP
3251 static struct irq_chip msi_ir_chip = {
3252 .name = "IR-PCI-MSI",
3253 .unmask = unmask_msi_irq,
3254 .mask = mask_msi_irq,
3255 .ack = ack_x2apic_edge,
3257 .set_affinity = ir_set_msi_irq_affinity,
3259 .retrigger = ioapic_retrigger_irq,
3263 * Map the PCI dev to the corresponding remapping hardware unit
3264 * and allocate 'nvec' consecutive interrupt-remapping table entries
3267 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3269 struct intel_iommu *iommu;
3272 iommu = map_dev_to_ir(dev);
3275 "Unable to map PCI %s to iommu\n", pci_name(dev));
3279 index = alloc_irte(iommu, irq, nvec);
3282 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3290 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3295 ret = msi_compose_msg(dev, irq, &msg);
3299 set_irq_msi(irq, msidesc);
3300 write_msi_msg(irq, &msg);
3302 #ifdef CONFIG_INTR_REMAP
3303 if (irq_remapped(irq)) {
3304 struct irq_desc *desc = irq_to_desc(irq);
3306 * irq migration in process context
3308 desc->status |= IRQ_MOVE_PCNTXT;
3309 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3312 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3314 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3319 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc)
3323 unsigned int irq_want;
3325 irq_want = nr_irqs_gsi;
3326 irq = create_irq_nr(irq_want);
3330 #ifdef CONFIG_INTR_REMAP
3331 if (!intr_remapping_enabled)
3334 ret = msi_alloc_irte(dev, irq, 1);
3339 ret = setup_msi_irq(dev, msidesc, irq);
3346 #ifdef CONFIG_INTR_REMAP
3353 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3356 int ret, sub_handle;
3357 struct msi_desc *msidesc;
3358 unsigned int irq_want;
3360 #ifdef CONFIG_INTR_REMAP
3361 struct intel_iommu *iommu = 0;
3365 irq_want = nr_irqs_gsi;
3367 list_for_each_entry(msidesc, &dev->msi_list, list) {
3368 irq = create_irq_nr(irq_want);
3372 #ifdef CONFIG_INTR_REMAP
3373 if (!intr_remapping_enabled)
3378 * allocate the consecutive block of IRTE's
3381 index = msi_alloc_irte(dev, irq, nvec);
3387 iommu = map_dev_to_ir(dev);
3393 * setup the mapping between the irq and the IRTE
3394 * base index, the sub_handle pointing to the
3395 * appropriate interrupt remap table entry.
3397 set_irte_irq(irq, iommu, index, sub_handle);
3401 ret = setup_msi_irq(dev, msidesc, irq);
3413 void arch_teardown_msi_irq(unsigned int irq)
3420 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3422 struct irq_desc *desc = irq_to_desc(irq);
3423 struct irq_cfg *cfg;
3428 cpus_and(tmp, mask, cpu_online_map);
3429 if (cpus_empty(tmp))
3432 cfg = desc->chip_data;
3433 if (assign_irq_vector(irq, cfg, mask))
3436 set_extra_move_desc(desc, mask);
3438 cpus_and(tmp, cfg->domain, mask);
3439 dest = cpu_mask_to_apicid(tmp);
3441 dmar_msi_read(irq, &msg);
3443 msg.data &= ~MSI_DATA_VECTOR_MASK;
3444 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3445 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3446 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3448 dmar_msi_write(irq, &msg);
3449 desc->affinity = mask;
3452 #endif /* CONFIG_SMP */
3454 struct irq_chip dmar_msi_type = {
3456 .unmask = dmar_msi_unmask,
3457 .mask = dmar_msi_mask,
3458 .ack = ack_apic_edge,
3460 .set_affinity = dmar_msi_set_affinity,
3462 .retrigger = ioapic_retrigger_irq,
3465 int arch_setup_dmar_msi(unsigned int irq)
3470 ret = msi_compose_msg(NULL, irq, &msg);
3473 dmar_msi_write(irq, &msg);
3474 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3480 #ifdef CONFIG_HPET_TIMER
3483 static void hpet_msi_set_affinity(unsigned int irq, cpumask_t mask)
3485 struct irq_desc *desc = irq_to_desc(irq);
3486 struct irq_cfg *cfg;
3491 cpus_and(tmp, mask, cpu_online_map);
3492 if (cpus_empty(tmp))
3495 cfg = desc->chip_data;
3496 if (assign_irq_vector(irq, cfg, mask))
3499 set_extra_move_desc(desc, mask);
3501 cpus_and(tmp, cfg->domain, mask);
3502 dest = cpu_mask_to_apicid(tmp);
3504 hpet_msi_read(irq, &msg);
3506 msg.data &= ~MSI_DATA_VECTOR_MASK;
3507 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3508 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3509 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3511 hpet_msi_write(irq, &msg);
3512 desc->affinity = mask;
3515 #endif /* CONFIG_SMP */
3517 struct irq_chip hpet_msi_type = {
3519 .unmask = hpet_msi_unmask,
3520 .mask = hpet_msi_mask,
3521 .ack = ack_apic_edge,
3523 .set_affinity = hpet_msi_set_affinity,
3525 .retrigger = ioapic_retrigger_irq,
3528 int arch_setup_hpet_msi(unsigned int irq)
3533 ret = msi_compose_msg(NULL, irq, &msg);
3537 hpet_msi_write(irq, &msg);
3538 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3545 #endif /* CONFIG_PCI_MSI */
3547 * Hypertransport interrupt support
3549 #ifdef CONFIG_HT_IRQ
3553 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3555 struct ht_irq_msg msg;
3556 fetch_ht_irq_msg(irq, &msg);
3558 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3559 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3561 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3562 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3564 write_ht_irq_msg(irq, &msg);
3567 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3569 struct irq_desc *desc = irq_to_desc(irq);
3570 struct irq_cfg *cfg;
3574 cpus_and(tmp, mask, cpu_online_map);
3575 if (cpus_empty(tmp))
3578 cfg = desc->chip_data;
3579 if (assign_irq_vector(irq, cfg, mask))
3582 set_extra_move_desc(desc, mask);
3584 cpus_and(tmp, cfg->domain, mask);
3585 dest = cpu_mask_to_apicid(tmp);
3587 target_ht_irq(irq, dest, cfg->vector);
3588 desc->affinity = mask;
3593 static struct irq_chip ht_irq_chip = {
3595 .mask = mask_ht_irq,
3596 .unmask = unmask_ht_irq,
3597 .ack = ack_apic_edge,
3599 .set_affinity = set_ht_irq_affinity,
3601 .retrigger = ioapic_retrigger_irq,
3604 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3606 struct irq_cfg *cfg;
3612 err = assign_irq_vector(irq, cfg, tmp);
3614 struct ht_irq_msg msg;
3617 cpus_and(tmp, cfg->domain, tmp);
3618 dest = cpu_mask_to_apicid(tmp);
3620 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3624 HT_IRQ_LOW_DEST_ID(dest) |
3625 HT_IRQ_LOW_VECTOR(cfg->vector) |
3626 ((INT_DEST_MODE == 0) ?
3627 HT_IRQ_LOW_DM_PHYSICAL :
3628 HT_IRQ_LOW_DM_LOGICAL) |
3629 HT_IRQ_LOW_RQEOI_EDGE |
3630 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3631 HT_IRQ_LOW_MT_FIXED :
3632 HT_IRQ_LOW_MT_ARBITRATED) |
3633 HT_IRQ_LOW_IRQ_MASKED;
3635 write_ht_irq_msg(irq, &msg);
3637 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3638 handle_edge_irq, "edge");
3640 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3644 #endif /* CONFIG_HT_IRQ */
3646 #ifdef CONFIG_X86_64
3648 * Re-target the irq to the specified CPU and enable the specified MMR located
3649 * on the specified blade to allow the sending of MSIs to the specified CPU.
3651 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3652 unsigned long mmr_offset)
3654 const cpumask_t *eligible_cpu = get_cpu_mask(cpu);
3655 struct irq_cfg *cfg;
3657 unsigned long mmr_value;
3658 struct uv_IO_APIC_route_entry *entry;
3659 unsigned long flags;
3664 err = assign_irq_vector(irq, cfg, *eligible_cpu);
3668 spin_lock_irqsave(&vector_lock, flags);
3669 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3671 spin_unlock_irqrestore(&vector_lock, flags);
3674 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3675 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3677 entry->vector = cfg->vector;
3678 entry->delivery_mode = INT_DELIVERY_MODE;
3679 entry->dest_mode = INT_DEST_MODE;
3680 entry->polarity = 0;
3683 entry->dest = cpu_mask_to_apicid(*eligible_cpu);
3685 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3686 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3692 * Disable the specified MMR located on the specified blade so that MSIs are
3693 * longer allowed to be sent.
3695 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3697 unsigned long mmr_value;
3698 struct uv_IO_APIC_route_entry *entry;
3702 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3703 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3707 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3708 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3710 #endif /* CONFIG_X86_64 */
3712 int __init io_apic_get_redir_entries (int ioapic)
3714 union IO_APIC_reg_01 reg_01;
3715 unsigned long flags;
3717 spin_lock_irqsave(&ioapic_lock, flags);
3718 reg_01.raw = io_apic_read(ioapic, 1);
3719 spin_unlock_irqrestore(&ioapic_lock, flags);
3721 return reg_01.bits.entries;
3724 void __init probe_nr_irqs_gsi(void)
3729 for (idx = 0; idx < nr_ioapics; idx++)
3730 nr += io_apic_get_redir_entries(idx) + 1;
3732 if (nr > nr_irqs_gsi)
3736 /* --------------------------------------------------------------------------
3737 ACPI-based IOAPIC Configuration
3738 -------------------------------------------------------------------------- */
3742 #ifdef CONFIG_X86_32
3743 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3745 union IO_APIC_reg_00 reg_00;
3746 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3748 unsigned long flags;
3752 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3753 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3754 * supports up to 16 on one shared APIC bus.
3756 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3757 * advantage of new APIC bus architecture.
3760 if (physids_empty(apic_id_map))
3761 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3763 spin_lock_irqsave(&ioapic_lock, flags);
3764 reg_00.raw = io_apic_read(ioapic, 0);
3765 spin_unlock_irqrestore(&ioapic_lock, flags);
3767 if (apic_id >= get_physical_broadcast()) {
3768 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3769 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3770 apic_id = reg_00.bits.ID;
3774 * Every APIC in a system must have a unique ID or we get lots of nice
3775 * 'stuck on smp_invalidate_needed IPI wait' messages.
3777 if (check_apicid_used(apic_id_map, apic_id)) {
3779 for (i = 0; i < get_physical_broadcast(); i++) {
3780 if (!check_apicid_used(apic_id_map, i))
3784 if (i == get_physical_broadcast())
3785 panic("Max apic_id exceeded!\n");
3787 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3788 "trying %d\n", ioapic, apic_id, i);
3793 tmp = apicid_to_cpu_present(apic_id);
3794 physids_or(apic_id_map, apic_id_map, tmp);
3796 if (reg_00.bits.ID != apic_id) {
3797 reg_00.bits.ID = apic_id;
3799 spin_lock_irqsave(&ioapic_lock, flags);
3800 io_apic_write(ioapic, 0, reg_00.raw);
3801 reg_00.raw = io_apic_read(ioapic, 0);
3802 spin_unlock_irqrestore(&ioapic_lock, flags);
3805 if (reg_00.bits.ID != apic_id) {
3806 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3811 apic_printk(APIC_VERBOSE, KERN_INFO
3812 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3817 int __init io_apic_get_version(int ioapic)
3819 union IO_APIC_reg_01 reg_01;
3820 unsigned long flags;
3822 spin_lock_irqsave(&ioapic_lock, flags);
3823 reg_01.raw = io_apic_read(ioapic, 1);
3824 spin_unlock_irqrestore(&ioapic_lock, flags);
3826 return reg_01.bits.version;
3830 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3832 struct irq_desc *desc;
3833 struct irq_cfg *cfg;
3834 int cpu = boot_cpu_id;
3836 if (!IO_APIC_IRQ(irq)) {
3837 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3842 desc = irq_to_desc_alloc_cpu(irq, cpu);
3844 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3849 * IRQs < 16 are already in the irq_2_pin[] map
3851 if (irq >= NR_IRQS_LEGACY) {
3852 cfg = desc->chip_data;
3853 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3856 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3862 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3866 if (skip_ioapic_setup)
3869 for (i = 0; i < mp_irq_entries; i++)
3870 if (mp_irqs[i].mp_irqtype == mp_INT &&
3871 mp_irqs[i].mp_srcbusirq == bus_irq)
3873 if (i >= mp_irq_entries)
3876 *trigger = irq_trigger(i);
3877 *polarity = irq_polarity(i);
3881 #endif /* CONFIG_ACPI */
3884 * This function currently is only a helper for the i386 smp boot process where
3885 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3886 * so mask in all cases should simply be TARGET_CPUS
3889 void __init setup_ioapic_dest(void)
3891 int pin, ioapic, irq, irq_entry;
3892 struct irq_desc *desc;
3893 struct irq_cfg *cfg;
3896 if (skip_ioapic_setup == 1)
3899 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3900 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3901 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3902 if (irq_entry == -1)
3904 irq = pin_2_irq(irq_entry, ioapic, pin);
3906 /* setup_IO_APIC_irqs could fail to get vector for some device
3907 * when you have too many devices, because at that time only boot
3910 desc = irq_to_desc(irq);
3911 cfg = desc->chip_data;
3913 setup_IO_APIC_irq(ioapic, pin, irq, desc,
3914 irq_trigger(irq_entry),
3915 irq_polarity(irq_entry));
3921 * Honour affinities which have been set in early boot
3924 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
3925 mask = desc->affinity;
3929 #ifdef CONFIG_INTR_REMAP
3930 if (intr_remapping_enabled)
3931 set_ir_ioapic_affinity_irq_desc(desc, mask);
3934 set_ioapic_affinity_irq_desc(desc, mask);
3941 #define IOAPIC_RESOURCE_NAME_SIZE 11
3943 static struct resource *ioapic_resources;
3945 static struct resource * __init ioapic_setup_resources(void)
3948 struct resource *res;
3952 if (nr_ioapics <= 0)
3955 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3958 mem = alloc_bootmem(n);
3962 mem += sizeof(struct resource) * nr_ioapics;
3964 for (i = 0; i < nr_ioapics; i++) {
3966 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3967 sprintf(mem, "IOAPIC %u", i);
3968 mem += IOAPIC_RESOURCE_NAME_SIZE;
3972 ioapic_resources = res;
3977 void __init ioapic_init_mappings(void)
3979 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3980 struct resource *ioapic_res;
3983 ioapic_res = ioapic_setup_resources();
3984 for (i = 0; i < nr_ioapics; i++) {
3985 if (smp_found_config) {
3986 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3987 #ifdef CONFIG_X86_32
3990 "WARNING: bogus zero IO-APIC "
3991 "address found in MPTABLE, "
3992 "disabling IO/APIC support!\n");
3993 smp_found_config = 0;
3994 skip_ioapic_setup = 1;
3995 goto fake_ioapic_page;
3999 #ifdef CONFIG_X86_32
4002 ioapic_phys = (unsigned long)
4003 alloc_bootmem_pages(PAGE_SIZE);
4004 ioapic_phys = __pa(ioapic_phys);
4006 set_fixmap_nocache(idx, ioapic_phys);
4007 apic_printk(APIC_VERBOSE,
4008 "mapped IOAPIC to %08lx (%08lx)\n",
4009 __fix_to_virt(idx), ioapic_phys);
4012 if (ioapic_res != NULL) {
4013 ioapic_res->start = ioapic_phys;
4014 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4020 static int __init ioapic_insert_resources(void)
4023 struct resource *r = ioapic_resources;
4027 "IO APIC resources could be not be allocated.\n");
4031 for (i = 0; i < nr_ioapics; i++) {
4032 insert_resource(&iomem_resource, r);
4039 /* Insert the IO APIC resources after PCI initialization has occured to handle
4040 * IO APICS that are mapped in on a BAR in PCI space. */
4041 late_initcall(ioapic_insert_resources);