2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
49 #include <asm/proto.h>
52 #include <asm/timer.h>
53 #include <asm/i8259.h>
55 #include <asm/msidef.h>
56 #include <asm/hypertransport.h>
57 #include <asm/setup.h>
58 #include <asm/irq_remapping.h>
61 #include <mach_apic.h>
62 #include <mach_apicdef.h>
64 #define __apicdebuginit(type) static type __init
67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
70 int sis_apic_bug = -1;
72 static DEFINE_SPINLOCK(ioapic_lock);
73 static DEFINE_SPINLOCK(vector_lock);
76 * # of IRQ routing registers
78 int nr_ioapic_registers[MAX_IO_APICS];
80 /* I/O APIC entries */
81 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
84 /* MP IRQ source entries */
85 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
87 /* # of MP IRQ source entries */
90 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
91 int mp_bus_id_to_type[MAX_MP_BUSSES];
94 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
96 int skip_ioapic_setup;
98 static int __init parse_noapic(char *str)
100 /* disable IO-APIC */
101 disable_ioapic_setup();
104 early_param("noapic", parse_noapic);
110 struct irq_cfg *next;
111 struct irq_pin_list *irq_2_pin;
113 cpumask_t old_domain;
114 unsigned move_cleanup_count;
116 u8 move_in_progress : 1;
119 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
120 static struct irq_cfg irq_cfg_legacy[] __initdata = {
121 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
122 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
123 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
124 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
125 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
126 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
127 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
128 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
129 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
130 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
131 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
132 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
133 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
134 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
135 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
136 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
139 static struct irq_cfg irq_cfg_init = { .irq = -1U, };
140 /* need to be biger than size of irq_cfg_legacy */
141 static int nr_irq_cfg = 32;
143 static int __init parse_nr_irq_cfg(char *arg)
146 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
153 early_param("nr_irq_cfg", parse_nr_irq_cfg);
155 static void init_one_irq_cfg(struct irq_cfg *cfg)
157 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
160 static struct irq_cfg *irq_cfgx;
161 static struct irq_cfg *irq_cfgx_free;
162 static void __init init_work(void *data)
164 struct dyn_array *da = data;
171 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
173 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
174 for (i = legacy_count; i < *da->nr; i++)
175 init_one_irq_cfg(&cfg[i]);
177 for (i = 1; i < *da->nr; i++)
178 cfg[i-1].next = &cfg[i];
180 irq_cfgx_free = &irq_cfgx[legacy_count];
181 irq_cfgx[legacy_count - 1].next = NULL;
184 #define for_each_irq_cfg(cfg) \
185 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
187 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
189 static struct irq_cfg *irq_cfg(unsigned int irq)
204 static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
206 struct irq_cfg *cfg, *cfg_pri;
210 cfg_pri = cfg = irq_cfgx;
220 if (!irq_cfgx_free) {
222 unsigned long total_bytes;
224 * we run out of pre-allocate ones, allocate more
226 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
228 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
230 cfg = kzalloc(total_bytes, GFP_ATOMIC);
232 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
235 panic("please boot with nr_irq_cfg= %d\n", count * 2);
238 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
240 for (i = 0; i < nr_irq_cfg; i++)
241 init_one_irq_cfg(&cfg[i]);
243 for (i = 1; i < nr_irq_cfg; i++)
244 cfg[i-1].next = &cfg[i];
250 irq_cfgx_free = irq_cfgx_free->next;
257 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
258 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
260 /* dump the results */
263 unsigned long bytes = sizeof(struct irq_cfg);
265 printk(KERN_DEBUG "=========================== %d\n", irq);
266 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
267 for_each_irq_cfg(cfg) {
269 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
271 printk(KERN_DEBUG "===========================\n");
278 * This is performance-critical, we want to do it O(1)
280 * the indexing order of this array favors 1:1 mappings
281 * between pins and IRQs.
284 struct irq_pin_list {
286 struct irq_pin_list *next;
289 static struct irq_pin_list *irq_2_pin_head;
290 /* fill one page ? */
291 static int nr_irq_2_pin = 0x100;
292 static struct irq_pin_list *irq_2_pin_ptr;
293 static void __init irq_2_pin_init_work(void *data)
295 struct dyn_array *da = data;
296 struct irq_pin_list *pin;
301 for (i = 1; i < *da->nr; i++)
302 pin[i-1].next = &pin[i];
304 irq_2_pin_ptr = &pin[0];
306 DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
308 static struct irq_pin_list *get_one_free_irq_2_pin(void)
310 struct irq_pin_list *pin;
316 irq_2_pin_ptr = pin->next;
322 * we run out of pre-allocate ones, allocate more
324 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
327 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
330 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
331 nr_irq_2_pin, PAGE_SIZE, 0);
334 panic("can not get more irq_2_pin\n");
336 for (i = 1; i < nr_irq_2_pin; i++)
337 pin[i-1].next = &pin[i];
339 irq_2_pin_ptr = pin->next;
347 unsigned int unused[3];
351 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
353 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
354 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
357 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
359 struct io_apic __iomem *io_apic = io_apic_base(apic);
360 writel(reg, &io_apic->index);
361 return readl(&io_apic->data);
364 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
366 struct io_apic __iomem *io_apic = io_apic_base(apic);
367 writel(reg, &io_apic->index);
368 writel(value, &io_apic->data);
372 * Re-write a value: to be used for read-modify-write
373 * cycles where the read already set up the index register.
375 * Older SiS APIC requires we rewrite the index register
377 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
379 struct io_apic __iomem *io_apic = io_apic_base(apic);
381 writel(reg, &io_apic->index);
382 writel(value, &io_apic->data);
385 static bool io_apic_level_ack_pending(unsigned int irq)
387 struct irq_pin_list *entry;
389 struct irq_cfg *cfg = irq_cfg(irq);
391 spin_lock_irqsave(&ioapic_lock, flags);
392 entry = cfg->irq_2_pin;
400 reg = io_apic_read(entry->apic, 0x10 + pin*2);
401 /* Is the remote IRR bit set? */
402 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
403 spin_unlock_irqrestore(&ioapic_lock, flags);
410 spin_unlock_irqrestore(&ioapic_lock, flags);
416 struct { u32 w1, w2; };
417 struct IO_APIC_route_entry entry;
420 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
422 union entry_union eu;
424 spin_lock_irqsave(&ioapic_lock, flags);
425 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
426 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
427 spin_unlock_irqrestore(&ioapic_lock, flags);
432 * When we write a new IO APIC routing entry, we need to write the high
433 * word first! If the mask bit in the low word is clear, we will enable
434 * the interrupt, and we need to make sure the entry is fully populated
435 * before that happens.
438 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
440 union entry_union eu;
442 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
443 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
446 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
449 spin_lock_irqsave(&ioapic_lock, flags);
450 __ioapic_write_entry(apic, pin, e);
451 spin_unlock_irqrestore(&ioapic_lock, flags);
455 * When we mask an IO APIC routing entry, we need to write the low
456 * word first, in order to set the mask bit before we change the
459 static void ioapic_mask_entry(int apic, int pin)
462 union entry_union eu = { .entry.mask = 1 };
464 spin_lock_irqsave(&ioapic_lock, flags);
465 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
466 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
467 spin_unlock_irqrestore(&ioapic_lock, flags);
471 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
475 struct irq_pin_list *entry;
478 entry = cfg->irq_2_pin;
487 #ifdef CONFIG_INTR_REMAP
489 * With interrupt-remapping, destination information comes
490 * from interrupt-remapping table entry.
492 if (!irq_remapped(irq))
493 io_apic_write(apic, 0x11 + pin*2, dest);
495 io_apic_write(apic, 0x11 + pin*2, dest);
497 reg = io_apic_read(apic, 0x10 + pin*2);
498 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
500 io_apic_modify(apic, 0x10 + pin*2, reg);
507 static int assign_irq_vector(int irq, cpumask_t mask);
509 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
515 struct irq_desc *desc;
517 cpus_and(tmp, mask, cpu_online_map);
522 if (assign_irq_vector(irq, mask))
525 cpus_and(tmp, cfg->domain, mask);
526 dest = cpu_mask_to_apicid(tmp);
528 * Only the high 8 bits are valid.
530 dest = SET_APIC_LOGICAL_ID(dest);
532 desc = irq_to_desc(irq);
533 spin_lock_irqsave(&ioapic_lock, flags);
534 __target_IO_APIC_irq(irq, dest, cfg->vector);
535 desc->affinity = mask;
536 spin_unlock_irqrestore(&ioapic_lock, flags);
538 #endif /* CONFIG_SMP */
541 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
542 * shared ISA-space IRQs, so we have to support them. We are super
543 * fast in the common case, and fast for shared ISA-space IRQs.
545 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
548 struct irq_pin_list *entry;
550 /* first time to refer irq_cfg, so with new */
551 cfg = irq_cfg_alloc(irq);
552 entry = cfg->irq_2_pin;
554 entry = get_one_free_irq_2_pin();
555 cfg->irq_2_pin = entry;
558 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
562 while (entry->next) {
563 /* not again, please */
564 if (entry->apic == apic && entry->pin == pin)
570 entry->next = get_one_free_irq_2_pin();
574 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
578 * Reroute an IRQ to a different pin.
580 static void __init replace_pin_at_irq(unsigned int irq,
581 int oldapic, int oldpin,
582 int newapic, int newpin)
584 struct irq_cfg *cfg = irq_cfg(irq);
585 struct irq_pin_list *entry = cfg->irq_2_pin;
589 if (entry->apic == oldapic && entry->pin == oldpin) {
590 entry->apic = newapic;
593 /* every one is different, right? */
599 /* why? call replace before add? */
601 add_pin_to_irq(irq, newapic, newpin);
604 #define __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
608 struct irq_cfg *cfg; \
609 struct irq_pin_list *entry; \
611 cfg = irq_cfg(irq); \
612 entry = cfg->irq_2_pin; \
618 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
619 reg ACTION_DISABLE; \
621 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
625 entry = entry->next; \
629 #define DO_ACTION(name,R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
631 static void name##_IO_APIC_irq (unsigned int irq) \
632 __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL)
635 DO_ACTION(__unmask, 0, |= 0, &= ~IO_APIC_REDIR_MASKED, )
639 * Synchronize the IO-APIC and the CPU by doing
640 * a dummy read from the IO-APIC
642 static inline void io_apic_sync(unsigned int apic)
644 struct io_apic __iomem *io_apic = io_apic_base(apic);
645 readl(&io_apic->data);
649 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, io_apic_sync(entry->apic))
654 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, )
656 /* mask = 1, trigger = 0 */
657 DO_ACTION(__mask_and_edge, 0, |= IO_APIC_REDIR_MASKED, &= ~IO_APIC_REDIR_LEVEL_TRIGGER, )
659 /* mask = 0, trigger = 1 */
660 DO_ACTION(__unmask_and_level, 0, |= IO_APIC_REDIR_LEVEL_TRIGGER, &= ~IO_APIC_REDIR_MASKED, )
664 static void mask_IO_APIC_irq (unsigned int irq)
668 spin_lock_irqsave(&ioapic_lock, flags);
669 __mask_IO_APIC_irq(irq);
670 spin_unlock_irqrestore(&ioapic_lock, flags);
673 static void unmask_IO_APIC_irq (unsigned int irq)
677 spin_lock_irqsave(&ioapic_lock, flags);
678 __unmask_IO_APIC_irq(irq);
679 spin_unlock_irqrestore(&ioapic_lock, flags);
682 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
684 struct IO_APIC_route_entry entry;
686 /* Check delivery_mode to be sure we're not clearing an SMI pin */
687 entry = ioapic_read_entry(apic, pin);
688 if (entry.delivery_mode == dest_SMI)
691 * Disable it in the IO-APIC irq-routing table:
693 ioapic_mask_entry(apic, pin);
696 static void clear_IO_APIC (void)
700 for (apic = 0; apic < nr_ioapics; apic++)
701 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
702 clear_IO_APIC_pin(apic, pin);
705 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
706 void send_IPI_self(int vector)
713 apic_wait_icr_idle();
714 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
716 * Send the IPI. The write to APIC_ICR fires this off.
718 apic_write(APIC_ICR, cfg);
720 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
724 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
725 * specific CPU-side IRQs.
729 static int pirq_entries [MAX_PIRQS];
730 static int pirqs_enabled;
732 static int __init ioapic_pirq_setup(char *str)
735 int ints[MAX_PIRQS+1];
737 get_options(str, ARRAY_SIZE(ints), ints);
739 for (i = 0; i < MAX_PIRQS; i++)
740 pirq_entries[i] = -1;
743 apic_printk(APIC_VERBOSE, KERN_INFO
744 "PIRQ redirection, working around broken MP-BIOS.\n");
746 if (ints[0] < MAX_PIRQS)
749 for (i = 0; i < max; i++) {
750 apic_printk(APIC_VERBOSE, KERN_DEBUG
751 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
753 * PIRQs are mapped upside down, usually.
755 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
760 __setup("pirq=", ioapic_pirq_setup);
761 #endif /* CONFIG_X86_32 */
763 #ifdef CONFIG_INTR_REMAP
764 /* I/O APIC RTE contents at the OS boot up */
765 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
768 * Saves and masks all the unmasked IO-APIC RTE's
770 int save_mask_IO_APIC_setup(void)
772 union IO_APIC_reg_01 reg_01;
777 * The number of IO-APIC IRQ registers (== #pins):
779 for (apic = 0; apic < nr_ioapics; apic++) {
780 spin_lock_irqsave(&ioapic_lock, flags);
781 reg_01.raw = io_apic_read(apic, 1);
782 spin_unlock_irqrestore(&ioapic_lock, flags);
783 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
786 for (apic = 0; apic < nr_ioapics; apic++) {
787 early_ioapic_entries[apic] =
788 kzalloc(sizeof(struct IO_APIC_route_entry) *
789 nr_ioapic_registers[apic], GFP_KERNEL);
790 if (!early_ioapic_entries[apic])
794 for (apic = 0; apic < nr_ioapics; apic++)
795 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
796 struct IO_APIC_route_entry entry;
798 entry = early_ioapic_entries[apic][pin] =
799 ioapic_read_entry(apic, pin);
802 ioapic_write_entry(apic, pin, entry);
808 void restore_IO_APIC_setup(void)
812 for (apic = 0; apic < nr_ioapics; apic++)
813 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
814 ioapic_write_entry(apic, pin,
815 early_ioapic_entries[apic][pin]);
818 void reinit_intr_remapped_IO_APIC(int intr_remapping)
821 * for now plain restore of previous settings.
822 * TBD: In the case of OS enabling interrupt-remapping,
823 * IO-APIC RTE's need to be setup to point to interrupt-remapping
824 * table entries. for now, do a plain restore, and wait for
825 * the setup_IO_APIC_irqs() to do proper initialization.
827 restore_IO_APIC_setup();
832 * Find the IRQ entry number of a certain pin.
834 static int find_irq_entry(int apic, int pin, int type)
838 for (i = 0; i < mp_irq_entries; i++)
839 if (mp_irqs[i].mp_irqtype == type &&
840 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
841 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
842 mp_irqs[i].mp_dstirq == pin)
849 * Find the pin to which IRQ[irq] (ISA) is connected
851 static int __init find_isa_irq_pin(int irq, int type)
855 for (i = 0; i < mp_irq_entries; i++) {
856 int lbus = mp_irqs[i].mp_srcbus;
858 if (test_bit(lbus, mp_bus_not_pci) &&
859 (mp_irqs[i].mp_irqtype == type) &&
860 (mp_irqs[i].mp_srcbusirq == irq))
862 return mp_irqs[i].mp_dstirq;
867 static int __init find_isa_irq_apic(int irq, int type)
871 for (i = 0; i < mp_irq_entries; i++) {
872 int lbus = mp_irqs[i].mp_srcbus;
874 if (test_bit(lbus, mp_bus_not_pci) &&
875 (mp_irqs[i].mp_irqtype == type) &&
876 (mp_irqs[i].mp_srcbusirq == irq))
879 if (i < mp_irq_entries) {
881 for(apic = 0; apic < nr_ioapics; apic++) {
882 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
891 * Find a specific PCI IRQ entry.
892 * Not an __init, possibly needed by modules
894 static int pin_2_irq(int idx, int apic, int pin);
896 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
898 int apic, i, best_guess = -1;
900 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
902 if (test_bit(bus, mp_bus_not_pci)) {
903 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
906 for (i = 0; i < mp_irq_entries; i++) {
907 int lbus = mp_irqs[i].mp_srcbus;
909 for (apic = 0; apic < nr_ioapics; apic++)
910 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
911 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
914 if (!test_bit(lbus, mp_bus_not_pci) &&
915 !mp_irqs[i].mp_irqtype &&
917 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
918 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
920 if (!(apic || IO_APIC_IRQ(irq)))
923 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
926 * Use the first all-but-pin matching entry as a
927 * best-guess fuzzy result for broken mptables.
936 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
938 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
940 * EISA Edge/Level control register, ELCR
942 static int EISA_ELCR(unsigned int irq)
945 unsigned int port = 0x4d0 + (irq >> 3);
946 return (inb(port) >> (irq & 7)) & 1;
948 apic_printk(APIC_VERBOSE, KERN_INFO
949 "Broken MPtable reports ISA irq %d\n", irq);
955 /* ISA interrupts are always polarity zero edge triggered,
956 * when listed as conforming in the MP table. */
958 #define default_ISA_trigger(idx) (0)
959 #define default_ISA_polarity(idx) (0)
961 /* EISA interrupts are always polarity zero and can be edge or level
962 * trigger depending on the ELCR value. If an interrupt is listed as
963 * EISA conforming in the MP table, that means its trigger type must
964 * be read in from the ELCR */
966 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
967 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
969 /* PCI interrupts are always polarity one level triggered,
970 * when listed as conforming in the MP table. */
972 #define default_PCI_trigger(idx) (1)
973 #define default_PCI_polarity(idx) (1)
975 /* MCA interrupts are always polarity zero level triggered,
976 * when listed as conforming in the MP table. */
978 #define default_MCA_trigger(idx) (1)
979 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
981 static int MPBIOS_polarity(int idx)
983 int bus = mp_irqs[idx].mp_srcbus;
987 * Determine IRQ line polarity (high active or low active):
989 switch (mp_irqs[idx].mp_irqflag & 3)
991 case 0: /* conforms, ie. bus-type dependent polarity */
992 if (test_bit(bus, mp_bus_not_pci))
993 polarity = default_ISA_polarity(idx);
995 polarity = default_PCI_polarity(idx);
997 case 1: /* high active */
1002 case 2: /* reserved */
1004 printk(KERN_WARNING "broken BIOS!!\n");
1008 case 3: /* low active */
1013 default: /* invalid */
1015 printk(KERN_WARNING "broken BIOS!!\n");
1023 static int MPBIOS_trigger(int idx)
1025 int bus = mp_irqs[idx].mp_srcbus;
1029 * Determine IRQ trigger mode (edge or level sensitive):
1031 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1033 case 0: /* conforms, ie. bus-type dependent */
1034 if (test_bit(bus, mp_bus_not_pci))
1035 trigger = default_ISA_trigger(idx);
1037 trigger = default_PCI_trigger(idx);
1038 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1039 switch (mp_bus_id_to_type[bus]) {
1040 case MP_BUS_ISA: /* ISA pin */
1042 /* set before the switch */
1045 case MP_BUS_EISA: /* EISA pin */
1047 trigger = default_EISA_trigger(idx);
1050 case MP_BUS_PCI: /* PCI pin */
1052 /* set before the switch */
1055 case MP_BUS_MCA: /* MCA pin */
1057 trigger = default_MCA_trigger(idx);
1062 printk(KERN_WARNING "broken BIOS!!\n");
1074 case 2: /* reserved */
1076 printk(KERN_WARNING "broken BIOS!!\n");
1085 default: /* invalid */
1087 printk(KERN_WARNING "broken BIOS!!\n");
1095 static inline int irq_polarity(int idx)
1097 return MPBIOS_polarity(idx);
1100 static inline int irq_trigger(int idx)
1102 return MPBIOS_trigger(idx);
1105 int (*ioapic_renumber_irq)(int ioapic, int irq);
1106 static int pin_2_irq(int idx, int apic, int pin)
1109 int bus = mp_irqs[idx].mp_srcbus;
1112 * Debugging check, we are in big trouble if this message pops up!
1114 if (mp_irqs[idx].mp_dstirq != pin)
1115 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1117 if (test_bit(bus, mp_bus_not_pci)) {
1118 irq = mp_irqs[idx].mp_srcbusirq;
1121 * PCI IRQs are mapped in order
1125 irq += nr_ioapic_registers[i++];
1128 * For MPS mode, so far only needed by ES7000 platform
1130 if (ioapic_renumber_irq)
1131 irq = ioapic_renumber_irq(apic, irq);
1134 #ifdef CONFIG_X86_32
1136 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1138 if ((pin >= 16) && (pin <= 23)) {
1139 if (pirq_entries[pin-16] != -1) {
1140 if (!pirq_entries[pin-16]) {
1141 apic_printk(APIC_VERBOSE, KERN_DEBUG
1142 "disabling PIRQ%d\n", pin-16);
1144 irq = pirq_entries[pin-16];
1145 apic_printk(APIC_VERBOSE, KERN_DEBUG
1146 "using PIRQ%d -> IRQ %d\n",
1156 void lock_vector_lock(void)
1158 /* Used to the online set of cpus does not change
1159 * during assign_irq_vector.
1161 spin_lock(&vector_lock);
1164 void unlock_vector_lock(void)
1166 spin_unlock(&vector_lock);
1169 static int __assign_irq_vector(int irq, cpumask_t mask)
1172 * NOTE! The local APIC isn't very good at handling
1173 * multiple interrupts at the same interrupt level.
1174 * As the interrupt level is determined by taking the
1175 * vector number and shifting that right by 4, we
1176 * want to spread these out a bit so that they don't
1177 * all fall in the same interrupt level.
1179 * Also, we've got to be careful not to trash gate
1180 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1182 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1183 unsigned int old_vector;
1185 struct irq_cfg *cfg;
1189 /* Only try and allocate irqs on cpus that are present */
1190 cpus_and(mask, mask, cpu_online_map);
1192 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1195 old_vector = cfg->vector;
1198 cpus_and(tmp, cfg->domain, mask);
1199 if (!cpus_empty(tmp))
1203 for_each_cpu_mask_nr(cpu, mask) {
1204 cpumask_t domain, new_mask;
1208 domain = vector_allocation_domain(cpu);
1209 cpus_and(new_mask, domain, cpu_online_map);
1211 vector = current_vector;
1212 offset = current_offset;
1215 if (vector >= first_system_vector) {
1216 /* If we run out of vectors on large boxen, must share them. */
1217 offset = (offset + 1) % 8;
1218 vector = FIRST_DEVICE_VECTOR + offset;
1220 if (unlikely(current_vector == vector))
1222 #ifdef CONFIG_X86_64
1223 if (vector == IA32_SYSCALL_VECTOR)
1226 if (vector == SYSCALL_VECTOR)
1229 for_each_cpu_mask_nr(new_cpu, new_mask)
1230 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1233 current_vector = vector;
1234 current_offset = offset;
1236 cfg->move_in_progress = 1;
1237 cfg->old_domain = cfg->domain;
1239 for_each_cpu_mask_nr(new_cpu, new_mask)
1240 per_cpu(vector_irq, new_cpu)[vector] = irq;
1241 cfg->vector = vector;
1242 cfg->domain = domain;
1248 static int assign_irq_vector(int irq, cpumask_t mask)
1251 unsigned long flags;
1253 spin_lock_irqsave(&vector_lock, flags);
1254 err = __assign_irq_vector(irq, mask);
1255 spin_unlock_irqrestore(&vector_lock, flags);
1259 static void __clear_irq_vector(int irq)
1261 struct irq_cfg *cfg;
1266 BUG_ON(!cfg->vector);
1268 vector = cfg->vector;
1269 cpus_and(mask, cfg->domain, cpu_online_map);
1270 for_each_cpu_mask_nr(cpu, mask)
1271 per_cpu(vector_irq, cpu)[vector] = -1;
1274 cpus_clear(cfg->domain);
1277 void __setup_vector_irq(int cpu)
1279 /* Initialize vector_irq on a new cpu */
1280 /* This function must be called with vector_lock held */
1282 struct irq_cfg *cfg;
1284 /* Mark the inuse vectors */
1285 for_each_irq_cfg(cfg) {
1286 if (!cpu_isset(cpu, cfg->domain))
1288 vector = cfg->vector;
1290 per_cpu(vector_irq, cpu)[vector] = irq;
1292 /* Mark the free vectors */
1293 for (vector = 0; vector < NR_VECTORS; ++vector) {
1294 irq = per_cpu(vector_irq, cpu)[vector];
1299 if (!cpu_isset(cpu, cfg->domain))
1300 per_cpu(vector_irq, cpu)[vector] = -1;
1304 static struct irq_chip ioapic_chip;
1305 #ifdef CONFIG_INTR_REMAP
1306 static struct irq_chip ir_ioapic_chip;
1309 #define IOAPIC_AUTO -1
1310 #define IOAPIC_EDGE 0
1311 #define IOAPIC_LEVEL 1
1313 #ifdef CONFIG_X86_32
1314 static inline int IO_APIC_irq_trigger(int irq)
1318 for (apic = 0; apic < nr_ioapics; apic++) {
1319 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1320 idx = find_irq_entry(apic, pin, mp_INT);
1321 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1322 return irq_trigger(idx);
1326 * nonexistent IRQs are edge default
1331 static inline int IO_APIC_irq_trigger(int irq)
1337 static void ioapic_register_intr(int irq, unsigned long trigger)
1339 struct irq_desc *desc;
1341 /* first time to use this irq_desc */
1343 desc = irq_to_desc(irq);
1345 desc = irq_to_desc_alloc(irq);
1347 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1348 trigger == IOAPIC_LEVEL)
1349 desc->status |= IRQ_LEVEL;
1351 desc->status &= ~IRQ_LEVEL;
1353 #ifdef CONFIG_INTR_REMAP
1354 if (irq_remapped(irq)) {
1355 desc->status |= IRQ_MOVE_PCNTXT;
1357 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1361 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1362 handle_edge_irq, "edge");
1366 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1367 trigger == IOAPIC_LEVEL)
1368 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1372 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1373 handle_edge_irq, "edge");
1376 static int setup_ioapic_entry(int apic, int irq,
1377 struct IO_APIC_route_entry *entry,
1378 unsigned int destination, int trigger,
1379 int polarity, int vector)
1382 * add it to the IO-APIC irq-routing table:
1384 memset(entry,0,sizeof(*entry));
1386 #ifdef CONFIG_INTR_REMAP
1387 if (intr_remapping_enabled) {
1388 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1390 struct IR_IO_APIC_route_entry *ir_entry =
1391 (struct IR_IO_APIC_route_entry *) entry;
1395 panic("No mapping iommu for ioapic %d\n", apic);
1397 index = alloc_irte(iommu, irq, 1);
1399 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1401 memset(&irte, 0, sizeof(irte));
1404 irte.dst_mode = INT_DEST_MODE;
1405 irte.trigger_mode = trigger;
1406 irte.dlvry_mode = INT_DELIVERY_MODE;
1407 irte.vector = vector;
1408 irte.dest_id = IRTE_DEST(destination);
1410 modify_irte(irq, &irte);
1412 ir_entry->index2 = (index >> 15) & 0x1;
1414 ir_entry->format = 1;
1415 ir_entry->index = (index & 0x7fff);
1419 entry->delivery_mode = INT_DELIVERY_MODE;
1420 entry->dest_mode = INT_DEST_MODE;
1421 entry->dest = destination;
1424 entry->mask = 0; /* enable IRQ */
1425 entry->trigger = trigger;
1426 entry->polarity = polarity;
1427 entry->vector = vector;
1429 /* Mask level triggered irqs.
1430 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1437 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1438 int trigger, int polarity)
1440 struct irq_cfg *cfg;
1441 struct IO_APIC_route_entry entry;
1444 if (!IO_APIC_IRQ(irq))
1450 if (assign_irq_vector(irq, mask))
1453 cpus_and(mask, cfg->domain, mask);
1455 apic_printk(APIC_VERBOSE,KERN_DEBUG
1456 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1457 "IRQ %d Mode:%i Active:%i)\n",
1458 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1459 irq, trigger, polarity);
1462 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1463 cpu_mask_to_apicid(mask), trigger, polarity,
1465 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1466 mp_ioapics[apic].mp_apicid, pin);
1467 __clear_irq_vector(irq);
1471 ioapic_register_intr(irq, trigger);
1473 disable_8259A_irq(irq);
1475 ioapic_write_entry(apic, pin, entry);
1478 static void __init setup_IO_APIC_irqs(void)
1480 int apic, pin, idx, irq, first_notcon = 1;
1482 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1484 for (apic = 0; apic < nr_ioapics; apic++) {
1485 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1487 idx = find_irq_entry(apic,pin,mp_INT);
1490 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1493 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1496 if (!first_notcon) {
1497 apic_printk(APIC_VERBOSE, " not connected.\n");
1501 irq = pin_2_irq(idx, apic, pin);
1502 #ifdef CONFIG_X86_32
1503 if (multi_timer_check(apic, irq))
1506 add_pin_to_irq(irq, apic, pin);
1508 setup_IO_APIC_irq(apic, pin, irq,
1509 irq_trigger(idx), irq_polarity(idx));
1514 apic_printk(APIC_VERBOSE, " not connected.\n");
1518 * Set up the timer pin, possibly with the 8259A-master behind.
1520 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1523 struct IO_APIC_route_entry entry;
1525 #ifdef CONFIG_INTR_REMAP
1526 if (intr_remapping_enabled)
1530 memset(&entry, 0, sizeof(entry));
1533 * We use logical delivery to get the timer IRQ
1536 entry.dest_mode = INT_DEST_MODE;
1537 entry.mask = 1; /* mask IRQ now */
1538 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1539 entry.delivery_mode = INT_DELIVERY_MODE;
1542 entry.vector = vector;
1545 * The timer IRQ doesn't have to know that behind the
1546 * scene we may have a 8259A-master in AEOI mode ...
1548 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1551 * Add it to the IO-APIC irq-routing table:
1553 ioapic_write_entry(apic, pin, entry);
1557 __apicdebuginit(void) print_IO_APIC(void)
1560 union IO_APIC_reg_00 reg_00;
1561 union IO_APIC_reg_01 reg_01;
1562 union IO_APIC_reg_02 reg_02;
1563 union IO_APIC_reg_03 reg_03;
1564 unsigned long flags;
1565 struct irq_cfg *cfg;
1567 if (apic_verbosity == APIC_QUIET)
1570 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1571 for (i = 0; i < nr_ioapics; i++)
1572 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1573 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1576 * We are a bit conservative about what we expect. We have to
1577 * know about every hardware change ASAP.
1579 printk(KERN_INFO "testing the IO APIC.......................\n");
1581 for (apic = 0; apic < nr_ioapics; apic++) {
1583 spin_lock_irqsave(&ioapic_lock, flags);
1584 reg_00.raw = io_apic_read(apic, 0);
1585 reg_01.raw = io_apic_read(apic, 1);
1586 if (reg_01.bits.version >= 0x10)
1587 reg_02.raw = io_apic_read(apic, 2);
1588 if (reg_01.bits.version >= 0x20)
1589 reg_03.raw = io_apic_read(apic, 3);
1590 spin_unlock_irqrestore(&ioapic_lock, flags);
1593 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1594 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1595 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1596 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1597 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1599 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1600 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1602 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1603 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1606 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1607 * but the value of reg_02 is read as the previous read register
1608 * value, so ignore it if reg_02 == reg_01.
1610 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1611 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1612 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1616 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1617 * or reg_03, but the value of reg_0[23] is read as the previous read
1618 * register value, so ignore it if reg_03 == reg_0[12].
1620 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1621 reg_03.raw != reg_01.raw) {
1622 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1623 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1626 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1628 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1629 " Stat Dmod Deli Vect: \n");
1631 for (i = 0; i <= reg_01.bits.entries; i++) {
1632 struct IO_APIC_route_entry entry;
1634 entry = ioapic_read_entry(apic, i);
1636 printk(KERN_DEBUG " %02x %03X ",
1641 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1646 entry.delivery_status,
1648 entry.delivery_mode,
1653 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1654 for_each_irq_cfg(cfg) {
1655 struct irq_pin_list *entry = cfg->irq_2_pin;
1658 printk(KERN_DEBUG "IRQ%d ", cfg->irq);
1660 printk("-> %d:%d", entry->apic, entry->pin);
1663 entry = entry->next;
1668 printk(KERN_INFO ".................................... done.\n");
1673 __apicdebuginit(void) print_APIC_bitfield(int base)
1678 if (apic_verbosity == APIC_QUIET)
1681 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1682 for (i = 0; i < 8; i++) {
1683 v = apic_read(base + i*0x10);
1684 for (j = 0; j < 32; j++) {
1694 __apicdebuginit(void) print_local_APIC(void *dummy)
1696 unsigned int v, ver, maxlvt;
1699 if (apic_verbosity == APIC_QUIET)
1702 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1703 smp_processor_id(), hard_smp_processor_id());
1704 v = apic_read(APIC_ID);
1705 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1706 v = apic_read(APIC_LVR);
1707 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1708 ver = GET_APIC_VERSION(v);
1709 maxlvt = lapic_get_maxlvt();
1711 v = apic_read(APIC_TASKPRI);
1712 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1714 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1715 v = apic_read(APIC_ARBPRI);
1716 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1717 v & APIC_ARBPRI_MASK);
1718 v = apic_read(APIC_PROCPRI);
1719 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1722 v = apic_read(APIC_EOI);
1723 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1724 v = apic_read(APIC_RRR);
1725 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1726 v = apic_read(APIC_LDR);
1727 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1728 v = apic_read(APIC_DFR);
1729 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1730 v = apic_read(APIC_SPIV);
1731 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1733 printk(KERN_DEBUG "... APIC ISR field:\n");
1734 print_APIC_bitfield(APIC_ISR);
1735 printk(KERN_DEBUG "... APIC TMR field:\n");
1736 print_APIC_bitfield(APIC_TMR);
1737 printk(KERN_DEBUG "... APIC IRR field:\n");
1738 print_APIC_bitfield(APIC_IRR);
1740 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1741 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1742 apic_write(APIC_ESR, 0);
1744 v = apic_read(APIC_ESR);
1745 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1748 icr = apic_icr_read();
1749 printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
1750 printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
1752 v = apic_read(APIC_LVTT);
1753 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1755 if (maxlvt > 3) { /* PC is LVT#4. */
1756 v = apic_read(APIC_LVTPC);
1757 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1759 v = apic_read(APIC_LVT0);
1760 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1761 v = apic_read(APIC_LVT1);
1762 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1764 if (maxlvt > 2) { /* ERR is LVT#3. */
1765 v = apic_read(APIC_LVTERR);
1766 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1769 v = apic_read(APIC_TMICT);
1770 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1771 v = apic_read(APIC_TMCCT);
1772 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1773 v = apic_read(APIC_TDCR);
1774 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1778 __apicdebuginit(void) print_all_local_APICs(void)
1780 on_each_cpu(print_local_APIC, NULL, 1);
1783 __apicdebuginit(void) print_PIC(void)
1786 unsigned long flags;
1788 if (apic_verbosity == APIC_QUIET)
1791 printk(KERN_DEBUG "\nprinting PIC contents\n");
1793 spin_lock_irqsave(&i8259A_lock, flags);
1795 v = inb(0xa1) << 8 | inb(0x21);
1796 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1798 v = inb(0xa0) << 8 | inb(0x20);
1799 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1803 v = inb(0xa0) << 8 | inb(0x20);
1807 spin_unlock_irqrestore(&i8259A_lock, flags);
1809 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1811 v = inb(0x4d1) << 8 | inb(0x4d0);
1812 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1815 __apicdebuginit(int) print_all_ICs(void)
1818 print_all_local_APICs();
1824 fs_initcall(print_all_ICs);
1827 /* Where if anywhere is the i8259 connect in external int mode */
1828 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1830 void __init enable_IO_APIC(void)
1832 union IO_APIC_reg_01 reg_01;
1833 int i8259_apic, i8259_pin;
1835 unsigned long flags;
1837 #ifdef CONFIG_X86_32
1840 for (i = 0; i < MAX_PIRQS; i++)
1841 pirq_entries[i] = -1;
1845 * The number of IO-APIC IRQ registers (== #pins):
1847 for (apic = 0; apic < nr_ioapics; apic++) {
1848 spin_lock_irqsave(&ioapic_lock, flags);
1849 reg_01.raw = io_apic_read(apic, 1);
1850 spin_unlock_irqrestore(&ioapic_lock, flags);
1851 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1853 for(apic = 0; apic < nr_ioapics; apic++) {
1855 /* See if any of the pins is in ExtINT mode */
1856 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1857 struct IO_APIC_route_entry entry;
1858 entry = ioapic_read_entry(apic, pin);
1860 /* If the interrupt line is enabled and in ExtInt mode
1861 * I have found the pin where the i8259 is connected.
1863 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1864 ioapic_i8259.apic = apic;
1865 ioapic_i8259.pin = pin;
1871 /* Look to see what if the MP table has reported the ExtINT */
1872 /* If we could not find the appropriate pin by looking at the ioapic
1873 * the i8259 probably is not connected the ioapic but give the
1874 * mptable a chance anyway.
1876 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1877 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1878 /* Trust the MP table if nothing is setup in the hardware */
1879 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1880 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1881 ioapic_i8259.pin = i8259_pin;
1882 ioapic_i8259.apic = i8259_apic;
1884 /* Complain if the MP table and the hardware disagree */
1885 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1886 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1888 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1892 * Do not trust the IO-APIC being empty at bootup
1898 * Not an __init, needed by the reboot code
1900 void disable_IO_APIC(void)
1903 * Clear the IO-APIC before rebooting:
1908 * If the i8259 is routed through an IOAPIC
1909 * Put that IOAPIC in virtual wire mode
1910 * so legacy interrupts can be delivered.
1912 if (ioapic_i8259.pin != -1) {
1913 struct IO_APIC_route_entry entry;
1915 memset(&entry, 0, sizeof(entry));
1916 entry.mask = 0; /* Enabled */
1917 entry.trigger = 0; /* Edge */
1919 entry.polarity = 0; /* High */
1920 entry.delivery_status = 0;
1921 entry.dest_mode = 0; /* Physical */
1922 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1924 entry.dest = read_apic_id();
1927 * Add it to the IO-APIC irq-routing table:
1929 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1932 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1935 #ifdef CONFIG_X86_32
1937 * function to set the IO-APIC physical IDs based on the
1938 * values stored in the MPC table.
1940 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1943 static void __init setup_ioapic_ids_from_mpc(void)
1945 union IO_APIC_reg_00 reg_00;
1946 physid_mask_t phys_id_present_map;
1949 unsigned char old_id;
1950 unsigned long flags;
1952 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1956 * Don't check I/O APIC IDs for xAPIC systems. They have
1957 * no meaning without the serial APIC bus.
1959 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1960 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1963 * This is broken; anything with a real cpu count has to
1964 * circumvent this idiocy regardless.
1966 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1969 * Set the IOAPIC ID to the value stored in the MPC table.
1971 for (apic = 0; apic < nr_ioapics; apic++) {
1973 /* Read the register 0 value */
1974 spin_lock_irqsave(&ioapic_lock, flags);
1975 reg_00.raw = io_apic_read(apic, 0);
1976 spin_unlock_irqrestore(&ioapic_lock, flags);
1978 old_id = mp_ioapics[apic].mp_apicid;
1980 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1981 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1982 apic, mp_ioapics[apic].mp_apicid);
1983 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1985 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1989 * Sanity check, is the ID really free? Every APIC in a
1990 * system must have a unique ID or we get lots of nice
1991 * 'stuck on smp_invalidate_needed IPI wait' messages.
1993 if (check_apicid_used(phys_id_present_map,
1994 mp_ioapics[apic].mp_apicid)) {
1995 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1996 apic, mp_ioapics[apic].mp_apicid);
1997 for (i = 0; i < get_physical_broadcast(); i++)
1998 if (!physid_isset(i, phys_id_present_map))
2000 if (i >= get_physical_broadcast())
2001 panic("Max APIC ID exceeded!\n");
2002 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2004 physid_set(i, phys_id_present_map);
2005 mp_ioapics[apic].mp_apicid = i;
2008 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
2009 apic_printk(APIC_VERBOSE, "Setting %d in the "
2010 "phys_id_present_map\n",
2011 mp_ioapics[apic].mp_apicid);
2012 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2017 * We need to adjust the IRQ routing table
2018 * if the ID changed.
2020 if (old_id != mp_ioapics[apic].mp_apicid)
2021 for (i = 0; i < mp_irq_entries; i++)
2022 if (mp_irqs[i].mp_dstapic == old_id)
2023 mp_irqs[i].mp_dstapic
2024 = mp_ioapics[apic].mp_apicid;
2027 * Read the right value from the MPC table and
2028 * write it into the ID register.
2030 apic_printk(APIC_VERBOSE, KERN_INFO
2031 "...changing IO-APIC physical APIC ID to %d ...",
2032 mp_ioapics[apic].mp_apicid);
2034 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
2035 spin_lock_irqsave(&ioapic_lock, flags);
2040 spin_lock_irqsave(&ioapic_lock, flags);
2041 reg_00.raw = io_apic_read(apic, 0);
2042 spin_unlock_irqrestore(&ioapic_lock, flags);
2043 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
2044 printk("could not set ID!\n");
2046 apic_printk(APIC_VERBOSE, " ok.\n");
2051 int no_timer_check __initdata;
2053 static int __init notimercheck(char *s)
2058 __setup("no_timer_check", notimercheck);
2061 * There is a nasty bug in some older SMP boards, their mptable lies
2062 * about the timer IRQ. We do the following to work around the situation:
2064 * - timer IRQ defaults to IO-APIC IRQ
2065 * - if this function detects that timer IRQs are defunct, then we fall
2066 * back to ISA timer IRQs
2068 static int __init timer_irq_works(void)
2070 unsigned long t1 = jiffies;
2071 unsigned long flags;
2076 local_save_flags(flags);
2078 /* Let ten ticks pass... */
2079 mdelay((10 * 1000) / HZ);
2080 local_irq_restore(flags);
2083 * Expect a few ticks at least, to be sure some possible
2084 * glue logic does not lock up after one or two first
2085 * ticks in a non-ExtINT mode. Also the local APIC
2086 * might have cached one ExtINT interrupt. Finally, at
2087 * least one tick may be lost due to delays.
2091 if (time_after(jiffies, t1 + 4))
2097 * In the SMP+IOAPIC case it might happen that there are an unspecified
2098 * number of pending IRQ events unhandled. These cases are very rare,
2099 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2100 * better to do it this way as thus we do not have to be aware of
2101 * 'pending' interrupts in the IRQ path, except at this point.
2104 * Edge triggered needs to resend any interrupt
2105 * that was delayed but this is now handled in the device
2110 * Starting up a edge-triggered IO-APIC interrupt is
2111 * nasty - we need to make sure that we get the edge.
2112 * If it is already asserted for some reason, we need
2113 * return 1 to indicate that is was pending.
2115 * This is not complete - we should be able to fake
2116 * an edge even if it isn't on the 8259A...
2119 static unsigned int startup_ioapic_irq(unsigned int irq)
2121 int was_pending = 0;
2122 unsigned long flags;
2124 spin_lock_irqsave(&ioapic_lock, flags);
2126 disable_8259A_irq(irq);
2127 if (i8259A_irq_pending(irq))
2130 __unmask_IO_APIC_irq(irq);
2131 spin_unlock_irqrestore(&ioapic_lock, flags);
2136 #ifdef CONFIG_X86_64
2137 static int ioapic_retrigger_irq(unsigned int irq)
2140 struct irq_cfg *cfg = irq_cfg(irq);
2141 unsigned long flags;
2143 spin_lock_irqsave(&vector_lock, flags);
2144 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2145 spin_unlock_irqrestore(&vector_lock, flags);
2150 static int ioapic_retrigger_irq(unsigned int irq)
2152 send_IPI_self(irq_cfg(irq)->vector);
2159 * Level and edge triggered IO-APIC interrupts need different handling,
2160 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2161 * handled with the level-triggered descriptor, but that one has slightly
2162 * more overhead. Level-triggered interrupts cannot be handled with the
2163 * edge-triggered handler, without risking IRQ storms and other ugly
2169 #ifdef CONFIG_INTR_REMAP
2170 static void ir_irq_migration(struct work_struct *work);
2172 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2175 * Migrate the IO-APIC irq in the presence of intr-remapping.
2177 * For edge triggered, irq migration is a simple atomic update(of vector
2178 * and cpu destination) of IRTE and flush the hardware cache.
2180 * For level triggered, we need to modify the io-apic RTE aswell with the update
2181 * vector information, along with modifying IRTE with vector and destination.
2182 * So irq migration for level triggered is little bit more complex compared to
2183 * edge triggered migration. But the good news is, we use the same algorithm
2184 * for level triggered migration as we have today, only difference being,
2185 * we now initiate the irq migration from process context instead of the
2186 * interrupt context.
2188 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2189 * suppression) to the IO-APIC, level triggered irq migration will also be
2190 * as simple as edge triggered migration and we can do the irq migration
2191 * with a simple atomic update to IO-APIC RTE.
2193 static void migrate_ioapic_irq(int irq, cpumask_t mask)
2195 struct irq_cfg *cfg;
2196 struct irq_desc *desc;
2197 cpumask_t tmp, cleanup_mask;
2199 int modify_ioapic_rte;
2201 unsigned long flags;
2203 cpus_and(tmp, mask, cpu_online_map);
2204 if (cpus_empty(tmp))
2207 if (get_irte(irq, &irte))
2210 if (assign_irq_vector(irq, mask))
2214 cpus_and(tmp, cfg->domain, mask);
2215 dest = cpu_mask_to_apicid(tmp);
2217 desc = irq_to_desc(irq);
2218 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2219 if (modify_ioapic_rte) {
2220 spin_lock_irqsave(&ioapic_lock, flags);
2221 __target_IO_APIC_irq(irq, dest, cfg->vector);
2222 spin_unlock_irqrestore(&ioapic_lock, flags);
2225 irte.vector = cfg->vector;
2226 irte.dest_id = IRTE_DEST(dest);
2229 * Modified the IRTE and flushes the Interrupt entry cache.
2231 modify_irte(irq, &irte);
2233 if (cfg->move_in_progress) {
2234 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2235 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2236 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2237 cfg->move_in_progress = 0;
2240 desc->affinity = mask;
2243 static int migrate_irq_remapped_level(int irq)
2246 struct irq_desc *desc = irq_to_desc(irq);
2248 mask_IO_APIC_irq(irq);
2250 if (io_apic_level_ack_pending(irq)) {
2252 * Interrupt in progress. Migrating irq now will change the
2253 * vector information in the IO-APIC RTE and that will confuse
2254 * the EOI broadcast performed by cpu.
2255 * So, delay the irq migration to the next instance.
2257 schedule_delayed_work(&ir_migration_work, 1);
2261 /* everthing is clear. we have right of way */
2262 migrate_ioapic_irq(irq, desc->pending_mask);
2265 desc->status &= ~IRQ_MOVE_PENDING;
2266 cpus_clear(desc->pending_mask);
2269 unmask_IO_APIC_irq(irq);
2273 static void ir_irq_migration(struct work_struct *work)
2276 struct irq_desc *desc;
2278 for_each_irq_desc(irq, desc) {
2279 if (desc->status & IRQ_MOVE_PENDING) {
2280 unsigned long flags;
2282 spin_lock_irqsave(&desc->lock, flags);
2283 if (!desc->chip->set_affinity ||
2284 !(desc->status & IRQ_MOVE_PENDING)) {
2285 desc->status &= ~IRQ_MOVE_PENDING;
2286 spin_unlock_irqrestore(&desc->lock, flags);
2290 desc->chip->set_affinity(irq, desc->pending_mask);
2291 spin_unlock_irqrestore(&desc->lock, flags);
2297 * Migrates the IRQ destination in the process context.
2299 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2301 struct irq_desc *desc = irq_to_desc(irq);
2303 if (desc->status & IRQ_LEVEL) {
2304 desc->status |= IRQ_MOVE_PENDING;
2305 desc->pending_mask = mask;
2306 migrate_irq_remapped_level(irq);
2310 migrate_ioapic_irq(irq, mask);
2314 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2316 unsigned vector, me;
2318 #ifdef CONFIG_X86_64
2323 me = smp_processor_id();
2324 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2326 struct irq_desc *desc;
2327 struct irq_cfg *cfg;
2328 irq = __get_cpu_var(vector_irq)[vector];
2330 desc = irq_to_desc(irq);
2335 spin_lock(&desc->lock);
2336 if (!cfg->move_cleanup_count)
2339 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2342 __get_cpu_var(vector_irq)[vector] = -1;
2343 cfg->move_cleanup_count--;
2345 spin_unlock(&desc->lock);
2351 static void irq_complete_move(unsigned int irq)
2353 struct irq_cfg *cfg = irq_cfg(irq);
2354 unsigned vector, me;
2356 if (likely(!cfg->move_in_progress))
2359 vector = ~get_irq_regs()->orig_ax;
2360 me = smp_processor_id();
2361 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2362 cpumask_t cleanup_mask;
2364 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2365 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2366 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2367 cfg->move_in_progress = 0;
2371 static inline void irq_complete_move(unsigned int irq) {}
2373 #ifdef CONFIG_INTR_REMAP
2374 static void ack_x2apic_level(unsigned int irq)
2379 static void ack_x2apic_edge(unsigned int irq)
2385 static void ack_apic_edge(unsigned int irq)
2387 irq_complete_move(irq);
2388 move_native_irq(irq);
2392 #ifdef CONFIG_X86_32
2393 atomic_t irq_mis_count;
2396 static void ack_apic_level(unsigned int irq)
2398 #ifdef CONFIG_X86_32
2402 int do_unmask_irq = 0;
2404 irq_complete_move(irq);
2405 #ifdef CONFIG_GENERIC_PENDING_IRQ
2406 /* If we are moving the irq we need to mask it */
2407 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2409 mask_IO_APIC_irq(irq);
2413 #ifdef CONFIG_X86_32
2415 * It appears there is an erratum which affects at least version 0x11
2416 * of I/O APIC (that's the 82093AA and cores integrated into various
2417 * chipsets). Under certain conditions a level-triggered interrupt is
2418 * erroneously delivered as edge-triggered one but the respective IRR
2419 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2420 * message but it will never arrive and further interrupts are blocked
2421 * from the source. The exact reason is so far unknown, but the
2422 * phenomenon was observed when two consecutive interrupt requests
2423 * from a given source get delivered to the same CPU and the source is
2424 * temporarily disabled in between.
2426 * A workaround is to simulate an EOI message manually. We achieve it
2427 * by setting the trigger mode to edge and then to level when the edge
2428 * trigger mode gets detected in the TMR of a local APIC for a
2429 * level-triggered interrupt. We mask the source for the time of the
2430 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2431 * The idea is from Manfred Spraul. --macro
2433 i = irq_cfg(irq)->vector;
2435 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2439 * We must acknowledge the irq before we move it or the acknowledge will
2440 * not propagate properly.
2444 /* Now we can move and renable the irq */
2445 if (unlikely(do_unmask_irq)) {
2446 /* Only migrate the irq if the ack has been received.
2448 * On rare occasions the broadcast level triggered ack gets
2449 * delayed going to ioapics, and if we reprogram the
2450 * vector while Remote IRR is still set the irq will never
2453 * To prevent this scenario we read the Remote IRR bit
2454 * of the ioapic. This has two effects.
2455 * - On any sane system the read of the ioapic will
2456 * flush writes (and acks) going to the ioapic from
2458 * - We get to see if the ACK has actually been delivered.
2460 * Based on failed experiments of reprogramming the
2461 * ioapic entry from outside of irq context starting
2462 * with masking the ioapic entry and then polling until
2463 * Remote IRR was clear before reprogramming the
2464 * ioapic I don't trust the Remote IRR bit to be
2465 * completey accurate.
2467 * However there appears to be no other way to plug
2468 * this race, so if the Remote IRR bit is not
2469 * accurate and is causing problems then it is a hardware bug
2470 * and you can go talk to the chipset vendor about it.
2472 if (!io_apic_level_ack_pending(irq))
2473 move_masked_irq(irq);
2474 unmask_IO_APIC_irq(irq);
2477 #ifdef CONFIG_X86_32
2478 if (!(v & (1 << (i & 0x1f)))) {
2479 atomic_inc(&irq_mis_count);
2480 spin_lock(&ioapic_lock);
2481 __mask_and_edge_IO_APIC_irq(irq);
2482 __unmask_and_level_IO_APIC_irq(irq);
2483 spin_unlock(&ioapic_lock);
2488 static struct irq_chip ioapic_chip __read_mostly = {
2490 .startup = startup_ioapic_irq,
2491 .mask = mask_IO_APIC_irq,
2492 .unmask = unmask_IO_APIC_irq,
2493 .ack = ack_apic_edge,
2494 .eoi = ack_apic_level,
2496 .set_affinity = set_ioapic_affinity_irq,
2498 .retrigger = ioapic_retrigger_irq,
2501 #ifdef CONFIG_INTR_REMAP
2502 static struct irq_chip ir_ioapic_chip __read_mostly = {
2503 .name = "IR-IO-APIC",
2504 .startup = startup_ioapic_irq,
2505 .mask = mask_IO_APIC_irq,
2506 .unmask = unmask_IO_APIC_irq,
2507 .ack = ack_x2apic_edge,
2508 .eoi = ack_x2apic_level,
2510 .set_affinity = set_ir_ioapic_affinity_irq,
2512 .retrigger = ioapic_retrigger_irq,
2516 static inline void init_IO_APIC_traps(void)
2519 struct irq_desc *desc;
2520 struct irq_cfg *cfg;
2523 * NOTE! The local APIC isn't very good at handling
2524 * multiple interrupts at the same interrupt level.
2525 * As the interrupt level is determined by taking the
2526 * vector number and shifting that right by 4, we
2527 * want to spread these out a bit so that they don't
2528 * all fall in the same interrupt level.
2530 * Also, we've got to be careful not to trash gate
2531 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2533 for_each_irq_cfg(cfg) {
2535 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2537 * Hmm.. We don't have an entry for this,
2538 * so default to an old-fashioned 8259
2539 * interrupt if we can..
2542 make_8259A_irq(irq);
2544 desc = irq_to_desc(irq);
2545 /* Strange. Oh, well.. */
2546 desc->chip = &no_irq_chip;
2553 * The local APIC irq-chip implementation:
2556 static void mask_lapic_irq(unsigned int irq)
2560 v = apic_read(APIC_LVT0);
2561 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2564 static void unmask_lapic_irq(unsigned int irq)
2568 v = apic_read(APIC_LVT0);
2569 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2572 static void ack_lapic_irq (unsigned int irq)
2577 static struct irq_chip lapic_chip __read_mostly = {
2578 .name = "local-APIC",
2579 .mask = mask_lapic_irq,
2580 .unmask = unmask_lapic_irq,
2581 .ack = ack_lapic_irq,
2584 static void lapic_register_intr(int irq)
2586 struct irq_desc *desc;
2588 desc = irq_to_desc(irq);
2589 desc->status &= ~IRQ_LEVEL;
2590 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2594 static void __init setup_nmi(void)
2597 * Dirty trick to enable the NMI watchdog ...
2598 * We put the 8259A master into AEOI mode and
2599 * unmask on all local APICs LVT0 as NMI.
2601 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2602 * is from Maciej W. Rozycki - so we do not have to EOI from
2603 * the NMI handler or the timer interrupt.
2605 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2607 enable_NMI_through_LVT0();
2609 apic_printk(APIC_VERBOSE, " done.\n");
2613 * This looks a bit hackish but it's about the only one way of sending
2614 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2615 * not support the ExtINT mode, unfortunately. We need to send these
2616 * cycles as some i82489DX-based boards have glue logic that keeps the
2617 * 8259A interrupt line asserted until INTA. --macro
2619 static inline void __init unlock_ExtINT_logic(void)
2622 struct IO_APIC_route_entry entry0, entry1;
2623 unsigned char save_control, save_freq_select;
2625 pin = find_isa_irq_pin(8, mp_INT);
2630 apic = find_isa_irq_apic(8, mp_INT);
2636 entry0 = ioapic_read_entry(apic, pin);
2637 clear_IO_APIC_pin(apic, pin);
2639 memset(&entry1, 0, sizeof(entry1));
2641 entry1.dest_mode = 0; /* physical delivery */
2642 entry1.mask = 0; /* unmask IRQ now */
2643 entry1.dest = hard_smp_processor_id();
2644 entry1.delivery_mode = dest_ExtINT;
2645 entry1.polarity = entry0.polarity;
2649 ioapic_write_entry(apic, pin, entry1);
2651 save_control = CMOS_READ(RTC_CONTROL);
2652 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2653 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2655 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2660 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2664 CMOS_WRITE(save_control, RTC_CONTROL);
2665 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2666 clear_IO_APIC_pin(apic, pin);
2668 ioapic_write_entry(apic, pin, entry0);
2671 static int disable_timer_pin_1 __initdata;
2672 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2673 static int __init disable_timer_pin_setup(char *arg)
2675 disable_timer_pin_1 = 1;
2678 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2680 int timer_through_8259 __initdata;
2683 * This code may look a bit paranoid, but it's supposed to cooperate with
2684 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2685 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2686 * fanatically on his truly buggy board.
2688 * FIXME: really need to revamp this for all platforms.
2690 static inline void __init check_timer(void)
2692 struct irq_cfg *cfg = irq_cfg(0);
2693 int apic1, pin1, apic2, pin2;
2694 unsigned long flags;
2698 local_irq_save(flags);
2700 ver = apic_read(APIC_LVR);
2701 ver = GET_APIC_VERSION(ver);
2704 * get/set the timer IRQ vector:
2706 disable_8259A_irq(0);
2707 assign_irq_vector(0, TARGET_CPUS);
2710 * As IRQ0 is to be enabled in the 8259A, the virtual
2711 * wire has to be disabled in the local APIC. Also
2712 * timer interrupts need to be acknowledged manually in
2713 * the 8259A for the i82489DX when using the NMI
2714 * watchdog as that APIC treats NMIs as level-triggered.
2715 * The AEOI mode will finish them in the 8259A
2718 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2720 #ifdef CONFIG_X86_32
2721 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2724 pin1 = find_isa_irq_pin(0, mp_INT);
2725 apic1 = find_isa_irq_apic(0, mp_INT);
2726 pin2 = ioapic_i8259.pin;
2727 apic2 = ioapic_i8259.apic;
2729 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2730 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2731 cfg->vector, apic1, pin1, apic2, pin2);
2734 * Some BIOS writers are clueless and report the ExtINTA
2735 * I/O APIC input from the cascaded 8259A as the timer
2736 * interrupt input. So just in case, if only one pin
2737 * was found above, try it both directly and through the
2741 #ifdef CONFIG_INTR_REMAP
2742 if (intr_remapping_enabled)
2743 panic("BIOS bug: timer not connected to IO-APIC");
2748 } else if (pin2 == -1) {
2755 * Ok, does IRQ0 through the IOAPIC work?
2758 add_pin_to_irq(0, apic1, pin1);
2759 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2761 unmask_IO_APIC_irq(0);
2762 if (timer_irq_works()) {
2763 if (nmi_watchdog == NMI_IO_APIC) {
2765 enable_8259A_irq(0);
2767 if (disable_timer_pin_1 > 0)
2768 clear_IO_APIC_pin(0, pin1);
2771 #ifdef CONFIG_INTR_REMAP
2772 if (intr_remapping_enabled)
2773 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2775 clear_IO_APIC_pin(apic1, pin1);
2777 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2778 "8254 timer not connected to IO-APIC\n");
2780 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2781 "(IRQ0) through the 8259A ...\n");
2782 apic_printk(APIC_QUIET, KERN_INFO
2783 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2785 * legacy devices should be connected to IO APIC #0
2787 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2788 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2789 unmask_IO_APIC_irq(0);
2790 enable_8259A_irq(0);
2791 if (timer_irq_works()) {
2792 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2793 timer_through_8259 = 1;
2794 if (nmi_watchdog == NMI_IO_APIC) {
2795 disable_8259A_irq(0);
2797 enable_8259A_irq(0);
2802 * Cleanup, just in case ...
2804 disable_8259A_irq(0);
2805 clear_IO_APIC_pin(apic2, pin2);
2806 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2809 if (nmi_watchdog == NMI_IO_APIC) {
2810 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2811 "through the IO-APIC - disabling NMI Watchdog!\n");
2812 nmi_watchdog = NMI_NONE;
2814 #ifdef CONFIG_X86_32
2818 apic_printk(APIC_QUIET, KERN_INFO
2819 "...trying to set up timer as Virtual Wire IRQ...\n");
2821 lapic_register_intr(0);
2822 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2823 enable_8259A_irq(0);
2825 if (timer_irq_works()) {
2826 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2829 disable_8259A_irq(0);
2830 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2831 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2833 apic_printk(APIC_QUIET, KERN_INFO
2834 "...trying to set up timer as ExtINT IRQ...\n");
2838 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2840 unlock_ExtINT_logic();
2842 if (timer_irq_works()) {
2843 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2846 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2847 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2848 "report. Then try booting with the 'noapic' option.\n");
2850 local_irq_restore(flags);
2854 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2855 * to devices. However there may be an I/O APIC pin available for
2856 * this interrupt regardless. The pin may be left unconnected, but
2857 * typically it will be reused as an ExtINT cascade interrupt for
2858 * the master 8259A. In the MPS case such a pin will normally be
2859 * reported as an ExtINT interrupt in the MP table. With ACPI
2860 * there is no provision for ExtINT interrupts, and in the absence
2861 * of an override it would be treated as an ordinary ISA I/O APIC
2862 * interrupt, that is edge-triggered and unmasked by default. We
2863 * used to do this, but it caused problems on some systems because
2864 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2865 * the same ExtINT cascade interrupt to drive the local APIC of the
2866 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2867 * the I/O APIC in all cases now. No actual device should request
2868 * it anyway. --macro
2870 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2872 void __init setup_IO_APIC(void)
2875 #ifdef CONFIG_X86_32
2879 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2883 io_apic_irqs = ~PIC_IRQS;
2885 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2887 * Set up IO-APIC IRQ routing.
2889 #ifdef CONFIG_X86_32
2891 setup_ioapic_ids_from_mpc();
2894 setup_IO_APIC_irqs();
2895 init_IO_APIC_traps();
2900 * Called after all the initialization is done. If we didnt find any
2901 * APIC bugs then we can allow the modify fast path
2904 static int __init io_apic_bug_finalize(void)
2906 if (sis_apic_bug == -1)
2911 late_initcall(io_apic_bug_finalize);
2913 struct sysfs_ioapic_data {
2914 struct sys_device dev;
2915 struct IO_APIC_route_entry entry[0];
2917 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2919 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2921 struct IO_APIC_route_entry *entry;
2922 struct sysfs_ioapic_data *data;
2925 data = container_of(dev, struct sysfs_ioapic_data, dev);
2926 entry = data->entry;
2927 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2928 *entry = ioapic_read_entry(dev->id, i);
2933 static int ioapic_resume(struct sys_device *dev)
2935 struct IO_APIC_route_entry *entry;
2936 struct sysfs_ioapic_data *data;
2937 unsigned long flags;
2938 union IO_APIC_reg_00 reg_00;
2941 data = container_of(dev, struct sysfs_ioapic_data, dev);
2942 entry = data->entry;
2944 spin_lock_irqsave(&ioapic_lock, flags);
2945 reg_00.raw = io_apic_read(dev->id, 0);
2946 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2947 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2948 io_apic_write(dev->id, 0, reg_00.raw);
2950 spin_unlock_irqrestore(&ioapic_lock, flags);
2951 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2952 ioapic_write_entry(dev->id, i, entry[i]);
2957 static struct sysdev_class ioapic_sysdev_class = {
2959 .suspend = ioapic_suspend,
2960 .resume = ioapic_resume,
2963 static int __init ioapic_init_sysfs(void)
2965 struct sys_device * dev;
2968 error = sysdev_class_register(&ioapic_sysdev_class);
2972 for (i = 0; i < nr_ioapics; i++ ) {
2973 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2974 * sizeof(struct IO_APIC_route_entry);
2975 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2976 if (!mp_ioapic_data[i]) {
2977 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2980 dev = &mp_ioapic_data[i]->dev;
2982 dev->cls = &ioapic_sysdev_class;
2983 error = sysdev_register(dev);
2985 kfree(mp_ioapic_data[i]);
2986 mp_ioapic_data[i] = NULL;
2987 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2995 device_initcall(ioapic_init_sysfs);
2998 * Dynamic irq allocate and deallocation
3000 unsigned int create_irq_nr(unsigned int irq_want)
3002 /* Allocate an unused irq */
3005 unsigned long flags;
3006 struct irq_cfg *cfg_new;
3008 #ifndef CONFIG_HAVE_SPARSE_IRQ
3009 irq_want = nr_irqs - 1;
3013 spin_lock_irqsave(&vector_lock, flags);
3014 for (new = irq_want; new > 0; new--) {
3015 if (platform_legacy_irq(new))
3017 cfg_new = irq_cfg(new);
3018 if (cfg_new && cfg_new->vector != 0)
3020 /* check if need to create one */
3022 cfg_new = irq_cfg_alloc(new);
3023 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
3027 spin_unlock_irqrestore(&vector_lock, flags);
3030 dynamic_irq_init(irq);
3035 int create_irq(void)
3039 irq = create_irq_nr(nr_irqs - 1);
3047 void destroy_irq(unsigned int irq)
3049 unsigned long flags;
3051 dynamic_irq_cleanup(irq);
3053 #ifdef CONFIG_INTR_REMAP
3056 spin_lock_irqsave(&vector_lock, flags);
3057 __clear_irq_vector(irq);
3058 spin_unlock_irqrestore(&vector_lock, flags);
3062 * MSI message composition
3064 #ifdef CONFIG_PCI_MSI
3065 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3067 struct irq_cfg *cfg;
3073 err = assign_irq_vector(irq, tmp);
3078 cpus_and(tmp, cfg->domain, tmp);
3079 dest = cpu_mask_to_apicid(tmp);
3081 #ifdef CONFIG_INTR_REMAP
3082 if (irq_remapped(irq)) {
3087 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3088 BUG_ON(ir_index == -1);
3090 memset (&irte, 0, sizeof(irte));
3093 irte.dst_mode = INT_DEST_MODE;
3094 irte.trigger_mode = 0; /* edge */
3095 irte.dlvry_mode = INT_DELIVERY_MODE;
3096 irte.vector = cfg->vector;
3097 irte.dest_id = IRTE_DEST(dest);
3099 modify_irte(irq, &irte);
3101 msg->address_hi = MSI_ADDR_BASE_HI;
3102 msg->data = sub_handle;
3103 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3105 MSI_ADDR_IR_INDEX1(ir_index) |
3106 MSI_ADDR_IR_INDEX2(ir_index);
3110 msg->address_hi = MSI_ADDR_BASE_HI;
3113 ((INT_DEST_MODE == 0) ?
3114 MSI_ADDR_DEST_MODE_PHYSICAL:
3115 MSI_ADDR_DEST_MODE_LOGICAL) |
3116 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3117 MSI_ADDR_REDIRECTION_CPU:
3118 MSI_ADDR_REDIRECTION_LOWPRI) |
3119 MSI_ADDR_DEST_ID(dest);
3122 MSI_DATA_TRIGGER_EDGE |
3123 MSI_DATA_LEVEL_ASSERT |
3124 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3125 MSI_DATA_DELIVERY_FIXED:
3126 MSI_DATA_DELIVERY_LOWPRI) |
3127 MSI_DATA_VECTOR(cfg->vector);
3133 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3135 struct irq_cfg *cfg;
3139 struct irq_desc *desc;
3141 cpus_and(tmp, mask, cpu_online_map);
3142 if (cpus_empty(tmp))
3145 if (assign_irq_vector(irq, mask))
3149 cpus_and(tmp, cfg->domain, mask);
3150 dest = cpu_mask_to_apicid(tmp);
3152 read_msi_msg(irq, &msg);
3154 msg.data &= ~MSI_DATA_VECTOR_MASK;
3155 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3156 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3157 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3159 write_msi_msg(irq, &msg);
3160 desc = irq_to_desc(irq);
3161 desc->affinity = mask;
3164 #ifdef CONFIG_INTR_REMAP
3166 * Migrate the MSI irq to another cpumask. This migration is
3167 * done in the process context using interrupt-remapping hardware.
3169 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3171 struct irq_cfg *cfg;
3173 cpumask_t tmp, cleanup_mask;
3175 struct irq_desc *desc;
3177 cpus_and(tmp, mask, cpu_online_map);
3178 if (cpus_empty(tmp))
3181 if (get_irte(irq, &irte))
3184 if (assign_irq_vector(irq, mask))
3188 cpus_and(tmp, cfg->domain, mask);
3189 dest = cpu_mask_to_apicid(tmp);
3191 irte.vector = cfg->vector;
3192 irte.dest_id = IRTE_DEST(dest);
3195 * atomically update the IRTE with the new destination and vector.
3197 modify_irte(irq, &irte);
3200 * After this point, all the interrupts will start arriving
3201 * at the new destination. So, time to cleanup the previous
3202 * vector allocation.
3204 if (cfg->move_in_progress) {
3205 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3206 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3207 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3208 cfg->move_in_progress = 0;
3211 desc = irq_to_desc(irq);
3212 desc->affinity = mask;
3215 #endif /* CONFIG_SMP */
3218 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3219 * which implement the MSI or MSI-X Capability Structure.
3221 static struct irq_chip msi_chip = {
3223 .unmask = unmask_msi_irq,
3224 .mask = mask_msi_irq,
3225 .ack = ack_apic_edge,
3227 .set_affinity = set_msi_irq_affinity,
3229 .retrigger = ioapic_retrigger_irq,
3232 #ifdef CONFIG_INTR_REMAP
3233 static struct irq_chip msi_ir_chip = {
3234 .name = "IR-PCI-MSI",
3235 .unmask = unmask_msi_irq,
3236 .mask = mask_msi_irq,
3237 .ack = ack_x2apic_edge,
3239 .set_affinity = ir_set_msi_irq_affinity,
3241 .retrigger = ioapic_retrigger_irq,
3245 * Map the PCI dev to the corresponding remapping hardware unit
3246 * and allocate 'nvec' consecutive interrupt-remapping table entries
3249 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3251 struct intel_iommu *iommu;
3254 iommu = map_dev_to_ir(dev);
3257 "Unable to map PCI %s to iommu\n", pci_name(dev));
3261 index = alloc_irte(iommu, irq, nvec);
3264 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3272 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
3277 ret = msi_compose_msg(dev, irq, &msg);
3281 set_irq_msi(irq, desc);
3282 write_msi_msg(irq, &msg);
3284 #ifdef CONFIG_INTR_REMAP
3285 if (irq_remapped(irq)) {
3286 struct irq_desc *desc = irq_to_desc(irq);
3288 * irq migration in process context
3290 desc->status |= IRQ_MOVE_PCNTXT;
3291 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3294 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3299 static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
3303 irq = dev->bus->number;
3311 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3315 unsigned int irq_want;
3317 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3319 irq = create_irq_nr(irq_want);
3323 #ifdef CONFIG_INTR_REMAP
3324 if (!intr_remapping_enabled)
3327 ret = msi_alloc_irte(dev, irq, 1);
3332 ret = setup_msi_irq(dev, desc, irq);
3339 #ifdef CONFIG_INTR_REMAP
3346 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3349 int ret, sub_handle;
3350 struct msi_desc *desc;
3351 unsigned int irq_want;
3353 #ifdef CONFIG_INTR_REMAP
3354 struct intel_iommu *iommu = 0;
3358 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3360 list_for_each_entry(desc, &dev->msi_list, list) {
3361 irq = create_irq_nr(irq_want--);
3364 #ifdef CONFIG_INTR_REMAP
3365 if (!intr_remapping_enabled)
3370 * allocate the consecutive block of IRTE's
3373 index = msi_alloc_irte(dev, irq, nvec);
3379 iommu = map_dev_to_ir(dev);
3385 * setup the mapping between the irq and the IRTE
3386 * base index, the sub_handle pointing to the
3387 * appropriate interrupt remap table entry.
3389 set_irte_irq(irq, iommu, index, sub_handle);
3393 ret = setup_msi_irq(dev, desc, irq);
3405 void arch_teardown_msi_irq(unsigned int irq)
3412 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3414 struct irq_cfg *cfg;
3418 struct irq_desc *desc;
3420 cpus_and(tmp, mask, cpu_online_map);
3421 if (cpus_empty(tmp))
3424 if (assign_irq_vector(irq, mask))
3428 cpus_and(tmp, cfg->domain, mask);
3429 dest = cpu_mask_to_apicid(tmp);
3431 dmar_msi_read(irq, &msg);
3433 msg.data &= ~MSI_DATA_VECTOR_MASK;
3434 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3435 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3436 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3438 dmar_msi_write(irq, &msg);
3439 desc = irq_to_desc(irq);
3440 desc->affinity = mask;
3442 #endif /* CONFIG_SMP */
3444 struct irq_chip dmar_msi_type = {
3446 .unmask = dmar_msi_unmask,
3447 .mask = dmar_msi_mask,
3448 .ack = ack_apic_edge,
3450 .set_affinity = dmar_msi_set_affinity,
3452 .retrigger = ioapic_retrigger_irq,
3455 int arch_setup_dmar_msi(unsigned int irq)
3460 ret = msi_compose_msg(NULL, irq, &msg);
3463 dmar_msi_write(irq, &msg);
3464 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3470 #endif /* CONFIG_PCI_MSI */
3472 * Hypertransport interrupt support
3474 #ifdef CONFIG_HT_IRQ
3478 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3480 struct ht_irq_msg msg;
3481 fetch_ht_irq_msg(irq, &msg);
3483 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3484 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3486 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3487 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3489 write_ht_irq_msg(irq, &msg);
3492 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3494 struct irq_cfg *cfg;
3497 struct irq_desc *desc;
3499 cpus_and(tmp, mask, cpu_online_map);
3500 if (cpus_empty(tmp))
3503 if (assign_irq_vector(irq, mask))
3507 cpus_and(tmp, cfg->domain, mask);
3508 dest = cpu_mask_to_apicid(tmp);
3510 target_ht_irq(irq, dest, cfg->vector);
3511 desc = irq_to_desc(irq);
3512 desc->affinity = mask;
3516 static struct irq_chip ht_irq_chip = {
3518 .mask = mask_ht_irq,
3519 .unmask = unmask_ht_irq,
3520 .ack = ack_apic_edge,
3522 .set_affinity = set_ht_irq_affinity,
3524 .retrigger = ioapic_retrigger_irq,
3527 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3529 struct irq_cfg *cfg;
3534 err = assign_irq_vector(irq, tmp);
3536 struct ht_irq_msg msg;
3540 cpus_and(tmp, cfg->domain, tmp);
3541 dest = cpu_mask_to_apicid(tmp);
3543 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3547 HT_IRQ_LOW_DEST_ID(dest) |
3548 HT_IRQ_LOW_VECTOR(cfg->vector) |
3549 ((INT_DEST_MODE == 0) ?
3550 HT_IRQ_LOW_DM_PHYSICAL :
3551 HT_IRQ_LOW_DM_LOGICAL) |
3552 HT_IRQ_LOW_RQEOI_EDGE |
3553 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3554 HT_IRQ_LOW_MT_FIXED :
3555 HT_IRQ_LOW_MT_ARBITRATED) |
3556 HT_IRQ_LOW_IRQ_MASKED;
3558 write_ht_irq_msg(irq, &msg);
3560 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3561 handle_edge_irq, "edge");
3565 #endif /* CONFIG_HT_IRQ */
3567 /* --------------------------------------------------------------------------
3568 ACPI-based IOAPIC Configuration
3569 -------------------------------------------------------------------------- */
3573 #ifdef CONFIG_X86_32
3574 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3576 union IO_APIC_reg_00 reg_00;
3577 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3579 unsigned long flags;
3583 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3584 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3585 * supports up to 16 on one shared APIC bus.
3587 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3588 * advantage of new APIC bus architecture.
3591 if (physids_empty(apic_id_map))
3592 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3594 spin_lock_irqsave(&ioapic_lock, flags);
3595 reg_00.raw = io_apic_read(ioapic, 0);
3596 spin_unlock_irqrestore(&ioapic_lock, flags);
3598 if (apic_id >= get_physical_broadcast()) {
3599 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3600 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3601 apic_id = reg_00.bits.ID;
3605 * Every APIC in a system must have a unique ID or we get lots of nice
3606 * 'stuck on smp_invalidate_needed IPI wait' messages.
3608 if (check_apicid_used(apic_id_map, apic_id)) {
3610 for (i = 0; i < get_physical_broadcast(); i++) {
3611 if (!check_apicid_used(apic_id_map, i))
3615 if (i == get_physical_broadcast())
3616 panic("Max apic_id exceeded!\n");
3618 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3619 "trying %d\n", ioapic, apic_id, i);
3624 tmp = apicid_to_cpu_present(apic_id);
3625 physids_or(apic_id_map, apic_id_map, tmp);
3627 if (reg_00.bits.ID != apic_id) {
3628 reg_00.bits.ID = apic_id;
3630 spin_lock_irqsave(&ioapic_lock, flags);
3631 io_apic_write(ioapic, 0, reg_00.raw);
3632 reg_00.raw = io_apic_read(ioapic, 0);
3633 spin_unlock_irqrestore(&ioapic_lock, flags);
3636 if (reg_00.bits.ID != apic_id) {
3637 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3642 apic_printk(APIC_VERBOSE, KERN_INFO
3643 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3648 int __init io_apic_get_version(int ioapic)
3650 union IO_APIC_reg_01 reg_01;
3651 unsigned long flags;
3653 spin_lock_irqsave(&ioapic_lock, flags);
3654 reg_01.raw = io_apic_read(ioapic, 1);
3655 spin_unlock_irqrestore(&ioapic_lock, flags);
3657 return reg_01.bits.version;
3661 int __init io_apic_get_redir_entries (int ioapic)
3663 union IO_APIC_reg_01 reg_01;
3664 unsigned long flags;
3666 spin_lock_irqsave(&ioapic_lock, flags);
3667 reg_01.raw = io_apic_read(ioapic, 1);
3668 spin_unlock_irqrestore(&ioapic_lock, flags);
3670 return reg_01.bits.entries;
3674 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3676 if (!IO_APIC_IRQ(irq)) {
3677 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3683 * IRQs < 16 are already in the irq_2_pin[] map
3686 add_pin_to_irq(irq, ioapic, pin);
3688 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
3694 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3698 if (skip_ioapic_setup)
3701 for (i = 0; i < mp_irq_entries; i++)
3702 if (mp_irqs[i].mp_irqtype == mp_INT &&
3703 mp_irqs[i].mp_srcbusirq == bus_irq)
3705 if (i >= mp_irq_entries)
3708 *trigger = irq_trigger(i);
3709 *polarity = irq_polarity(i);
3713 #endif /* CONFIG_ACPI */
3716 * This function currently is only a helper for the i386 smp boot process where
3717 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3718 * so mask in all cases should simply be TARGET_CPUS
3721 void __init setup_ioapic_dest(void)
3723 int pin, ioapic, irq, irq_entry;
3724 struct irq_cfg *cfg;
3726 if (skip_ioapic_setup == 1)
3729 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3730 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3731 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3732 if (irq_entry == -1)
3734 irq = pin_2_irq(irq_entry, ioapic, pin);
3736 /* setup_IO_APIC_irqs could fail to get vector for some device
3737 * when you have too many devices, because at that time only boot
3742 setup_IO_APIC_irq(ioapic, pin, irq,
3743 irq_trigger(irq_entry),
3744 irq_polarity(irq_entry));
3745 #ifdef CONFIG_INTR_REMAP
3746 else if (intr_remapping_enabled)
3747 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3750 set_ioapic_affinity_irq(irq, TARGET_CPUS);
3757 #define IOAPIC_RESOURCE_NAME_SIZE 11
3759 static struct resource *ioapic_resources;
3761 static struct resource * __init ioapic_setup_resources(void)
3764 struct resource *res;
3768 if (nr_ioapics <= 0)
3771 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3774 mem = alloc_bootmem(n);
3778 mem += sizeof(struct resource) * nr_ioapics;
3780 for (i = 0; i < nr_ioapics; i++) {
3782 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3783 sprintf(mem, "IOAPIC %u", i);
3784 mem += IOAPIC_RESOURCE_NAME_SIZE;
3788 ioapic_resources = res;
3793 void __init ioapic_init_mappings(void)
3795 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3797 struct resource *ioapic_res;
3799 ioapic_res = ioapic_setup_resources();
3800 for (i = 0; i < nr_ioapics; i++) {
3801 if (smp_found_config) {
3802 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3803 #ifdef CONFIG_X86_32
3806 "WARNING: bogus zero IO-APIC "
3807 "address found in MPTABLE, "
3808 "disabling IO/APIC support!\n");
3809 smp_found_config = 0;
3810 skip_ioapic_setup = 1;
3811 goto fake_ioapic_page;
3815 #ifdef CONFIG_X86_32
3818 ioapic_phys = (unsigned long)
3819 alloc_bootmem_pages(PAGE_SIZE);
3820 ioapic_phys = __pa(ioapic_phys);
3822 set_fixmap_nocache(idx, ioapic_phys);
3823 apic_printk(APIC_VERBOSE,
3824 "mapped IOAPIC to %08lx (%08lx)\n",
3825 __fix_to_virt(idx), ioapic_phys);
3828 if (ioapic_res != NULL) {
3829 ioapic_res->start = ioapic_phys;
3830 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3836 static int __init ioapic_insert_resources(void)
3839 struct resource *r = ioapic_resources;
3843 "IO APIC resources could be not be allocated.\n");
3847 for (i = 0; i < nr_ioapics; i++) {
3848 insert_resource(&iomem_resource, r);
3855 /* Insert the IO APIC resources after PCI initialization has occured to handle
3856 * IO APICS that are mapped in on a BAR in PCI space. */
3857 late_initcall(ioapic_insert_resources);