2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
63 #include <mach_apic.h>
64 #include <mach_apicdef.h>
66 #define __apicdebuginit(type) static type __init
69 * Is the SiS APIC rmw bug present ?
70 * -1 = don't know, 0 = no, 1 = yes
72 int sis_apic_bug = -1;
74 static DEFINE_SPINLOCK(ioapic_lock);
75 static DEFINE_SPINLOCK(vector_lock);
78 * # of IRQ routing registers
80 int nr_ioapic_registers[MAX_IO_APICS];
82 /* I/O APIC entries */
83 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
86 /* MP IRQ source entries */
87 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
89 /* # of MP IRQ source entries */
92 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
93 int mp_bus_id_to_type[MAX_MP_BUSSES];
96 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
98 int skip_ioapic_setup;
100 static int __init parse_noapic(char *str)
102 /* disable IO-APIC */
103 disable_ioapic_setup();
106 early_param("noapic", parse_noapic);
112 #ifdef CONFIG_HAVE_SPARSE_IRQ
113 struct irq_cfg *next;
115 struct irq_pin_list *irq_2_pin;
117 cpumask_t old_domain;
118 unsigned move_cleanup_count;
120 u8 move_in_progress : 1;
123 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
124 static struct irq_cfg irq_cfg_legacy[] __initdata = {
125 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
126 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
127 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
128 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
129 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
130 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
131 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
132 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
133 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
134 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
135 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
136 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
137 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
138 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
139 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
140 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
143 static struct irq_cfg irq_cfg_init = { .irq = -1U, };
145 static void init_one_irq_cfg(struct irq_cfg *cfg)
147 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
150 static struct irq_cfg *irq_cfgx;
152 #ifdef CONFIG_HAVE_SPARSE_IRQ
154 * Protect the irq_cfgx_free freelist:
156 static DEFINE_SPINLOCK(irq_cfg_lock);
158 static struct irq_cfg *irq_cfgx_free;
161 static void __init init_work(void *data)
163 struct dyn_array *da = data;
170 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
172 legacy_count = ARRAY_SIZE(irq_cfg_legacy);
173 for (i = legacy_count; i < *da->nr; i++)
174 init_one_irq_cfg(&cfg[i]);
176 #ifdef CONFIG_HAVE_SPARSE_IRQ
177 for (i = 1; i < *da->nr; i++)
178 cfg[i-1].next = &cfg[i];
180 irq_cfgx_free = &irq_cfgx[legacy_count];
181 irq_cfgx[legacy_count - 1].next = NULL;
185 #ifdef CONFIG_HAVE_SPARSE_IRQ
186 /* need to be biger than size of irq_cfg_legacy */
187 static int nr_irq_cfg = 32;
189 static int __init parse_nr_irq_cfg(char *arg)
192 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
199 early_param("nr_irq_cfg", parse_nr_irq_cfg);
201 #define for_each_irq_cfg(irqX, cfg) \
202 for (cfg = irq_cfgx, irqX = cfg->irq; cfg; cfg = cfg->next, irqX = cfg ? cfg->irq : -1U)
205 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
207 static struct irq_cfg *irq_cfg(unsigned int irq)
222 static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
224 struct irq_cfg *cfg, *cfg_pri;
229 cfg_pri = cfg = irq_cfgx;
239 spin_lock_irqsave(&irq_cfg_lock, flags);
240 if (!irq_cfgx_free) {
242 unsigned long total_bytes;
244 * we run out of pre-allocate ones, allocate more
246 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
248 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
250 cfg = kzalloc(total_bytes, GFP_ATOMIC);
252 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
255 panic("please boot with nr_irq_cfg= %d\n", count * 2);
258 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
260 for (i = 0; i < nr_irq_cfg; i++)
261 init_one_irq_cfg(&cfg[i]);
263 for (i = 1; i < nr_irq_cfg; i++)
264 cfg[i-1].next = &cfg[i];
270 irq_cfgx_free = irq_cfgx_free->next;
278 spin_unlock_irqrestore(&irq_cfg_lock, flags);
284 #define for_each_irq_cfg(irq, cfg) \
285 for (irq = 0, cfg = &irq_cfgx[irq]; irq < nr_irqs; irq++, cfg = &irq_cfgx[irq])
287 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irqs, PAGE_SIZE, init_work);
289 struct irq_cfg *irq_cfg(unsigned int irq)
292 return &irq_cfgx[irq];
296 struct irq_cfg *irq_cfg_alloc(unsigned int irq)
303 * This is performance-critical, we want to do it O(1)
305 * the indexing order of this array favors 1:1 mappings
306 * between pins and IRQs.
309 struct irq_pin_list {
311 struct irq_pin_list *next;
314 static struct irq_pin_list *irq_2_pin_head;
315 /* fill one page ? */
316 static int nr_irq_2_pin = 0x100;
317 static struct irq_pin_list *irq_2_pin_ptr;
318 static void __init irq_2_pin_init_work(void *data)
320 struct dyn_array *da = data;
321 struct irq_pin_list *pin;
326 for (i = 1; i < *da->nr; i++)
327 pin[i-1].next = &pin[i];
329 irq_2_pin_ptr = &pin[0];
331 DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
333 static struct irq_pin_list *get_one_free_irq_2_pin(void)
335 struct irq_pin_list *pin;
341 irq_2_pin_ptr = pin->next;
347 * we run out of pre-allocate ones, allocate more
349 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
352 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
355 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
356 nr_irq_2_pin, PAGE_SIZE, 0);
359 panic("can not get more irq_2_pin\n");
361 for (i = 1; i < nr_irq_2_pin; i++)
362 pin[i-1].next = &pin[i];
364 irq_2_pin_ptr = pin->next;
372 unsigned int unused[3];
376 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
378 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
379 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
382 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
384 struct io_apic __iomem *io_apic = io_apic_base(apic);
385 writel(reg, &io_apic->index);
386 return readl(&io_apic->data);
389 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
391 struct io_apic __iomem *io_apic = io_apic_base(apic);
392 writel(reg, &io_apic->index);
393 writel(value, &io_apic->data);
397 * Re-write a value: to be used for read-modify-write
398 * cycles where the read already set up the index register.
400 * Older SiS APIC requires we rewrite the index register
402 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
404 struct io_apic __iomem *io_apic = io_apic_base(apic);
406 writel(reg, &io_apic->index);
407 writel(value, &io_apic->data);
410 static bool io_apic_level_ack_pending(unsigned int irq)
412 struct irq_pin_list *entry;
414 struct irq_cfg *cfg = irq_cfg(irq);
416 spin_lock_irqsave(&ioapic_lock, flags);
417 entry = cfg->irq_2_pin;
425 reg = io_apic_read(entry->apic, 0x10 + pin*2);
426 /* Is the remote IRR bit set? */
427 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
428 spin_unlock_irqrestore(&ioapic_lock, flags);
435 spin_unlock_irqrestore(&ioapic_lock, flags);
441 struct { u32 w1, w2; };
442 struct IO_APIC_route_entry entry;
445 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
447 union entry_union eu;
449 spin_lock_irqsave(&ioapic_lock, flags);
450 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
451 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
452 spin_unlock_irqrestore(&ioapic_lock, flags);
457 * When we write a new IO APIC routing entry, we need to write the high
458 * word first! If the mask bit in the low word is clear, we will enable
459 * the interrupt, and we need to make sure the entry is fully populated
460 * before that happens.
463 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
465 union entry_union eu;
467 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
468 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
471 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
474 spin_lock_irqsave(&ioapic_lock, flags);
475 __ioapic_write_entry(apic, pin, e);
476 spin_unlock_irqrestore(&ioapic_lock, flags);
480 * When we mask an IO APIC routing entry, we need to write the low
481 * word first, in order to set the mask bit before we change the
484 static void ioapic_mask_entry(int apic, int pin)
487 union entry_union eu = { .entry.mask = 1 };
489 spin_lock_irqsave(&ioapic_lock, flags);
490 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
491 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
492 spin_unlock_irqrestore(&ioapic_lock, flags);
496 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
500 struct irq_pin_list *entry;
503 entry = cfg->irq_2_pin;
512 #ifdef CONFIG_INTR_REMAP
514 * With interrupt-remapping, destination information comes
515 * from interrupt-remapping table entry.
517 if (!irq_remapped(irq))
518 io_apic_write(apic, 0x11 + pin*2, dest);
520 io_apic_write(apic, 0x11 + pin*2, dest);
522 reg = io_apic_read(apic, 0x10 + pin*2);
523 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
525 io_apic_modify(apic, 0x10 + pin*2, reg);
532 static int assign_irq_vector(int irq, cpumask_t mask);
534 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
540 struct irq_desc *desc;
542 cpus_and(tmp, mask, cpu_online_map);
547 if (assign_irq_vector(irq, mask))
550 cpus_and(tmp, cfg->domain, mask);
551 dest = cpu_mask_to_apicid(tmp);
553 * Only the high 8 bits are valid.
555 dest = SET_APIC_LOGICAL_ID(dest);
557 desc = irq_to_desc(irq);
558 spin_lock_irqsave(&ioapic_lock, flags);
559 __target_IO_APIC_irq(irq, dest, cfg->vector);
560 desc->affinity = mask;
561 spin_unlock_irqrestore(&ioapic_lock, flags);
563 #endif /* CONFIG_SMP */
566 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
567 * shared ISA-space IRQs, so we have to support them. We are super
568 * fast in the common case, and fast for shared ISA-space IRQs.
570 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
573 struct irq_pin_list *entry;
575 /* first time to refer irq_cfg, so with new */
576 cfg = irq_cfg_alloc(irq);
577 entry = cfg->irq_2_pin;
579 entry = get_one_free_irq_2_pin();
580 cfg->irq_2_pin = entry;
586 while (entry->next) {
587 /* not again, please */
588 if (entry->apic == apic && entry->pin == pin)
594 entry->next = get_one_free_irq_2_pin();
601 * Reroute an IRQ to a different pin.
603 static void __init replace_pin_at_irq(unsigned int irq,
604 int oldapic, int oldpin,
605 int newapic, int newpin)
607 struct irq_cfg *cfg = irq_cfg(irq);
608 struct irq_pin_list *entry = cfg->irq_2_pin;
612 if (entry->apic == oldapic && entry->pin == oldpin) {
613 entry->apic = newapic;
616 /* every one is different, right? */
622 /* why? call replace before add? */
624 add_pin_to_irq(irq, newapic, newpin);
627 static inline void io_apic_modify_irq(unsigned int irq,
628 int mask_and, int mask_or,
629 void (*final)(struct irq_pin_list *entry))
633 struct irq_pin_list *entry;
636 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
639 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
642 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
648 static void __unmask_IO_APIC_irq(unsigned int irq)
650 io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED, 0, NULL);
654 void io_apic_sync(struct irq_pin_list *entry)
657 * Synchronize the IO-APIC and the CPU by doing
658 * a dummy read from the IO-APIC
660 struct io_apic __iomem *io_apic;
661 io_apic = io_apic_base(entry->apic);
662 readl(&io_apic->data);
665 static void __mask_IO_APIC_irq(unsigned int irq)
667 io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
669 #else /* CONFIG_X86_32 */
670 static void __mask_IO_APIC_irq(unsigned int irq)
672 io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, NULL);
675 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
677 io_apic_modify_irq(irq, ~IO_APIC_REDIR_LEVEL_TRIGGER,
678 IO_APIC_REDIR_MASKED, NULL);
681 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
683 io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED,
684 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
686 #endif /* CONFIG_X86_32 */
688 static void mask_IO_APIC_irq (unsigned int irq)
692 spin_lock_irqsave(&ioapic_lock, flags);
693 __mask_IO_APIC_irq(irq);
694 spin_unlock_irqrestore(&ioapic_lock, flags);
697 static void unmask_IO_APIC_irq (unsigned int irq)
701 spin_lock_irqsave(&ioapic_lock, flags);
702 __unmask_IO_APIC_irq(irq);
703 spin_unlock_irqrestore(&ioapic_lock, flags);
706 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
708 struct IO_APIC_route_entry entry;
710 /* Check delivery_mode to be sure we're not clearing an SMI pin */
711 entry = ioapic_read_entry(apic, pin);
712 if (entry.delivery_mode == dest_SMI)
715 * Disable it in the IO-APIC irq-routing table:
717 ioapic_mask_entry(apic, pin);
720 static void clear_IO_APIC (void)
724 for (apic = 0; apic < nr_ioapics; apic++)
725 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
726 clear_IO_APIC_pin(apic, pin);
729 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
730 void send_IPI_self(int vector)
737 apic_wait_icr_idle();
738 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
740 * Send the IPI. The write to APIC_ICR fires this off.
742 apic_write(APIC_ICR, cfg);
744 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
748 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
749 * specific CPU-side IRQs.
753 static int pirq_entries [MAX_PIRQS];
754 static int pirqs_enabled;
756 static int __init ioapic_pirq_setup(char *str)
759 int ints[MAX_PIRQS+1];
761 get_options(str, ARRAY_SIZE(ints), ints);
763 for (i = 0; i < MAX_PIRQS; i++)
764 pirq_entries[i] = -1;
767 apic_printk(APIC_VERBOSE, KERN_INFO
768 "PIRQ redirection, working around broken MP-BIOS.\n");
770 if (ints[0] < MAX_PIRQS)
773 for (i = 0; i < max; i++) {
774 apic_printk(APIC_VERBOSE, KERN_DEBUG
775 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
777 * PIRQs are mapped upside down, usually.
779 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
784 __setup("pirq=", ioapic_pirq_setup);
785 #endif /* CONFIG_X86_32 */
787 #ifdef CONFIG_INTR_REMAP
788 /* I/O APIC RTE contents at the OS boot up */
789 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
792 * Saves and masks all the unmasked IO-APIC RTE's
794 int save_mask_IO_APIC_setup(void)
796 union IO_APIC_reg_01 reg_01;
801 * The number of IO-APIC IRQ registers (== #pins):
803 for (apic = 0; apic < nr_ioapics; apic++) {
804 spin_lock_irqsave(&ioapic_lock, flags);
805 reg_01.raw = io_apic_read(apic, 1);
806 spin_unlock_irqrestore(&ioapic_lock, flags);
807 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
810 for (apic = 0; apic < nr_ioapics; apic++) {
811 early_ioapic_entries[apic] =
812 kzalloc(sizeof(struct IO_APIC_route_entry) *
813 nr_ioapic_registers[apic], GFP_KERNEL);
814 if (!early_ioapic_entries[apic])
818 for (apic = 0; apic < nr_ioapics; apic++)
819 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
820 struct IO_APIC_route_entry entry;
822 entry = early_ioapic_entries[apic][pin] =
823 ioapic_read_entry(apic, pin);
826 ioapic_write_entry(apic, pin, entry);
832 void restore_IO_APIC_setup(void)
836 for (apic = 0; apic < nr_ioapics; apic++)
837 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
838 ioapic_write_entry(apic, pin,
839 early_ioapic_entries[apic][pin]);
842 void reinit_intr_remapped_IO_APIC(int intr_remapping)
845 * for now plain restore of previous settings.
846 * TBD: In the case of OS enabling interrupt-remapping,
847 * IO-APIC RTE's need to be setup to point to interrupt-remapping
848 * table entries. for now, do a plain restore, and wait for
849 * the setup_IO_APIC_irqs() to do proper initialization.
851 restore_IO_APIC_setup();
856 * Find the IRQ entry number of a certain pin.
858 static int find_irq_entry(int apic, int pin, int type)
862 for (i = 0; i < mp_irq_entries; i++)
863 if (mp_irqs[i].mp_irqtype == type &&
864 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
865 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
866 mp_irqs[i].mp_dstirq == pin)
873 * Find the pin to which IRQ[irq] (ISA) is connected
875 static int __init find_isa_irq_pin(int irq, int type)
879 for (i = 0; i < mp_irq_entries; i++) {
880 int lbus = mp_irqs[i].mp_srcbus;
882 if (test_bit(lbus, mp_bus_not_pci) &&
883 (mp_irqs[i].mp_irqtype == type) &&
884 (mp_irqs[i].mp_srcbusirq == irq))
886 return mp_irqs[i].mp_dstirq;
891 static int __init find_isa_irq_apic(int irq, int type)
895 for (i = 0; i < mp_irq_entries; i++) {
896 int lbus = mp_irqs[i].mp_srcbus;
898 if (test_bit(lbus, mp_bus_not_pci) &&
899 (mp_irqs[i].mp_irqtype == type) &&
900 (mp_irqs[i].mp_srcbusirq == irq))
903 if (i < mp_irq_entries) {
905 for(apic = 0; apic < nr_ioapics; apic++) {
906 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
915 * Find a specific PCI IRQ entry.
916 * Not an __init, possibly needed by modules
918 static int pin_2_irq(int idx, int apic, int pin);
920 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
922 int apic, i, best_guess = -1;
924 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
926 if (test_bit(bus, mp_bus_not_pci)) {
927 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
930 for (i = 0; i < mp_irq_entries; i++) {
931 int lbus = mp_irqs[i].mp_srcbus;
933 for (apic = 0; apic < nr_ioapics; apic++)
934 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
935 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
938 if (!test_bit(lbus, mp_bus_not_pci) &&
939 !mp_irqs[i].mp_irqtype &&
941 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
942 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
944 if (!(apic || IO_APIC_IRQ(irq)))
947 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
950 * Use the first all-but-pin matching entry as a
951 * best-guess fuzzy result for broken mptables.
960 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
962 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
964 * EISA Edge/Level control register, ELCR
966 static int EISA_ELCR(unsigned int irq)
969 unsigned int port = 0x4d0 + (irq >> 3);
970 return (inb(port) >> (irq & 7)) & 1;
972 apic_printk(APIC_VERBOSE, KERN_INFO
973 "Broken MPtable reports ISA irq %d\n", irq);
979 /* ISA interrupts are always polarity zero edge triggered,
980 * when listed as conforming in the MP table. */
982 #define default_ISA_trigger(idx) (0)
983 #define default_ISA_polarity(idx) (0)
985 /* EISA interrupts are always polarity zero and can be edge or level
986 * trigger depending on the ELCR value. If an interrupt is listed as
987 * EISA conforming in the MP table, that means its trigger type must
988 * be read in from the ELCR */
990 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
991 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
993 /* PCI interrupts are always polarity one level triggered,
994 * when listed as conforming in the MP table. */
996 #define default_PCI_trigger(idx) (1)
997 #define default_PCI_polarity(idx) (1)
999 /* MCA interrupts are always polarity zero level triggered,
1000 * when listed as conforming in the MP table. */
1002 #define default_MCA_trigger(idx) (1)
1003 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1005 static int MPBIOS_polarity(int idx)
1007 int bus = mp_irqs[idx].mp_srcbus;
1011 * Determine IRQ line polarity (high active or low active):
1013 switch (mp_irqs[idx].mp_irqflag & 3)
1015 case 0: /* conforms, ie. bus-type dependent polarity */
1016 if (test_bit(bus, mp_bus_not_pci))
1017 polarity = default_ISA_polarity(idx);
1019 polarity = default_PCI_polarity(idx);
1021 case 1: /* high active */
1026 case 2: /* reserved */
1028 printk(KERN_WARNING "broken BIOS!!\n");
1032 case 3: /* low active */
1037 default: /* invalid */
1039 printk(KERN_WARNING "broken BIOS!!\n");
1047 static int MPBIOS_trigger(int idx)
1049 int bus = mp_irqs[idx].mp_srcbus;
1053 * Determine IRQ trigger mode (edge or level sensitive):
1055 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1057 case 0: /* conforms, ie. bus-type dependent */
1058 if (test_bit(bus, mp_bus_not_pci))
1059 trigger = default_ISA_trigger(idx);
1061 trigger = default_PCI_trigger(idx);
1062 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1063 switch (mp_bus_id_to_type[bus]) {
1064 case MP_BUS_ISA: /* ISA pin */
1066 /* set before the switch */
1069 case MP_BUS_EISA: /* EISA pin */
1071 trigger = default_EISA_trigger(idx);
1074 case MP_BUS_PCI: /* PCI pin */
1076 /* set before the switch */
1079 case MP_BUS_MCA: /* MCA pin */
1081 trigger = default_MCA_trigger(idx);
1086 printk(KERN_WARNING "broken BIOS!!\n");
1098 case 2: /* reserved */
1100 printk(KERN_WARNING "broken BIOS!!\n");
1109 default: /* invalid */
1111 printk(KERN_WARNING "broken BIOS!!\n");
1119 static inline int irq_polarity(int idx)
1121 return MPBIOS_polarity(idx);
1124 static inline int irq_trigger(int idx)
1126 return MPBIOS_trigger(idx);
1129 int (*ioapic_renumber_irq)(int ioapic, int irq);
1130 static int pin_2_irq(int idx, int apic, int pin)
1133 int bus = mp_irqs[idx].mp_srcbus;
1136 * Debugging check, we are in big trouble if this message pops up!
1138 if (mp_irqs[idx].mp_dstirq != pin)
1139 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1141 if (test_bit(bus, mp_bus_not_pci)) {
1142 irq = mp_irqs[idx].mp_srcbusirq;
1145 * PCI IRQs are mapped in order
1149 irq += nr_ioapic_registers[i++];
1152 * For MPS mode, so far only needed by ES7000 platform
1154 if (ioapic_renumber_irq)
1155 irq = ioapic_renumber_irq(apic, irq);
1158 #ifdef CONFIG_X86_32
1160 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1162 if ((pin >= 16) && (pin <= 23)) {
1163 if (pirq_entries[pin-16] != -1) {
1164 if (!pirq_entries[pin-16]) {
1165 apic_printk(APIC_VERBOSE, KERN_DEBUG
1166 "disabling PIRQ%d\n", pin-16);
1168 irq = pirq_entries[pin-16];
1169 apic_printk(APIC_VERBOSE, KERN_DEBUG
1170 "using PIRQ%d -> IRQ %d\n",
1180 void lock_vector_lock(void)
1182 /* Used to the online set of cpus does not change
1183 * during assign_irq_vector.
1185 spin_lock(&vector_lock);
1188 void unlock_vector_lock(void)
1190 spin_unlock(&vector_lock);
1193 static int __assign_irq_vector(int irq, cpumask_t mask)
1196 * NOTE! The local APIC isn't very good at handling
1197 * multiple interrupts at the same interrupt level.
1198 * As the interrupt level is determined by taking the
1199 * vector number and shifting that right by 4, we
1200 * want to spread these out a bit so that they don't
1201 * all fall in the same interrupt level.
1203 * Also, we've got to be careful not to trash gate
1204 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1206 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1207 unsigned int old_vector;
1209 struct irq_cfg *cfg;
1213 /* Only try and allocate irqs on cpus that are present */
1214 cpus_and(mask, mask, cpu_online_map);
1216 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1219 old_vector = cfg->vector;
1222 cpus_and(tmp, cfg->domain, mask);
1223 if (!cpus_empty(tmp))
1227 for_each_cpu_mask_nr(cpu, mask) {
1228 cpumask_t domain, new_mask;
1232 domain = vector_allocation_domain(cpu);
1233 cpus_and(new_mask, domain, cpu_online_map);
1235 vector = current_vector;
1236 offset = current_offset;
1239 if (vector >= first_system_vector) {
1240 /* If we run out of vectors on large boxen, must share them. */
1241 offset = (offset + 1) % 8;
1242 vector = FIRST_DEVICE_VECTOR + offset;
1244 if (unlikely(current_vector == vector))
1246 #ifdef CONFIG_X86_64
1247 if (vector == IA32_SYSCALL_VECTOR)
1250 if (vector == SYSCALL_VECTOR)
1253 for_each_cpu_mask_nr(new_cpu, new_mask)
1254 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1257 current_vector = vector;
1258 current_offset = offset;
1260 cfg->move_in_progress = 1;
1261 cfg->old_domain = cfg->domain;
1263 for_each_cpu_mask_nr(new_cpu, new_mask)
1264 per_cpu(vector_irq, new_cpu)[vector] = irq;
1265 cfg->vector = vector;
1266 cfg->domain = domain;
1272 static int assign_irq_vector(int irq, cpumask_t mask)
1275 unsigned long flags;
1277 spin_lock_irqsave(&vector_lock, flags);
1278 err = __assign_irq_vector(irq, mask);
1279 spin_unlock_irqrestore(&vector_lock, flags);
1283 static void __clear_irq_vector(int irq)
1285 struct irq_cfg *cfg;
1290 BUG_ON(!cfg->vector);
1292 vector = cfg->vector;
1293 cpus_and(mask, cfg->domain, cpu_online_map);
1294 for_each_cpu_mask_nr(cpu, mask)
1295 per_cpu(vector_irq, cpu)[vector] = -1;
1298 cpus_clear(cfg->domain);
1301 void __setup_vector_irq(int cpu)
1303 /* Initialize vector_irq on a new cpu */
1304 /* This function must be called with vector_lock held */
1306 struct irq_cfg *cfg;
1308 /* Mark the inuse vectors */
1309 for_each_irq_cfg(irq, cfg) {
1310 if (!cpu_isset(cpu, cfg->domain))
1312 vector = cfg->vector;
1313 per_cpu(vector_irq, cpu)[vector] = irq;
1315 /* Mark the free vectors */
1316 for (vector = 0; vector < NR_VECTORS; ++vector) {
1317 irq = per_cpu(vector_irq, cpu)[vector];
1322 if (!cpu_isset(cpu, cfg->domain))
1323 per_cpu(vector_irq, cpu)[vector] = -1;
1327 static struct irq_chip ioapic_chip;
1328 #ifdef CONFIG_INTR_REMAP
1329 static struct irq_chip ir_ioapic_chip;
1332 #define IOAPIC_AUTO -1
1333 #define IOAPIC_EDGE 0
1334 #define IOAPIC_LEVEL 1
1336 #ifdef CONFIG_X86_32
1337 static inline int IO_APIC_irq_trigger(int irq)
1341 for (apic = 0; apic < nr_ioapics; apic++) {
1342 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1343 idx = find_irq_entry(apic, pin, mp_INT);
1344 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1345 return irq_trigger(idx);
1349 * nonexistent IRQs are edge default
1354 static inline int IO_APIC_irq_trigger(int irq)
1360 static void ioapic_register_intr(int irq, unsigned long trigger)
1362 struct irq_desc *desc;
1364 /* first time to use this irq_desc */
1366 desc = irq_to_desc(irq);
1368 desc = irq_to_desc_alloc(irq);
1370 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1371 trigger == IOAPIC_LEVEL)
1372 desc->status |= IRQ_LEVEL;
1374 desc->status &= ~IRQ_LEVEL;
1376 #ifdef CONFIG_INTR_REMAP
1377 if (irq_remapped(irq)) {
1378 desc->status |= IRQ_MOVE_PCNTXT;
1380 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1384 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1385 handle_edge_irq, "edge");
1389 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1390 trigger == IOAPIC_LEVEL)
1391 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1395 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1396 handle_edge_irq, "edge");
1399 static int setup_ioapic_entry(int apic, int irq,
1400 struct IO_APIC_route_entry *entry,
1401 unsigned int destination, int trigger,
1402 int polarity, int vector)
1405 * add it to the IO-APIC irq-routing table:
1407 memset(entry,0,sizeof(*entry));
1409 #ifdef CONFIG_INTR_REMAP
1410 if (intr_remapping_enabled) {
1411 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1413 struct IR_IO_APIC_route_entry *ir_entry =
1414 (struct IR_IO_APIC_route_entry *) entry;
1418 panic("No mapping iommu for ioapic %d\n", apic);
1420 index = alloc_irte(iommu, irq, 1);
1422 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1424 memset(&irte, 0, sizeof(irte));
1427 irte.dst_mode = INT_DEST_MODE;
1428 irte.trigger_mode = trigger;
1429 irte.dlvry_mode = INT_DELIVERY_MODE;
1430 irte.vector = vector;
1431 irte.dest_id = IRTE_DEST(destination);
1433 modify_irte(irq, &irte);
1435 ir_entry->index2 = (index >> 15) & 0x1;
1437 ir_entry->format = 1;
1438 ir_entry->index = (index & 0x7fff);
1442 entry->delivery_mode = INT_DELIVERY_MODE;
1443 entry->dest_mode = INT_DEST_MODE;
1444 entry->dest = destination;
1447 entry->mask = 0; /* enable IRQ */
1448 entry->trigger = trigger;
1449 entry->polarity = polarity;
1450 entry->vector = vector;
1452 /* Mask level triggered irqs.
1453 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1460 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1461 int trigger, int polarity)
1463 struct irq_cfg *cfg;
1464 struct IO_APIC_route_entry entry;
1467 if (!IO_APIC_IRQ(irq))
1473 if (assign_irq_vector(irq, mask))
1476 cpus_and(mask, cfg->domain, mask);
1478 apic_printk(APIC_VERBOSE,KERN_DEBUG
1479 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1480 "IRQ %d Mode:%i Active:%i)\n",
1481 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1482 irq, trigger, polarity);
1485 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1486 cpu_mask_to_apicid(mask), trigger, polarity,
1488 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1489 mp_ioapics[apic].mp_apicid, pin);
1490 __clear_irq_vector(irq);
1494 ioapic_register_intr(irq, trigger);
1496 disable_8259A_irq(irq);
1498 ioapic_write_entry(apic, pin, entry);
1501 static void __init setup_IO_APIC_irqs(void)
1503 int apic, pin, idx, irq;
1506 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1508 for (apic = 0; apic < nr_ioapics; apic++) {
1509 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1511 idx = find_irq_entry(apic, pin, mp_INT);
1515 apic_printk(APIC_VERBOSE,
1516 KERN_DEBUG " %d-%d",
1517 mp_ioapics[apic].mp_apicid,
1520 apic_printk(APIC_VERBOSE, " %d-%d",
1521 mp_ioapics[apic].mp_apicid,
1526 apic_printk(APIC_VERBOSE,
1527 " (apicid-pin) not connected\n");
1531 irq = pin_2_irq(idx, apic, pin);
1532 #ifdef CONFIG_X86_32
1533 if (multi_timer_check(apic, irq))
1536 add_pin_to_irq(irq, apic, pin);
1538 setup_IO_APIC_irq(apic, pin, irq,
1539 irq_trigger(idx), irq_polarity(idx));
1544 apic_printk(APIC_VERBOSE,
1545 " (apicid-pin) not connected\n");
1549 * Set up the timer pin, possibly with the 8259A-master behind.
1551 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1554 struct IO_APIC_route_entry entry;
1556 #ifdef CONFIG_INTR_REMAP
1557 if (intr_remapping_enabled)
1561 memset(&entry, 0, sizeof(entry));
1564 * We use logical delivery to get the timer IRQ
1567 entry.dest_mode = INT_DEST_MODE;
1568 entry.mask = 1; /* mask IRQ now */
1569 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1570 entry.delivery_mode = INT_DELIVERY_MODE;
1573 entry.vector = vector;
1576 * The timer IRQ doesn't have to know that behind the
1577 * scene we may have a 8259A-master in AEOI mode ...
1579 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1582 * Add it to the IO-APIC irq-routing table:
1584 ioapic_write_entry(apic, pin, entry);
1588 __apicdebuginit(void) print_IO_APIC(void)
1591 union IO_APIC_reg_00 reg_00;
1592 union IO_APIC_reg_01 reg_01;
1593 union IO_APIC_reg_02 reg_02;
1594 union IO_APIC_reg_03 reg_03;
1595 unsigned long flags;
1596 struct irq_cfg *cfg;
1599 if (apic_verbosity == APIC_QUIET)
1602 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1603 for (i = 0; i < nr_ioapics; i++)
1604 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1605 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1608 * We are a bit conservative about what we expect. We have to
1609 * know about every hardware change ASAP.
1611 printk(KERN_INFO "testing the IO APIC.......................\n");
1613 for (apic = 0; apic < nr_ioapics; apic++) {
1615 spin_lock_irqsave(&ioapic_lock, flags);
1616 reg_00.raw = io_apic_read(apic, 0);
1617 reg_01.raw = io_apic_read(apic, 1);
1618 if (reg_01.bits.version >= 0x10)
1619 reg_02.raw = io_apic_read(apic, 2);
1620 if (reg_01.bits.version >= 0x20)
1621 reg_03.raw = io_apic_read(apic, 3);
1622 spin_unlock_irqrestore(&ioapic_lock, flags);
1625 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1626 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1627 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1628 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1629 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1631 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1632 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1634 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1635 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1638 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1639 * but the value of reg_02 is read as the previous read register
1640 * value, so ignore it if reg_02 == reg_01.
1642 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1643 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1644 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1648 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1649 * or reg_03, but the value of reg_0[23] is read as the previous read
1650 * register value, so ignore it if reg_03 == reg_0[12].
1652 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1653 reg_03.raw != reg_01.raw) {
1654 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1655 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1658 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1660 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1661 " Stat Dmod Deli Vect: \n");
1663 for (i = 0; i <= reg_01.bits.entries; i++) {
1664 struct IO_APIC_route_entry entry;
1666 entry = ioapic_read_entry(apic, i);
1668 printk(KERN_DEBUG " %02x %03X ",
1673 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1678 entry.delivery_status,
1680 entry.delivery_mode,
1685 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1686 for_each_irq_cfg(irq, cfg) {
1687 struct irq_pin_list *entry = cfg->irq_2_pin;
1690 printk(KERN_DEBUG "IRQ%d ", irq);
1692 printk("-> %d:%d", entry->apic, entry->pin);
1695 entry = entry->next;
1700 printk(KERN_INFO ".................................... done.\n");
1705 __apicdebuginit(void) print_APIC_bitfield(int base)
1710 if (apic_verbosity == APIC_QUIET)
1713 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1714 for (i = 0; i < 8; i++) {
1715 v = apic_read(base + i*0x10);
1716 for (j = 0; j < 32; j++) {
1726 __apicdebuginit(void) print_local_APIC(void *dummy)
1728 unsigned int v, ver, maxlvt;
1731 if (apic_verbosity == APIC_QUIET)
1734 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1735 smp_processor_id(), hard_smp_processor_id());
1736 v = apic_read(APIC_ID);
1737 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1738 v = apic_read(APIC_LVR);
1739 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1740 ver = GET_APIC_VERSION(v);
1741 maxlvt = lapic_get_maxlvt();
1743 v = apic_read(APIC_TASKPRI);
1744 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1746 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1747 if (!APIC_XAPIC(ver)) {
1748 v = apic_read(APIC_ARBPRI);
1749 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1750 v & APIC_ARBPRI_MASK);
1752 v = apic_read(APIC_PROCPRI);
1753 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1757 * Remote read supported only in the 82489DX and local APIC for
1758 * Pentium processors.
1760 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1761 v = apic_read(APIC_RRR);
1762 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1765 v = apic_read(APIC_LDR);
1766 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1767 if (!x2apic_enabled()) {
1768 v = apic_read(APIC_DFR);
1769 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1771 v = apic_read(APIC_SPIV);
1772 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1774 printk(KERN_DEBUG "... APIC ISR field:\n");
1775 print_APIC_bitfield(APIC_ISR);
1776 printk(KERN_DEBUG "... APIC TMR field:\n");
1777 print_APIC_bitfield(APIC_TMR);
1778 printk(KERN_DEBUG "... APIC IRR field:\n");
1779 print_APIC_bitfield(APIC_IRR);
1781 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1782 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1783 apic_write(APIC_ESR, 0);
1785 v = apic_read(APIC_ESR);
1786 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1789 icr = apic_icr_read();
1790 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1791 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1793 v = apic_read(APIC_LVTT);
1794 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1796 if (maxlvt > 3) { /* PC is LVT#4. */
1797 v = apic_read(APIC_LVTPC);
1798 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1800 v = apic_read(APIC_LVT0);
1801 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1802 v = apic_read(APIC_LVT1);
1803 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1805 if (maxlvt > 2) { /* ERR is LVT#3. */
1806 v = apic_read(APIC_LVTERR);
1807 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1810 v = apic_read(APIC_TMICT);
1811 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1812 v = apic_read(APIC_TMCCT);
1813 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1814 v = apic_read(APIC_TDCR);
1815 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1819 __apicdebuginit(void) print_all_local_APICs(void)
1824 for_each_online_cpu(cpu)
1825 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1829 __apicdebuginit(void) print_PIC(void)
1832 unsigned long flags;
1834 if (apic_verbosity == APIC_QUIET)
1837 printk(KERN_DEBUG "\nprinting PIC contents\n");
1839 spin_lock_irqsave(&i8259A_lock, flags);
1841 v = inb(0xa1) << 8 | inb(0x21);
1842 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1844 v = inb(0xa0) << 8 | inb(0x20);
1845 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1849 v = inb(0xa0) << 8 | inb(0x20);
1853 spin_unlock_irqrestore(&i8259A_lock, flags);
1855 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1857 v = inb(0x4d1) << 8 | inb(0x4d0);
1858 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1861 __apicdebuginit(int) print_all_ICs(void)
1864 print_all_local_APICs();
1870 fs_initcall(print_all_ICs);
1873 /* Where if anywhere is the i8259 connect in external int mode */
1874 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1876 void __init enable_IO_APIC(void)
1878 union IO_APIC_reg_01 reg_01;
1879 int i8259_apic, i8259_pin;
1881 unsigned long flags;
1883 #ifdef CONFIG_X86_32
1886 for (i = 0; i < MAX_PIRQS; i++)
1887 pirq_entries[i] = -1;
1891 * The number of IO-APIC IRQ registers (== #pins):
1893 for (apic = 0; apic < nr_ioapics; apic++) {
1894 spin_lock_irqsave(&ioapic_lock, flags);
1895 reg_01.raw = io_apic_read(apic, 1);
1896 spin_unlock_irqrestore(&ioapic_lock, flags);
1897 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1899 for(apic = 0; apic < nr_ioapics; apic++) {
1901 /* See if any of the pins is in ExtINT mode */
1902 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1903 struct IO_APIC_route_entry entry;
1904 entry = ioapic_read_entry(apic, pin);
1906 /* If the interrupt line is enabled and in ExtInt mode
1907 * I have found the pin where the i8259 is connected.
1909 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1910 ioapic_i8259.apic = apic;
1911 ioapic_i8259.pin = pin;
1917 /* Look to see what if the MP table has reported the ExtINT */
1918 /* If we could not find the appropriate pin by looking at the ioapic
1919 * the i8259 probably is not connected the ioapic but give the
1920 * mptable a chance anyway.
1922 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1923 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1924 /* Trust the MP table if nothing is setup in the hardware */
1925 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1926 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1927 ioapic_i8259.pin = i8259_pin;
1928 ioapic_i8259.apic = i8259_apic;
1930 /* Complain if the MP table and the hardware disagree */
1931 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1932 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1934 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1938 * Do not trust the IO-APIC being empty at bootup
1944 * Not an __init, needed by the reboot code
1946 void disable_IO_APIC(void)
1949 * Clear the IO-APIC before rebooting:
1954 * If the i8259 is routed through an IOAPIC
1955 * Put that IOAPIC in virtual wire mode
1956 * so legacy interrupts can be delivered.
1958 if (ioapic_i8259.pin != -1) {
1959 struct IO_APIC_route_entry entry;
1961 memset(&entry, 0, sizeof(entry));
1962 entry.mask = 0; /* Enabled */
1963 entry.trigger = 0; /* Edge */
1965 entry.polarity = 0; /* High */
1966 entry.delivery_status = 0;
1967 entry.dest_mode = 0; /* Physical */
1968 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1970 entry.dest = read_apic_id();
1973 * Add it to the IO-APIC irq-routing table:
1975 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1978 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1981 #ifdef CONFIG_X86_32
1983 * function to set the IO-APIC physical IDs based on the
1984 * values stored in the MPC table.
1986 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1989 static void __init setup_ioapic_ids_from_mpc(void)
1991 union IO_APIC_reg_00 reg_00;
1992 physid_mask_t phys_id_present_map;
1995 unsigned char old_id;
1996 unsigned long flags;
1998 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2002 * Don't check I/O APIC IDs for xAPIC systems. They have
2003 * no meaning without the serial APIC bus.
2005 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2006 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2009 * This is broken; anything with a real cpu count has to
2010 * circumvent this idiocy regardless.
2012 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
2015 * Set the IOAPIC ID to the value stored in the MPC table.
2017 for (apic = 0; apic < nr_ioapics; apic++) {
2019 /* Read the register 0 value */
2020 spin_lock_irqsave(&ioapic_lock, flags);
2021 reg_00.raw = io_apic_read(apic, 0);
2022 spin_unlock_irqrestore(&ioapic_lock, flags);
2024 old_id = mp_ioapics[apic].mp_apicid;
2026 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
2027 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2028 apic, mp_ioapics[apic].mp_apicid);
2029 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2031 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
2035 * Sanity check, is the ID really free? Every APIC in a
2036 * system must have a unique ID or we get lots of nice
2037 * 'stuck on smp_invalidate_needed IPI wait' messages.
2039 if (check_apicid_used(phys_id_present_map,
2040 mp_ioapics[apic].mp_apicid)) {
2041 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2042 apic, mp_ioapics[apic].mp_apicid);
2043 for (i = 0; i < get_physical_broadcast(); i++)
2044 if (!physid_isset(i, phys_id_present_map))
2046 if (i >= get_physical_broadcast())
2047 panic("Max APIC ID exceeded!\n");
2048 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2050 physid_set(i, phys_id_present_map);
2051 mp_ioapics[apic].mp_apicid = i;
2054 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
2055 apic_printk(APIC_VERBOSE, "Setting %d in the "
2056 "phys_id_present_map\n",
2057 mp_ioapics[apic].mp_apicid);
2058 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2063 * We need to adjust the IRQ routing table
2064 * if the ID changed.
2066 if (old_id != mp_ioapics[apic].mp_apicid)
2067 for (i = 0; i < mp_irq_entries; i++)
2068 if (mp_irqs[i].mp_dstapic == old_id)
2069 mp_irqs[i].mp_dstapic
2070 = mp_ioapics[apic].mp_apicid;
2073 * Read the right value from the MPC table and
2074 * write it into the ID register.
2076 apic_printk(APIC_VERBOSE, KERN_INFO
2077 "...changing IO-APIC physical APIC ID to %d ...",
2078 mp_ioapics[apic].mp_apicid);
2080 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
2081 spin_lock_irqsave(&ioapic_lock, flags);
2082 io_apic_write(apic, 0, reg_00.raw);
2083 spin_unlock_irqrestore(&ioapic_lock, flags);
2088 spin_lock_irqsave(&ioapic_lock, flags);
2089 reg_00.raw = io_apic_read(apic, 0);
2090 spin_unlock_irqrestore(&ioapic_lock, flags);
2091 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
2092 printk("could not set ID!\n");
2094 apic_printk(APIC_VERBOSE, " ok.\n");
2099 int no_timer_check __initdata;
2101 static int __init notimercheck(char *s)
2106 __setup("no_timer_check", notimercheck);
2109 * There is a nasty bug in some older SMP boards, their mptable lies
2110 * about the timer IRQ. We do the following to work around the situation:
2112 * - timer IRQ defaults to IO-APIC IRQ
2113 * - if this function detects that timer IRQs are defunct, then we fall
2114 * back to ISA timer IRQs
2116 static int __init timer_irq_works(void)
2118 unsigned long t1 = jiffies;
2119 unsigned long flags;
2124 local_save_flags(flags);
2126 /* Let ten ticks pass... */
2127 mdelay((10 * 1000) / HZ);
2128 local_irq_restore(flags);
2131 * Expect a few ticks at least, to be sure some possible
2132 * glue logic does not lock up after one or two first
2133 * ticks in a non-ExtINT mode. Also the local APIC
2134 * might have cached one ExtINT interrupt. Finally, at
2135 * least one tick may be lost due to delays.
2139 if (time_after(jiffies, t1 + 4))
2145 * In the SMP+IOAPIC case it might happen that there are an unspecified
2146 * number of pending IRQ events unhandled. These cases are very rare,
2147 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2148 * better to do it this way as thus we do not have to be aware of
2149 * 'pending' interrupts in the IRQ path, except at this point.
2152 * Edge triggered needs to resend any interrupt
2153 * that was delayed but this is now handled in the device
2158 * Starting up a edge-triggered IO-APIC interrupt is
2159 * nasty - we need to make sure that we get the edge.
2160 * If it is already asserted for some reason, we need
2161 * return 1 to indicate that is was pending.
2163 * This is not complete - we should be able to fake
2164 * an edge even if it isn't on the 8259A...
2167 static unsigned int startup_ioapic_irq(unsigned int irq)
2169 int was_pending = 0;
2170 unsigned long flags;
2172 spin_lock_irqsave(&ioapic_lock, flags);
2174 disable_8259A_irq(irq);
2175 if (i8259A_irq_pending(irq))
2178 __unmask_IO_APIC_irq(irq);
2179 spin_unlock_irqrestore(&ioapic_lock, flags);
2184 #ifdef CONFIG_X86_64
2185 static int ioapic_retrigger_irq(unsigned int irq)
2188 struct irq_cfg *cfg = irq_cfg(irq);
2189 unsigned long flags;
2191 spin_lock_irqsave(&vector_lock, flags);
2192 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2193 spin_unlock_irqrestore(&vector_lock, flags);
2198 static int ioapic_retrigger_irq(unsigned int irq)
2200 send_IPI_self(irq_cfg(irq)->vector);
2207 * Level and edge triggered IO-APIC interrupts need different handling,
2208 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2209 * handled with the level-triggered descriptor, but that one has slightly
2210 * more overhead. Level-triggered interrupts cannot be handled with the
2211 * edge-triggered handler, without risking IRQ storms and other ugly
2217 #ifdef CONFIG_INTR_REMAP
2218 static void ir_irq_migration(struct work_struct *work);
2220 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2223 * Migrate the IO-APIC irq in the presence of intr-remapping.
2225 * For edge triggered, irq migration is a simple atomic update(of vector
2226 * and cpu destination) of IRTE and flush the hardware cache.
2228 * For level triggered, we need to modify the io-apic RTE aswell with the update
2229 * vector information, along with modifying IRTE with vector and destination.
2230 * So irq migration for level triggered is little bit more complex compared to
2231 * edge triggered migration. But the good news is, we use the same algorithm
2232 * for level triggered migration as we have today, only difference being,
2233 * we now initiate the irq migration from process context instead of the
2234 * interrupt context.
2236 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2237 * suppression) to the IO-APIC, level triggered irq migration will also be
2238 * as simple as edge triggered migration and we can do the irq migration
2239 * with a simple atomic update to IO-APIC RTE.
2241 static void migrate_ioapic_irq(int irq, cpumask_t mask)
2243 struct irq_cfg *cfg;
2244 struct irq_desc *desc;
2245 cpumask_t tmp, cleanup_mask;
2247 int modify_ioapic_rte;
2249 unsigned long flags;
2251 cpus_and(tmp, mask, cpu_online_map);
2252 if (cpus_empty(tmp))
2255 if (get_irte(irq, &irte))
2258 if (assign_irq_vector(irq, mask))
2262 cpus_and(tmp, cfg->domain, mask);
2263 dest = cpu_mask_to_apicid(tmp);
2265 desc = irq_to_desc(irq);
2266 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2267 if (modify_ioapic_rte) {
2268 spin_lock_irqsave(&ioapic_lock, flags);
2269 __target_IO_APIC_irq(irq, dest, cfg->vector);
2270 spin_unlock_irqrestore(&ioapic_lock, flags);
2273 irte.vector = cfg->vector;
2274 irte.dest_id = IRTE_DEST(dest);
2277 * Modified the IRTE and flushes the Interrupt entry cache.
2279 modify_irte(irq, &irte);
2281 if (cfg->move_in_progress) {
2282 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2283 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2284 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2285 cfg->move_in_progress = 0;
2288 desc->affinity = mask;
2291 static int migrate_irq_remapped_level(int irq)
2294 struct irq_desc *desc = irq_to_desc(irq);
2296 mask_IO_APIC_irq(irq);
2298 if (io_apic_level_ack_pending(irq)) {
2300 * Interrupt in progress. Migrating irq now will change the
2301 * vector information in the IO-APIC RTE and that will confuse
2302 * the EOI broadcast performed by cpu.
2303 * So, delay the irq migration to the next instance.
2305 schedule_delayed_work(&ir_migration_work, 1);
2309 /* everthing is clear. we have right of way */
2310 migrate_ioapic_irq(irq, desc->pending_mask);
2313 desc->status &= ~IRQ_MOVE_PENDING;
2314 cpus_clear(desc->pending_mask);
2317 unmask_IO_APIC_irq(irq);
2321 static void ir_irq_migration(struct work_struct *work)
2324 struct irq_desc *desc;
2326 for_each_irq_desc(irq, desc) {
2327 if (desc->status & IRQ_MOVE_PENDING) {
2328 unsigned long flags;
2330 spin_lock_irqsave(&desc->lock, flags);
2331 if (!desc->chip->set_affinity ||
2332 !(desc->status & IRQ_MOVE_PENDING)) {
2333 desc->status &= ~IRQ_MOVE_PENDING;
2334 spin_unlock_irqrestore(&desc->lock, flags);
2338 desc->chip->set_affinity(irq, desc->pending_mask);
2339 spin_unlock_irqrestore(&desc->lock, flags);
2345 * Migrates the IRQ destination in the process context.
2347 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2349 struct irq_desc *desc = irq_to_desc(irq);
2351 if (desc->status & IRQ_LEVEL) {
2352 desc->status |= IRQ_MOVE_PENDING;
2353 desc->pending_mask = mask;
2354 migrate_irq_remapped_level(irq);
2358 migrate_ioapic_irq(irq, mask);
2362 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2364 unsigned vector, me;
2366 #ifdef CONFIG_X86_64
2371 me = smp_processor_id();
2372 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2374 struct irq_desc *desc;
2375 struct irq_cfg *cfg;
2376 irq = __get_cpu_var(vector_irq)[vector];
2378 desc = irq_to_desc(irq);
2383 spin_lock(&desc->lock);
2384 if (!cfg->move_cleanup_count)
2387 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2390 __get_cpu_var(vector_irq)[vector] = -1;
2391 cfg->move_cleanup_count--;
2393 spin_unlock(&desc->lock);
2399 static void irq_complete_move(unsigned int irq)
2401 struct irq_cfg *cfg = irq_cfg(irq);
2402 unsigned vector, me;
2404 if (likely(!cfg->move_in_progress))
2407 vector = ~get_irq_regs()->orig_ax;
2408 me = smp_processor_id();
2409 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2410 cpumask_t cleanup_mask;
2412 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2413 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2414 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2415 cfg->move_in_progress = 0;
2419 static inline void irq_complete_move(unsigned int irq) {}
2421 #ifdef CONFIG_INTR_REMAP
2422 static void ack_x2apic_level(unsigned int irq)
2427 static void ack_x2apic_edge(unsigned int irq)
2433 static void ack_apic_edge(unsigned int irq)
2435 irq_complete_move(irq);
2436 move_native_irq(irq);
2440 #ifdef CONFIG_X86_32
2441 atomic_t irq_mis_count;
2444 static void ack_apic_level(unsigned int irq)
2446 #ifdef CONFIG_X86_32
2450 int do_unmask_irq = 0;
2452 irq_complete_move(irq);
2453 #ifdef CONFIG_GENERIC_PENDING_IRQ
2454 /* If we are moving the irq we need to mask it */
2455 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2457 mask_IO_APIC_irq(irq);
2461 #ifdef CONFIG_X86_32
2463 * It appears there is an erratum which affects at least version 0x11
2464 * of I/O APIC (that's the 82093AA and cores integrated into various
2465 * chipsets). Under certain conditions a level-triggered interrupt is
2466 * erroneously delivered as edge-triggered one but the respective IRR
2467 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2468 * message but it will never arrive and further interrupts are blocked
2469 * from the source. The exact reason is so far unknown, but the
2470 * phenomenon was observed when two consecutive interrupt requests
2471 * from a given source get delivered to the same CPU and the source is
2472 * temporarily disabled in between.
2474 * A workaround is to simulate an EOI message manually. We achieve it
2475 * by setting the trigger mode to edge and then to level when the edge
2476 * trigger mode gets detected in the TMR of a local APIC for a
2477 * level-triggered interrupt. We mask the source for the time of the
2478 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2479 * The idea is from Manfred Spraul. --macro
2481 i = irq_cfg(irq)->vector;
2483 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2487 * We must acknowledge the irq before we move it or the acknowledge will
2488 * not propagate properly.
2492 /* Now we can move and renable the irq */
2493 if (unlikely(do_unmask_irq)) {
2494 /* Only migrate the irq if the ack has been received.
2496 * On rare occasions the broadcast level triggered ack gets
2497 * delayed going to ioapics, and if we reprogram the
2498 * vector while Remote IRR is still set the irq will never
2501 * To prevent this scenario we read the Remote IRR bit
2502 * of the ioapic. This has two effects.
2503 * - On any sane system the read of the ioapic will
2504 * flush writes (and acks) going to the ioapic from
2506 * - We get to see if the ACK has actually been delivered.
2508 * Based on failed experiments of reprogramming the
2509 * ioapic entry from outside of irq context starting
2510 * with masking the ioapic entry and then polling until
2511 * Remote IRR was clear before reprogramming the
2512 * ioapic I don't trust the Remote IRR bit to be
2513 * completey accurate.
2515 * However there appears to be no other way to plug
2516 * this race, so if the Remote IRR bit is not
2517 * accurate and is causing problems then it is a hardware bug
2518 * and you can go talk to the chipset vendor about it.
2520 if (!io_apic_level_ack_pending(irq))
2521 move_masked_irq(irq);
2522 unmask_IO_APIC_irq(irq);
2525 #ifdef CONFIG_X86_32
2526 if (!(v & (1 << (i & 0x1f)))) {
2527 atomic_inc(&irq_mis_count);
2528 spin_lock(&ioapic_lock);
2529 __mask_and_edge_IO_APIC_irq(irq);
2530 __unmask_and_level_IO_APIC_irq(irq);
2531 spin_unlock(&ioapic_lock);
2536 static struct irq_chip ioapic_chip __read_mostly = {
2538 .startup = startup_ioapic_irq,
2539 .mask = mask_IO_APIC_irq,
2540 .unmask = unmask_IO_APIC_irq,
2541 .ack = ack_apic_edge,
2542 .eoi = ack_apic_level,
2544 .set_affinity = set_ioapic_affinity_irq,
2546 .retrigger = ioapic_retrigger_irq,
2549 #ifdef CONFIG_INTR_REMAP
2550 static struct irq_chip ir_ioapic_chip __read_mostly = {
2551 .name = "IR-IO-APIC",
2552 .startup = startup_ioapic_irq,
2553 .mask = mask_IO_APIC_irq,
2554 .unmask = unmask_IO_APIC_irq,
2555 .ack = ack_x2apic_edge,
2556 .eoi = ack_x2apic_level,
2558 .set_affinity = set_ir_ioapic_affinity_irq,
2560 .retrigger = ioapic_retrigger_irq,
2564 static inline void init_IO_APIC_traps(void)
2567 struct irq_desc *desc;
2568 struct irq_cfg *cfg;
2571 * NOTE! The local APIC isn't very good at handling
2572 * multiple interrupts at the same interrupt level.
2573 * As the interrupt level is determined by taking the
2574 * vector number and shifting that right by 4, we
2575 * want to spread these out a bit so that they don't
2576 * all fall in the same interrupt level.
2578 * Also, we've got to be careful not to trash gate
2579 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2581 for_each_irq_cfg(irq, cfg) {
2582 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2584 * Hmm.. We don't have an entry for this,
2585 * so default to an old-fashioned 8259
2586 * interrupt if we can..
2589 make_8259A_irq(irq);
2591 desc = irq_to_desc(irq);
2592 /* Strange. Oh, well.. */
2593 desc->chip = &no_irq_chip;
2600 * The local APIC irq-chip implementation:
2603 static void mask_lapic_irq(unsigned int irq)
2607 v = apic_read(APIC_LVT0);
2608 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2611 static void unmask_lapic_irq(unsigned int irq)
2615 v = apic_read(APIC_LVT0);
2616 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2619 static void ack_lapic_irq (unsigned int irq)
2624 static struct irq_chip lapic_chip __read_mostly = {
2625 .name = "local-APIC",
2626 .mask = mask_lapic_irq,
2627 .unmask = unmask_lapic_irq,
2628 .ack = ack_lapic_irq,
2631 static void lapic_register_intr(int irq)
2633 struct irq_desc *desc;
2635 desc = irq_to_desc(irq);
2636 desc->status &= ~IRQ_LEVEL;
2637 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2641 static void __init setup_nmi(void)
2644 * Dirty trick to enable the NMI watchdog ...
2645 * We put the 8259A master into AEOI mode and
2646 * unmask on all local APICs LVT0 as NMI.
2648 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2649 * is from Maciej W. Rozycki - so we do not have to EOI from
2650 * the NMI handler or the timer interrupt.
2652 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2654 enable_NMI_through_LVT0();
2656 apic_printk(APIC_VERBOSE, " done.\n");
2660 * This looks a bit hackish but it's about the only one way of sending
2661 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2662 * not support the ExtINT mode, unfortunately. We need to send these
2663 * cycles as some i82489DX-based boards have glue logic that keeps the
2664 * 8259A interrupt line asserted until INTA. --macro
2666 static inline void __init unlock_ExtINT_logic(void)
2669 struct IO_APIC_route_entry entry0, entry1;
2670 unsigned char save_control, save_freq_select;
2672 pin = find_isa_irq_pin(8, mp_INT);
2677 apic = find_isa_irq_apic(8, mp_INT);
2683 entry0 = ioapic_read_entry(apic, pin);
2684 clear_IO_APIC_pin(apic, pin);
2686 memset(&entry1, 0, sizeof(entry1));
2688 entry1.dest_mode = 0; /* physical delivery */
2689 entry1.mask = 0; /* unmask IRQ now */
2690 entry1.dest = hard_smp_processor_id();
2691 entry1.delivery_mode = dest_ExtINT;
2692 entry1.polarity = entry0.polarity;
2696 ioapic_write_entry(apic, pin, entry1);
2698 save_control = CMOS_READ(RTC_CONTROL);
2699 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2700 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2702 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2707 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2711 CMOS_WRITE(save_control, RTC_CONTROL);
2712 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2713 clear_IO_APIC_pin(apic, pin);
2715 ioapic_write_entry(apic, pin, entry0);
2718 static int disable_timer_pin_1 __initdata;
2719 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2720 static int __init disable_timer_pin_setup(char *arg)
2722 disable_timer_pin_1 = 1;
2725 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2727 int timer_through_8259 __initdata;
2730 * This code may look a bit paranoid, but it's supposed to cooperate with
2731 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2732 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2733 * fanatically on his truly buggy board.
2735 * FIXME: really need to revamp this for all platforms.
2737 static inline void __init check_timer(void)
2739 struct irq_cfg *cfg = irq_cfg(0);
2740 int apic1, pin1, apic2, pin2;
2741 unsigned long flags;
2745 local_irq_save(flags);
2747 ver = apic_read(APIC_LVR);
2748 ver = GET_APIC_VERSION(ver);
2751 * get/set the timer IRQ vector:
2753 disable_8259A_irq(0);
2754 assign_irq_vector(0, TARGET_CPUS);
2757 * As IRQ0 is to be enabled in the 8259A, the virtual
2758 * wire has to be disabled in the local APIC. Also
2759 * timer interrupts need to be acknowledged manually in
2760 * the 8259A for the i82489DX when using the NMI
2761 * watchdog as that APIC treats NMIs as level-triggered.
2762 * The AEOI mode will finish them in the 8259A
2765 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2767 #ifdef CONFIG_X86_32
2768 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2771 pin1 = find_isa_irq_pin(0, mp_INT);
2772 apic1 = find_isa_irq_apic(0, mp_INT);
2773 pin2 = ioapic_i8259.pin;
2774 apic2 = ioapic_i8259.apic;
2776 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2777 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2778 cfg->vector, apic1, pin1, apic2, pin2);
2781 * Some BIOS writers are clueless and report the ExtINTA
2782 * I/O APIC input from the cascaded 8259A as the timer
2783 * interrupt input. So just in case, if only one pin
2784 * was found above, try it both directly and through the
2788 #ifdef CONFIG_INTR_REMAP
2789 if (intr_remapping_enabled)
2790 panic("BIOS bug: timer not connected to IO-APIC");
2795 } else if (pin2 == -1) {
2802 * Ok, does IRQ0 through the IOAPIC work?
2805 add_pin_to_irq(0, apic1, pin1);
2806 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2808 unmask_IO_APIC_irq(0);
2809 if (timer_irq_works()) {
2810 if (nmi_watchdog == NMI_IO_APIC) {
2812 enable_8259A_irq(0);
2814 if (disable_timer_pin_1 > 0)
2815 clear_IO_APIC_pin(0, pin1);
2818 #ifdef CONFIG_INTR_REMAP
2819 if (intr_remapping_enabled)
2820 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2822 clear_IO_APIC_pin(apic1, pin1);
2824 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2825 "8254 timer not connected to IO-APIC\n");
2827 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2828 "(IRQ0) through the 8259A ...\n");
2829 apic_printk(APIC_QUIET, KERN_INFO
2830 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2832 * legacy devices should be connected to IO APIC #0
2834 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2835 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2836 unmask_IO_APIC_irq(0);
2837 enable_8259A_irq(0);
2838 if (timer_irq_works()) {
2839 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2840 timer_through_8259 = 1;
2841 if (nmi_watchdog == NMI_IO_APIC) {
2842 disable_8259A_irq(0);
2844 enable_8259A_irq(0);
2849 * Cleanup, just in case ...
2851 disable_8259A_irq(0);
2852 clear_IO_APIC_pin(apic2, pin2);
2853 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2856 if (nmi_watchdog == NMI_IO_APIC) {
2857 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2858 "through the IO-APIC - disabling NMI Watchdog!\n");
2859 nmi_watchdog = NMI_NONE;
2861 #ifdef CONFIG_X86_32
2865 apic_printk(APIC_QUIET, KERN_INFO
2866 "...trying to set up timer as Virtual Wire IRQ...\n");
2868 lapic_register_intr(0);
2869 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2870 enable_8259A_irq(0);
2872 if (timer_irq_works()) {
2873 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2876 disable_8259A_irq(0);
2877 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2878 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2880 apic_printk(APIC_QUIET, KERN_INFO
2881 "...trying to set up timer as ExtINT IRQ...\n");
2885 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2887 unlock_ExtINT_logic();
2889 if (timer_irq_works()) {
2890 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2893 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2894 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2895 "report. Then try booting with the 'noapic' option.\n");
2897 local_irq_restore(flags);
2901 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2902 * to devices. However there may be an I/O APIC pin available for
2903 * this interrupt regardless. The pin may be left unconnected, but
2904 * typically it will be reused as an ExtINT cascade interrupt for
2905 * the master 8259A. In the MPS case such a pin will normally be
2906 * reported as an ExtINT interrupt in the MP table. With ACPI
2907 * there is no provision for ExtINT interrupts, and in the absence
2908 * of an override it would be treated as an ordinary ISA I/O APIC
2909 * interrupt, that is edge-triggered and unmasked by default. We
2910 * used to do this, but it caused problems on some systems because
2911 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2912 * the same ExtINT cascade interrupt to drive the local APIC of the
2913 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2914 * the I/O APIC in all cases now. No actual device should request
2915 * it anyway. --macro
2917 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2919 void __init setup_IO_APIC(void)
2922 #ifdef CONFIG_X86_32
2926 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2930 io_apic_irqs = ~PIC_IRQS;
2932 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2934 * Set up IO-APIC IRQ routing.
2936 #ifdef CONFIG_X86_32
2938 setup_ioapic_ids_from_mpc();
2941 setup_IO_APIC_irqs();
2942 init_IO_APIC_traps();
2947 * Called after all the initialization is done. If we didnt find any
2948 * APIC bugs then we can allow the modify fast path
2951 static int __init io_apic_bug_finalize(void)
2953 if (sis_apic_bug == -1)
2958 late_initcall(io_apic_bug_finalize);
2960 struct sysfs_ioapic_data {
2961 struct sys_device dev;
2962 struct IO_APIC_route_entry entry[0];
2964 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2966 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2968 struct IO_APIC_route_entry *entry;
2969 struct sysfs_ioapic_data *data;
2972 data = container_of(dev, struct sysfs_ioapic_data, dev);
2973 entry = data->entry;
2974 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2975 *entry = ioapic_read_entry(dev->id, i);
2980 static int ioapic_resume(struct sys_device *dev)
2982 struct IO_APIC_route_entry *entry;
2983 struct sysfs_ioapic_data *data;
2984 unsigned long flags;
2985 union IO_APIC_reg_00 reg_00;
2988 data = container_of(dev, struct sysfs_ioapic_data, dev);
2989 entry = data->entry;
2991 spin_lock_irqsave(&ioapic_lock, flags);
2992 reg_00.raw = io_apic_read(dev->id, 0);
2993 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2994 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2995 io_apic_write(dev->id, 0, reg_00.raw);
2997 spin_unlock_irqrestore(&ioapic_lock, flags);
2998 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2999 ioapic_write_entry(dev->id, i, entry[i]);
3004 static struct sysdev_class ioapic_sysdev_class = {
3006 .suspend = ioapic_suspend,
3007 .resume = ioapic_resume,
3010 static int __init ioapic_init_sysfs(void)
3012 struct sys_device * dev;
3015 error = sysdev_class_register(&ioapic_sysdev_class);
3019 for (i = 0; i < nr_ioapics; i++ ) {
3020 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3021 * sizeof(struct IO_APIC_route_entry);
3022 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3023 if (!mp_ioapic_data[i]) {
3024 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3027 dev = &mp_ioapic_data[i]->dev;
3029 dev->cls = &ioapic_sysdev_class;
3030 error = sysdev_register(dev);
3032 kfree(mp_ioapic_data[i]);
3033 mp_ioapic_data[i] = NULL;
3034 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3042 device_initcall(ioapic_init_sysfs);
3045 * Dynamic irq allocate and deallocation
3047 unsigned int create_irq_nr(unsigned int irq_want)
3049 /* Allocate an unused irq */
3052 unsigned long flags;
3053 struct irq_cfg *cfg_new;
3055 #ifndef CONFIG_HAVE_SPARSE_IRQ
3056 irq_want = nr_irqs - 1;
3060 spin_lock_irqsave(&vector_lock, flags);
3061 for (new = irq_want; new > 0; new--) {
3062 if (platform_legacy_irq(new))
3064 cfg_new = irq_cfg(new);
3065 if (cfg_new && cfg_new->vector != 0)
3067 /* check if need to create one */
3069 cfg_new = irq_cfg_alloc(new);
3070 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
3074 spin_unlock_irqrestore(&vector_lock, flags);
3077 dynamic_irq_init(irq);
3082 int create_irq(void)
3086 irq = create_irq_nr(nr_irqs - 1);
3094 void destroy_irq(unsigned int irq)
3096 unsigned long flags;
3098 dynamic_irq_cleanup(irq);
3100 #ifdef CONFIG_INTR_REMAP
3103 spin_lock_irqsave(&vector_lock, flags);
3104 __clear_irq_vector(irq);
3105 spin_unlock_irqrestore(&vector_lock, flags);
3109 * MSI message composition
3111 #ifdef CONFIG_PCI_MSI
3112 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3114 struct irq_cfg *cfg;
3120 err = assign_irq_vector(irq, tmp);
3125 cpus_and(tmp, cfg->domain, tmp);
3126 dest = cpu_mask_to_apicid(tmp);
3128 #ifdef CONFIG_INTR_REMAP
3129 if (irq_remapped(irq)) {
3134 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3135 BUG_ON(ir_index == -1);
3137 memset (&irte, 0, sizeof(irte));
3140 irte.dst_mode = INT_DEST_MODE;
3141 irte.trigger_mode = 0; /* edge */
3142 irte.dlvry_mode = INT_DELIVERY_MODE;
3143 irte.vector = cfg->vector;
3144 irte.dest_id = IRTE_DEST(dest);
3146 modify_irte(irq, &irte);
3148 msg->address_hi = MSI_ADDR_BASE_HI;
3149 msg->data = sub_handle;
3150 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3152 MSI_ADDR_IR_INDEX1(ir_index) |
3153 MSI_ADDR_IR_INDEX2(ir_index);
3157 msg->address_hi = MSI_ADDR_BASE_HI;
3160 ((INT_DEST_MODE == 0) ?
3161 MSI_ADDR_DEST_MODE_PHYSICAL:
3162 MSI_ADDR_DEST_MODE_LOGICAL) |
3163 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3164 MSI_ADDR_REDIRECTION_CPU:
3165 MSI_ADDR_REDIRECTION_LOWPRI) |
3166 MSI_ADDR_DEST_ID(dest);
3169 MSI_DATA_TRIGGER_EDGE |
3170 MSI_DATA_LEVEL_ASSERT |
3171 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3172 MSI_DATA_DELIVERY_FIXED:
3173 MSI_DATA_DELIVERY_LOWPRI) |
3174 MSI_DATA_VECTOR(cfg->vector);
3180 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3182 struct irq_cfg *cfg;
3186 struct irq_desc *desc;
3188 cpus_and(tmp, mask, cpu_online_map);
3189 if (cpus_empty(tmp))
3192 if (assign_irq_vector(irq, mask))
3196 cpus_and(tmp, cfg->domain, mask);
3197 dest = cpu_mask_to_apicid(tmp);
3199 read_msi_msg(irq, &msg);
3201 msg.data &= ~MSI_DATA_VECTOR_MASK;
3202 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3203 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3204 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3206 write_msi_msg(irq, &msg);
3207 desc = irq_to_desc(irq);
3208 desc->affinity = mask;
3211 #ifdef CONFIG_INTR_REMAP
3213 * Migrate the MSI irq to another cpumask. This migration is
3214 * done in the process context using interrupt-remapping hardware.
3216 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3218 struct irq_cfg *cfg;
3220 cpumask_t tmp, cleanup_mask;
3222 struct irq_desc *desc;
3224 cpus_and(tmp, mask, cpu_online_map);
3225 if (cpus_empty(tmp))
3228 if (get_irte(irq, &irte))
3231 if (assign_irq_vector(irq, mask))
3235 cpus_and(tmp, cfg->domain, mask);
3236 dest = cpu_mask_to_apicid(tmp);
3238 irte.vector = cfg->vector;
3239 irte.dest_id = IRTE_DEST(dest);
3242 * atomically update the IRTE with the new destination and vector.
3244 modify_irte(irq, &irte);
3247 * After this point, all the interrupts will start arriving
3248 * at the new destination. So, time to cleanup the previous
3249 * vector allocation.
3251 if (cfg->move_in_progress) {
3252 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3253 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3254 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3255 cfg->move_in_progress = 0;
3258 desc = irq_to_desc(irq);
3259 desc->affinity = mask;
3262 #endif /* CONFIG_SMP */
3265 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3266 * which implement the MSI or MSI-X Capability Structure.
3268 static struct irq_chip msi_chip = {
3270 .unmask = unmask_msi_irq,
3271 .mask = mask_msi_irq,
3272 .ack = ack_apic_edge,
3274 .set_affinity = set_msi_irq_affinity,
3276 .retrigger = ioapic_retrigger_irq,
3279 #ifdef CONFIG_INTR_REMAP
3280 static struct irq_chip msi_ir_chip = {
3281 .name = "IR-PCI-MSI",
3282 .unmask = unmask_msi_irq,
3283 .mask = mask_msi_irq,
3284 .ack = ack_x2apic_edge,
3286 .set_affinity = ir_set_msi_irq_affinity,
3288 .retrigger = ioapic_retrigger_irq,
3292 * Map the PCI dev to the corresponding remapping hardware unit
3293 * and allocate 'nvec' consecutive interrupt-remapping table entries
3296 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3298 struct intel_iommu *iommu;
3301 iommu = map_dev_to_ir(dev);
3304 "Unable to map PCI %s to iommu\n", pci_name(dev));
3308 index = alloc_irte(iommu, irq, nvec);
3311 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3319 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
3324 ret = msi_compose_msg(dev, irq, &msg);
3328 set_irq_msi(irq, desc);
3329 write_msi_msg(irq, &msg);
3331 #ifdef CONFIG_INTR_REMAP
3332 if (irq_remapped(irq)) {
3333 struct irq_desc *desc = irq_to_desc(irq);
3335 * irq migration in process context
3337 desc->status |= IRQ_MOVE_PCNTXT;
3338 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3341 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3346 static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
3350 irq = dev->bus->number;
3358 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3362 unsigned int irq_want;
3364 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3366 irq = create_irq_nr(irq_want);
3370 #ifdef CONFIG_INTR_REMAP
3371 if (!intr_remapping_enabled)
3374 ret = msi_alloc_irte(dev, irq, 1);
3379 ret = setup_msi_irq(dev, desc, irq);
3386 #ifdef CONFIG_INTR_REMAP
3393 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3396 int ret, sub_handle;
3397 struct msi_desc *desc;
3398 unsigned int irq_want;
3400 #ifdef CONFIG_INTR_REMAP
3401 struct intel_iommu *iommu = 0;
3405 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3407 list_for_each_entry(desc, &dev->msi_list, list) {
3408 irq = create_irq_nr(irq_want--);
3411 #ifdef CONFIG_INTR_REMAP
3412 if (!intr_remapping_enabled)
3417 * allocate the consecutive block of IRTE's
3420 index = msi_alloc_irte(dev, irq, nvec);
3426 iommu = map_dev_to_ir(dev);
3432 * setup the mapping between the irq and the IRTE
3433 * base index, the sub_handle pointing to the
3434 * appropriate interrupt remap table entry.
3436 set_irte_irq(irq, iommu, index, sub_handle);
3440 ret = setup_msi_irq(dev, desc, irq);
3452 void arch_teardown_msi_irq(unsigned int irq)
3459 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3461 struct irq_cfg *cfg;
3465 struct irq_desc *desc;
3467 cpus_and(tmp, mask, cpu_online_map);
3468 if (cpus_empty(tmp))
3471 if (assign_irq_vector(irq, mask))
3475 cpus_and(tmp, cfg->domain, mask);
3476 dest = cpu_mask_to_apicid(tmp);
3478 dmar_msi_read(irq, &msg);
3480 msg.data &= ~MSI_DATA_VECTOR_MASK;
3481 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3482 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3483 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3485 dmar_msi_write(irq, &msg);
3486 desc = irq_to_desc(irq);
3487 desc->affinity = mask;
3489 #endif /* CONFIG_SMP */
3491 struct irq_chip dmar_msi_type = {
3493 .unmask = dmar_msi_unmask,
3494 .mask = dmar_msi_mask,
3495 .ack = ack_apic_edge,
3497 .set_affinity = dmar_msi_set_affinity,
3499 .retrigger = ioapic_retrigger_irq,
3502 int arch_setup_dmar_msi(unsigned int irq)
3507 ret = msi_compose_msg(NULL, irq, &msg);
3510 dmar_msi_write(irq, &msg);
3511 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3517 #ifdef CONFIG_HPET_TIMER
3520 static void hpet_msi_set_affinity(unsigned int irq, cpumask_t mask)
3522 struct irq_cfg *cfg;
3523 struct irq_desc *desc;
3528 cpus_and(tmp, mask, cpu_online_map);
3529 if (cpus_empty(tmp))
3532 if (assign_irq_vector(irq, mask))
3536 cpus_and(tmp, cfg->domain, mask);
3537 dest = cpu_mask_to_apicid(tmp);
3539 hpet_msi_read(irq, &msg);
3541 msg.data &= ~MSI_DATA_VECTOR_MASK;
3542 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3543 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3544 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3546 hpet_msi_write(irq, &msg);
3547 desc = irq_to_desc(irq);
3548 desc->affinity = mask;
3550 #endif /* CONFIG_SMP */
3552 struct irq_chip hpet_msi_type = {
3554 .unmask = hpet_msi_unmask,
3555 .mask = hpet_msi_mask,
3556 .ack = ack_apic_edge,
3558 .set_affinity = hpet_msi_set_affinity,
3560 .retrigger = ioapic_retrigger_irq,
3563 int arch_setup_hpet_msi(unsigned int irq)
3568 ret = msi_compose_msg(NULL, irq, &msg);
3572 hpet_msi_write(irq, &msg);
3573 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3579 #endif /* CONFIG_PCI_MSI */
3581 * Hypertransport interrupt support
3583 #ifdef CONFIG_HT_IRQ
3587 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3589 struct ht_irq_msg msg;
3590 fetch_ht_irq_msg(irq, &msg);
3592 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3593 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3595 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3596 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3598 write_ht_irq_msg(irq, &msg);
3601 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3603 struct irq_cfg *cfg;
3606 struct irq_desc *desc;
3608 cpus_and(tmp, mask, cpu_online_map);
3609 if (cpus_empty(tmp))
3612 if (assign_irq_vector(irq, mask))
3616 cpus_and(tmp, cfg->domain, mask);
3617 dest = cpu_mask_to_apicid(tmp);
3619 target_ht_irq(irq, dest, cfg->vector);
3620 desc = irq_to_desc(irq);
3621 desc->affinity = mask;
3625 static struct irq_chip ht_irq_chip = {
3627 .mask = mask_ht_irq,
3628 .unmask = unmask_ht_irq,
3629 .ack = ack_apic_edge,
3631 .set_affinity = set_ht_irq_affinity,
3633 .retrigger = ioapic_retrigger_irq,
3636 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3638 struct irq_cfg *cfg;
3643 err = assign_irq_vector(irq, tmp);
3645 struct ht_irq_msg msg;
3649 cpus_and(tmp, cfg->domain, tmp);
3650 dest = cpu_mask_to_apicid(tmp);
3652 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3656 HT_IRQ_LOW_DEST_ID(dest) |
3657 HT_IRQ_LOW_VECTOR(cfg->vector) |
3658 ((INT_DEST_MODE == 0) ?
3659 HT_IRQ_LOW_DM_PHYSICAL :
3660 HT_IRQ_LOW_DM_LOGICAL) |
3661 HT_IRQ_LOW_RQEOI_EDGE |
3662 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3663 HT_IRQ_LOW_MT_FIXED :
3664 HT_IRQ_LOW_MT_ARBITRATED) |
3665 HT_IRQ_LOW_IRQ_MASKED;
3667 write_ht_irq_msg(irq, &msg);
3669 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3670 handle_edge_irq, "edge");
3674 #endif /* CONFIG_HT_IRQ */
3676 int __init io_apic_get_redir_entries (int ioapic)
3678 union IO_APIC_reg_01 reg_01;
3679 unsigned long flags;
3681 spin_lock_irqsave(&ioapic_lock, flags);
3682 reg_01.raw = io_apic_read(ioapic, 1);
3683 spin_unlock_irqrestore(&ioapic_lock, flags);
3685 return reg_01.bits.entries;
3688 int __init probe_nr_irqs(void)
3695 int nr_min = NR_IRQS;
3698 for (idx = 0; idx < nr_ioapics; idx++)
3699 nr += io_apic_get_redir_entries(idx) + 1;
3701 /* double it for hotplug and msi and nmi */
3704 /* something wrong ? */
3711 /* --------------------------------------------------------------------------
3712 ACPI-based IOAPIC Configuration
3713 -------------------------------------------------------------------------- */
3717 #ifdef CONFIG_X86_32
3718 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3720 union IO_APIC_reg_00 reg_00;
3721 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3723 unsigned long flags;
3727 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3728 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3729 * supports up to 16 on one shared APIC bus.
3731 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3732 * advantage of new APIC bus architecture.
3735 if (physids_empty(apic_id_map))
3736 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3738 spin_lock_irqsave(&ioapic_lock, flags);
3739 reg_00.raw = io_apic_read(ioapic, 0);
3740 spin_unlock_irqrestore(&ioapic_lock, flags);
3742 if (apic_id >= get_physical_broadcast()) {
3743 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3744 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3745 apic_id = reg_00.bits.ID;
3749 * Every APIC in a system must have a unique ID or we get lots of nice
3750 * 'stuck on smp_invalidate_needed IPI wait' messages.
3752 if (check_apicid_used(apic_id_map, apic_id)) {
3754 for (i = 0; i < get_physical_broadcast(); i++) {
3755 if (!check_apicid_used(apic_id_map, i))
3759 if (i == get_physical_broadcast())
3760 panic("Max apic_id exceeded!\n");
3762 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3763 "trying %d\n", ioapic, apic_id, i);
3768 tmp = apicid_to_cpu_present(apic_id);
3769 physids_or(apic_id_map, apic_id_map, tmp);
3771 if (reg_00.bits.ID != apic_id) {
3772 reg_00.bits.ID = apic_id;
3774 spin_lock_irqsave(&ioapic_lock, flags);
3775 io_apic_write(ioapic, 0, reg_00.raw);
3776 reg_00.raw = io_apic_read(ioapic, 0);
3777 spin_unlock_irqrestore(&ioapic_lock, flags);
3780 if (reg_00.bits.ID != apic_id) {
3781 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3786 apic_printk(APIC_VERBOSE, KERN_INFO
3787 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3792 int __init io_apic_get_version(int ioapic)
3794 union IO_APIC_reg_01 reg_01;
3795 unsigned long flags;
3797 spin_lock_irqsave(&ioapic_lock, flags);
3798 reg_01.raw = io_apic_read(ioapic, 1);
3799 spin_unlock_irqrestore(&ioapic_lock, flags);
3801 return reg_01.bits.version;
3805 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3807 if (!IO_APIC_IRQ(irq)) {
3808 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3814 * IRQs < 16 are already in the irq_2_pin[] map
3817 add_pin_to_irq(irq, ioapic, pin);
3819 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
3825 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3829 if (skip_ioapic_setup)
3832 for (i = 0; i < mp_irq_entries; i++)
3833 if (mp_irqs[i].mp_irqtype == mp_INT &&
3834 mp_irqs[i].mp_srcbusirq == bus_irq)
3836 if (i >= mp_irq_entries)
3839 *trigger = irq_trigger(i);
3840 *polarity = irq_polarity(i);
3844 #endif /* CONFIG_ACPI */
3847 * This function currently is only a helper for the i386 smp boot process where
3848 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3849 * so mask in all cases should simply be TARGET_CPUS
3852 void __init setup_ioapic_dest(void)
3854 int pin, ioapic, irq, irq_entry;
3855 struct irq_cfg *cfg;
3857 if (skip_ioapic_setup == 1)
3860 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3861 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3862 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3863 if (irq_entry == -1)
3865 irq = pin_2_irq(irq_entry, ioapic, pin);
3867 /* setup_IO_APIC_irqs could fail to get vector for some device
3868 * when you have too many devices, because at that time only boot
3873 setup_IO_APIC_irq(ioapic, pin, irq,
3874 irq_trigger(irq_entry),
3875 irq_polarity(irq_entry));
3876 #ifdef CONFIG_INTR_REMAP
3877 else if (intr_remapping_enabled)
3878 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3881 set_ioapic_affinity_irq(irq, TARGET_CPUS);
3888 #define IOAPIC_RESOURCE_NAME_SIZE 11
3890 static struct resource *ioapic_resources;
3892 static struct resource * __init ioapic_setup_resources(void)
3895 struct resource *res;
3899 if (nr_ioapics <= 0)
3902 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3905 mem = alloc_bootmem(n);
3909 mem += sizeof(struct resource) * nr_ioapics;
3911 for (i = 0; i < nr_ioapics; i++) {
3913 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3914 sprintf(mem, "IOAPIC %u", i);
3915 mem += IOAPIC_RESOURCE_NAME_SIZE;
3919 ioapic_resources = res;
3924 void __init ioapic_init_mappings(void)
3926 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3928 struct resource *ioapic_res;
3930 ioapic_res = ioapic_setup_resources();
3931 for (i = 0; i < nr_ioapics; i++) {
3932 if (smp_found_config) {
3933 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3934 #ifdef CONFIG_X86_32
3937 "WARNING: bogus zero IO-APIC "
3938 "address found in MPTABLE, "
3939 "disabling IO/APIC support!\n");
3940 smp_found_config = 0;
3941 skip_ioapic_setup = 1;
3942 goto fake_ioapic_page;
3946 #ifdef CONFIG_X86_32
3949 ioapic_phys = (unsigned long)
3950 alloc_bootmem_pages(PAGE_SIZE);
3951 ioapic_phys = __pa(ioapic_phys);
3953 set_fixmap_nocache(idx, ioapic_phys);
3954 apic_printk(APIC_VERBOSE,
3955 "mapped IOAPIC to %08lx (%08lx)\n",
3956 __fix_to_virt(idx), ioapic_phys);
3959 if (ioapic_res != NULL) {
3960 ioapic_res->start = ioapic_phys;
3961 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3967 static int __init ioapic_insert_resources(void)
3970 struct resource *r = ioapic_resources;
3974 "IO APIC resources could be not be allocated.\n");
3978 for (i = 0; i < nr_ioapics; i++) {
3979 insert_resource(&iomem_resource, r);
3986 /* Insert the IO APIC resources after PCI initialization has occured to handle
3987 * IO APICS that are mapped in on a BAR in PCI space. */
3988 late_initcall(ioapic_insert_resources);