1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/delay.h>
4 #include <linux/errno.h>
5 #include <linux/hpet.h>
6 #include <linux/init.h>
7 #include <linux/sysdev.h>
9 #include <linux/interrupt.h>
10 #include <linux/cpu.h>
12 #include <asm/fixmap.h>
14 #include <asm/i8253.h>
17 #define HPET_MASK CLOCKSOURCE_MASK(32)
22 #define FSEC_PER_NSEC 1000000L
25 * HPET address is set in acpi/boot.c, when an ACPI entry exists
27 unsigned long hpet_address;
28 static void __iomem *hpet_virt_address;
31 struct clock_event_device evt;
39 unsigned long hpet_readl(unsigned long a)
41 return readl(hpet_virt_address + a);
44 static inline void hpet_writel(unsigned long d, unsigned long a)
46 writel(d, hpet_virt_address + a);
50 #include <asm/pgtable.h>
53 static inline void hpet_set_mapping(void)
55 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
57 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
61 static inline void hpet_clear_mapping(void)
63 iounmap(hpet_virt_address);
64 hpet_virt_address = NULL;
68 * HPET command line enable / disable
70 static int boot_hpet_disable;
73 static int __init hpet_setup(char* str)
76 if (!strncmp("disable", str, 7))
77 boot_hpet_disable = 1;
78 if (!strncmp("force", str, 5))
83 __setup("hpet=", hpet_setup);
85 static int __init disable_hpet(char *str)
87 boot_hpet_disable = 1;
90 __setup("nohpet", disable_hpet);
92 static inline int is_hpet_capable(void)
94 return (!boot_hpet_disable && hpet_address);
98 * HPET timer interrupt enable / disable
100 static int hpet_legacy_int_enabled;
103 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
105 int is_hpet_enabled(void)
107 return is_hpet_capable() && hpet_legacy_int_enabled;
109 EXPORT_SYMBOL_GPL(is_hpet_enabled);
112 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
113 * timer 0 and timer 1 in case of RTC emulation.
116 static void hpet_reserve_platform_timers(unsigned long id)
118 struct hpet __iomem *hpet = hpet_virt_address;
119 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
120 unsigned int nrtimers, i;
123 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
125 memset(&hd, 0, sizeof (hd));
126 hd.hd_phys_address = hpet_address;
127 hd.hd_address = hpet;
128 hd.hd_nirqs = nrtimers;
129 hpet_reserve_timer(&hd, 0);
131 #ifdef CONFIG_HPET_EMULATE_RTC
132 hpet_reserve_timer(&hd, 1);
136 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
137 * is wrong for i8259!) not the output IRQ. Many BIOS writers
138 * don't bother configuring *any* comparator interrupts.
140 hd.hd_irq[0] = HPET_LEGACY_8254;
141 hd.hd_irq[1] = HPET_LEGACY_RTC;
143 for (i = 2; i < nrtimers; timer++, i++) {
144 hd.hd_irq[i] = (readl(&timer->hpet_config) & Tn_INT_ROUTE_CNF_MASK) >>
145 Tn_INT_ROUTE_CNF_SHIFT;
152 static void hpet_reserve_platform_timers(unsigned long id) { }
158 static unsigned long hpet_period;
160 static void hpet_legacy_set_mode(enum clock_event_mode mode,
161 struct clock_event_device *evt);
162 static int hpet_legacy_next_event(unsigned long delta,
163 struct clock_event_device *evt);
166 * The hpet clock event device
168 static struct clock_event_device hpet_clockevent = {
170 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
171 .set_mode = hpet_legacy_set_mode,
172 .set_next_event = hpet_legacy_next_event,
178 static void hpet_start_counter(void)
180 unsigned long cfg = hpet_readl(HPET_CFG);
182 cfg &= ~HPET_CFG_ENABLE;
183 hpet_writel(cfg, HPET_CFG);
184 hpet_writel(0, HPET_COUNTER);
185 hpet_writel(0, HPET_COUNTER + 4);
186 cfg |= HPET_CFG_ENABLE;
187 hpet_writel(cfg, HPET_CFG);
190 static void hpet_resume_device(void)
195 static void hpet_restart_counter(void)
197 hpet_resume_device();
198 hpet_start_counter();
201 static void hpet_enable_legacy_int(void)
203 unsigned long cfg = hpet_readl(HPET_CFG);
205 cfg |= HPET_CFG_LEGACY;
206 hpet_writel(cfg, HPET_CFG);
207 hpet_legacy_int_enabled = 1;
210 static void hpet_legacy_clockevent_register(void)
212 /* Start HPET legacy interrupts */
213 hpet_enable_legacy_int();
216 * The mult factor is defined as (include/linux/clockchips.h)
217 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
218 * hpet_period is in units of femtoseconds (per cycle), so
219 * mult/2^shift = cyc/ns = 10^6/hpet_period
220 * mult = (10^6 * 2^shift)/hpet_period
221 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
223 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
224 hpet_period, hpet_clockevent.shift);
225 /* Calculate the min / max delta */
226 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
228 /* 5 usec minimum reprogramming delta. */
229 hpet_clockevent.min_delta_ns = 5000;
232 * Start hpet with the boot cpu mask and make it
233 * global after the IO_APIC has been initialized.
235 hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
236 clockevents_register_device(&hpet_clockevent);
237 global_clock_event = &hpet_clockevent;
238 printk(KERN_DEBUG "hpet clockevent registered\n");
241 static void hpet_set_mode(enum clock_event_mode mode,
242 struct clock_event_device *evt, int timer)
244 unsigned long cfg, cmp, now;
248 case CLOCK_EVT_MODE_PERIODIC:
249 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
250 delta >>= evt->shift;
251 now = hpet_readl(HPET_COUNTER);
252 cmp = now + (unsigned long) delta;
253 cfg = hpet_readl(HPET_Tn_CFG(timer));
254 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
255 HPET_TN_SETVAL | HPET_TN_32BIT;
256 hpet_writel(cfg, HPET_Tn_CFG(timer));
258 * The first write after writing TN_SETVAL to the
259 * config register sets the counter value, the second
260 * write sets the period.
262 hpet_writel(cmp, HPET_Tn_CMP(timer));
264 hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer));
267 case CLOCK_EVT_MODE_ONESHOT:
268 cfg = hpet_readl(HPET_Tn_CFG(timer));
269 cfg &= ~HPET_TN_PERIODIC;
270 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
271 hpet_writel(cfg, HPET_Tn_CFG(timer));
274 case CLOCK_EVT_MODE_UNUSED:
275 case CLOCK_EVT_MODE_SHUTDOWN:
276 cfg = hpet_readl(HPET_Tn_CFG(timer));
277 cfg &= ~HPET_TN_ENABLE;
278 hpet_writel(cfg, HPET_Tn_CFG(timer));
281 case CLOCK_EVT_MODE_RESUME:
282 hpet_enable_legacy_int();
287 static int hpet_next_event(unsigned long delta,
288 struct clock_event_device *evt, int timer)
292 cnt = hpet_readl(HPET_COUNTER);
294 hpet_writel(cnt, HPET_Tn_CMP(timer));
297 * We need to read back the CMP register to make sure that
298 * what we wrote hit the chip before we compare it to the
301 WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt);
303 return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
306 static void hpet_legacy_set_mode(enum clock_event_mode mode,
307 struct clock_event_device *evt)
309 hpet_set_mode(mode, evt, 0);
312 static int hpet_legacy_next_event(unsigned long delta,
313 struct clock_event_device *evt)
315 return hpet_next_event(delta, evt, 0);
322 void hpet_msi_unmask(unsigned int irq)
324 struct hpet_dev *hdev = get_irq_data(irq);
328 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
330 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
333 void hpet_msi_mask(unsigned int irq)
336 struct hpet_dev *hdev = get_irq_data(irq);
339 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
341 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
344 void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
346 struct hpet_dev *hdev = get_irq_data(irq);
348 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
349 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
352 void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
354 struct hpet_dev *hdev = get_irq_data(irq);
356 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
357 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
362 * Clock source related code
364 static cycle_t read_hpet(void)
366 return (cycle_t)hpet_readl(HPET_COUNTER);
370 static cycle_t __vsyscall_fn vread_hpet(void)
372 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
376 static struct clocksource clocksource_hpet = {
382 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
383 .resume = hpet_restart_counter,
389 static int hpet_clocksource_register(void)
394 /* Start the counter */
395 hpet_start_counter();
397 /* Verify whether hpet counter works */
402 * We don't know the TSC frequency yet, but waiting for
403 * 200000 TSC cycles is safe:
410 } while ((now - start) < 200000UL);
412 if (t1 == read_hpet()) {
414 "HPET counter not counting. HPET disabled\n");
419 * The definition of mult is (include/linux/clocksource.h)
420 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
421 * so we first need to convert hpet_period to ns/cyc units:
422 * mult/2^shift = ns/cyc = hpet_period/10^6
423 * mult = (hpet_period * 2^shift)/10^6
424 * mult = (hpet_period << shift)/FSEC_PER_NSEC
426 clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
428 clocksource_register(&clocksource_hpet);
434 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
436 int __init hpet_enable(void)
441 if (!is_hpet_capable())
447 * Read the period and check for a sane value:
449 hpet_period = hpet_readl(HPET_PERIOD);
452 * AMD SB700 based systems with spread spectrum enabled use a
453 * SMM based HPET emulation to provide proper frequency
454 * setting. The SMM code is initialized with the first HPET
455 * register access and takes some time to complete. During
456 * this time the config register reads 0xffffffff. We check
457 * for max. 1000 loops whether the config register reads a non
458 * 0xffffffff value to make sure that HPET is up and running
459 * before we go further. A counting loop is safe, as the HPET
460 * access takes thousands of CPU cycles. On non SB700 based
461 * machines this check is only done once and has no side
464 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
467 "HPET config register value = 0xFFFFFFFF. "
473 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
477 * Read the HPET ID register to retrieve the IRQ routing
478 * information and the number of channels
480 id = hpet_readl(HPET_ID);
482 #ifdef CONFIG_HPET_EMULATE_RTC
484 * The legacy routing mode needs at least two channels, tick timer
485 * and the rtc emulation channel.
487 if (!(id & HPET_ID_NUMBER))
491 if (hpet_clocksource_register())
494 if (id & HPET_ID_LEGSUP) {
495 hpet_legacy_clockevent_register();
501 hpet_clear_mapping();
502 boot_hpet_disable = 1;
507 * Needs to be late, as the reserve_timer code calls kalloc !
509 * Not a problem on i386 as hpet_enable is called from late_time_init,
510 * but on x86_64 it is necessary !
512 static __init int hpet_late_init(void)
514 if (boot_hpet_disable)
518 if (!force_hpet_address)
521 hpet_address = force_hpet_address;
523 if (!hpet_virt_address)
527 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
531 fs_initcall(hpet_late_init);
533 void hpet_disable(void)
535 if (is_hpet_capable()) {
536 unsigned long cfg = hpet_readl(HPET_CFG);
538 if (hpet_legacy_int_enabled) {
539 cfg &= ~HPET_CFG_LEGACY;
540 hpet_legacy_int_enabled = 0;
542 cfg &= ~HPET_CFG_ENABLE;
543 hpet_writel(cfg, HPET_CFG);
547 #ifdef CONFIG_HPET_EMULATE_RTC
549 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
550 * is enabled, we support RTC interrupt functionality in software.
551 * RTC has 3 kinds of interrupts:
552 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
554 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
555 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
556 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
557 * (1) and (2) above are implemented using polling at a frequency of
558 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
559 * overhead. (DEFAULT_RTC_INT_FREQ)
560 * For (3), we use interrupts at 64Hz or user specified periodic
561 * frequency, whichever is higher.
563 #include <linux/mc146818rtc.h>
564 #include <linux/rtc.h>
567 #define DEFAULT_RTC_INT_FREQ 64
568 #define DEFAULT_RTC_SHIFT 6
569 #define RTC_NUM_INTS 1
571 static unsigned long hpet_rtc_flags;
572 static int hpet_prev_update_sec;
573 static struct rtc_time hpet_alarm_time;
574 static unsigned long hpet_pie_count;
575 static unsigned long hpet_t1_cmp;
576 static unsigned long hpet_default_delta;
577 static unsigned long hpet_pie_delta;
578 static unsigned long hpet_pie_limit;
580 static rtc_irq_handler irq_handler;
583 * Registers a IRQ handler.
585 int hpet_register_irq_handler(rtc_irq_handler handler)
587 if (!is_hpet_enabled())
592 irq_handler = handler;
596 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
599 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
602 void hpet_unregister_irq_handler(rtc_irq_handler handler)
604 if (!is_hpet_enabled())
610 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
613 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
614 * is not supported by all HPET implementations for timer 1.
616 * hpet_rtc_timer_init() is called when the rtc is initialized.
618 int hpet_rtc_timer_init(void)
620 unsigned long cfg, cnt, delta, flags;
622 if (!is_hpet_enabled())
625 if (!hpet_default_delta) {
628 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
629 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
630 hpet_default_delta = (unsigned long) clc;
633 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
634 delta = hpet_default_delta;
636 delta = hpet_pie_delta;
638 local_irq_save(flags);
640 cnt = delta + hpet_readl(HPET_COUNTER);
641 hpet_writel(cnt, HPET_T1_CMP);
644 cfg = hpet_readl(HPET_T1_CFG);
645 cfg &= ~HPET_TN_PERIODIC;
646 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
647 hpet_writel(cfg, HPET_T1_CFG);
649 local_irq_restore(flags);
653 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
656 * The functions below are called from rtc driver.
657 * Return 0 if HPET is not being used.
658 * Otherwise do the necessary changes and return 1.
660 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
662 if (!is_hpet_enabled())
665 hpet_rtc_flags &= ~bit_mask;
668 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
670 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
672 unsigned long oldbits = hpet_rtc_flags;
674 if (!is_hpet_enabled())
677 hpet_rtc_flags |= bit_mask;
679 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
680 hpet_prev_update_sec = -1;
683 hpet_rtc_timer_init();
687 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
689 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
692 if (!is_hpet_enabled())
695 hpet_alarm_time.tm_hour = hrs;
696 hpet_alarm_time.tm_min = min;
697 hpet_alarm_time.tm_sec = sec;
701 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
703 int hpet_set_periodic_freq(unsigned long freq)
707 if (!is_hpet_enabled())
710 if (freq <= DEFAULT_RTC_INT_FREQ)
711 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
713 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
715 clc >>= hpet_clockevent.shift;
716 hpet_pie_delta = (unsigned long) clc;
720 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
722 int hpet_rtc_dropped_irq(void)
724 return is_hpet_enabled();
726 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
728 static void hpet_rtc_timer_reinit(void)
730 unsigned long cfg, delta;
733 if (unlikely(!hpet_rtc_flags)) {
734 cfg = hpet_readl(HPET_T1_CFG);
735 cfg &= ~HPET_TN_ENABLE;
736 hpet_writel(cfg, HPET_T1_CFG);
740 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
741 delta = hpet_default_delta;
743 delta = hpet_pie_delta;
746 * Increment the comparator value until we are ahead of the
750 hpet_t1_cmp += delta;
751 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
753 } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
756 if (hpet_rtc_flags & RTC_PIE)
757 hpet_pie_count += lost_ints;
758 if (printk_ratelimit())
759 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
764 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
766 struct rtc_time curr_time;
767 unsigned long rtc_int_flag = 0;
769 hpet_rtc_timer_reinit();
770 memset(&curr_time, 0, sizeof(struct rtc_time));
772 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
773 get_rtc_time(&curr_time);
775 if (hpet_rtc_flags & RTC_UIE &&
776 curr_time.tm_sec != hpet_prev_update_sec) {
777 if (hpet_prev_update_sec >= 0)
778 rtc_int_flag = RTC_UF;
779 hpet_prev_update_sec = curr_time.tm_sec;
782 if (hpet_rtc_flags & RTC_PIE &&
783 ++hpet_pie_count >= hpet_pie_limit) {
784 rtc_int_flag |= RTC_PF;
788 if (hpet_rtc_flags & RTC_AIE &&
789 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
790 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
791 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
792 rtc_int_flag |= RTC_AF;
795 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
797 irq_handler(rtc_int_flag, dev_id);
801 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);