2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #include <linux/kernel.h>
12 #include <linux/threads.h>
13 #include <linux/cpumask.h>
14 #include <linux/string.h>
15 #include <linux/kernel.h>
16 #include <linux/ctype.h>
17 #include <linux/init.h>
18 #include <linux/sched.h>
19 #include <linux/bootmem.h>
20 #include <linux/module.h>
21 #include <linux/hardirq.h>
24 #include <asm/genapic.h>
25 #include <asm/pgtable.h>
26 #include <asm/uv/uv_mmrs.h>
27 #include <asm/uv/uv_hub.h>
29 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
30 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
32 struct uv_blade_info *uv_blade_info;
33 EXPORT_SYMBOL_GPL(uv_blade_info);
35 short *uv_node_to_blade;
36 EXPORT_SYMBOL_GPL(uv_node_to_blade);
38 short *uv_cpu_to_blade;
39 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
41 short uv_possible_blades;
42 EXPORT_SYMBOL_GPL(uv_possible_blades);
44 /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
46 static cpumask_t uv_target_cpus(void)
48 return cpumask_of_cpu(0);
51 static cpumask_t uv_vector_allocation_domain(int cpu)
53 cpumask_t domain = CPU_MASK_NONE;
58 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
63 pnode = uv_apicid_to_pnode(phys_apicid);
64 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
65 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
66 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
68 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
71 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
72 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
73 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
75 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
79 static void uv_send_IPI_one(int cpu, int vector)
81 unsigned long val, apicid, lapicid;
84 apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
85 lapicid = apicid & 0x3f; /* ZZZ macro needed */
86 pnode = uv_apicid_to_pnode(apicid);
88 (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
89 UVH_IPI_INT_APIC_ID_SHFT) |
90 (vector << UVH_IPI_INT_VECTOR_SHFT);
91 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
94 static void uv_send_IPI_mask(cpumask_t mask, int vector)
98 for (cpu = 0; cpu < NR_CPUS; ++cpu)
99 if (cpu_isset(cpu, mask))
100 uv_send_IPI_one(cpu, vector);
103 static void uv_send_IPI_allbutself(int vector)
105 cpumask_t mask = cpu_online_map;
107 cpu_clear(smp_processor_id(), mask);
109 if (!cpus_empty(mask))
110 uv_send_IPI_mask(mask, vector);
113 static void uv_send_IPI_all(int vector)
115 uv_send_IPI_mask(cpu_online_map, vector);
118 static int uv_apic_id_registered(void)
123 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
128 * We're using fixed IRQ delivery, can only return one phys APIC ID.
129 * May as well be the first.
131 cpu = first_cpu(cpumask);
132 if ((unsigned)cpu < NR_CPUS)
133 return per_cpu(x86_cpu_to_apicid, cpu);
138 static unsigned int uv_read_apic_id(void)
142 WARN_ON(preemptible() && num_online_cpus() > 1);
143 id = apic_read(APIC_ID) | __get_cpu_var(x2apic_extra_bits);
148 static unsigned int phys_pkg_id(int index_msb)
150 return uv_read_apic_id() >> index_msb;
153 #ifdef ZZZ /* Needs x2apic patch */
154 static void uv_send_IPI_self(int vector)
156 apic_write(APIC_SELF_IPI, vector);
160 struct genapic apic_x2apic_uv_x = {
161 .name = "UV large system",
162 .int_delivery_mode = dest_Fixed,
163 .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
164 .target_cpus = uv_target_cpus,
165 .vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
166 .apic_id_registered = uv_apic_id_registered,
167 .send_IPI_all = uv_send_IPI_all,
168 .send_IPI_allbutself = uv_send_IPI_allbutself,
169 .send_IPI_mask = uv_send_IPI_mask,
170 /* ZZZ.send_IPI_self = uv_send_IPI_self, */
171 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
172 .phys_pkg_id = phys_pkg_id, /* Fixme ZZZ */
173 .read_apic_id = uv_read_apic_id,
176 static __cpuinit void set_x2apic_extra_bits(int pnode)
178 __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
182 * Called on boot cpu.
184 static __init int boot_pnode_to_blade(int pnode)
188 for (blade = 0; blade < uv_num_possible_blades(); blade++)
189 if (pnode == uv_blade_info[blade].pnode)
195 unsigned long redirect;
199 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
201 static __initdata struct redir_addr redir_addrs[] = {
202 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
203 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
204 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
207 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
209 union uvh_si_alias0_overlay_config_u alias;
210 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
213 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
214 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
215 if (alias.s.base == 0) {
216 *size = (1UL << alias.s.m_alias);
217 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
218 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
225 static __init void map_low_mmrs(void)
227 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
228 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
231 enum map_type {map_wb, map_uc};
233 static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
235 unsigned long bytes, paddr;
237 paddr = base << shift;
238 bytes = (1UL << shift);
239 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
241 if (map_type == map_uc)
242 init_extra_mapping_uc(paddr, bytes);
244 init_extra_mapping_wb(paddr, bytes);
247 static __init void map_gru_high(int max_pnode)
249 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
250 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
252 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
254 map_high("GRU", gru.s.base, shift, map_wb);
257 static __init void map_config_high(int max_pnode)
259 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
260 int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
262 cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
264 map_high("CONFIG", cfg.s.base, shift, map_uc);
267 static __init void map_mmr_high(int max_pnode)
269 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
270 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
272 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
274 map_high("MMR", mmr.s.base, shift, map_uc);
277 static __init void map_mmioh_high(int max_pnode)
279 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
280 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
282 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
284 map_high("MMIOH", mmioh.s.base, shift, map_uc);
287 static __init void uv_system_init(void)
289 union uvh_si_addr_map_config_u m_n_config;
290 union uvh_node_id_u node_id;
291 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
292 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
294 unsigned long mmr_base, present;
298 m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
299 m_val = m_n_config.s.m_skt;
300 n_val = m_n_config.s.n_skt;
302 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
304 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
306 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
307 uv_possible_blades +=
308 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
309 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
311 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
312 uv_blade_info = alloc_bootmem_pages(bytes);
314 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
316 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
317 uv_node_to_blade = alloc_bootmem_pages(bytes);
318 memset(uv_node_to_blade, 255, bytes);
320 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
321 uv_cpu_to_blade = alloc_bootmem_pages(bytes);
322 memset(uv_cpu_to_blade, 255, bytes);
325 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
326 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
327 for (j = 0; j < 64; j++) {
328 if (!test_bit(j, &present))
330 uv_blade_info[blade].pnode = (i * 64 + j);
331 uv_blade_info[blade].nr_possible_cpus = 0;
332 uv_blade_info[blade].nr_online_cpus = 0;
337 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
338 gnode_upper = (((unsigned long)node_id.s.node_id) &
339 ~((1 << n_val) - 1)) << m_val;
341 for_each_present_cpu(cpu) {
342 nid = cpu_to_node(cpu);
343 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
344 blade = boot_pnode_to_blade(pnode);
345 lcpu = uv_blade_info[blade].nr_possible_cpus;
346 uv_blade_info[blade].nr_possible_cpus++;
348 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
349 uv_cpu_hub_info(cpu)->lowmem_remap_top =
350 lowmem_redir_base + lowmem_redir_size;
351 uv_cpu_hub_info(cpu)->m_val = m_val;
352 uv_cpu_hub_info(cpu)->n_val = m_val;
353 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
354 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
355 uv_cpu_hub_info(cpu)->pnode = pnode;
356 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
357 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
358 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
359 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
360 uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
361 uv_node_to_blade[nid] = blade;
362 uv_cpu_to_blade[cpu] = blade;
363 max_pnode = max(pnode, max_pnode);
365 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
366 "lcpu %d, blade %d\n",
367 cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
371 map_gru_high(max_pnode);
372 map_mmr_high(max_pnode);
373 map_config_high(max_pnode);
374 map_mmioh_high(max_pnode);
378 * Called on each cpu to initialize the per_cpu UV data area.
379 * ZZZ hotplug not supported yet
381 void __cpuinit uv_cpu_init(void)
383 if (!uv_node_to_blade)
386 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
388 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
389 set_x2apic_extra_bits(uv_hub_info->pnode);