arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/string.h>
  15 #include <linux/ctype.h>
  16 #include <linux/init.h>
  17 #include <linux/sched.h>
  18 #include <linux/module.h>
  19 #include <linux/hardirq.h>
  20 #include <asm/smp.h>
  21 #include <asm/ipi.h>
  22 #include <asm/genapic.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/uv/uv_mmrs.h>
  25 #include <asm/uv/uv_hub.h>
  26 #include <asm/uv/bios.h>
  27
  28 DEFINE_PER_CPU(int, x2apic_extra_bits);
  29
  30 static enum uv_system_type uv_system_type;
  31
  32 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  33 {
  34         if (!strcmp(oem_id, "SGI")) {
  35                 if (!strcmp(oem_table_id, "UVL"))
  36                         uv_system_type = UV_LEGACY_APIC;
  37                 else if (!strcmp(oem_table_id, "UVX"))
  38                         uv_system_type = UV_X2APIC;
  39                 else if (!strcmp(oem_table_id, "UVH")) {
  40                         uv_system_type = UV_NON_UNIQUE_APIC;
  41                         return 1;
  42                 }
  43         }
  44         return 0;
  45 }
  46
  47 enum uv_system_type get_uv_system_type(void)
  48 {
  49         return uv_system_type;
  50 }
  51
  52 int is_uv_system(void)
  53 {
  54         return uv_system_type != UV_NONE;
  55 }
  56 EXPORT_SYMBOL_GPL(is_uv_system);
  57
  58 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  59 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  60
  61 struct uv_blade_info *uv_blade_info;
  62 EXPORT_SYMBOL_GPL(uv_blade_info);
  63
  64 short *uv_node_to_blade;
  65 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  66
  67 short *uv_cpu_to_blade;
  68 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  69
  70 short uv_possible_blades;
  71 EXPORT_SYMBOL_GPL(uv_possible_blades);
  72
  73 unsigned long sn_rtc_cycles_per_second;
  74 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  75
  76 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  77
  78 static const cpumask_t *uv_target_cpus(void)
  79 {
  80         return &cpumask_of_cpu(0);
  81 }
  82
  83 static void uv_vector_allocation_domain(int cpu, cpumask_t *retmask)
  84 {
  85         cpus_clear(*retmask);
  86         cpu_set(cpu, *retmask);
  87 }
  88
  89 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  90 {
  91         unsigned long val;
  92         int pnode;
  93
  94         pnode = uv_apicid_to_pnode(phys_apicid);
  95         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  96             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  97             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
  98             APIC_DM_INIT;
  99         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 100         mdelay(10);
 101
 102         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 103             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 104             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 105             APIC_DM_STARTUP;
 106         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 107         return 0;
 108 }
 109
 110 static void uv_send_IPI_one(int cpu, int vector)
 111 {
 112         unsigned long val, apicid, lapicid;
 113         int pnode;
 114
 115         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 116         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
 117         pnode = uv_apicid_to_pnode(apicid);
 118         val =
 119             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
 120                                               UVH_IPI_INT_APIC_ID_SHFT) |
 121             (vector << UVH_IPI_INT_VECTOR_SHFT);
 122         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 123 }
 124
 125 static void uv_send_IPI_mask(const cpumask_t *mask, int vector)
 126 {
 127         unsigned int cpu;
 128
 129         for_each_cpu_mask_nr(cpu, *mask)
 130                 uv_send_IPI_one(cpu, vector);
 131 }
 132
 133 static void uv_send_IPI_mask_allbutself(const cpumask_t *mask, int vector)
 134 {
 135         unsigned int cpu;
 136         unsigned int this_cpu = smp_processor_id();
 137
 138         for_each_cpu_mask_nr(cpu, *mask)
 139                 if (cpu != this_cpu)
 140                         uv_send_IPI_one(cpu, vector);
 141 }
 142
 143 static void uv_send_IPI_allbutself(int vector)
 144 {
 145         unsigned int cpu;
 146         unsigned int this_cpu = smp_processor_id();
 147
 148         for_each_online_cpu(cpu)
 149                 if (cpu != this_cpu)
 150                         uv_send_IPI_one(cpu, vector);
 151 }
 152
 153 static void uv_send_IPI_all(int vector)
 154 {
 155         uv_send_IPI_mask(&cpu_online_map, vector);
 156 }
 157
 158 static int uv_apic_id_registered(void)
 159 {
 160         return 1;
 161 }
 162
 163 static void uv_init_apic_ldr(void)
 164 {
 165 }
 166
 167 static unsigned int uv_cpu_mask_to_apicid(const cpumask_t *cpumask)
 168 {
 169         int cpu;
 170
 171         /*
 172          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 173          * May as well be the first.
 174          */
 175         cpu = first_cpu(*cpumask);
 176         if ((unsigned)cpu < nr_cpu_ids)
 177                 return per_cpu(x86_cpu_to_apicid, cpu);
 178         else
 179                 return BAD_APICID;
 180 }
 181
 182 static unsigned int get_apic_id(unsigned long x)
 183 {
 184         unsigned int id;
 185
 186         WARN_ON(preemptible() && num_online_cpus() > 1);
 187         id = x | __get_cpu_var(x2apic_extra_bits);
 188
 189         return id;
 190 }
 191
 192 static unsigned long set_apic_id(unsigned int id)
 193 {
 194         unsigned long x;
 195
 196         /* maskout x2apic_extra_bits ? */
 197         x = id;
 198         return x;
 199 }
 200
 201 static unsigned int uv_read_apic_id(void)
 202 {
 203
 204         return get_apic_id(apic_read(APIC_ID));
 205 }
 206
 207 static unsigned int phys_pkg_id(int index_msb)
 208 {
 209         return uv_read_apic_id() >> index_msb;
 210 }
 211
 212 static void uv_send_IPI_self(int vector)
 213 {
 214         apic_write(APIC_SELF_IPI, vector);
 215 }
 216
 217 struct genapic apic_x2apic_uv_x = {
 218         .name = "UV large system",
 219         .acpi_madt_oem_check = uv_acpi_madt_oem_check,
 220         .int_delivery_mode = dest_Fixed,
 221         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 222         .target_cpus = uv_target_cpus,
 223         .vector_allocation_domain = uv_vector_allocation_domain,
 224         .apic_id_registered = uv_apic_id_registered,
 225         .init_apic_ldr = uv_init_apic_ldr,
 226         .send_IPI_all = uv_send_IPI_all,
 227         .send_IPI_allbutself = uv_send_IPI_allbutself,
 228         .send_IPI_mask = uv_send_IPI_mask,
 229         .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
 230         .send_IPI_self = uv_send_IPI_self,
 231         .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
 232         .phys_pkg_id = phys_pkg_id,
 233         .get_apic_id = get_apic_id,
 234         .set_apic_id = set_apic_id,
 235         .apic_id_mask = (0xFFFFFFFFu),
 236 };
 237
 238 static __cpuinit void set_x2apic_extra_bits(int pnode)
 239 {
 240         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 241 }
 242
 243 /*
 244  * Called on boot cpu.
 245  */
 246 static __init int boot_pnode_to_blade(int pnode)
 247 {
 248         int blade;
 249
 250         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 251                 if (pnode == uv_blade_info[blade].pnode)
 252                         return blade;
 253         BUG();
 254 }
 255
 256 struct redir_addr {
 257         unsigned long redirect;
 258         unsigned long alias;
 259 };
 260
 261 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 262
 263 static __initdata struct redir_addr redir_addrs[] = {
 264         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 265         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 266         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 267 };
 268
 269 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 270 {
 271         union uvh_si_alias0_overlay_config_u alias;
 272         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 273         int i;
 274
 275         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 276                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 277                 if (alias.s.base == 0) {
 278                         *size = (1UL << alias.s.m_alias);
 279                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 280                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 281                         return;
 282                 }
 283         }
 284         BUG();
 285 }
 286
 287 static __init void map_low_mmrs(void)
 288 {
 289         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 290         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 291 }
 292
 293 enum map_type {map_wb, map_uc};
 294
 295 static __init void map_high(char *id, unsigned long base, int shift,
 296                             int max_pnode, enum map_type map_type)
 297 {
 298         unsigned long bytes, paddr;
 299
 300         paddr = base << shift;
 301         bytes = (1UL << shift) * (max_pnode + 1);
 302         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 303                                                 paddr + bytes);
 304         if (map_type == map_uc)
 305                 init_extra_mapping_uc(paddr, bytes);
 306         else
 307                 init_extra_mapping_wb(paddr, bytes);
 308
 309 }
 310 static __init void map_gru_high(int max_pnode)
 311 {
 312         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 313         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 314
 315         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 316         if (gru.s.enable)
 317                 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
 318 }
 319
 320 static __init void map_config_high(int max_pnode)
 321 {
 322         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 323         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 324
 325         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 326         if (cfg.s.enable)
 327                 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
 328 }
 329
 330 static __init void map_mmr_high(int max_pnode)
 331 {
 332         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 333         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 334
 335         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 336         if (mmr.s.enable)
 337                 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
 338 }
 339
 340 static __init void map_mmioh_high(int max_pnode)
 341 {
 342         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 343         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 344
 345         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 346         if (mmioh.s.enable)
 347                 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
 348 }
 349
 350 static __init void uv_rtc_init(void)
 351 {
 352         long status;
 353         u64 ticks_per_sec;
 354
 355         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 356                                         &ticks_per_sec);
 357         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 358                 printk(KERN_WARNING
 359                         "unable to determine platform RTC clock frequency, "
 360                         "guessing.\n");
 361                 /* BIOS gives wrong value for clock freq. so guess */
 362                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 363         } else
 364                 sn_rtc_cycles_per_second = ticks_per_sec;
 365 }
 366
 367 /*
 368  * Called on each cpu to initialize the per_cpu UV data area.
 369  *      ZZZ hotplug not supported yet
 370  */
 371 void __cpuinit uv_cpu_init(void)
 372 {
 373         /* CPU 0 initilization will be done via uv_system_init. */
 374         if (!uv_blade_info)
 375                 return;
 376
 377         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 378
 379         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 380                 set_x2apic_extra_bits(uv_hub_info->pnode);
 381 }
 382
 383
 384 void __init uv_system_init(void)
 385 {
 386         union uvh_si_addr_map_config_u m_n_config;
 387         union uvh_node_id_u node_id;
 388         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 389         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 390         int max_pnode = 0;
 391         unsigned long mmr_base, present;
 392
 393         map_low_mmrs();
 394
 395         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 396         m_val = m_n_config.s.m_skt;
 397         n_val = m_n_config.s.n_skt;
 398         mmr_base =
 399             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 400             ~UV_MMR_ENABLE;
 401         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 402
 403         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 404                 uv_possible_blades +=
 405                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 406         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 407
 408         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 409         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 410
 411         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 412
 413         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 414         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 415         memset(uv_node_to_blade, 255, bytes);
 416
 417         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 418         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 419         memset(uv_cpu_to_blade, 255, bytes);
 420
 421         blade = 0;
 422         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 423                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 424                 for (j = 0; j < 64; j++) {
 425                         if (!test_bit(j, &present))
 426                                 continue;
 427                         uv_blade_info[blade].pnode = (i * 64 + j);
 428                         uv_blade_info[blade].nr_possible_cpus = 0;
 429                         uv_blade_info[blade].nr_online_cpus = 0;
 430                         blade++;
 431                 }
 432         }
 433
 434         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 435         gnode_upper = (((unsigned long)node_id.s.node_id) &
 436                        ~((1 << n_val) - 1)) << m_val;
 437
 438         uv_bios_init();
 439         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 440                             &uv_coherency_id, &uv_region_size);
 441         uv_rtc_init();
 442
 443         for_each_present_cpu(cpu) {
 444                 nid = cpu_to_node(cpu);
 445                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 446                 blade = boot_pnode_to_blade(pnode);
 447                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 448                 uv_blade_info[blade].nr_possible_cpus++;
 449
 450                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 451                 uv_cpu_hub_info(cpu)->lowmem_remap_top =
 452                                         lowmem_redir_base + lowmem_redir_size;
 453                 uv_cpu_hub_info(cpu)->m_val = m_val;
 454                 uv_cpu_hub_info(cpu)->n_val = m_val;
 455                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 456                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 457                 uv_cpu_hub_info(cpu)->pnode = pnode;
 458                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 459                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 460                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 461                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 462                 uv_cpu_hub_info(cpu)->coherency_domain_number = uv_coherency_id;
 463                 uv_node_to_blade[nid] = blade;
 464                 uv_cpu_to_blade[cpu] = blade;
 465                 max_pnode = max(pnode, max_pnode);
 466
 467                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 468                         "lcpu %d, blade %d\n",
 469                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 470                         lcpu, blade);
 471         }
 472
 473         map_gru_high(max_pnode);
 474         map_mmr_high(max_pnode);
 475         map_config_high(max_pnode);
 476         map_mmioh_high(max_pnode);
 477
 478         uv_cpu_init();
 479 }