arch/x86/kernel/cpu/cpu_debug.c

   1 /*
   2  * CPU x86 architecture debug code
   3  *
   4  * Copyright(C) 2009 Jaswinder Singh Rajput
   5  *
   6  * For licencing details see kernel-base/COPYING
   7  */
   8
   9 #include <linux/interrupt.h>
  10 #include <linux/compiler.h>
  11 #include <linux/seq_file.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/kprobes.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/percpu.h>
  17 #include <linux/signal.h>
  18 #include <linux/errno.h>
  19 #include <linux/sched.h>
  20 #include <linux/types.h>
  21 #include <linux/init.h>
  22 #include <linux/slab.h>
  23 #include <linux/smp.h>
  24
  25 #include <asm/cpu_debug.h>
  26 #include <asm/paravirt.h>
  27 #include <asm/system.h>
  28 #include <asm/traps.h>
  29 #include <asm/apic.h>
  30 #include <asm/desc.h>
  31
  32 static DEFINE_PER_CPU(struct cpu_cpuX_base, cpu_arr[CPU_REG_ALL_BIT]);
  33 static DEFINE_PER_CPU(struct cpu_private *, priv_arr[MAX_CPU_FILES]);
  34 static DEFINE_PER_CPU(unsigned, cpu_modelflag);
  35 static DEFINE_PER_CPU(int, cpu_priv_count);
  36 static DEFINE_PER_CPU(unsigned, cpu_model);
  37
  38 static DEFINE_MUTEX(cpu_debug_lock);
  39
  40 static struct dentry *cpu_debugfs_dir;
  41
  42 static struct cpu_debug_base cpu_base[] = {
  43         { "mc",         CPU_MC          },      /* Machine Check        */
  44         { "monitor",    CPU_MONITOR     },      /* Monitor              */
  45         { "time",       CPU_TIME        },      /* Time                 */
  46         { "pmc",        CPU_PMC         },      /* Performance Monitor  */
  47         { "platform",   CPU_PLATFORM    },      /* Platform             */
  48         { "apic",       CPU_APIC        },      /* APIC                 */
  49         { "poweron",    CPU_POWERON     },      /* Power-on             */
  50         { "control",    CPU_CONTROL     },      /* Control              */
  51         { "features",   CPU_FEATURES    },      /* Features control     */
  52         { "lastbranch", CPU_LBRANCH     },      /* Last Branch          */
  53         { "bios",       CPU_BIOS        },      /* BIOS                 */
  54         { "freq",       CPU_FREQ        },      /* Frequency            */
  55         { "mtrr",       CPU_MTRR        },      /* MTRR                 */
  56         { "perf",       CPU_PERF        },      /* Performance          */
  57         { "cache",      CPU_CACHE       },      /* Cache                */
  58         { "sysenter",   CPU_SYSENTER    },      /* Sysenter             */
  59         { "therm",      CPU_THERM       },      /* Thermal              */
  60         { "misc",       CPU_MISC        },      /* Miscellaneous        */
  61         { "debug",      CPU_DEBUG       },      /* Debug                */
  62         { "pat",        CPU_PAT         },      /* PAT                  */
  63         { "vmx",        CPU_VMX         },      /* VMX                  */
  64         { "call",       CPU_CALL        },      /* System Call          */
  65         { "base",       CPU_BASE        },      /* BASE Address         */
  66         { "smm",        CPU_SMM         },      /* System mgmt mode     */
  67         { "svm",        CPU_SVM         },      /*Secure Virtial Machine*/
  68         { "osvm",       CPU_OSVM        },      /* OS-Visible Workaround*/
  69         { "tss",        CPU_TSS         },      /* Task Stack Segment   */
  70         { "cr",         CPU_CR          },      /* Control Registers    */
  71         { "dt",         CPU_DT          },      /* Descriptor Table     */
  72         { "registers",  CPU_REG_ALL     },      /* Select all Registers */
  73 };
  74
  75 static struct cpu_file_base cpu_file[] = {
  76         { "index",      CPU_REG_ALL     },      /* index                */
  77         { "value",      CPU_REG_ALL     },      /* value                */
  78 };
  79
  80 /* Intel Registers Range */
  81 static struct cpu_debug_range cpu_intel_range[] = {
  82         { 0x00000000, 0x00000001, CPU_MC,       CPU_INTEL_ALL           },
  83         { 0x00000006, 0x00000007, CPU_MONITOR,  CPU_CX_AT_XE            },
  84         { 0x00000010, 0x00000010, CPU_TIME,     CPU_INTEL_ALL           },
  85         { 0x00000011, 0x00000013, CPU_PMC,      CPU_INTEL_PENTIUM       },
  86         { 0x00000017, 0x00000017, CPU_PLATFORM, CPU_PX_CX_AT_XE         },
  87         { 0x0000001B, 0x0000001B, CPU_APIC,     CPU_P6_CX_AT_XE         },
  88
  89         { 0x0000002A, 0x0000002A, CPU_POWERON,  CPU_PX_CX_AT_XE         },
  90         { 0x0000002B, 0x0000002B, CPU_POWERON,  CPU_INTEL_XEON          },
  91         { 0x0000002C, 0x0000002C, CPU_FREQ,     CPU_INTEL_XEON          },
  92         { 0x0000003A, 0x0000003A, CPU_CONTROL,  CPU_CX_AT_XE            },
  93
  94         { 0x00000040, 0x00000043, CPU_LBRANCH,  CPU_PM_CX_AT_XE         },
  95         { 0x00000044, 0x00000047, CPU_LBRANCH,  CPU_PM_CO_AT            },
  96         { 0x00000060, 0x00000063, CPU_LBRANCH,  CPU_C2_AT               },
  97         { 0x00000064, 0x00000067, CPU_LBRANCH,  CPU_INTEL_ATOM          },
  98
  99         { 0x00000079, 0x00000079, CPU_BIOS,     CPU_P6_CX_AT_XE         },
 100         { 0x00000088, 0x0000008A, CPU_CACHE,    CPU_INTEL_P6            },
 101         { 0x0000008B, 0x0000008B, CPU_BIOS,     CPU_P6_CX_AT_XE         },
 102         { 0x0000009B, 0x0000009B, CPU_MONITOR,  CPU_INTEL_XEON          },
 103
 104         { 0x000000C1, 0x000000C2, CPU_PMC,      CPU_P6_CX_AT            },
 105         { 0x000000CD, 0x000000CD, CPU_FREQ,     CPU_CX_AT               },
 106         { 0x000000E7, 0x000000E8, CPU_PERF,     CPU_CX_AT               },
 107         { 0x000000FE, 0x000000FE, CPU_MTRR,     CPU_P6_CX_XE            },
 108
 109         { 0x00000116, 0x00000116, CPU_CACHE,    CPU_INTEL_P6            },
 110         { 0x00000118, 0x00000118, CPU_CACHE,    CPU_INTEL_P6            },
 111         { 0x00000119, 0x00000119, CPU_CACHE,    CPU_INTEL_PX            },
 112         { 0x0000011A, 0x0000011B, CPU_CACHE,    CPU_INTEL_P6            },
 113         { 0x0000011E, 0x0000011E, CPU_CACHE,    CPU_PX_CX_AT            },
 114
 115         { 0x00000174, 0x00000176, CPU_SYSENTER, CPU_P6_CX_AT_XE         },
 116         { 0x00000179, 0x0000017A, CPU_MC,       CPU_PX_CX_AT_XE         },
 117         { 0x0000017B, 0x0000017B, CPU_MC,       CPU_P6_XE               },
 118         { 0x00000186, 0x00000187, CPU_PMC,      CPU_P6_CX_AT            },
 119         { 0x00000198, 0x00000199, CPU_PERF,     CPU_PM_CX_AT_XE         },
 120         { 0x0000019A, 0x0000019A, CPU_TIME,     CPU_PM_CX_AT_XE         },
 121         { 0x0000019B, 0x0000019D, CPU_THERM,    CPU_PM_CX_AT_XE         },
 122         { 0x000001A0, 0x000001A0, CPU_MISC,     CPU_PM_CX_AT_XE         },
 123
 124         { 0x000001C9, 0x000001C9, CPU_LBRANCH,  CPU_PM_CX_AT            },
 125         { 0x000001D7, 0x000001D8, CPU_LBRANCH,  CPU_INTEL_XEON          },
 126         { 0x000001D9, 0x000001D9, CPU_DEBUG,    CPU_CX_AT_XE            },
 127         { 0x000001DA, 0x000001DA, CPU_LBRANCH,  CPU_INTEL_XEON          },
 128         { 0x000001DB, 0x000001DB, CPU_LBRANCH,  CPU_P6_XE               },
 129         { 0x000001DC, 0x000001DC, CPU_LBRANCH,  CPU_INTEL_P6            },
 130         { 0x000001DD, 0x000001DE, CPU_LBRANCH,  CPU_PX_CX_AT_XE         },
 131         { 0x000001E0, 0x000001E0, CPU_LBRANCH,  CPU_INTEL_P6            },
 132
 133         { 0x00000200, 0x0000020F, CPU_MTRR,     CPU_P6_CX_XE            },
 134         { 0x00000250, 0x00000250, CPU_MTRR,     CPU_P6_CX_XE            },
 135         { 0x00000258, 0x00000259, CPU_MTRR,     CPU_P6_CX_XE            },
 136         { 0x00000268, 0x0000026F, CPU_MTRR,     CPU_P6_CX_XE            },
 137         { 0x00000277, 0x00000277, CPU_PAT,      CPU_C2_AT_XE            },
 138         { 0x000002FF, 0x000002FF, CPU_MTRR,     CPU_P6_CX_XE            },
 139
 140         { 0x00000300, 0x00000308, CPU_PMC,      CPU_INTEL_XEON          },
 141         { 0x00000309, 0x0000030B, CPU_PMC,      CPU_C2_AT_XE            },
 142         { 0x0000030C, 0x00000311, CPU_PMC,      CPU_INTEL_XEON          },
 143         { 0x00000345, 0x00000345, CPU_PMC,      CPU_C2_AT               },
 144         { 0x00000360, 0x00000371, CPU_PMC,      CPU_INTEL_XEON          },
 145         { 0x0000038D, 0x00000390, CPU_PMC,      CPU_C2_AT               },
 146         { 0x000003A0, 0x000003BE, CPU_PMC,      CPU_INTEL_XEON          },
 147         { 0x000003C0, 0x000003CD, CPU_PMC,      CPU_INTEL_XEON          },
 148         { 0x000003E0, 0x000003E1, CPU_PMC,      CPU_INTEL_XEON          },
 149         { 0x000003F0, 0x000003F0, CPU_PMC,      CPU_INTEL_XEON          },
 150         { 0x000003F1, 0x000003F1, CPU_PMC,      CPU_C2_AT_XE            },
 151         { 0x000003F2, 0x000003F2, CPU_PMC,      CPU_INTEL_XEON          },
 152
 153         { 0x00000400, 0x00000402, CPU_MC,       CPU_PM_CX_AT_XE         },
 154         { 0x00000403, 0x00000403, CPU_MC,       CPU_INTEL_XEON          },
 155         { 0x00000404, 0x00000406, CPU_MC,       CPU_PM_CX_AT_XE         },
 156         { 0x00000407, 0x00000407, CPU_MC,       CPU_INTEL_XEON          },
 157         { 0x00000408, 0x0000040A, CPU_MC,       CPU_PM_CX_AT_XE         },
 158         { 0x0000040B, 0x0000040B, CPU_MC,       CPU_INTEL_XEON          },
 159         { 0x0000040C, 0x0000040E, CPU_MC,       CPU_PM_CX_XE            },
 160         { 0x0000040F, 0x0000040F, CPU_MC,       CPU_INTEL_XEON          },
 161         { 0x00000410, 0x00000412, CPU_MC,       CPU_PM_CX_AT_XE         },
 162         { 0x00000413, 0x00000417, CPU_MC,       CPU_CX_AT_XE            },
 163         { 0x00000480, 0x0000048B, CPU_VMX,      CPU_CX_AT_XE            },
 164
 165         { 0x00000600, 0x00000600, CPU_DEBUG,    CPU_PM_CX_AT_XE         },
 166         { 0x00000680, 0x0000068F, CPU_LBRANCH,  CPU_INTEL_XEON          },
 167         { 0x000006C0, 0x000006CF, CPU_LBRANCH,  CPU_INTEL_XEON          },
 168
 169         { 0x000107CC, 0x000107D3, CPU_PMC,      CPU_INTEL_XEON_MP       },
 170
 171         { 0xC0000080, 0xC0000080, CPU_FEATURES, CPU_INTEL_XEON          },
 172         { 0xC0000081, 0xC0000082, CPU_CALL,     CPU_INTEL_XEON          },
 173         { 0xC0000084, 0xC0000084, CPU_CALL,     CPU_INTEL_XEON          },
 174         { 0xC0000100, 0xC0000102, CPU_BASE,     CPU_INTEL_XEON          },
 175 };
 176
 177 /* AMD Registers Range */
 178 static struct cpu_debug_range cpu_amd_range[] = {
 179         { 0x00000010, 0x00000010, CPU_TIME,     CPU_ALL,                },
 180         { 0x0000001B, 0x0000001B, CPU_APIC,     CPU_ALL,                },
 181         { 0x000000FE, 0x000000FE, CPU_MTRR,     CPU_ALL,                },
 182
 183         { 0x00000174, 0x00000176, CPU_SYSENTER, CPU_ALL,                },
 184         { 0x00000179, 0x0000017A, CPU_MC,       CPU_ALL,                },
 185         { 0x0000017B, 0x0000017B, CPU_MC,       CPU_ALL,                },
 186         { 0x000001D9, 0x000001D9, CPU_DEBUG,    CPU_ALL,                },
 187         { 0x000001DB, 0x000001DE, CPU_LBRANCH,  CPU_ALL,                },
 188
 189         { 0x00000200, 0x0000020F, CPU_MTRR,     CPU_ALL,                },
 190         { 0x00000250, 0x00000250, CPU_MTRR,     CPU_ALL,                },
 191         { 0x00000258, 0x00000259, CPU_MTRR,     CPU_ALL,                },
 192         { 0x00000268, 0x0000026F, CPU_MTRR,     CPU_ALL,                },
 193         { 0x00000277, 0x00000277, CPU_PAT,      CPU_ALL,                },
 194         { 0x000002FF, 0x000002FF, CPU_MTRR,     CPU_ALL,                },
 195
 196         { 0x00000400, 0x00000417, CPU_MC,       CPU_ALL,                },
 197
 198         { 0xC0000080, 0xC0000080, CPU_FEATURES, CPU_ALL,                },
 199         { 0xC0000081, 0xC0000084, CPU_CALL,     CPU_ALL,                },
 200         { 0xC0000100, 0xC0000102, CPU_BASE,     CPU_ALL,                },
 201         { 0xC0000103, 0xC0000103, CPU_TIME,     CPU_ALL,                },
 202
 203         { 0xC0000408, 0xC000040A, CPU_MC,       CPU_ALL,                },
 204
 205         { 0xc0010000, 0xc0010007, CPU_PMC,      CPU_ALL,                },
 206         { 0xc0010010, 0xc0010010, CPU_MTRR,     CPU_ALL,                },
 207         { 0xc0010016, 0xc001001A, CPU_MTRR,     CPU_ALL,                },
 208         { 0xc001001D, 0xc001001D, CPU_MTRR,     CPU_ALL,                },
 209         { 0xc0010030, 0xc0010035, CPU_BIOS,     CPU_ALL,                },
 210         { 0xc0010056, 0xc0010056, CPU_SMM,      CPU_ALL,                },
 211         { 0xc0010061, 0xc0010063, CPU_SMM,      CPU_ALL,                },
 212         { 0xc0010074, 0xc0010074, CPU_MC,       CPU_ALL,                },
 213         { 0xc0010111, 0xc0010113, CPU_SMM,      CPU_ALL,                },
 214         { 0xc0010114, 0xc0010118, CPU_SVM,      CPU_ALL,                },
 215         { 0xc0010119, 0xc001011A, CPU_SMM,      CPU_ALL,                },
 216         { 0xc0010140, 0xc0010141, CPU_OSVM,     CPU_ALL,                },
 217         { 0xc0010156, 0xc0010156, CPU_SMM,      CPU_ALL,                },
 218 };
 219
 220
 221 static int get_cpu_modelflag(unsigned cpu)
 222 {
 223         int flag;
 224
 225         switch (per_cpu(cpu_model, cpu)) {
 226         /* Intel */
 227         case 0x0501:
 228         case 0x0502:
 229         case 0x0504:
 230                 flag = CPU_INTEL_PENTIUM;
 231                 break;
 232         case 0x0601:
 233         case 0x0603:
 234         case 0x0605:
 235         case 0x0607:
 236         case 0x0608:
 237         case 0x060A:
 238         case 0x060B:
 239                 flag = CPU_INTEL_P6;
 240                 break;
 241         case 0x0609:
 242         case 0x060D:
 243                 flag = CPU_INTEL_PENTIUM_M;
 244                 break;
 245         case 0x060E:
 246                 flag = CPU_INTEL_CORE;
 247                 break;
 248         case 0x060F:
 249         case 0x0617:
 250                 flag = CPU_INTEL_CORE2;
 251                 break;
 252         case 0x061C:
 253                 flag = CPU_INTEL_ATOM;
 254                 break;
 255         case 0x0F00:
 256         case 0x0F01:
 257         case 0x0F02:
 258         case 0x0F03:
 259         case 0x0F04:
 260                 flag = CPU_INTEL_XEON_P4;
 261                 break;
 262         case 0x0F06:
 263                 flag = CPU_INTEL_XEON_MP;
 264                 break;
 265         default:
 266                 flag = CPU_NONE;
 267                 break;
 268         }
 269
 270         return flag;
 271 }
 272
 273 static int get_cpu_range_count(unsigned cpu)
 274 {
 275         int index;
 276
 277         switch (per_cpu(cpu_model, cpu) >> 16) {
 278         case X86_VENDOR_INTEL:
 279                 index = ARRAY_SIZE(cpu_intel_range);
 280                 break;
 281         case X86_VENDOR_AMD:
 282                 index = ARRAY_SIZE(cpu_amd_range);
 283                 break;
 284         default:
 285                 index = 0;
 286                 break;
 287         }
 288
 289         return index;
 290 }
 291
 292 static int is_typeflag_valid(unsigned cpu, unsigned flag)
 293 {
 294         unsigned vendor, modelflag;
 295         int i, index;
 296
 297         /* Standard Registers should be always valid */
 298         if (flag >= CPU_TSS)
 299                 return 1;
 300
 301         modelflag = per_cpu(cpu_modelflag, cpu);
 302         vendor = per_cpu(cpu_model, cpu) >> 16;
 303         index = get_cpu_range_count(cpu);
 304
 305         for (i = 0; i < index; i++) {
 306                 switch (vendor) {
 307                 case X86_VENDOR_INTEL:
 308                         if ((cpu_intel_range[i].model & modelflag) &&
 309                             (cpu_intel_range[i].flag & flag))
 310                                 return 1;
 311                         break;
 312                 case X86_VENDOR_AMD:
 313                         if (cpu_amd_range[i].flag & flag)
 314                                 return 1;
 315                         break;
 316                 }
 317         }
 318
 319         /* Invalid */
 320         return 0;
 321 }
 322
 323 static unsigned get_cpu_range(unsigned cpu, unsigned *min, unsigned *max,
 324                               int index, unsigned flag)
 325 {
 326         unsigned modelflag;
 327
 328         modelflag = per_cpu(cpu_modelflag, cpu);
 329         *max = 0;
 330         switch (per_cpu(cpu_model, cpu) >> 16) {
 331         case X86_VENDOR_INTEL:
 332                 if ((cpu_intel_range[index].model & modelflag) &&
 333                     (cpu_intel_range[index].flag & flag)) {
 334                         *min = cpu_intel_range[index].min;
 335                         *max = cpu_intel_range[index].max;
 336                 }
 337                 break;
 338         case X86_VENDOR_AMD:
 339                 if (cpu_amd_range[index].flag & flag) {
 340                         *min = cpu_amd_range[index].min;
 341                         *max = cpu_amd_range[index].max;
 342                 }
 343                 break;
 344         }
 345
 346         return *max;
 347 }
 348
 349 /* This function can also be called with seq = NULL for printk */
 350 static void print_cpu_data(struct seq_file *seq, unsigned type,
 351                            u32 low, u32 high)
 352 {
 353         struct cpu_private *priv;
 354         u64 val = high;
 355
 356         if (seq) {
 357                 priv = seq->private;
 358                 if (priv->file) {
 359                         val = (val << 32) | low;
 360                         seq_printf(seq, "0x%llx\n", val);
 361                 } else
 362                         seq_printf(seq, " %08x: %08x_%08x\n",
 363                                    type, high, low);
 364         } else
 365                 printk(KERN_INFO " %08x: %08x_%08x\n", type, high, low);
 366 }
 367
 368 /* This function can also be called with seq = NULL for printk */
 369 static void print_msr(struct seq_file *seq, unsigned cpu, unsigned flag)
 370 {
 371         unsigned msr, msr_min, msr_max;
 372         struct cpu_private *priv;
 373         u32 low, high;
 374         int i, range;
 375
 376         if (seq) {
 377                 priv = seq->private;
 378                 if (priv->file) {
 379                         if (!rdmsr_safe_on_cpu(priv->cpu, priv->reg,
 380                                                &low, &high))
 381                                 print_cpu_data(seq, priv->reg, low, high);
 382                         return;
 383                 }
 384         }
 385
 386         range = get_cpu_range_count(cpu);
 387
 388         for (i = 0; i < range; i++) {
 389                 if (!get_cpu_range(cpu, &msr_min, &msr_max, i, flag))
 390                         continue;
 391
 392                 for (msr = msr_min; msr <= msr_max; msr++) {
 393                         if (rdmsr_safe_on_cpu(cpu, msr, &low, &high))
 394                                 continue;
 395                         print_cpu_data(seq, msr, low, high);
 396                 }
 397         }
 398 }
 399
 400 static void print_tss(void *arg)
 401 {
 402         struct pt_regs *regs = task_pt_regs(current);
 403         struct seq_file *seq = arg;
 404         unsigned int seg;
 405
 406         seq_printf(seq, " RAX\t: %016lx\n", regs->ax);
 407         seq_printf(seq, " RBX\t: %016lx\n", regs->bx);
 408         seq_printf(seq, " RCX\t: %016lx\n", regs->cx);
 409         seq_printf(seq, " RDX\t: %016lx\n", regs->dx);
 410
 411         seq_printf(seq, " RSI\t: %016lx\n", regs->si);
 412         seq_printf(seq, " RDI\t: %016lx\n", regs->di);
 413         seq_printf(seq, " RBP\t: %016lx\n", regs->bp);
 414         seq_printf(seq, " ESP\t: %016lx\n", regs->sp);
 415
 416 #ifdef CONFIG_X86_64
 417         seq_printf(seq, " R08\t: %016lx\n", regs->r8);
 418         seq_printf(seq, " R09\t: %016lx\n", regs->r9);
 419         seq_printf(seq, " R10\t: %016lx\n", regs->r10);
 420         seq_printf(seq, " R11\t: %016lx\n", regs->r11);
 421         seq_printf(seq, " R12\t: %016lx\n", regs->r12);
 422         seq_printf(seq, " R13\t: %016lx\n", regs->r13);
 423         seq_printf(seq, " R14\t: %016lx\n", regs->r14);
 424         seq_printf(seq, " R15\t: %016lx\n", regs->r15);
 425 #endif
 426
 427         asm("movl %%cs,%0" : "=r" (seg));
 428         seq_printf(seq, " CS\t:             %04x\n", seg);
 429         asm("movl %%ds,%0" : "=r" (seg));
 430         seq_printf(seq, " DS\t:             %04x\n", seg);
 431         seq_printf(seq, " SS\t:             %04lx\n", regs->ss & 0xffff);
 432         asm("movl %%es,%0" : "=r" (seg));
 433         seq_printf(seq, " ES\t:             %04x\n", seg);
 434         asm("movl %%fs,%0" : "=r" (seg));
 435         seq_printf(seq, " FS\t:             %04x\n", seg);
 436         asm("movl %%gs,%0" : "=r" (seg));
 437         seq_printf(seq, " GS\t:             %04x\n", seg);
 438
 439         seq_printf(seq, " EFLAGS\t: %016lx\n", regs->flags);
 440
 441         seq_printf(seq, " EIP\t: %016lx\n", regs->ip);
 442 }
 443
 444 static void print_cr(void *arg)
 445 {
 446         struct seq_file *seq = arg;
 447
 448         seq_printf(seq, " cr0\t: %016lx\n", read_cr0());
 449         seq_printf(seq, " cr2\t: %016lx\n", read_cr2());
 450         seq_printf(seq, " cr3\t: %016lx\n", read_cr3());
 451         seq_printf(seq, " cr4\t: %016lx\n", read_cr4_safe());
 452 #ifdef CONFIG_X86_64
 453         seq_printf(seq, " cr8\t: %016lx\n", read_cr8());
 454 #endif
 455 }
 456
 457 static void print_desc_ptr(char *str, struct seq_file *seq, struct desc_ptr dt)
 458 {
 459         seq_printf(seq, " %s\t: %016llx\n", str, (u64)(dt.address | dt.size));
 460 }
 461
 462 static void print_dt(void *seq)
 463 {
 464         struct desc_ptr dt;
 465         unsigned long ldt;
 466
 467         /* IDT */
 468         store_idt((struct desc_ptr *)&dt);
 469         print_desc_ptr("IDT", seq, dt);
 470
 471         /* GDT */
 472         store_gdt((struct desc_ptr *)&dt);
 473         print_desc_ptr("GDT", seq, dt);
 474
 475         /* LDT */
 476         store_ldt(ldt);
 477         seq_printf(seq, " LDT\t: %016lx\n", ldt);
 478
 479         /* TR */
 480         store_tr(ldt);
 481         seq_printf(seq, " TR\t: %016lx\n", ldt);
 482 }
 483
 484 static void print_dr(void *arg)
 485 {
 486         struct seq_file *seq = arg;
 487         unsigned long dr;
 488         int i;
 489
 490         for (i = 0; i < 8; i++) {
 491                 /* Ignore db4, db5 */
 492                 if ((i == 4) || (i == 5))
 493                         continue;
 494                 get_debugreg(dr, i);
 495                 seq_printf(seq, " dr%d\t: %016lx\n", i, dr);
 496         }
 497
 498         seq_printf(seq, "\n MSR\t:\n");
 499 }
 500
 501 static void print_apic(void *arg)
 502 {
 503         struct seq_file *seq = arg;
 504
 505 #ifdef CONFIG_X86_LOCAL_APIC
 506         seq_printf(seq, " LAPIC\t:\n");
 507         seq_printf(seq, " ID\t\t: %08x\n",  apic_read(APIC_ID) >> 24);
 508         seq_printf(seq, " LVR\t\t: %08x\n",  apic_read(APIC_LVR));
 509         seq_printf(seq, " TASKPRI\t: %08x\n",  apic_read(APIC_TASKPRI));
 510         seq_printf(seq, " ARBPRI\t\t: %08x\n",  apic_read(APIC_ARBPRI));
 511         seq_printf(seq, " PROCPRI\t: %08x\n",  apic_read(APIC_PROCPRI));
 512         seq_printf(seq, " LDR\t\t: %08x\n",  apic_read(APIC_LDR));
 513         seq_printf(seq, " DFR\t\t: %08x\n",  apic_read(APIC_DFR));
 514         seq_printf(seq, " SPIV\t\t: %08x\n",  apic_read(APIC_SPIV));
 515         seq_printf(seq, " ISR\t\t: %08x\n",  apic_read(APIC_ISR));
 516         seq_printf(seq, " ESR\t\t: %08x\n",  apic_read(APIC_ESR));
 517         seq_printf(seq, " ICR\t\t: %08x\n",  apic_read(APIC_ICR));
 518         seq_printf(seq, " ICR2\t\t: %08x\n",  apic_read(APIC_ICR2));
 519         seq_printf(seq, " LVTT\t\t: %08x\n",  apic_read(APIC_LVTT));
 520         seq_printf(seq, " LVTTHMR\t: %08x\n",  apic_read(APIC_LVTTHMR));
 521         seq_printf(seq, " LVTPC\t\t: %08x\n",  apic_read(APIC_LVTPC));
 522         seq_printf(seq, " LVT0\t\t: %08x\n",  apic_read(APIC_LVT0));
 523         seq_printf(seq, " LVT1\t\t: %08x\n",  apic_read(APIC_LVT1));
 524         seq_printf(seq, " LVTERR\t\t: %08x\n",  apic_read(APIC_LVTERR));
 525         seq_printf(seq, " TMICT\t\t: %08x\n",  apic_read(APIC_TMICT));
 526         seq_printf(seq, " TMCCT\t\t: %08x\n",  apic_read(APIC_TMCCT));
 527         seq_printf(seq, " TDCR\t\t: %08x\n",  apic_read(APIC_TDCR));
 528 #endif /* CONFIG_X86_LOCAL_APIC */
 529
 530         seq_printf(seq, "\n MSR\t:\n");
 531 }
 532
 533 static int cpu_seq_show(struct seq_file *seq, void *v)
 534 {
 535         struct cpu_private *priv = seq->private;
 536
 537         if (priv == NULL)
 538                 return -EINVAL;
 539
 540         switch (cpu_base[priv->type].flag) {
 541         case CPU_TSS:
 542                 smp_call_function_single(priv->cpu, print_tss, seq, 1);
 543                 break;
 544         case CPU_CR:
 545                 smp_call_function_single(priv->cpu, print_cr, seq, 1);
 546                 break;
 547         case CPU_DT:
 548                 smp_call_function_single(priv->cpu, print_dt, seq, 1);
 549                 break;
 550         case CPU_DEBUG:
 551                 if (priv->file == CPU_INDEX_BIT)
 552                         smp_call_function_single(priv->cpu, print_dr, seq, 1);
 553                 print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
 554                 break;
 555         case CPU_APIC:
 556                 if (priv->file == CPU_INDEX_BIT)
 557                         smp_call_function_single(priv->cpu, print_apic, seq, 1);
 558                 print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
 559                 break;
 560
 561         default:
 562                 print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
 563                 break;
 564         }
 565         seq_printf(seq, "\n");
 566
 567         return 0;
 568 }
 569
 570 static void *cpu_seq_start(struct seq_file *seq, loff_t *pos)
 571 {
 572         if (*pos == 0) /* One time is enough ;-) */
 573                 return seq;
 574
 575         return NULL;
 576 }
 577
 578 static void *cpu_seq_next(struct seq_file *seq, void *v, loff_t *pos)
 579 {
 580         (*pos)++;
 581
 582         return cpu_seq_start(seq, pos);
 583 }
 584
 585 static void cpu_seq_stop(struct seq_file *seq, void *v)
 586 {
 587 }
 588
 589 static const struct seq_operations cpu_seq_ops = {
 590         .start          = cpu_seq_start,
 591         .next           = cpu_seq_next,
 592         .stop           = cpu_seq_stop,
 593         .show           = cpu_seq_show,
 594 };
 595
 596 static int cpu_seq_open(struct inode *inode, struct file *file)
 597 {
 598         struct cpu_private *priv = inode->i_private;
 599         struct seq_file *seq;
 600         int err;
 601
 602         err = seq_open(file, &cpu_seq_ops);
 603         if (!err) {
 604                 seq = file->private_data;
 605                 seq->private = priv;
 606         }
 607
 608         return err;
 609 }
 610
 611 static const struct file_operations cpu_fops = {
 612         .open           = cpu_seq_open,
 613         .read           = seq_read,
 614         .llseek         = seq_lseek,
 615         .release        = seq_release,
 616 };
 617
 618 static int cpu_create_file(unsigned cpu, unsigned type, unsigned reg,
 619                            unsigned file, struct dentry *dentry)
 620 {
 621         struct cpu_private *priv = NULL;
 622
 623         /* Already intialized */
 624         if (file == CPU_INDEX_BIT)
 625                 if (per_cpu(cpu_arr[type].init, cpu))
 626                         return 0;
 627
 628         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 629         if (priv == NULL)
 630                 return -ENOMEM;
 631
 632         priv->cpu = cpu;
 633         priv->type = type;
 634         priv->reg = reg;
 635         priv->file = file;
 636         mutex_lock(&cpu_debug_lock);
 637         per_cpu(priv_arr[type], cpu) = priv;
 638         per_cpu(cpu_priv_count, cpu)++;
 639         mutex_unlock(&cpu_debug_lock);
 640
 641         if (file)
 642                 debugfs_create_file(cpu_file[file].name, S_IRUGO,
 643                                     dentry, (void *)priv, &cpu_fops);
 644         else {
 645                 debugfs_create_file(cpu_base[type].name, S_IRUGO,
 646                                     per_cpu(cpu_arr[type].dentry, cpu),
 647                                     (void *)priv, &cpu_fops);
 648                 mutex_lock(&cpu_debug_lock);
 649                 per_cpu(cpu_arr[type].init, cpu) = 1;
 650                 mutex_unlock(&cpu_debug_lock);
 651         }
 652
 653         return 0;
 654 }
 655
 656 static int cpu_init_regfiles(unsigned cpu, unsigned int type, unsigned reg,
 657                              struct dentry *dentry)
 658 {
 659         unsigned file;
 660         int err = 0;
 661
 662         for (file = 0; file <  ARRAY_SIZE(cpu_file); file++) {
 663                 err = cpu_create_file(cpu, type, reg, file, dentry);
 664                 if (err)
 665                         return err;
 666         }
 667
 668         return err;
 669 }
 670
 671 static int cpu_init_msr(unsigned cpu, unsigned type, struct dentry *dentry)
 672 {
 673         struct dentry *cpu_dentry = NULL;
 674         unsigned reg, reg_min, reg_max;
 675         int i, range, err = 0;
 676         char reg_dir[12];
 677         u32 low, high;
 678
 679         range = get_cpu_range_count(cpu);
 680
 681         for (i = 0; i < range; i++) {
 682                 if (!get_cpu_range(cpu, &reg_min, &reg_max, i,
 683                                    cpu_base[type].flag))
 684                         continue;
 685
 686                 for (reg = reg_min; reg <= reg_max; reg++) {
 687                         if (rdmsr_safe_on_cpu(cpu, reg, &low, &high))
 688                                 continue;
 689
 690                         sprintf(reg_dir, "0x%x", reg);
 691                         cpu_dentry = debugfs_create_dir(reg_dir, dentry);
 692                         err = cpu_init_regfiles(cpu, type, reg, cpu_dentry);
 693                         if (err)
 694                                 return err;
 695                 }
 696         }
 697
 698         return err;
 699 }
 700
 701 static int cpu_init_allreg(unsigned cpu, struct dentry *dentry)
 702 {
 703         struct dentry *cpu_dentry = NULL;
 704         unsigned type;
 705         int err = 0;
 706
 707         for (type = 0; type <  ARRAY_SIZE(cpu_base) - 1; type++) {
 708                 if (!is_typeflag_valid(cpu, cpu_base[type].flag))
 709                         continue;
 710                 cpu_dentry = debugfs_create_dir(cpu_base[type].name, dentry);
 711                 per_cpu(cpu_arr[type].dentry, cpu) = cpu_dentry;
 712
 713                 if (type < CPU_TSS_BIT)
 714                         err = cpu_init_msr(cpu, type, cpu_dentry);
 715                 else
 716                         err = cpu_create_file(cpu, type, 0, CPU_INDEX_BIT,
 717                                               cpu_dentry);
 718                 if (err)
 719                         return err;
 720         }
 721
 722         return err;
 723 }
 724
 725 static int cpu_init_cpu(void)
 726 {
 727         struct dentry *cpu_dentry = NULL;
 728         struct cpuinfo_x86 *cpui;
 729         char cpu_dir[12];
 730         unsigned cpu;
 731         int err = 0;
 732
 733         for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
 734                 cpui = &cpu_data(cpu);
 735                 if (!cpu_has(cpui, X86_FEATURE_MSR))
 736                         continue;
 737                 per_cpu(cpu_model, cpu) = ((cpui->x86_vendor << 16) |
 738                                            (cpui->x86 << 8) |
 739                                            (cpui->x86_model));
 740                 per_cpu(cpu_modelflag, cpu) = get_cpu_modelflag(cpu);
 741
 742                 sprintf(cpu_dir, "cpu%d", cpu);
 743                 cpu_dentry = debugfs_create_dir(cpu_dir, cpu_debugfs_dir);
 744                 err = cpu_init_allreg(cpu, cpu_dentry);
 745
 746                 pr_info("cpu%d(%d) debug files %d\n",
 747                         cpu, nr_cpu_ids, per_cpu(cpu_priv_count, cpu));
 748                 if (per_cpu(cpu_priv_count, cpu) > MAX_CPU_FILES) {
 749                         pr_err("Register files count %d exceeds limit %d\n",
 750                                 per_cpu(cpu_priv_count, cpu), MAX_CPU_FILES);
 751                         per_cpu(cpu_priv_count, cpu) = MAX_CPU_FILES;
 752                         err = -ENFILE;
 753                 }
 754                 if (err)
 755                         return err;
 756         }
 757
 758         return err;
 759 }
 760
 761 static int __init cpu_debug_init(void)
 762 {
 763         cpu_debugfs_dir = debugfs_create_dir("cpu", arch_debugfs_dir);
 764
 765         return cpu_init_cpu();
 766 }
 767
 768 static void __exit cpu_debug_exit(void)
 769 {
 770         int i, cpu;
 771
 772         if (cpu_debugfs_dir)
 773                 debugfs_remove_recursive(cpu_debugfs_dir);
 774
 775         for (cpu = 0; cpu <  nr_cpu_ids; cpu++)
 776                 for (i = 0; i < per_cpu(cpu_priv_count, cpu); i++)
 777                         kfree(per_cpu(priv_arr[i], cpu));
 778 }
 779
 780 module_init(cpu_debug_init);
 781 module_exit(cpu_debug_exit);
 782
 783 MODULE_AUTHOR("Jaswinder Singh Rajput");
 784 MODULE_DESCRIPTION("CPU Debug module");
 785 MODULE_LICENSE("GPL");